GCR_RST1

Macros
#define	MXC_F_GCR_RST1_I2C1_POS   0
#define	MXC_F_GCR_RST1_I2C1   ((uint32_t)(0x1UL << MXC_F_GCR_RST1_I2C1_POS))
#define	MXC_F_GCR_RST1_WDT1_POS   8
#define	MXC_F_GCR_RST1_WDT1   ((uint32_t)(0x1UL << MXC_F_GCR_RST1_WDT1_POS))
#define	MXC_F_GCR_RST1_CRC_POS   9
#define	MXC_F_GCR_RST1_CRC   ((uint32_t)(0x1UL << MXC_F_GCR_RST1_CRC_POS))
#define	MXC_F_GCR_RST1_AES_POS   10
#define	MXC_F_GCR_RST1_AES   ((uint32_t)(0x1UL << MXC_F_GCR_RST1_AES_POS))
#define	MXC_F_GCR_RST1_AC_POS   14
#define	MXC_F_GCR_RST1_AC   ((uint32_t)(0x1UL << MXC_F_GCR_RST1_AC_POS))
#define	MXC_F_GCR_RST1_I2C2_POS   17
#define	MXC_F_GCR_RST1_I2C2   ((uint32_t)(0x1UL << MXC_F_GCR_RST1_I2C2_POS))
#define	MXC_F_GCR_RST1_I2S_POS   23
#define	MXC_F_GCR_RST1_I2S   ((uint32_t)(0x1UL << MXC_F_GCR_RST1_I2S_POS))
#define	MXC_F_GCR_RST1_AFE_POS   25
#define	MXC_F_GCR_RST1_AFE   ((uint32_t)(0x1UL << MXC_F_GCR_RST1_AFE_POS))

Detailed Description

Reset 1.

Macro Definition Documentation

MXC_F_GCR_RST1_AC

#define MXC_F_GCR_RST1_AC   ((uint32_t)(0x1UL << MXC_F_GCR_RST1_AC_POS))

RST1_AC Mask

MXC_F_GCR_RST1_AC_POS

#define MXC_F_GCR_RST1_AC_POS   14

RST1_AC Position

MXC_F_GCR_RST1_AES

#define MXC_F_GCR_RST1_AES   ((uint32_t)(0x1UL << MXC_F_GCR_RST1_AES_POS))

RST1_AES Mask

MXC_F_GCR_RST1_AES_POS

#define MXC_F_GCR_RST1_AES_POS   10

RST1_AES Position

MXC_F_GCR_RST1_AFE

#define MXC_F_GCR_RST1_AFE   ((uint32_t)(0x1UL << MXC_F_GCR_RST1_AFE_POS))

RST1_AFE Mask

MXC_F_GCR_RST1_AFE_POS

#define MXC_F_GCR_RST1_AFE_POS   25

RST1_AFE Position

MXC_F_GCR_RST1_CRC

#define MXC_F_GCR_RST1_CRC   ((uint32_t)(0x1UL << MXC_F_GCR_RST1_CRC_POS))

RST1_CRC Mask

MXC_F_GCR_RST1_CRC_POS

#define MXC_F_GCR_RST1_CRC_POS   9

RST1_CRC Position

MXC_F_GCR_RST1_I2C1

#define MXC_F_GCR_RST1_I2C1   ((uint32_t)(0x1UL << MXC_F_GCR_RST1_I2C1_POS))

RST1_I2C1 Mask

MXC_F_GCR_RST1_I2C1_POS

#define MXC_F_GCR_RST1_I2C1_POS   0

RST1_I2C1 Position

MXC_F_GCR_RST1_I2C2

#define MXC_F_GCR_RST1_I2C2   ((uint32_t)(0x1UL << MXC_F_GCR_RST1_I2C2_POS))

RST1_I2C2 Mask

MXC_F_GCR_RST1_I2C2_POS

#define MXC_F_GCR_RST1_I2C2_POS   17

RST1_I2C2 Position

MXC_F_GCR_RST1_I2S

#define MXC_F_GCR_RST1_I2S   ((uint32_t)(0x1UL << MXC_F_GCR_RST1_I2S_POS))

RST1_I2S Mask

MXC_F_GCR_RST1_I2S_POS

#define MXC_F_GCR_RST1_I2S_POS   23

RST1_I2S Position

MXC_F_GCR_RST1_WDT1

#define MXC_F_GCR_RST1_WDT1   ((uint32_t)(0x1UL << MXC_F_GCR_RST1_WDT1_POS))

RST1_WDT1 Mask

MXC_F_GCR_RST1_WDT1_POS

#define MXC_F_GCR_RST1_WDT1_POS   8

RST1_WDT1 Position