|
#define | MXC_R_I2S_CTRL0CH0 ((uint32_t)0x00000000UL) |
|
#define | MXC_R_I2S_CTRL1CH0 ((uint32_t)0x00000010UL) |
|
#define | MXC_R_I2S_DMACH0 ((uint32_t)0x00000030UL) |
|
#define | MXC_R_I2S_FIFOCH0 ((uint32_t)0x00000040UL) |
|
#define | MXC_R_I2S_INTFL ((uint32_t)0x00000050UL) |
|
#define | MXC_R_I2S_INTEN ((uint32_t)0x00000054UL) |
|
#define | MXC_R_I2S_EXTSETUP ((uint32_t)0x00000058UL) |
|
#define | MXC_F_I2S_CTRL0CH0_LSB_FIRST_POS 1 |
|
#define | MXC_F_I2S_CTRL0CH0_LSB_FIRST ((uint32_t)(0x1UL << MXC_F_I2S_CTRL0CH0_LSB_FIRST_POS)) |
|
#define | MXC_F_I2S_CTRL0CH0_CH_MODE_POS 6 |
|
#define | MXC_F_I2S_CTRL0CH0_CH_MODE ((uint32_t)(0x3UL << MXC_F_I2S_CTRL0CH0_CH_MODE_POS)) |
|
#define | MXC_F_I2S_CTRL0CH0_WS_POL_POS 8 |
|
#define | MXC_F_I2S_CTRL0CH0_WS_POL ((uint32_t)(0x1UL << MXC_F_I2S_CTRL0CH0_WS_POL_POS)) |
|
#define | MXC_F_I2S_CTRL0CH0_MSB_LOC_POS 9 |
|
#define | MXC_F_I2S_CTRL0CH0_MSB_LOC ((uint32_t)(0x1UL << MXC_F_I2S_CTRL0CH0_MSB_LOC_POS)) |
|
#define | MXC_F_I2S_CTRL0CH0_ALIGN_POS 10 |
|
#define | MXC_F_I2S_CTRL0CH0_ALIGN ((uint32_t)(0x1UL << MXC_F_I2S_CTRL0CH0_ALIGN_POS)) |
|
#define | MXC_F_I2S_CTRL0CH0_EXT_SEL_POS 11 |
|
#define | MXC_F_I2S_CTRL0CH0_EXT_SEL ((uint32_t)(0x1UL << MXC_F_I2S_CTRL0CH0_EXT_SEL_POS)) |
|
#define | MXC_F_I2S_CTRL0CH0_STEREO_POS 12 |
|
#define | MXC_F_I2S_CTRL0CH0_STEREO ((uint32_t)(0x3UL << MXC_F_I2S_CTRL0CH0_STEREO_POS)) |
|
#define | MXC_F_I2S_CTRL0CH0_WSIZE_POS 14 |
|
#define | MXC_F_I2S_CTRL0CH0_WSIZE ((uint32_t)(0x3UL << MXC_F_I2S_CTRL0CH0_WSIZE_POS)) |
|
#define | MXC_F_I2S_CTRL0CH0_TX_EN_POS 16 |
|
#define | MXC_F_I2S_CTRL0CH0_TX_EN ((uint32_t)(0x1UL << MXC_F_I2S_CTRL0CH0_TX_EN_POS)) |
|
#define | MXC_F_I2S_CTRL0CH0_RX_EN_POS 17 |
|
#define | MXC_F_I2S_CTRL0CH0_RX_EN ((uint32_t)(0x1UL << MXC_F_I2S_CTRL0CH0_RX_EN_POS)) |
|
#define | MXC_F_I2S_CTRL0CH0_FLUSH_POS 18 |
|
#define | MXC_F_I2S_CTRL0CH0_FLUSH ((uint32_t)(0x1UL << MXC_F_I2S_CTRL0CH0_FLUSH_POS)) |
|
#define | MXC_F_I2S_CTRL0CH0_RST_POS 19 |
|
#define | MXC_F_I2S_CTRL0CH0_RST ((uint32_t)(0x1UL << MXC_F_I2S_CTRL0CH0_RST_POS)) |
|
#define | MXC_F_I2S_CTRL0CH0_FIFO_LSB_POS 20 |
|
#define | MXC_F_I2S_CTRL0CH0_FIFO_LSB ((uint32_t)(0x1UL << MXC_F_I2S_CTRL0CH0_FIFO_LSB_POS)) |
|
#define | MXC_F_I2S_CTRL0CH0_RX_THD_VAL_POS 24 |
|
#define | MXC_F_I2S_CTRL0CH0_RX_THD_VAL ((uint32_t)(0xFFUL << MXC_F_I2S_CTRL0CH0_RX_THD_VAL_POS)) |
|
#define | MXC_F_I2S_CTRL1CH0_BITS_WORD_POS 0 |
|
#define | MXC_F_I2S_CTRL1CH0_BITS_WORD ((uint32_t)(0x1FUL << MXC_F_I2S_CTRL1CH0_BITS_WORD_POS)) |
|
#define | MXC_F_I2S_CTRL1CH0_EN_POS 8 |
|
#define | MXC_F_I2S_CTRL1CH0_EN ((uint32_t)(0x1UL << MXC_F_I2S_CTRL1CH0_EN_POS)) |
|
#define | MXC_F_I2S_CTRL1CH0_SMP_SIZE_POS 9 |
|
#define | MXC_F_I2S_CTRL1CH0_SMP_SIZE ((uint32_t)(0x1FUL << MXC_F_I2S_CTRL1CH0_SMP_SIZE_POS)) |
|
#define | MXC_F_I2S_CTRL1CH0_ADJST_POS 15 |
|
#define | MXC_F_I2S_CTRL1CH0_ADJST ((uint32_t)(0x1UL << MXC_F_I2S_CTRL1CH0_ADJST_POS)) |
|
#define | MXC_F_I2S_CTRL1CH0_CLKDIV_POS 16 |
|
#define | MXC_F_I2S_CTRL1CH0_CLKDIV ((uint32_t)(0xFFFFUL << MXC_F_I2S_CTRL1CH0_CLKDIV_POS)) |
|
#define | MXC_F_I2S_DMACH0_DMA_TX_THD_VAL_POS 0 |
|
#define | MXC_F_I2S_DMACH0_DMA_TX_THD_VAL ((uint32_t)(0x7FUL << MXC_F_I2S_DMACH0_DMA_TX_THD_VAL_POS)) |
|
#define | MXC_F_I2S_DMACH0_DMA_TX_EN_POS 7 |
|
#define | MXC_F_I2S_DMACH0_DMA_TX_EN ((uint32_t)(0x1UL << MXC_F_I2S_DMACH0_DMA_TX_EN_POS)) |
|
#define | MXC_F_I2S_DMACH0_DMA_RX_THD_VAL_POS 8 |
|
#define | MXC_F_I2S_DMACH0_DMA_RX_THD_VAL ((uint32_t)(0x7FUL << MXC_F_I2S_DMACH0_DMA_RX_THD_VAL_POS)) |
|
#define | MXC_F_I2S_DMACH0_DMA_RX_EN_POS 15 |
|
#define | MXC_F_I2S_DMACH0_DMA_RX_EN ((uint32_t)(0x1UL << MXC_F_I2S_DMACH0_DMA_RX_EN_POS)) |
|
#define | MXC_F_I2S_DMACH0_TX_LVL_POS 16 |
|
#define | MXC_F_I2S_DMACH0_TX_LVL ((uint32_t)(0xFFUL << MXC_F_I2S_DMACH0_TX_LVL_POS)) |
|
#define | MXC_F_I2S_DMACH0_RX_LVL_POS 24 |
|
#define | MXC_F_I2S_DMACH0_RX_LVL ((uint32_t)(0xFFUL << MXC_F_I2S_DMACH0_RX_LVL_POS)) |
|
#define | MXC_F_I2S_FIFOCH0_DATA_POS 0 |
|
#define | MXC_F_I2S_FIFOCH0_DATA ((uint32_t)(0xFFFFFFFFUL << MXC_F_I2S_FIFOCH0_DATA_POS)) |
|
#define | MXC_F_I2S_INTFL_RX_OV_CH0_POS 0 |
|
#define | MXC_F_I2S_INTFL_RX_OV_CH0 ((uint32_t)(0x1UL << MXC_F_I2S_INTFL_RX_OV_CH0_POS)) |
|
#define | MXC_F_I2S_INTFL_RX_THD_CH0_POS 1 |
|
#define | MXC_F_I2S_INTFL_RX_THD_CH0 ((uint32_t)(0x1UL << MXC_F_I2S_INTFL_RX_THD_CH0_POS)) |
|
#define | MXC_F_I2S_INTFL_TX_OB_CH0_POS 2 |
|
#define | MXC_F_I2S_INTFL_TX_OB_CH0 ((uint32_t)(0x1UL << MXC_F_I2S_INTFL_TX_OB_CH0_POS)) |
|
#define | MXC_F_I2S_INTFL_TX_HE_CH0_POS 3 |
|
#define | MXC_F_I2S_INTFL_TX_HE_CH0 ((uint32_t)(0x1UL << MXC_F_I2S_INTFL_TX_HE_CH0_POS)) |
|
#define | MXC_F_I2S_INTEN_RX_OV_CH0_POS 0 |
|
#define | MXC_F_I2S_INTEN_RX_OV_CH0 ((uint32_t)(0x1UL << MXC_F_I2S_INTEN_RX_OV_CH0_POS)) |
|
#define | MXC_F_I2S_INTEN_RX_THD_CH0_POS 1 |
|
#define | MXC_F_I2S_INTEN_RX_THD_CH0 ((uint32_t)(0x1UL << MXC_F_I2S_INTEN_RX_THD_CH0_POS)) |
|
#define | MXC_F_I2S_INTEN_TX_OB_CH0_POS 2 |
|
#define | MXC_F_I2S_INTEN_TX_OB_CH0 ((uint32_t)(0x1UL << MXC_F_I2S_INTEN_TX_OB_CH0_POS)) |
|
#define | MXC_F_I2S_INTEN_TX_HE_CH0_POS 3 |
|
#define | MXC_F_I2S_INTEN_TX_HE_CH0 ((uint32_t)(0x1UL << MXC_F_I2S_INTEN_TX_HE_CH0_POS)) |
|
#define | MXC_F_I2S_EXTSETUP_EXT_BITS_WORD_POS 0 |
|
#define | MXC_F_I2S_EXTSETUP_EXT_BITS_WORD ((uint32_t)(0x1FUL << MXC_F_I2S_EXTSETUP_EXT_BITS_WORD_POS)) |
|