|
| #define | MXC_R_AFE_ADC_ONE_PD ((uint32_t)0x00800001UL) |
| |
| #define | MXC_R_AFE_ADC_ONE_CONV_START ((uint32_t)0x00810001UL) |
| |
| #define | MXC_R_AFE_ADC_ONE_SEQ_START ((uint32_t)0x00820001UL) |
| |
| #define | MXC_R_AFE_ADC_ONE_CAL_START ((uint32_t)0x00830001UL) |
| |
| #define | MXC_R_AFE_ADC_ONE_GP0_CTRL ((uint32_t)0x00840001UL) |
| |
| #define | MXC_R_AFE_ADC_ONE_GP1_CTRL ((uint32_t)0x00850001UL) |
| |
| #define | MXC_R_AFE_ADC_ONE_GP_CONV ((uint32_t)0x00860001UL) |
| |
| #define | MXC_R_AFE_ADC_ONE_GP_SEQ_ADDR ((uint32_t)0x00870001UL) |
| |
| #define | MXC_R_AFE_ADC_ONE_FILTER ((uint32_t)0x00880001UL) |
| |
| #define | MXC_R_AFE_ADC_ONE_CTRL ((uint32_t)0x00890001UL) |
| |
| #define | MXC_R_AFE_ADC_ONE_SOURCE ((uint32_t)0x008A0001UL) |
| |
| #define | MXC_R_AFE_ADC_ONE_MUX_CTRL0 ((uint32_t)0x008B0001UL) |
| |
| #define | MXC_R_AFE_ADC_ONE_MUX_CTRL1 ((uint32_t)0x008C0001UL) |
| |
| #define | MXC_R_AFE_ADC_ONE_MUX_CTRL2 ((uint32_t)0x008D0001UL) |
| |
| #define | MXC_R_AFE_ADC_ONE_PGA ((uint32_t)0x008E0001UL) |
| |
| #define | MXC_R_AFE_ADC_ONE_WAIT_EXT ((uint32_t)0x008F0001UL) |
| |
| #define | MXC_R_AFE_ADC_ONE_WAIT_START ((uint32_t)0x00900001UL) |
| |
| #define | MXC_R_AFE_ADC_ONE_PART_ID ((uint32_t)0x00910003UL) |
| |
| #define | MXC_R_AFE_ADC_ONE_SYSC_SEL ((uint32_t)0x00920003UL) |
| |
| #define | MXC_R_AFE_ADC_ONE_SYS_OFF_A ((uint32_t)0x00930003UL) |
| |
| #define | MXC_R_AFE_ADC_ONE_SYS_OFF_B ((uint32_t)0x00940003UL) |
| |
| #define | MXC_R_AFE_ADC_ONE_SYS_GAIN_A ((uint32_t)0x00950003UL) |
| |
| #define | MXC_R_AFE_ADC_ONE_SYS_GAIN_B ((uint32_t)0x00960003UL) |
| |
| #define | MXC_R_AFE_ADC_ONE_SELF_OFF ((uint32_t)0x00970003UL) |
| |
| #define | MXC_R_AFE_ADC_ONE_SELF_GAIN_1 ((uint32_t)0x00980003UL) |
| |
| #define | MXC_R_AFE_ADC_ONE_SELF_GAIN_2 ((uint32_t)0x00990003UL) |
| |
| #define | MXC_R_AFE_ADC_ONE_SELF_GAIN_4 ((uint32_t)0x009A0003UL) |
| |
| #define | MXC_R_AFE_ADC_ONE_SELF_GAIN_8 ((uint32_t)0x009B0003UL) |
| |
| #define | MXC_R_AFE_ADC_ONE_SELF_GAIN_16 ((uint32_t)0x009C0003UL) |
| |
| #define | MXC_R_AFE_ADC_ONE_SELF_GAIN_32 ((uint32_t)0x009D0003UL) |
| |
| #define | MXC_R_AFE_ADC_ONE_SELF_GAIN_64 ((uint32_t)0x009E0003UL) |
| |
| #define | MXC_R_AFE_ADC_ONE_SELF_GAIN_128 ((uint32_t)0x009F0003UL) |
| |
| #define | MXC_R_AFE_ADC_ONE_LTHRESH0 ((uint32_t)0x00A00003UL) |
| |
| #define | MXC_R_AFE_ADC_ONE_LTHRESH1 ((uint32_t)0x00A10003UL) |
| |
| #define | MXC_R_AFE_ADC_ONE_LTHRESH2 ((uint32_t)0x00A20003UL) |
| |
| #define | MXC_R_AFE_ADC_ONE_LTHRESH3 ((uint32_t)0x00A30003UL) |
| |
| #define | MXC_R_AFE_ADC_ONE_LTHRESH4 ((uint32_t)0x00A40003UL) |
| |
| #define | MXC_R_AFE_ADC_ONE_LTHRESH5 ((uint32_t)0x00A50003UL) |
| |
| #define | MXC_R_AFE_ADC_ONE_LTHRESH6 ((uint32_t)0x00A60003UL) |
| |
| #define | MXC_R_AFE_ADC_ONE_LTHRESH7 ((uint32_t)0x00A70003UL) |
| |
| #define | MXC_R_AFE_ADC_ONE_UTHRESH0 ((uint32_t)0x00A80003UL) |
| |
| #define | MXC_R_AFE_ADC_ONE_UTHRESH1 ((uint32_t)0x00A90003UL) |
| |
| #define | MXC_R_AFE_ADC_ONE_UTHRESH2 ((uint32_t)0x00AA0003UL) |
| |
| #define | MXC_R_AFE_ADC_ONE_UTHRESH3 ((uint32_t)0x00AB0003UL) |
| |
| #define | MXC_R_AFE_ADC_ONE_UTHRESH4 ((uint32_t)0x00AC0003UL) |
| |
| #define | MXC_R_AFE_ADC_ONE_UTHRESH5 ((uint32_t)0x00AD0003UL) |
| |
| #define | MXC_R_AFE_ADC_ONE_UTHRESH6 ((uint32_t)0x00AE0003UL) |
| |
| #define | MXC_R_AFE_ADC_ONE_UTHRESH7 ((uint32_t)0x00AF0003UL) |
| |
| #define | MXC_R_AFE_ADC_ONE_DATA0 ((uint32_t)0x00B00003UL) |
| |
| #define | MXC_R_AFE_ADC_ONE_DATA1 ((uint32_t)0x00B10003UL) |
| |
| #define | MXC_R_AFE_ADC_ONE_DATA2 ((uint32_t)0x00B20003UL) |
| |
| #define | MXC_R_AFE_ADC_ONE_DATA3 ((uint32_t)0x00B30003UL) |
| |
| #define | MXC_R_AFE_ADC_ONE_DATA4 ((uint32_t)0x00B40003UL) |
| |
| #define | MXC_R_AFE_ADC_ONE_DATA5 ((uint32_t)0x00B50003UL) |
| |
| #define | MXC_R_AFE_ADC_ONE_DATA6 ((uint32_t)0x00B60003UL) |
| |
| #define | MXC_R_AFE_ADC_ONE_DATA7 ((uint32_t)0x00B70003UL) |
| |
| #define | MXC_R_AFE_ADC_ONE_STATUS ((uint32_t)0x00B80003UL) |
| |
| #define | MXC_R_AFE_ADC_ONE_STATUS_IE ((uint32_t)0x00B90003UL) |
| |
| #define | MXC_R_AFE_ADC_ONE_UC_0 ((uint32_t)0x00BA0002UL) |
| |
| #define | MXC_R_AFE_ADC_ONE_UC_1 ((uint32_t)0x00BB0002UL) |
| |
| #define | MXC_R_AFE_ADC_ONE_UC_2 ((uint32_t)0x00BC0002UL) |
| |
| #define | MXC_R_AFE_ADC_ONE_UC_3 ((uint32_t)0x00BD0002UL) |
| |
| #define | MXC_R_AFE_ADC_ONE_UC_4 ((uint32_t)0x00BE0002UL) |
| |
| #define | MXC_R_AFE_ADC_ONE_UC_5 ((uint32_t)0x00BF0002UL) |
| |
| #define | MXC_R_AFE_ADC_ONE_UC_6 ((uint32_t)0x00C00002UL) |
| |
| #define | MXC_R_AFE_ADC_ONE_UC_7 ((uint32_t)0x00C10002UL) |
| |
| #define | MXC_R_AFE_ADC_ONE_UC_8 ((uint32_t)0x00C20002UL) |
| |
| #define | MXC_R_AFE_ADC_ONE_UC_9 ((uint32_t)0x00C30002UL) |
| |
| #define | MXC_R_AFE_ADC_ONE_UC_10 ((uint32_t)0x00C40002UL) |
| |
| #define | MXC_R_AFE_ADC_ONE_UC_11 ((uint32_t)0x00C50002UL) |
| |
| #define | MXC_R_AFE_ADC_ONE_UC_12 ((uint32_t)0x00C60002UL) |
| |
| #define | MXC_R_AFE_ADC_ONE_UC_13 ((uint32_t)0x00C70002UL) |
| |
| #define | MXC_R_AFE_ADC_ONE_UC_14 ((uint32_t)0x00C80002UL) |
| |
| #define | MXC_R_AFE_ADC_ONE_UC_15 ((uint32_t)0x00C90002UL) |
| |
| #define | MXC_R_AFE_ADC_ONE_UC_16 ((uint32_t)0x00CA0002UL) |
| |
| #define | MXC_R_AFE_ADC_ONE_UC_17 ((uint32_t)0x00CB0002UL) |
| |
| #define | MXC_R_AFE_ADC_ONE_UC_18 ((uint32_t)0x00CC0002UL) |
| |
| #define | MXC_R_AFE_ADC_ONE_UC_19 ((uint32_t)0x00CD0002UL) |
| |
| #define | MXC_R_AFE_ADC_ONE_UC_20 ((uint32_t)0x00CE0002UL) |
| |
| #define | MXC_R_AFE_ADC_ONE_UC_21 ((uint32_t)0x00CF0002UL) |
| |
| #define | MXC_R_AFE_ADC_ONE_UC_22 ((uint32_t)0x00D00002UL) |
| |
| #define | MXC_R_AFE_ADC_ONE_UC_23 ((uint32_t)0x00D10002UL) |
| |
| #define | MXC_R_AFE_ADC_ONE_UC_24 ((uint32_t)0x00D20002UL) |
| |
| #define | MXC_R_AFE_ADC_ONE_UC_25 ((uint32_t)0x00D30002UL) |
| |
| #define | MXC_R_AFE_ADC_ONE_UC_26 ((uint32_t)0x00D40002UL) |
| |
| #define | MXC_R_AFE_ADC_ONE_UC_27 ((uint32_t)0x00D50002UL) |
| |
| #define | MXC_R_AFE_ADC_ONE_UC_28 ((uint32_t)0x00D60002UL) |
| |
| #define | MXC_R_AFE_ADC_ONE_UC_29 ((uint32_t)0x00D70002UL) |
| |
| #define | MXC_R_AFE_ADC_ONE_UC_30 ((uint32_t)0x00D80002UL) |
| |
| #define | MXC_R_AFE_ADC_ONE_UC_31 ((uint32_t)0x00D90002UL) |
| |
| #define | MXC_R_AFE_ADC_ONE_UC_32 ((uint32_t)0x00DA0002UL) |
| |
| #define | MXC_R_AFE_ADC_ONE_UC_33 ((uint32_t)0x00DB0002UL) |
| |
| #define | MXC_R_AFE_ADC_ONE_UC_34 ((uint32_t)0x00DC0002UL) |
| |
| #define | MXC_R_AFE_ADC_ONE_UC_35 ((uint32_t)0x00DD0002UL) |
| |
| #define | MXC_R_AFE_ADC_ONE_UC_36 ((uint32_t)0x00DE0002UL) |
| |
| #define | MXC_R_AFE_ADC_ONE_UC_37 ((uint32_t)0x00DF0002UL) |
| |
| #define | MXC_R_AFE_ADC_ONE_UC_38 ((uint32_t)0x00E00002UL) |
| |
| #define | MXC_R_AFE_ADC_ONE_UC_39 ((uint32_t)0x00E10002UL) |
| |
| #define | MXC_R_AFE_ADC_ONE_UC_40 ((uint32_t)0x00E20002UL) |
| |
| #define | MXC_R_AFE_ADC_ONE_UC_41 ((uint32_t)0x00E30002UL) |
| |
| #define | MXC_R_AFE_ADC_ONE_UC_42 ((uint32_t)0x00E40002UL) |
| |
| #define | MXC_R_AFE_ADC_ONE_UC_43 ((uint32_t)0x00E50002UL) |
| |
| #define | MXC_R_AFE_ADC_ONE_UC_44 ((uint32_t)0x00E60002UL) |
| |
| #define | MXC_R_AFE_ADC_ONE_UC_45 ((uint32_t)0x00E70002UL) |
| |
| #define | MXC_R_AFE_ADC_ONE_UC_46 ((uint32_t)0x00E80002UL) |
| |
| #define | MXC_R_AFE_ADC_ONE_UC_47 ((uint32_t)0x00E90002UL) |
| |
| #define | MXC_R_AFE_ADC_ONE_UC_48 ((uint32_t)0x00EA0002UL) |
| |
| #define | MXC_R_AFE_ADC_ONE_UC_49 ((uint32_t)0x00EB0002UL) |
| |
| #define | MXC_R_AFE_ADC_ONE_UC_50 ((uint32_t)0x00EC0002UL) |
| |
| #define | MXC_R_AFE_ADC_ONE_UC_51 ((uint32_t)0x00ED0002UL) |
| |
| #define | MXC_R_AFE_ADC_ONE_UC_52 ((uint32_t)0x00EE0002UL) |
| |
| #define | MXC_R_AFE_ADC_ONE_UCADDR ((uint32_t)0x00EF0001UL) |
| |
| #define | MXC_R_AFE_ADC_ONE_FT_PWORD ((uint32_t)0x00F00001UL) |
| |
| #define | MXC_R_AFE_ADC_ONE_ADC_TRIM0 ((uint32_t)0x00F70003UL) |
| |
| #define | MXC_R_AFE_ADC_ONE_ADC_TRIM1 ((uint32_t)0x00F80002UL) |
| |
| #define | MXC_R_AFE_ADC_ONE_ANA_TRIM ((uint32_t)0x00F90002UL) |
| |
| #define | MXC_R_AFE_ADC_ONE_SYS_CTRL ((uint32_t)0x00FA0001UL) |
| |
| #define | MXC_F_AFE_ADC_ONE_PD_PD_POS 0 |
| |
| #define | MXC_F_AFE_ADC_ONE_PD_PD ((uint8_t)(0x3UL << MXC_F_AFE_ADC_ONE_PD_PD_POS)) |
| |
| #define | MXC_V_AFE_ADC_ONE_PD_PD_NORMAL_MODE ((uint8_t)0x0UL) |
| |
| #define | MXC_S_AFE_ADC_ONE_PD_PD_NORMAL_MODE (MXC_V_AFE_ADC_ONE_PD_PD_NORMAL_MODE << MXC_F_AFE_ADC_ONE_PD_PD_POS) |
| |
| #define | MXC_V_AFE_ADC_ONE_PD_PD_STANDBY_MODE ((uint8_t)0x1UL) |
| |
| #define | MXC_S_AFE_ADC_ONE_PD_PD_STANDBY_MODE (MXC_V_AFE_ADC_ONE_PD_PD_STANDBY_MODE << MXC_F_AFE_ADC_ONE_PD_PD_POS) |
| |
| #define | MXC_V_AFE_ADC_ONE_PD_PD_SLEEP_MODE ((uint8_t)0x2UL) |
| |
| #define | MXC_S_AFE_ADC_ONE_PD_PD_SLEEP_MODE (MXC_V_AFE_ADC_ONE_PD_PD_SLEEP_MODE << MXC_F_AFE_ADC_ONE_PD_PD_POS) |
| |
| #define | MXC_V_AFE_ADC_ONE_PD_PD_RESET ((uint8_t)0x3UL) |
| |
| #define | MXC_S_AFE_ADC_ONE_PD_PD_RESET (MXC_V_AFE_ADC_ONE_PD_PD_RESET << MXC_F_AFE_ADC_ONE_PD_PD_POS) |
| |
| #define | MXC_F_AFE_ADC_ONE_CONV_START_CONV_TYPE_POS 0 |
| |
| #define | MXC_F_AFE_ADC_ONE_CONV_START_CONV_TYPE ((uint8_t)(0x3UL << MXC_F_AFE_ADC_ONE_CONV_START_CONV_TYPE_POS)) |
| |
| #define | MXC_V_AFE_ADC_ONE_CONV_START_CONV_TYPE_SINGLE ((uint8_t)0x0UL) |
| |
| #define | MXC_S_AFE_ADC_ONE_CONV_START_CONV_TYPE_SINGLE (MXC_V_AFE_ADC_ONE_CONV_START_CONV_TYPE_SINGLE << MXC_F_AFE_ADC_ONE_CONV_START_CONV_TYPE_POS) |
| |
| #define | MXC_V_AFE_ADC_ONE_CONV_START_CONV_TYPE_CONTINUOUS ((uint8_t)0x1UL) |
| |
| #define | MXC_S_AFE_ADC_ONE_CONV_START_CONV_TYPE_CONTINUOUS (MXC_V_AFE_ADC_ONE_CONV_START_CONV_TYPE_CONTINUOUS << MXC_F_AFE_ADC_ONE_CONV_START_CONV_TYPE_POS) |
| |
| #define | MXC_V_AFE_ADC_ONE_CONV_START_CONV_TYPE_DUTY_CYCLED_1_TO_4 ((uint8_t)0x2UL) |
| |
| #define | MXC_S_AFE_ADC_ONE_CONV_START_CONV_TYPE_DUTY_CYCLED_1_TO_4 (MXC_V_AFE_ADC_ONE_CONV_START_CONV_TYPE_DUTY_CYCLED_1_TO_4 << MXC_F_AFE_ADC_ONE_CONV_START_CONV_TYPE_POS) |
| |
| #define | MXC_F_AFE_ADC_ONE_CONV_START_DEST_POS 4 |
| |
| #define | MXC_F_AFE_ADC_ONE_CONV_START_DEST ((uint8_t)(0x7UL << MXC_F_AFE_ADC_ONE_CONV_START_DEST_POS)) |
| |
| #define | MXC_F_AFE_ADC_ONE_SEQ_START_SEQ_ADDRESS_POS 0 |
| |
| #define | MXC_F_AFE_ADC_ONE_SEQ_START_SEQ_ADDRESS ((uint8_t)(0xFFUL << MXC_F_AFE_ADC_ONE_SEQ_START_SEQ_ADDRESS_POS)) |
| |
| #define | MXC_F_AFE_ADC_ONE_CAL_START_CAL_TYPE_POS 0 |
| |
| #define | MXC_F_AFE_ADC_ONE_CAL_START_CAL_TYPE ((uint8_t)(0x7UL << MXC_F_AFE_ADC_ONE_CAL_START_CAL_TYPE_POS)) |
| |
| #define | MXC_F_AFE_ADC_ONE_GP0_CTRL_GP0_OSEL_POS 0 |
| |
| #define | MXC_F_AFE_ADC_ONE_GP0_CTRL_GP0_OSEL ((uint8_t)(0x7UL << MXC_F_AFE_ADC_ONE_GP0_CTRL_GP0_OSEL_POS)) |
| |
| #define | MXC_F_AFE_ADC_ONE_GP0_CTRL_GP0_ISEL_POS 4 |
| |
| #define | MXC_F_AFE_ADC_ONE_GP0_CTRL_GP0_ISEL ((uint8_t)(0x3UL << MXC_F_AFE_ADC_ONE_GP0_CTRL_GP0_ISEL_POS)) |
| |
| #define | MXC_F_AFE_ADC_ONE_GP0_CTRL_GP0_DIR_POS 6 |
| |
| #define | MXC_F_AFE_ADC_ONE_GP0_CTRL_GP0_DIR ((uint8_t)(0x3UL << MXC_F_AFE_ADC_ONE_GP0_CTRL_GP0_DIR_POS)) |
| |
| #define | MXC_F_AFE_ADC_ONE_GP1_CTRL_GP1_OSEL_POS 0 |
| |
| #define | MXC_F_AFE_ADC_ONE_GP1_CTRL_GP1_OSEL ((uint8_t)(0x7UL << MXC_F_AFE_ADC_ONE_GP1_CTRL_GP1_OSEL_POS)) |
| |
| #define | MXC_F_AFE_ADC_ONE_GP1_CTRL_GP1_ISEL_POS 4 |
| |
| #define | MXC_F_AFE_ADC_ONE_GP1_CTRL_GP1_ISEL ((uint8_t)(0x3UL << MXC_F_AFE_ADC_ONE_GP1_CTRL_GP1_ISEL_POS)) |
| |
| #define | MXC_F_AFE_ADC_ONE_GP1_CTRL_GP1_DIR_POS 6 |
| |
| #define | MXC_F_AFE_ADC_ONE_GP1_CTRL_GP1_DIR ((uint8_t)(0x3UL << MXC_F_AFE_ADC_ONE_GP1_CTRL_GP1_DIR_POS)) |
| |
| #define | MXC_F_AFE_ADC_ONE_GP_CONV_GP_CONV_TYPE_POS 0 |
| |
| #define | MXC_F_AFE_ADC_ONE_GP_CONV_GP_CONV_TYPE ((uint8_t)(0x3UL << MXC_F_AFE_ADC_ONE_GP_CONV_GP_CONV_TYPE_POS)) |
| |
| #define | MXC_V_AFE_ADC_ONE_GP_CONV_GP_CONV_TYPE_SINGLE ((uint8_t)0x0UL) |
| |
| #define | MXC_S_AFE_ADC_ONE_GP_CONV_GP_CONV_TYPE_SINGLE (MXC_V_AFE_ADC_ONE_GP_CONV_GP_CONV_TYPE_SINGLE << MXC_F_AFE_ADC_ONE_GP_CONV_GP_CONV_TYPE_POS) |
| |
| #define | MXC_V_AFE_ADC_ONE_GP_CONV_GP_CONV_TYPE_CONTINUOUS ((uint8_t)0x1UL) |
| |
| #define | MXC_S_AFE_ADC_ONE_GP_CONV_GP_CONV_TYPE_CONTINUOUS (MXC_V_AFE_ADC_ONE_GP_CONV_GP_CONV_TYPE_CONTINUOUS << MXC_F_AFE_ADC_ONE_GP_CONV_GP_CONV_TYPE_POS) |
| |
| #define | MXC_V_AFE_ADC_ONE_GP_CONV_GP_CONV_TYPE_DUTY_CYCLED_1_TO_4 ((uint8_t)0x2UL) |
| |
| #define | MXC_S_AFE_ADC_ONE_GP_CONV_GP_CONV_TYPE_DUTY_CYCLED_1_TO_4 (MXC_V_AFE_ADC_ONE_GP_CONV_GP_CONV_TYPE_DUTY_CYCLED_1_TO_4 << MXC_F_AFE_ADC_ONE_GP_CONV_GP_CONV_TYPE_POS) |
| |
| #define | MXC_F_AFE_ADC_ONE_GP_CONV_GP_DEST_POS 4 |
| |
| #define | MXC_F_AFE_ADC_ONE_GP_CONV_GP_DEST ((uint8_t)(0x7UL << MXC_F_AFE_ADC_ONE_GP_CONV_GP_DEST_POS)) |
| |
| #define | MXC_F_AFE_ADC_ONE_GP_SEQ_ADDR_GP_SEQ_ADDR_POS 0 |
| |
| #define | MXC_F_AFE_ADC_ONE_GP_SEQ_ADDR_GP_SEQ_ADDR ((uint8_t)(0x7FUL << MXC_F_AFE_ADC_ONE_GP_SEQ_ADDR_GP_SEQ_ADDR_POS)) |
| |
| #define | MXC_F_AFE_ADC_ONE_FILTER_RATE_POS 0 |
| |
| #define | MXC_F_AFE_ADC_ONE_FILTER_RATE ((uint8_t)(0xFUL << MXC_F_AFE_ADC_ONE_FILTER_RATE_POS)) |
| |
| #define | MXC_F_AFE_ADC_ONE_FILTER_LINEF_POS 4 |
| |
| #define | MXC_F_AFE_ADC_ONE_FILTER_LINEF ((uint8_t)(0x3UL << MXC_F_AFE_ADC_ONE_FILTER_LINEF_POS)) |
| |
| #define | MXC_V_AFE_ADC_ONE_FILTER_LINEF_SIMULTANEOUS_FIR_REJECT_50HZ_AND_60HZ ((uint8_t)0x0UL) |
| |
| #define | MXC_S_AFE_ADC_ONE_FILTER_LINEF_SIMULTANEOUS_FIR_REJECT_50HZ_AND_60HZ (MXC_V_AFE_ADC_ONE_FILTER_LINEF_SIMULTANEOUS_FIR_REJECT_50HZ_AND_60HZ << MXC_F_AFE_ADC_ONE_FILTER_LINEF_POS) |
| |
| #define | MXC_V_AFE_ADC_ONE_FILTER_LINEF_FIR_REJECT_50HZ ((uint8_t)0x1UL) |
| |
| #define | MXC_S_AFE_ADC_ONE_FILTER_LINEF_FIR_REJECT_50HZ (MXC_V_AFE_ADC_ONE_FILTER_LINEF_FIR_REJECT_50HZ << MXC_F_AFE_ADC_ONE_FILTER_LINEF_POS) |
| |
| #define | MXC_V_AFE_ADC_ONE_FILTER_LINEF_FIR_REJECT_60HZ ((uint8_t)0x2UL) |
| |
| #define | MXC_S_AFE_ADC_ONE_FILTER_LINEF_FIR_REJECT_60HZ (MXC_V_AFE_ADC_ONE_FILTER_LINEF_FIR_REJECT_60HZ << MXC_F_AFE_ADC_ONE_FILTER_LINEF_POS) |
| |
| #define | MXC_V_AFE_ADC_ONE_FILTER_LINEF_SINC4 ((uint8_t)0x3UL) |
| |
| #define | MXC_S_AFE_ADC_ONE_FILTER_LINEF_SINC4 (MXC_V_AFE_ADC_ONE_FILTER_LINEF_SINC4 << MXC_F_AFE_ADC_ONE_FILTER_LINEF_POS) |
| |
| #define | MXC_F_AFE_ADC_ONE_CTRL_REF_SEL_POS 0 |
| |
| #define | MXC_F_AFE_ADC_ONE_CTRL_REF_SEL ((uint8_t)(0x7UL << MXC_F_AFE_ADC_ONE_CTRL_REF_SEL_POS)) |
| |
| #define | MXC_V_AFE_ADC_ONE_CTRL_REF_SEL_AIN0P_AND_AIN1N ((uint8_t)0x0UL) |
| |
| #define | MXC_S_AFE_ADC_ONE_CTRL_REF_SEL_AIN0P_AND_AIN1N (MXC_V_AFE_ADC_ONE_CTRL_REF_SEL_AIN0P_AND_AIN1N << MXC_F_AFE_ADC_ONE_CTRL_REF_SEL_POS) |
| |
| #define | MXC_V_AFE_ADC_ONE_CTRL_REF_SEL_REF1P_AND_REF1N ((uint8_t)0x1UL) |
| |
| #define | MXC_S_AFE_ADC_ONE_CTRL_REF_SEL_REF1P_AND_REF1N (MXC_V_AFE_ADC_ONE_CTRL_REF_SEL_REF1P_AND_REF1N << MXC_F_AFE_ADC_ONE_CTRL_REF_SEL_POS) |
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| #define | MXC_V_AFE_ADC_ONE_CTRL_REF_SEL_REF0P_AND_REF0N ((uint8_t)0x2UL) |
| |
| #define | MXC_S_AFE_ADC_ONE_CTRL_REF_SEL_REF0P_AND_REF0N (MXC_V_AFE_ADC_ONE_CTRL_REF_SEL_REF0P_AND_REF0N << MXC_F_AFE_ADC_ONE_CTRL_REF_SEL_POS) |
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| #define | MXC_V_AFE_ADC_ONE_CTRL_REF_SEL_AVDD_AND_AGND ((uint8_t)0x3UL) |
| |
| #define | MXC_S_AFE_ADC_ONE_CTRL_REF_SEL_AVDD_AND_AGND (MXC_V_AFE_ADC_ONE_CTRL_REF_SEL_AVDD_AND_AGND << MXC_F_AFE_ADC_ONE_CTRL_REF_SEL_POS) |
| |
| #define | MXC_V_AFE_ADC_ONE_CTRL_REF_SEL_AIN0P_AND_AGND ((uint8_t)0x4UL) |
| |
| #define | MXC_S_AFE_ADC_ONE_CTRL_REF_SEL_AIN0P_AND_AGND (MXC_V_AFE_ADC_ONE_CTRL_REF_SEL_AIN0P_AND_AGND << MXC_F_AFE_ADC_ONE_CTRL_REF_SEL_POS) |
| |
| #define | MXC_V_AFE_ADC_ONE_CTRL_REF_SEL_REF1P_AND_AGND ((uint8_t)0x5UL) |
| |
| #define | MXC_S_AFE_ADC_ONE_CTRL_REF_SEL_REF1P_AND_AGND (MXC_V_AFE_ADC_ONE_CTRL_REF_SEL_REF1P_AND_AGND << MXC_F_AFE_ADC_ONE_CTRL_REF_SEL_POS) |
| |
| #define | MXC_V_AFE_ADC_ONE_CTRL_REF_SEL_REF0P_AND_AGND ((uint8_t)0x6UL) |
| |
| #define | MXC_S_AFE_ADC_ONE_CTRL_REF_SEL_REF0P_AND_AGND (MXC_V_AFE_ADC_ONE_CTRL_REF_SEL_REF0P_AND_AGND << MXC_F_AFE_ADC_ONE_CTRL_REF_SEL_POS) |
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| #define | MXC_F_AFE_ADC_ONE_CTRL_REFBUFN_EN_POS 3 |
| |
| #define | MXC_F_AFE_ADC_ONE_CTRL_REFBUFN_EN ((uint8_t)(0x1UL << MXC_F_AFE_ADC_ONE_CTRL_REFBUFN_EN_POS)) |
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| #define | MXC_F_AFE_ADC_ONE_CTRL_REFBUFP_EN_POS 4 |
| |
| #define | MXC_F_AFE_ADC_ONE_CTRL_REFBUFP_EN ((uint8_t)(0x1UL << MXC_F_AFE_ADC_ONE_CTRL_REFBUFP_EN_POS)) |
| |
| #define | MXC_F_AFE_ADC_ONE_CTRL_FORMAT_POS 5 |
| |
| #define | MXC_F_AFE_ADC_ONE_CTRL_FORMAT ((uint8_t)(0x1UL << MXC_F_AFE_ADC_ONE_CTRL_FORMAT_POS)) |
| |
| #define | MXC_F_AFE_ADC_ONE_CTRL_U_BN_POS 6 |
| |
| #define | MXC_F_AFE_ADC_ONE_CTRL_U_BN ((uint8_t)(0x1UL << MXC_F_AFE_ADC_ONE_CTRL_U_BN_POS)) |
| |
| #define | MXC_F_AFE_ADC_ONE_CTRL_EXTCLK_POS 7 |
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| #define | MXC_F_AFE_ADC_ONE_CTRL_EXTCLK ((uint8_t)(0x1UL << MXC_F_AFE_ADC_ONE_CTRL_EXTCLK_POS)) |
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| #define | MXC_F_AFE_ADC_ONE_SOURCE_IDAC_MODE_POS 0 |
| |
| #define | MXC_F_AFE_ADC_ONE_SOURCE_IDAC_MODE ((uint8_t)(0xFUL << MXC_F_AFE_ADC_ONE_SOURCE_IDAC_MODE_POS)) |
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| #define | MXC_V_AFE_ADC_ONE_SOURCE_IDAC_MODE_CUR_10UA ((uint8_t)0x0UL) |
| |
| #define | MXC_S_AFE_ADC_ONE_SOURCE_IDAC_MODE_CUR_10UA (MXC_V_AFE_ADC_ONE_SOURCE_IDAC_MODE_CUR_10UA << MXC_F_AFE_ADC_ONE_SOURCE_IDAC_MODE_POS) |
| |
| #define | MXC_V_AFE_ADC_ONE_SOURCE_IDAC_MODE_CUR_50UA ((uint8_t)0x1UL) |
| |
| #define | MXC_S_AFE_ADC_ONE_SOURCE_IDAC_MODE_CUR_50UA (MXC_V_AFE_ADC_ONE_SOURCE_IDAC_MODE_CUR_50UA << MXC_F_AFE_ADC_ONE_SOURCE_IDAC_MODE_POS) |
| |
| #define | MXC_V_AFE_ADC_ONE_SOURCE_IDAC_MODE_CUR_75UA ((uint8_t)0x2UL) |
| |
| #define | MXC_S_AFE_ADC_ONE_SOURCE_IDAC_MODE_CUR_75UA (MXC_V_AFE_ADC_ONE_SOURCE_IDAC_MODE_CUR_75UA << MXC_F_AFE_ADC_ONE_SOURCE_IDAC_MODE_POS) |
| |
| #define | MXC_V_AFE_ADC_ONE_SOURCE_IDAC_MODE_CUR_100UA ((uint8_t)0x3UL) |
| |
| #define | MXC_S_AFE_ADC_ONE_SOURCE_IDAC_MODE_CUR_100UA (MXC_V_AFE_ADC_ONE_SOURCE_IDAC_MODE_CUR_100UA << MXC_F_AFE_ADC_ONE_SOURCE_IDAC_MODE_POS) |
| |
| #define | MXC_V_AFE_ADC_ONE_SOURCE_IDAC_MODE_CUR_125UA ((uint8_t)0x4UL) |
| |
| #define | MXC_S_AFE_ADC_ONE_SOURCE_IDAC_MODE_CUR_125UA (MXC_V_AFE_ADC_ONE_SOURCE_IDAC_MODE_CUR_125UA << MXC_F_AFE_ADC_ONE_SOURCE_IDAC_MODE_POS) |
| |
| #define | MXC_V_AFE_ADC_ONE_SOURCE_IDAC_MODE_CUR_150UA ((uint8_t)0x5UL) |
| |
| #define | MXC_S_AFE_ADC_ONE_SOURCE_IDAC_MODE_CUR_150UA (MXC_V_AFE_ADC_ONE_SOURCE_IDAC_MODE_CUR_150UA << MXC_F_AFE_ADC_ONE_SOURCE_IDAC_MODE_POS) |
| |
| #define | MXC_V_AFE_ADC_ONE_SOURCE_IDAC_MODE_CUR_175UA ((uint8_t)0x6UL) |
| |
| #define | MXC_S_AFE_ADC_ONE_SOURCE_IDAC_MODE_CUR_175UA (MXC_V_AFE_ADC_ONE_SOURCE_IDAC_MODE_CUR_175UA << MXC_F_AFE_ADC_ONE_SOURCE_IDAC_MODE_POS) |
| |
| #define | MXC_V_AFE_ADC_ONE_SOURCE_IDAC_MODE_CUR_200UA ((uint8_t)0x7UL) |
| |
| #define | MXC_S_AFE_ADC_ONE_SOURCE_IDAC_MODE_CUR_200UA (MXC_V_AFE_ADC_ONE_SOURCE_IDAC_MODE_CUR_200UA << MXC_F_AFE_ADC_ONE_SOURCE_IDAC_MODE_POS) |
| |
| #define | MXC_V_AFE_ADC_ONE_SOURCE_IDAC_MODE_CUR_225UA ((uint8_t)0x8UL) |
| |
| #define | MXC_S_AFE_ADC_ONE_SOURCE_IDAC_MODE_CUR_225UA (MXC_V_AFE_ADC_ONE_SOURCE_IDAC_MODE_CUR_225UA << MXC_F_AFE_ADC_ONE_SOURCE_IDAC_MODE_POS) |
| |
| #define | MXC_V_AFE_ADC_ONE_SOURCE_IDAC_MODE_CUR_250UA ((uint8_t)0x9UL) |
| |
| #define | MXC_S_AFE_ADC_ONE_SOURCE_IDAC_MODE_CUR_250UA (MXC_V_AFE_ADC_ONE_SOURCE_IDAC_MODE_CUR_250UA << MXC_F_AFE_ADC_ONE_SOURCE_IDAC_MODE_POS) |
| |
| #define | MXC_V_AFE_ADC_ONE_SOURCE_IDAC_MODE_CUR_300UA ((uint8_t)0xAUL) |
| |
| #define | MXC_S_AFE_ADC_ONE_SOURCE_IDAC_MODE_CUR_300UA (MXC_V_AFE_ADC_ONE_SOURCE_IDAC_MODE_CUR_300UA << MXC_F_AFE_ADC_ONE_SOURCE_IDAC_MODE_POS) |
| |
| #define | MXC_V_AFE_ADC_ONE_SOURCE_IDAC_MODE_CUR_400UA ((uint8_t)0xBUL) |
| |
| #define | MXC_S_AFE_ADC_ONE_SOURCE_IDAC_MODE_CUR_400UA (MXC_V_AFE_ADC_ONE_SOURCE_IDAC_MODE_CUR_400UA << MXC_F_AFE_ADC_ONE_SOURCE_IDAC_MODE_POS) |
| |
| #define | MXC_V_AFE_ADC_ONE_SOURCE_IDAC_MODE_CUR_600UA ((uint8_t)0xCUL) |
| |
| #define | MXC_S_AFE_ADC_ONE_SOURCE_IDAC_MODE_CUR_600UA (MXC_V_AFE_ADC_ONE_SOURCE_IDAC_MODE_CUR_600UA << MXC_F_AFE_ADC_ONE_SOURCE_IDAC_MODE_POS) |
| |
| #define | MXC_V_AFE_ADC_ONE_SOURCE_IDAC_MODE_CUR_800UA ((uint8_t)0xDUL) |
| |
| #define | MXC_S_AFE_ADC_ONE_SOURCE_IDAC_MODE_CUR_800UA (MXC_V_AFE_ADC_ONE_SOURCE_IDAC_MODE_CUR_800UA << MXC_F_AFE_ADC_ONE_SOURCE_IDAC_MODE_POS) |
| |
| #define | MXC_V_AFE_ADC_ONE_SOURCE_IDAC_MODE_CUR_1200UA ((uint8_t)0xEUL) |
| |
| #define | MXC_S_AFE_ADC_ONE_SOURCE_IDAC_MODE_CUR_1200UA (MXC_V_AFE_ADC_ONE_SOURCE_IDAC_MODE_CUR_1200UA << MXC_F_AFE_ADC_ONE_SOURCE_IDAC_MODE_POS) |
| |
| #define | MXC_V_AFE_ADC_ONE_SOURCE_IDAC_MODE_CUR_1600UA ((uint8_t)0xFUL) |
| |
| #define | MXC_S_AFE_ADC_ONE_SOURCE_IDAC_MODE_CUR_1600UA (MXC_V_AFE_ADC_ONE_SOURCE_IDAC_MODE_CUR_1600UA << MXC_F_AFE_ADC_ONE_SOURCE_IDAC_MODE_POS) |
| |
| #define | MXC_F_AFE_ADC_ONE_SOURCE_BRN_MODE_POS 4 |
| |
| #define | MXC_F_AFE_ADC_ONE_SOURCE_BRN_MODE ((uint8_t)(0x3UL << MXC_F_AFE_ADC_ONE_SOURCE_BRN_MODE_POS)) |
| |
| #define | MXC_V_AFE_ADC_ONE_SOURCE_BRN_MODE_POW_DOWN_CUR_SRC_DISABLED ((uint8_t)0x0UL) |
| |
| #define | MXC_S_AFE_ADC_ONE_SOURCE_BRN_MODE_POW_DOWN_CUR_SRC_DISABLED (MXC_V_AFE_ADC_ONE_SOURCE_BRN_MODE_POW_DOWN_CUR_SRC_DISABLED << MXC_F_AFE_ADC_ONE_SOURCE_BRN_MODE_POS) |
| |
| #define | MXC_V_AFE_ADC_ONE_SOURCE_BRN_MODE_CUR_SRC_0_5UA ((uint8_t)0x1UL) |
| |
| #define | MXC_S_AFE_ADC_ONE_SOURCE_BRN_MODE_CUR_SRC_0_5UA (MXC_V_AFE_ADC_ONE_SOURCE_BRN_MODE_CUR_SRC_0_5UA << MXC_F_AFE_ADC_ONE_SOURCE_BRN_MODE_POS) |
| |
| #define | MXC_V_AFE_ADC_ONE_SOURCE_BRN_MODE_CUR_SRC_1UA ((uint8_t)0x2UL) |
| |
| #define | MXC_S_AFE_ADC_ONE_SOURCE_BRN_MODE_CUR_SRC_1UA (MXC_V_AFE_ADC_ONE_SOURCE_BRN_MODE_CUR_SRC_1UA << MXC_F_AFE_ADC_ONE_SOURCE_BRN_MODE_POS) |
| |
| #define | MXC_V_AFE_ADC_ONE_SOURCE_BRN_MODE_CUR_SRC_10_UA ((uint8_t)0x3UL) |
| |
| #define | MXC_S_AFE_ADC_ONE_SOURCE_BRN_MODE_CUR_SRC_10_UA (MXC_V_AFE_ADC_ONE_SOURCE_BRN_MODE_CUR_SRC_10_UA << MXC_F_AFE_ADC_ONE_SOURCE_BRN_MODE_POS) |
| |
| #define | MXC_F_AFE_ADC_ONE_SOURCE_VBIAS_MODE_POS 6 |
| |
| #define | MXC_F_AFE_ADC_ONE_SOURCE_VBIAS_MODE ((uint8_t)(0x3UL << MXC_F_AFE_ADC_ONE_SOURCE_VBIAS_MODE_POS)) |
| |
| #define | MXC_V_AFE_ADC_ONE_SOURCE_VBIAS_MODE_ACTIVE_MODE ((uint8_t)0x0UL) |
| |
| #define | MXC_S_AFE_ADC_ONE_SOURCE_VBIAS_MODE_ACTIVE_MODE (MXC_V_AFE_ADC_ONE_SOURCE_VBIAS_MODE_ACTIVE_MODE << MXC_F_AFE_ADC_ONE_SOURCE_VBIAS_MODE_POS) |
| |
| #define | MXC_V_AFE_ADC_ONE_SOURCE_VBIAS_MODE_OUTPUT_IMPEDANCE_125K_OHM ((uint8_t)0x1UL) |
| |
| #define | MXC_S_AFE_ADC_ONE_SOURCE_VBIAS_MODE_OUTPUT_IMPEDANCE_125K_OHM (MXC_V_AFE_ADC_ONE_SOURCE_VBIAS_MODE_OUTPUT_IMPEDANCE_125K_OHM << MXC_F_AFE_ADC_ONE_SOURCE_VBIAS_MODE_POS) |
| |
| #define | MXC_V_AFE_ADC_ONE_SOURCE_VBIAS_MODE_OUTPUT_IMPEDANCE_20K_OHM ((uint8_t)0x2UL) |
| |
| #define | MXC_S_AFE_ADC_ONE_SOURCE_VBIAS_MODE_OUTPUT_IMPEDANCE_20K_OHM (MXC_V_AFE_ADC_ONE_SOURCE_VBIAS_MODE_OUTPUT_IMPEDANCE_20K_OHM << MXC_F_AFE_ADC_ONE_SOURCE_VBIAS_MODE_POS) |
| |
| #define | MXC_F_AFE_ADC_ONE_MUX_CTRL0_AINN_SEL_POS 0 |
| |
| #define | MXC_F_AFE_ADC_ONE_MUX_CTRL0_AINN_SEL ((uint8_t)(0xFUL << MXC_F_AFE_ADC_ONE_MUX_CTRL0_AINN_SEL_POS)) |
| |
| #define | MXC_F_AFE_ADC_ONE_MUX_CTRL0_AINP_SEL_POS 4 |
| |
| #define | MXC_F_AFE_ADC_ONE_MUX_CTRL0_AINP_SEL ((uint8_t)(0xFUL << MXC_F_AFE_ADC_ONE_MUX_CTRL0_AINP_SEL_POS)) |
| |
| #define | MXC_F_AFE_ADC_ONE_MUX_CTRL1_IDAC0_SEL_POS 0 |
| |
| #define | MXC_F_AFE_ADC_ONE_MUX_CTRL1_IDAC0_SEL ((uint8_t)(0xFUL << MXC_F_AFE_ADC_ONE_MUX_CTRL1_IDAC0_SEL_POS)) |
| |
| #define | MXC_F_AFE_ADC_ONE_MUX_CTRL1_IDAC1_SEL_POS 4 |
| |
| #define | MXC_F_AFE_ADC_ONE_MUX_CTRL1_IDAC1_SEL ((uint8_t)(0xFUL << MXC_F_AFE_ADC_ONE_MUX_CTRL1_IDAC1_SEL_POS)) |
| |
| #define | MXC_F_AFE_ADC_ONE_MUX_CTRL2_VBIAS_SEL_0_POS 0 |
| |
| #define | MXC_F_AFE_ADC_ONE_MUX_CTRL2_VBIAS_SEL_0 ((uint8_t)(0x1UL << MXC_F_AFE_ADC_ONE_MUX_CTRL2_VBIAS_SEL_0_POS)) |
| |
| #define | MXC_F_AFE_ADC_ONE_MUX_CTRL2_VBIAS_SEL_1_POS 1 |
| |
| #define | MXC_F_AFE_ADC_ONE_MUX_CTRL2_VBIAS_SEL_1 ((uint8_t)(0x1UL << MXC_F_AFE_ADC_ONE_MUX_CTRL2_VBIAS_SEL_1_POS)) |
| |
| #define | MXC_F_AFE_ADC_ONE_MUX_CTRL2_VBIAS_SEL_2_POS 2 |
| |
| #define | MXC_F_AFE_ADC_ONE_MUX_CTRL2_VBIAS_SEL_2 ((uint8_t)(0x1UL << MXC_F_AFE_ADC_ONE_MUX_CTRL2_VBIAS_SEL_2_POS)) |
| |
| #define | MXC_F_AFE_ADC_ONE_MUX_CTRL2_VBIAS_SEL_3_POS 3 |
| |
| #define | MXC_F_AFE_ADC_ONE_MUX_CTRL2_VBIAS_SEL_3 ((uint8_t)(0x1UL << MXC_F_AFE_ADC_ONE_MUX_CTRL2_VBIAS_SEL_3_POS)) |
| |
| #define | MXC_F_AFE_ADC_ONE_MUX_CTRL2_VBIAS_SEL_4_POS 4 |
| |
| #define | MXC_F_AFE_ADC_ONE_MUX_CTRL2_VBIAS_SEL_4 ((uint8_t)(0x1UL << MXC_F_AFE_ADC_ONE_MUX_CTRL2_VBIAS_SEL_4_POS)) |
| |
| #define | MXC_F_AFE_ADC_ONE_MUX_CTRL2_VBIAS_SEL_5_POS 5 |
| |
| #define | MXC_F_AFE_ADC_ONE_MUX_CTRL2_VBIAS_SEL_5 ((uint8_t)(0x1UL << MXC_F_AFE_ADC_ONE_MUX_CTRL2_VBIAS_SEL_5_POS)) |
| |
| #define | MXC_F_AFE_ADC_ONE_MUX_CTRL2_VBIAS_SEL_6_POS 6 |
| |
| #define | MXC_F_AFE_ADC_ONE_MUX_CTRL2_VBIAS_SEL_6 ((uint8_t)(0x1UL << MXC_F_AFE_ADC_ONE_MUX_CTRL2_VBIAS_SEL_6_POS)) |
| |
| #define | MXC_F_AFE_ADC_ONE_MUX_CTRL2_VBIAS_SEL_7_POS 7 |
| |
| #define | MXC_F_AFE_ADC_ONE_MUX_CTRL2_VBIAS_SEL_7 ((uint8_t)(0x1UL << MXC_F_AFE_ADC_ONE_MUX_CTRL2_VBIAS_SEL_7_POS)) |
| |
| #define | MXC_F_AFE_ADC_ONE_PGA_GAIN_POS 0 |
| |
| #define | MXC_F_AFE_ADC_ONE_PGA_GAIN ((uint8_t)(0x7UL << MXC_F_AFE_ADC_ONE_PGA_GAIN_POS)) |
| |
| #define | MXC_V_AFE_ADC_ONE_PGA_GAIN_GAIN_1X ((uint8_t)0x0UL) |
| |
| #define | MXC_S_AFE_ADC_ONE_PGA_GAIN_GAIN_1X (MXC_V_AFE_ADC_ONE_PGA_GAIN_GAIN_1X << MXC_F_AFE_ADC_ONE_PGA_GAIN_POS) |
| |
| #define | MXC_V_AFE_ADC_ONE_PGA_GAIN_GAIN_2X ((uint8_t)0x1UL) |
| |
| #define | MXC_S_AFE_ADC_ONE_PGA_GAIN_GAIN_2X (MXC_V_AFE_ADC_ONE_PGA_GAIN_GAIN_2X << MXC_F_AFE_ADC_ONE_PGA_GAIN_POS) |
| |
| #define | MXC_V_AFE_ADC_ONE_PGA_GAIN_GAIN_4X ((uint8_t)0x2UL) |
| |
| #define | MXC_S_AFE_ADC_ONE_PGA_GAIN_GAIN_4X (MXC_V_AFE_ADC_ONE_PGA_GAIN_GAIN_4X << MXC_F_AFE_ADC_ONE_PGA_GAIN_POS) |
| |
| #define | MXC_V_AFE_ADC_ONE_PGA_GAIN_GAIN_8X ((uint8_t)0x3UL) |
| |
| #define | MXC_S_AFE_ADC_ONE_PGA_GAIN_GAIN_8X (MXC_V_AFE_ADC_ONE_PGA_GAIN_GAIN_8X << MXC_F_AFE_ADC_ONE_PGA_GAIN_POS) |
| |
| #define | MXC_V_AFE_ADC_ONE_PGA_GAIN_GAIN_16X ((uint8_t)0x4UL) |
| |
| #define | MXC_S_AFE_ADC_ONE_PGA_GAIN_GAIN_16X (MXC_V_AFE_ADC_ONE_PGA_GAIN_GAIN_16X << MXC_F_AFE_ADC_ONE_PGA_GAIN_POS) |
| |
| #define | MXC_V_AFE_ADC_ONE_PGA_GAIN_GAIN_32X ((uint8_t)0x5UL) |
| |
| #define | MXC_S_AFE_ADC_ONE_PGA_GAIN_GAIN_32X (MXC_V_AFE_ADC_ONE_PGA_GAIN_GAIN_32X << MXC_F_AFE_ADC_ONE_PGA_GAIN_POS) |
| |
| #define | MXC_V_AFE_ADC_ONE_PGA_GAIN_GAIN_64X ((uint8_t)0x6UL) |
| |
| #define | MXC_S_AFE_ADC_ONE_PGA_GAIN_GAIN_64X (MXC_V_AFE_ADC_ONE_PGA_GAIN_GAIN_64X << MXC_F_AFE_ADC_ONE_PGA_GAIN_POS) |
| |
| #define | MXC_V_AFE_ADC_ONE_PGA_GAIN_GAIN_128X ((uint8_t)0x7UL) |
| |
| #define | MXC_S_AFE_ADC_ONE_PGA_GAIN_GAIN_128X (MXC_V_AFE_ADC_ONE_PGA_GAIN_GAIN_128X << MXC_F_AFE_ADC_ONE_PGA_GAIN_POS) |
| |
| #define | MXC_F_AFE_ADC_ONE_PGA_SIG_PATH_POS 4 |
| |
| #define | MXC_F_AFE_ADC_ONE_PGA_SIG_PATH ((uint8_t)(0x3UL << MXC_F_AFE_ADC_ONE_PGA_SIG_PATH_POS)) |
| |
| #define | MXC_V_AFE_ADC_ONE_PGA_SIG_PATH_BUFFERED_UNITY_GAIN_PATH ((uint8_t)0x0UL) |
| |
| #define | MXC_S_AFE_ADC_ONE_PGA_SIG_PATH_BUFFERED_UNITY_GAIN_PATH (MXC_V_AFE_ADC_ONE_PGA_SIG_PATH_BUFFERED_UNITY_GAIN_PATH << MXC_F_AFE_ADC_ONE_PGA_SIG_PATH_POS) |
| |
| #define | MXC_V_AFE_ADC_ONE_PGA_SIG_PATH_BYPASS_PATH ((uint8_t)0x1UL) |
| |
| #define | MXC_S_AFE_ADC_ONE_PGA_SIG_PATH_BYPASS_PATH (MXC_V_AFE_ADC_ONE_PGA_SIG_PATH_BYPASS_PATH << MXC_F_AFE_ADC_ONE_PGA_SIG_PATH_POS) |
| |
| #define | MXC_V_AFE_ADC_ONE_PGA_SIG_PATH_PGA_PATH ((uint8_t)0x2UL) |
| |
| #define | MXC_S_AFE_ADC_ONE_PGA_SIG_PATH_PGA_PATH (MXC_V_AFE_ADC_ONE_PGA_SIG_PATH_PGA_PATH << MXC_F_AFE_ADC_ONE_PGA_SIG_PATH_POS) |
| |
| #define | MXC_V_AFE_ADC_ONE_PGA_SIG_PATH_RESERVED ((uint8_t)0x3UL) |
| |
| #define | MXC_S_AFE_ADC_ONE_PGA_SIG_PATH_RESERVED (MXC_V_AFE_ADC_ONE_PGA_SIG_PATH_RESERVED << MXC_F_AFE_ADC_ONE_PGA_SIG_PATH_POS) |
| |
| #define | MXC_F_AFE_ADC_ONE_WAIT_EXT_WAIT_EXT_POS 0 |
| |
| #define | MXC_F_AFE_ADC_ONE_WAIT_EXT_WAIT_EXT ((uint8_t)(0xFFUL << MXC_F_AFE_ADC_ONE_WAIT_EXT_WAIT_EXT_POS)) |
| |
| #define | MXC_F_AFE_ADC_ONE_PART_ID_REV_ID_POS 0 |
| |
| #define | MXC_F_AFE_ADC_ONE_PART_ID_REV_ID ((uint32_t)(0x1FUL << MXC_F_AFE_ADC_ONE_PART_ID_REV_ID_POS)) |
| |
| #define | MXC_F_AFE_ADC_ONE_PART_ID_ADC_SEL_POS 5 |
| |
| #define | MXC_F_AFE_ADC_ONE_PART_ID_ADC_SEL ((uint32_t)(0x1UL << MXC_F_AFE_ADC_ONE_PART_ID_ADC_SEL_POS)) |
| |
| #define | MXC_F_AFE_ADC_ONE_SYSC_SEL_SYSC_SEL_0_POS 0 |
| |
| #define | MXC_F_AFE_ADC_ONE_SYSC_SEL_SYSC_SEL_0 ((uint32_t)(0x3UL << MXC_F_AFE_ADC_ONE_SYSC_SEL_SYSC_SEL_0_POS)) |
| |
| #define | MXC_F_AFE_ADC_ONE_SYSC_SEL_SYSC_SEL_1_POS 2 |
| |
| #define | MXC_F_AFE_ADC_ONE_SYSC_SEL_SYSC_SEL_1 ((uint32_t)(0x3UL << MXC_F_AFE_ADC_ONE_SYSC_SEL_SYSC_SEL_1_POS)) |
| |
| #define | MXC_F_AFE_ADC_ONE_SYSC_SEL_SYSC_SEL_2_POS 4 |
| |
| #define | MXC_F_AFE_ADC_ONE_SYSC_SEL_SYSC_SEL_2 ((uint32_t)(0x3UL << MXC_F_AFE_ADC_ONE_SYSC_SEL_SYSC_SEL_2_POS)) |
| |
| #define | MXC_F_AFE_ADC_ONE_SYSC_SEL_SYSC_SEL_3_POS 6 |
| |
| #define | MXC_F_AFE_ADC_ONE_SYSC_SEL_SYSC_SEL_3 ((uint32_t)(0x3UL << MXC_F_AFE_ADC_ONE_SYSC_SEL_SYSC_SEL_3_POS)) |
| |
| #define | MXC_F_AFE_ADC_ONE_SYSC_SEL_SYSC_SEL_4_POS 8 |
| |
| #define | MXC_F_AFE_ADC_ONE_SYSC_SEL_SYSC_SEL_4 ((uint32_t)(0x3UL << MXC_F_AFE_ADC_ONE_SYSC_SEL_SYSC_SEL_4_POS)) |
| |
| #define | MXC_F_AFE_ADC_ONE_SYSC_SEL_SYSC_SEL_5_POS 10 |
| |
| #define | MXC_F_AFE_ADC_ONE_SYSC_SEL_SYSC_SEL_5 ((uint32_t)(0x3UL << MXC_F_AFE_ADC_ONE_SYSC_SEL_SYSC_SEL_5_POS)) |
| |
| #define | MXC_F_AFE_ADC_ONE_SYSC_SEL_SYSC_SEL_6_POS 12 |
| |
| #define | MXC_F_AFE_ADC_ONE_SYSC_SEL_SYSC_SEL_6 ((uint32_t)(0x3UL << MXC_F_AFE_ADC_ONE_SYSC_SEL_SYSC_SEL_6_POS)) |
| |
| #define | MXC_F_AFE_ADC_ONE_SYSC_SEL_SYSC_SEL_7_POS 14 |
| |
| #define | MXC_F_AFE_ADC_ONE_SYSC_SEL_SYSC_SEL_7 ((uint32_t)(0x3UL << MXC_F_AFE_ADC_ONE_SYSC_SEL_SYSC_SEL_7_POS)) |
| |
| #define | MXC_F_AFE_ADC_ONE_SYS_OFF_A_SYS_OFF_A_POS 0 |
| |
| #define | MXC_F_AFE_ADC_ONE_SYS_OFF_A_SYS_OFF_A ((uint32_t)(0xFFFFFFUL << MXC_F_AFE_ADC_ONE_SYS_OFF_A_SYS_OFF_A_POS)) |
| |
| #define | MXC_F_AFE_ADC_ONE_SYS_OFF_B_SYS_OFF_B_POS 0 |
| |
| #define | MXC_F_AFE_ADC_ONE_SYS_OFF_B_SYS_OFF_B ((uint32_t)(0xFFFFFFUL << MXC_F_AFE_ADC_ONE_SYS_OFF_B_SYS_OFF_B_POS)) |
| |
| #define | MXC_F_AFE_ADC_ONE_SYS_GAIN_A_SYS_GAIN_A_POS 0 |
| |
| #define | MXC_F_AFE_ADC_ONE_SYS_GAIN_A_SYS_GAIN_A ((uint32_t)(0xFFFFFFUL << MXC_F_AFE_ADC_ONE_SYS_GAIN_A_SYS_GAIN_A_POS)) |
| |
| #define | MXC_F_AFE_ADC_ONE_SYS_GAIN_B_SYS_GAIN_B_POS 0 |
| |
| #define | MXC_F_AFE_ADC_ONE_SYS_GAIN_B_SYS_GAIN_B ((uint32_t)(0xFFFFFFUL << MXC_F_AFE_ADC_ONE_SYS_GAIN_B_SYS_GAIN_B_POS)) |
| |
| #define | MXC_F_AFE_ADC_ONE_SELF_OFF_SELF_OFF_POS 0 |
| |
| #define | MXC_F_AFE_ADC_ONE_SELF_OFF_SELF_OFF ((uint32_t)(0xFFFFFFUL << MXC_F_AFE_ADC_ONE_SELF_OFF_SELF_OFF_POS)) |
| |
| #define | MXC_F_AFE_ADC_ONE_SELF_GAIN_1_SELF_GAIN_1_POS 0 |
| |
| #define | MXC_F_AFE_ADC_ONE_SELF_GAIN_1_SELF_GAIN_1 ((uint32_t)(0xFFFFFFUL << MXC_F_AFE_ADC_ONE_SELF_GAIN_1_SELF_GAIN_1_POS)) |
| |
| #define | MXC_F_AFE_ADC_ONE_SELF_GAIN_2_SELF_GAIN_1_POS 0 |
| |
| #define | MXC_F_AFE_ADC_ONE_SELF_GAIN_2_SELF_GAIN_1 ((uint32_t)(0xFFFFFFUL << MXC_F_AFE_ADC_ONE_SELF_GAIN_2_SELF_GAIN_1_POS)) |
| |
| #define | MXC_F_AFE_ADC_ONE_SELF_GAIN_4_SELF_GAIN_4_POS 0 |
| |
| #define | MXC_F_AFE_ADC_ONE_SELF_GAIN_4_SELF_GAIN_4 ((uint32_t)(0xFFFFFFUL << MXC_F_AFE_ADC_ONE_SELF_GAIN_4_SELF_GAIN_4_POS)) |
| |
| #define | MXC_F_AFE_ADC_ONE_SELF_GAIN_8_SELF_GAIN_8_POS 0 |
| |
| #define | MXC_F_AFE_ADC_ONE_SELF_GAIN_8_SELF_GAIN_8 ((uint32_t)(0xFFFFFFUL << MXC_F_AFE_ADC_ONE_SELF_GAIN_8_SELF_GAIN_8_POS)) |
| |
| #define | MXC_F_AFE_ADC_ONE_SELF_GAIN_16_SELF_GAIN_16_POS 0 |
| |
| #define | MXC_F_AFE_ADC_ONE_SELF_GAIN_16_SELF_GAIN_16 ((uint32_t)(0xFFFFFFUL << MXC_F_AFE_ADC_ONE_SELF_GAIN_16_SELF_GAIN_16_POS)) |
| |
| #define | MXC_F_AFE_ADC_ONE_SELF_GAIN_32_SELF_GAIN_32_POS 0 |
| |
| #define | MXC_F_AFE_ADC_ONE_SELF_GAIN_32_SELF_GAIN_32 ((uint32_t)(0xFFFFFFUL << MXC_F_AFE_ADC_ONE_SELF_GAIN_32_SELF_GAIN_32_POS)) |
| |
| #define | MXC_F_AFE_ADC_ONE_SELF_GAIN_64_SELF_GAIN_64_POS 0 |
| |
| #define | MXC_F_AFE_ADC_ONE_SELF_GAIN_64_SELF_GAIN_64 ((uint32_t)(0xFFFFFFUL << MXC_F_AFE_ADC_ONE_SELF_GAIN_64_SELF_GAIN_64_POS)) |
| |
| #define | MXC_F_AFE_ADC_ONE_SELF_GAIN_128_LTHRESH0_POS 0 |
| |
| #define | MXC_F_AFE_ADC_ONE_SELF_GAIN_128_LTHRESH0 ((uint32_t)(0xFFFFFFUL << MXC_F_AFE_ADC_ONE_SELF_GAIN_128_LTHRESH0_POS)) |
| |
| #define | MXC_F_AFE_ADC_ONE_LTHRESH0_LTHRESH_POS 0 |
| |
| #define | MXC_F_AFE_ADC_ONE_LTHRESH0_LTHRESH ((uint32_t)(0xFFFFFFUL << MXC_F_AFE_ADC_ONE_LTHRESH0_LTHRESH_POS)) |
| |
| #define | MXC_F_AFE_ADC_ONE_LTHRESH1_LTHRESH_POS 0 |
| |
| #define | MXC_F_AFE_ADC_ONE_LTHRESH1_LTHRESH ((uint32_t)(0xFFFFFFUL << MXC_F_AFE_ADC_ONE_LTHRESH1_LTHRESH_POS)) |
| |
| #define | MXC_F_AFE_ADC_ONE_LTHRESH2_LTHRESH_POS 0 |
| |
| #define | MXC_F_AFE_ADC_ONE_LTHRESH2_LTHRESH ((uint32_t)(0xFFFFFFUL << MXC_F_AFE_ADC_ONE_LTHRESH2_LTHRESH_POS)) |
| |
| #define | MXC_F_AFE_ADC_ONE_LTHRESH3_LTHRESH_POS 0 |
| |
| #define | MXC_F_AFE_ADC_ONE_LTHRESH3_LTHRESH ((uint32_t)(0xFFFFFFUL << MXC_F_AFE_ADC_ONE_LTHRESH3_LTHRESH_POS)) |
| |
| #define | MXC_F_AFE_ADC_ONE_LTHRESH4_LTHRESH_POS 0 |
| |
| #define | MXC_F_AFE_ADC_ONE_LTHRESH4_LTHRESH ((uint32_t)(0xFFFFFFUL << MXC_F_AFE_ADC_ONE_LTHRESH4_LTHRESH_POS)) |
| |
| #define | MXC_F_AFE_ADC_ONE_LTHRESH5_LTHRESH_POS 0 |
| |
| #define | MXC_F_AFE_ADC_ONE_LTHRESH5_LTHRESH ((uint32_t)(0xFFFFFFUL << MXC_F_AFE_ADC_ONE_LTHRESH5_LTHRESH_POS)) |
| |
| #define | MXC_F_AFE_ADC_ONE_LTHRESH6_LTHRESH_POS 0 |
| |
| #define | MXC_F_AFE_ADC_ONE_LTHRESH6_LTHRESH ((uint32_t)(0xFFFFFFUL << MXC_F_AFE_ADC_ONE_LTHRESH6_LTHRESH_POS)) |
| |
| #define | MXC_F_AFE_ADC_ONE_LTHRESH7_LTHRESH_POS 0 |
| |
| #define | MXC_F_AFE_ADC_ONE_LTHRESH7_LTHRESH ((uint32_t)(0xFFFFFFUL << MXC_F_AFE_ADC_ONE_LTHRESH7_LTHRESH_POS)) |
| |
| #define | MXC_F_AFE_ADC_ONE_UTHRESH0_UTHRESH_POS 0 |
| |
| #define | MXC_F_AFE_ADC_ONE_UTHRESH0_UTHRESH ((uint32_t)(0xFFFFFFUL << MXC_F_AFE_ADC_ONE_UTHRESH0_UTHRESH_POS)) |
| |
| #define | MXC_F_AFE_ADC_ONE_UTHRESH1_UTHRESH_POS 0 |
| |
| #define | MXC_F_AFE_ADC_ONE_UTHRESH1_UTHRESH ((uint32_t)(0xFFFFFFUL << MXC_F_AFE_ADC_ONE_UTHRESH1_UTHRESH_POS)) |
| |
| #define | MXC_F_AFE_ADC_ONE_UTHRESH2_UTHRESH_POS 0 |
| |
| #define | MXC_F_AFE_ADC_ONE_UTHRESH2_UTHRESH ((uint32_t)(0xFFFFFFUL << MXC_F_AFE_ADC_ONE_UTHRESH2_UTHRESH_POS)) |
| |
| #define | MXC_F_AFE_ADC_ONE_UTHRESH3_UTHRESH_POS 0 |
| |
| #define | MXC_F_AFE_ADC_ONE_UTHRESH3_UTHRESH ((uint32_t)(0xFFFFFFUL << MXC_F_AFE_ADC_ONE_UTHRESH3_UTHRESH_POS)) |
| |
| #define | MXC_F_AFE_ADC_ONE_UTHRESH4_UTHRESH_POS 0 |
| |
| #define | MXC_F_AFE_ADC_ONE_UTHRESH4_UTHRESH ((uint32_t)(0xFFFFFFUL << MXC_F_AFE_ADC_ONE_UTHRESH4_UTHRESH_POS)) |
| |
| #define | MXC_F_AFE_ADC_ONE_UTHRESH5_UTHRESH_POS 0 |
| |
| #define | MXC_F_AFE_ADC_ONE_UTHRESH5_UTHRESH ((uint32_t)(0xFFFFFFUL << MXC_F_AFE_ADC_ONE_UTHRESH5_UTHRESH_POS)) |
| |
| #define | MXC_F_AFE_ADC_ONE_UTHRESH6_UTHRESH_POS 0 |
| |
| #define | MXC_F_AFE_ADC_ONE_UTHRESH6_UTHRESH ((uint32_t)(0xFFFFFFUL << MXC_F_AFE_ADC_ONE_UTHRESH6_UTHRESH_POS)) |
| |
| #define | MXC_F_AFE_ADC_ONE_UTHRESH7_UTHRESH_POS 0 |
| |
| #define | MXC_F_AFE_ADC_ONE_UTHRESH7_UTHRESH ((uint32_t)(0xFFFFFFUL << MXC_F_AFE_ADC_ONE_UTHRESH7_UTHRESH_POS)) |
| |
| #define | MXC_F_AFE_ADC_ONE_DATA0_DATA0_POS 0 |
| |
| #define | MXC_F_AFE_ADC_ONE_DATA0_DATA0 ((uint32_t)(0xFFFFFFUL << MXC_F_AFE_ADC_ONE_DATA0_DATA0_POS)) |
| |
| #define | MXC_F_AFE_ADC_ONE_DATA1_DATA1_POS 0 |
| |
| #define | MXC_F_AFE_ADC_ONE_DATA1_DATA1 ((uint32_t)(0xFFFFFFUL << MXC_F_AFE_ADC_ONE_DATA1_DATA1_POS)) |
| |
| #define | MXC_F_AFE_ADC_ONE_DATA2_DATA2_POS 0 |
| |
| #define | MXC_F_AFE_ADC_ONE_DATA2_DATA2 ((uint32_t)(0xFFFFFFUL << MXC_F_AFE_ADC_ONE_DATA2_DATA2_POS)) |
| |
| #define | MXC_F_AFE_ADC_ONE_DATA3_DATA3_POS 0 |
| |
| #define | MXC_F_AFE_ADC_ONE_DATA3_DATA3 ((uint32_t)(0xFFFFFFUL << MXC_F_AFE_ADC_ONE_DATA3_DATA3_POS)) |
| |
| #define | MXC_F_AFE_ADC_ONE_DATA4_DATA4_POS 0 |
| |
| #define | MXC_F_AFE_ADC_ONE_DATA4_DATA4 ((uint32_t)(0xFFFFFFUL << MXC_F_AFE_ADC_ONE_DATA4_DATA4_POS)) |
| |
| #define | MXC_F_AFE_ADC_ONE_DATA5_DATA5_POS 0 |
| |
| #define | MXC_F_AFE_ADC_ONE_DATA5_DATA5 ((uint32_t)(0xFFFFFFUL << MXC_F_AFE_ADC_ONE_DATA5_DATA5_POS)) |
| |
| #define | MXC_F_AFE_ADC_ONE_DATA6_DATA6_POS 0 |
| |
| #define | MXC_F_AFE_ADC_ONE_DATA6_DATA6 ((uint32_t)(0xFFFFFFUL << MXC_F_AFE_ADC_ONE_DATA6_DATA6_POS)) |
| |
| #define | MXC_F_AFE_ADC_ONE_DATA7_DATA7_POS 0 |
| |
| #define | MXC_F_AFE_ADC_ONE_DATA7_DATA7 ((uint32_t)(0xFFFFFFUL << MXC_F_AFE_ADC_ONE_DATA7_DATA7_POS)) |
| |
| #define | MXC_F_AFE_ADC_ONE_STATUS_CONV_RDY_POS 0 |
| |
| #define | MXC_F_AFE_ADC_ONE_STATUS_CONV_RDY ((uint32_t)(0x1UL << MXC_F_AFE_ADC_ONE_STATUS_CONV_RDY_POS)) |
| |
| #define | MXC_F_AFE_ADC_ONE_STATUS_SEQ_RDY_POS 1 |
| |
| #define | MXC_F_AFE_ADC_ONE_STATUS_SEQ_RDY ((uint32_t)(0x1UL << MXC_F_AFE_ADC_ONE_STATUS_SEQ_RDY_POS)) |
| |
| #define | MXC_F_AFE_ADC_ONE_STATUS_CAL_RDY_POS 2 |
| |
| #define | MXC_F_AFE_ADC_ONE_STATUS_CAL_RDY ((uint32_t)(0x1UL << MXC_F_AFE_ADC_ONE_STATUS_CAL_RDY_POS)) |
| |
| #define | MXC_F_AFE_ADC_ONE_STATUS_WAIT_DONE_POS 3 |
| |
| #define | MXC_F_AFE_ADC_ONE_STATUS_WAIT_DONE ((uint32_t)(0x1UL << MXC_F_AFE_ADC_ONE_STATUS_WAIT_DONE_POS)) |
| |
| #define | MXC_F_AFE_ADC_ONE_STATUS_DATA_RDY_POS 4 |
| |
| #define | MXC_F_AFE_ADC_ONE_STATUS_DATA_RDY ((uint32_t)(0x1UL << MXC_F_AFE_ADC_ONE_STATUS_DATA_RDY_POS)) |
| |
| #define | MXC_F_AFE_ADC_ONE_STATUS_SYSGOR_POS 7 |
| |
| #define | MXC_F_AFE_ADC_ONE_STATUS_SYSGOR ((uint32_t)(0x1UL << MXC_F_AFE_ADC_ONE_STATUS_SYSGOR_POS)) |
| |
| #define | MXC_F_AFE_ADC_ONE_STATUS_TUR_0_POS 8 |
| |
| #define | MXC_F_AFE_ADC_ONE_STATUS_TUR_0 ((uint32_t)(0x1UL << MXC_F_AFE_ADC_ONE_STATUS_TUR_0_POS)) |
| |
| #define | MXC_F_AFE_ADC_ONE_STATUS_TUR_1_POS 9 |
| |
| #define | MXC_F_AFE_ADC_ONE_STATUS_TUR_1 ((uint32_t)(0x1UL << MXC_F_AFE_ADC_ONE_STATUS_TUR_1_POS)) |
| |
| #define | MXC_F_AFE_ADC_ONE_STATUS_TUR_2_POS 10 |
| |
| #define | MXC_F_AFE_ADC_ONE_STATUS_TUR_2 ((uint32_t)(0x1UL << MXC_F_AFE_ADC_ONE_STATUS_TUR_2_POS)) |
| |
| #define | MXC_F_AFE_ADC_ONE_STATUS_TUR_3_POS 11 |
| |
| #define | MXC_F_AFE_ADC_ONE_STATUS_TUR_3 ((uint32_t)(0x1UL << MXC_F_AFE_ADC_ONE_STATUS_TUR_3_POS)) |
| |
| #define | MXC_F_AFE_ADC_ONE_STATUS_TUR_4_POS 12 |
| |
| #define | MXC_F_AFE_ADC_ONE_STATUS_TUR_4 ((uint32_t)(0x1UL << MXC_F_AFE_ADC_ONE_STATUS_TUR_4_POS)) |
| |
| #define | MXC_F_AFE_ADC_ONE_STATUS_TUR_5_POS 13 |
| |
| #define | MXC_F_AFE_ADC_ONE_STATUS_TUR_5 ((uint32_t)(0x1UL << MXC_F_AFE_ADC_ONE_STATUS_TUR_5_POS)) |
| |
| #define | MXC_F_AFE_ADC_ONE_STATUS_TUR_6_POS 14 |
| |
| #define | MXC_F_AFE_ADC_ONE_STATUS_TUR_6 ((uint32_t)(0x1UL << MXC_F_AFE_ADC_ONE_STATUS_TUR_6_POS)) |
| |
| #define | MXC_F_AFE_ADC_ONE_STATUS_TUR_7_POS 15 |
| |
| #define | MXC_F_AFE_ADC_ONE_STATUS_TUR_7 ((uint32_t)(0x1UL << MXC_F_AFE_ADC_ONE_STATUS_TUR_7_POS)) |
| |
| #define | MXC_F_AFE_ADC_ONE_STATUS_TOR_0_POS 16 |
| |
| #define | MXC_F_AFE_ADC_ONE_STATUS_TOR_0 ((uint32_t)(0x1UL << MXC_F_AFE_ADC_ONE_STATUS_TOR_0_POS)) |
| |
| #define | MXC_F_AFE_ADC_ONE_STATUS_TOR_1_POS 17 |
| |
| #define | MXC_F_AFE_ADC_ONE_STATUS_TOR_1 ((uint32_t)(0x1UL << MXC_F_AFE_ADC_ONE_STATUS_TOR_1_POS)) |
| |
| #define | MXC_F_AFE_ADC_ONE_STATUS_TOR_2_POS 18 |
| |
| #define | MXC_F_AFE_ADC_ONE_STATUS_TOR_2 ((uint32_t)(0x1UL << MXC_F_AFE_ADC_ONE_STATUS_TOR_2_POS)) |
| |
| #define | MXC_F_AFE_ADC_ONE_STATUS_TOR_3_POS 19 |
| |
| #define | MXC_F_AFE_ADC_ONE_STATUS_TOR_3 ((uint32_t)(0x1UL << MXC_F_AFE_ADC_ONE_STATUS_TOR_3_POS)) |
| |
| #define | MXC_F_AFE_ADC_ONE_STATUS_TOR_4_POS 20 |
| |
| #define | MXC_F_AFE_ADC_ONE_STATUS_TOR_4 ((uint32_t)(0x1UL << MXC_F_AFE_ADC_ONE_STATUS_TOR_4_POS)) |
| |
| #define | MXC_F_AFE_ADC_ONE_STATUS_TOR_5_POS 21 |
| |
| #define | MXC_F_AFE_ADC_ONE_STATUS_TOR_5 ((uint32_t)(0x1UL << MXC_F_AFE_ADC_ONE_STATUS_TOR_5_POS)) |
| |
| #define | MXC_F_AFE_ADC_ONE_STATUS_TOR_6_POS 22 |
| |
| #define | MXC_F_AFE_ADC_ONE_STATUS_TOR_6 ((uint32_t)(0x1UL << MXC_F_AFE_ADC_ONE_STATUS_TOR_6_POS)) |
| |
| #define | MXC_F_AFE_ADC_ONE_STATUS_TOR_7_POS 23 |
| |
| #define | MXC_F_AFE_ADC_ONE_STATUS_TOR_7 ((uint32_t)(0x1UL << MXC_F_AFE_ADC_ONE_STATUS_TOR_7_POS)) |
| |
| #define | MXC_F_AFE_ADC_ONE_STATUS_IE_CONV_RDY_IE_POS 0 |
| |
| #define | MXC_F_AFE_ADC_ONE_STATUS_IE_CONV_RDY_IE ((uint32_t)(0x1UL << MXC_F_AFE_ADC_ONE_STATUS_IE_CONV_RDY_IE_POS)) |
| |
| #define | MXC_F_AFE_ADC_ONE_STATUS_IE_SEQ_RDY_IE_POS 1 |
| |
| #define | MXC_F_AFE_ADC_ONE_STATUS_IE_SEQ_RDY_IE ((uint32_t)(0x1UL << MXC_F_AFE_ADC_ONE_STATUS_IE_SEQ_RDY_IE_POS)) |
| |
| #define | MXC_F_AFE_ADC_ONE_STATUS_IE_CAL_RDY_IE_POS 2 |
| |
| #define | MXC_F_AFE_ADC_ONE_STATUS_IE_CAL_RDY_IE ((uint32_t)(0x1UL << MXC_F_AFE_ADC_ONE_STATUS_IE_CAL_RDY_IE_POS)) |
| |
| #define | MXC_F_AFE_ADC_ONE_STATUS_IE_WAIT_DONE_IE_POS 3 |
| |
| #define | MXC_F_AFE_ADC_ONE_STATUS_IE_WAIT_DONE_IE ((uint32_t)(0x1UL << MXC_F_AFE_ADC_ONE_STATUS_IE_WAIT_DONE_IE_POS)) |
| |
| #define | MXC_F_AFE_ADC_ONE_STATUS_IE_DATA_RDY_IE_POS 4 |
| |
| #define | MXC_F_AFE_ADC_ONE_STATUS_IE_DATA_RDY_IE ((uint32_t)(0x1UL << MXC_F_AFE_ADC_ONE_STATUS_IE_DATA_RDY_IE_POS)) |
| |
| #define | MXC_F_AFE_ADC_ONE_STATUS_IE_SYSGOR_IE_POS 7 |
| |
| #define | MXC_F_AFE_ADC_ONE_STATUS_IE_SYSGOR_IE ((uint32_t)(0x1UL << MXC_F_AFE_ADC_ONE_STATUS_IE_SYSGOR_IE_POS)) |
| |
| #define | MXC_F_AFE_ADC_ONE_STATUS_IE_TUR_IE_0_POS 8 |
| |
| #define | MXC_F_AFE_ADC_ONE_STATUS_IE_TUR_IE_0 ((uint32_t)(0x1UL << MXC_F_AFE_ADC_ONE_STATUS_IE_TUR_IE_0_POS)) |
| |
| #define | MXC_F_AFE_ADC_ONE_STATUS_IE_TUR_IE_1_POS 9 |
| |
| #define | MXC_F_AFE_ADC_ONE_STATUS_IE_TUR_IE_1 ((uint32_t)(0x1UL << MXC_F_AFE_ADC_ONE_STATUS_IE_TUR_IE_1_POS)) |
| |
| #define | MXC_F_AFE_ADC_ONE_STATUS_IE_TUR_IE_2_POS 10 |
| |
| #define | MXC_F_AFE_ADC_ONE_STATUS_IE_TUR_IE_2 ((uint32_t)(0x1UL << MXC_F_AFE_ADC_ONE_STATUS_IE_TUR_IE_2_POS)) |
| |
| #define | MXC_F_AFE_ADC_ONE_STATUS_IE_TUR_IE_3_POS 11 |
| |
| #define | MXC_F_AFE_ADC_ONE_STATUS_IE_TUR_IE_3 ((uint32_t)(0x1UL << MXC_F_AFE_ADC_ONE_STATUS_IE_TUR_IE_3_POS)) |
| |
| #define | MXC_F_AFE_ADC_ONE_STATUS_IE_TUR_IE_4_POS 12 |
| |
| #define | MXC_F_AFE_ADC_ONE_STATUS_IE_TUR_IE_4 ((uint32_t)(0x1UL << MXC_F_AFE_ADC_ONE_STATUS_IE_TUR_IE_4_POS)) |
| |
| #define | MXC_F_AFE_ADC_ONE_STATUS_IE_TUR_IE_5_POS 13 |
| |
| #define | MXC_F_AFE_ADC_ONE_STATUS_IE_TUR_IE_5 ((uint32_t)(0x1UL << MXC_F_AFE_ADC_ONE_STATUS_IE_TUR_IE_5_POS)) |
| |
| #define | MXC_F_AFE_ADC_ONE_STATUS_IE_TUR_IE_6_POS 14 |
| |
| #define | MXC_F_AFE_ADC_ONE_STATUS_IE_TUR_IE_6 ((uint32_t)(0x1UL << MXC_F_AFE_ADC_ONE_STATUS_IE_TUR_IE_6_POS)) |
| |
| #define | MXC_F_AFE_ADC_ONE_STATUS_IE_TUR_IE_7_POS 15 |
| |
| #define | MXC_F_AFE_ADC_ONE_STATUS_IE_TUR_IE_7 ((uint32_t)(0x1UL << MXC_F_AFE_ADC_ONE_STATUS_IE_TUR_IE_7_POS)) |
| |
| #define | MXC_F_AFE_ADC_ONE_STATUS_IE_TOR_IE_0_POS 16 |
| |
| #define | MXC_F_AFE_ADC_ONE_STATUS_IE_TOR_IE_0 ((uint32_t)(0x1UL << MXC_F_AFE_ADC_ONE_STATUS_IE_TOR_IE_0_POS)) |
| |
| #define | MXC_F_AFE_ADC_ONE_STATUS_IE_TOR_IE_1_POS 17 |
| |
| #define | MXC_F_AFE_ADC_ONE_STATUS_IE_TOR_IE_1 ((uint32_t)(0x1UL << MXC_F_AFE_ADC_ONE_STATUS_IE_TOR_IE_1_POS)) |
| |
| #define | MXC_F_AFE_ADC_ONE_STATUS_IE_TOR_IE_2_POS 18 |
| |
| #define | MXC_F_AFE_ADC_ONE_STATUS_IE_TOR_IE_2 ((uint32_t)(0x1UL << MXC_F_AFE_ADC_ONE_STATUS_IE_TOR_IE_2_POS)) |
| |
| #define | MXC_F_AFE_ADC_ONE_STATUS_IE_TOR_IE_3_POS 19 |
| |
| #define | MXC_F_AFE_ADC_ONE_STATUS_IE_TOR_IE_3 ((uint32_t)(0x1UL << MXC_F_AFE_ADC_ONE_STATUS_IE_TOR_IE_3_POS)) |
| |
| #define | MXC_F_AFE_ADC_ONE_STATUS_IE_TOR_IE_4_POS 20 |
| |
| #define | MXC_F_AFE_ADC_ONE_STATUS_IE_TOR_IE_4 ((uint32_t)(0x1UL << MXC_F_AFE_ADC_ONE_STATUS_IE_TOR_IE_4_POS)) |
| |
| #define | MXC_F_AFE_ADC_ONE_STATUS_IE_TOR_IE_5_POS 21 |
| |
| #define | MXC_F_AFE_ADC_ONE_STATUS_IE_TOR_IE_5 ((uint32_t)(0x1UL << MXC_F_AFE_ADC_ONE_STATUS_IE_TOR_IE_5_POS)) |
| |
| #define | MXC_F_AFE_ADC_ONE_STATUS_IE_TOR_IE_6_POS 22 |
| |
| #define | MXC_F_AFE_ADC_ONE_STATUS_IE_TOR_IE_6 ((uint32_t)(0x1UL << MXC_F_AFE_ADC_ONE_STATUS_IE_TOR_IE_6_POS)) |
| |
| #define | MXC_F_AFE_ADC_ONE_STATUS_IE_TOR_IE_7_POS 23 |
| |
| #define | MXC_F_AFE_ADC_ONE_STATUS_IE_TOR_IE_7 ((uint32_t)(0x1UL << MXC_F_AFE_ADC_ONE_STATUS_IE_TOR_IE_7_POS)) |
| |
| #define | MXC_F_AFE_ADC_ONE_UC_0_REG_DATA_POS 0 |
| |
| #define | MXC_F_AFE_ADC_ONE_UC_0_REG_DATA ((uint16_t)(0xFFUL << MXC_F_AFE_ADC_ONE_UC_0_REG_DATA_POS)) |
| |
| #define | MXC_F_AFE_ADC_ONE_UC_0_REG_ADDR_POS 8 |
| |
| #define | MXC_F_AFE_ADC_ONE_UC_0_REG_ADDR ((uint16_t)(0x7FUL << MXC_F_AFE_ADC_ONE_UC_0_REG_ADDR_POS)) |
| |
| #define | MXC_F_AFE_ADC_ONE_UC_1_REG_DATA_POS 0 |
| |
| #define | MXC_F_AFE_ADC_ONE_UC_1_REG_DATA ((uint16_t)(0xFFUL << MXC_F_AFE_ADC_ONE_UC_1_REG_DATA_POS)) |
| |
| #define | MXC_F_AFE_ADC_ONE_UC_1_REG_ADDR_POS 8 |
| |
| #define | MXC_F_AFE_ADC_ONE_UC_1_REG_ADDR ((uint16_t)(0x7FUL << MXC_F_AFE_ADC_ONE_UC_1_REG_ADDR_POS)) |
| |
| #define | MXC_F_AFE_ADC_ONE_UC_2_REG_DATA_POS 0 |
| |
| #define | MXC_F_AFE_ADC_ONE_UC_2_REG_DATA ((uint16_t)(0xFFUL << MXC_F_AFE_ADC_ONE_UC_2_REG_DATA_POS)) |
| |
| #define | MXC_F_AFE_ADC_ONE_UC_2_REG_ADDR_POS 8 |
| |
| #define | MXC_F_AFE_ADC_ONE_UC_2_REG_ADDR ((uint16_t)(0x7FUL << MXC_F_AFE_ADC_ONE_UC_2_REG_ADDR_POS)) |
| |
| #define | MXC_F_AFE_ADC_ONE_UC_3_REG_DATA_POS 0 |
| |
| #define | MXC_F_AFE_ADC_ONE_UC_3_REG_DATA ((uint16_t)(0xFFUL << MXC_F_AFE_ADC_ONE_UC_3_REG_DATA_POS)) |
| |
| #define | MXC_F_AFE_ADC_ONE_UC_3_REG_ADDR_POS 8 |
| |
| #define | MXC_F_AFE_ADC_ONE_UC_3_REG_ADDR ((uint16_t)(0x7FUL << MXC_F_AFE_ADC_ONE_UC_3_REG_ADDR_POS)) |
| |
| #define | MXC_F_AFE_ADC_ONE_UC_4_REG_DATA_POS 0 |
| |
| #define | MXC_F_AFE_ADC_ONE_UC_4_REG_DATA ((uint16_t)(0xFFUL << MXC_F_AFE_ADC_ONE_UC_4_REG_DATA_POS)) |
| |
| #define | MXC_F_AFE_ADC_ONE_UC_4_REG_ADDR_POS 8 |
| |
| #define | MXC_F_AFE_ADC_ONE_UC_4_REG_ADDR ((uint16_t)(0x7FUL << MXC_F_AFE_ADC_ONE_UC_4_REG_ADDR_POS)) |
| |
| #define | MXC_F_AFE_ADC_ONE_UC_5_REG_DATA_POS 0 |
| |
| #define | MXC_F_AFE_ADC_ONE_UC_5_REG_DATA ((uint16_t)(0xFFUL << MXC_F_AFE_ADC_ONE_UC_5_REG_DATA_POS)) |
| |
| #define | MXC_F_AFE_ADC_ONE_UC_5_REG_ADDR_POS 8 |
| |
| #define | MXC_F_AFE_ADC_ONE_UC_5_REG_ADDR ((uint16_t)(0x7FUL << MXC_F_AFE_ADC_ONE_UC_5_REG_ADDR_POS)) |
| |
| #define | MXC_F_AFE_ADC_ONE_UC_6_REG_DATA_POS 0 |
| |
| #define | MXC_F_AFE_ADC_ONE_UC_6_REG_DATA ((uint16_t)(0xFFUL << MXC_F_AFE_ADC_ONE_UC_6_REG_DATA_POS)) |
| |
| #define | MXC_F_AFE_ADC_ONE_UC_6_REG_ADDR_POS 8 |
| |
| #define | MXC_F_AFE_ADC_ONE_UC_6_REG_ADDR ((uint16_t)(0x7FUL << MXC_F_AFE_ADC_ONE_UC_6_REG_ADDR_POS)) |
| |
| #define | MXC_F_AFE_ADC_ONE_UC_7_REG_DATA_POS 0 |
| |
| #define | MXC_F_AFE_ADC_ONE_UC_7_REG_DATA ((uint16_t)(0xFFUL << MXC_F_AFE_ADC_ONE_UC_7_REG_DATA_POS)) |
| |
| #define | MXC_F_AFE_ADC_ONE_UC_7_REG_ADDR_POS 8 |
| |
| #define | MXC_F_AFE_ADC_ONE_UC_7_REG_ADDR ((uint16_t)(0x7FUL << MXC_F_AFE_ADC_ONE_UC_7_REG_ADDR_POS)) |
| |
| #define | MXC_F_AFE_ADC_ONE_UC_8_REG_DATA_POS 0 |
| |
| #define | MXC_F_AFE_ADC_ONE_UC_8_REG_DATA ((uint16_t)(0xFFUL << MXC_F_AFE_ADC_ONE_UC_8_REG_DATA_POS)) |
| |
| #define | MXC_F_AFE_ADC_ONE_UC_8_REG_ADDR_POS 8 |
| |
| #define | MXC_F_AFE_ADC_ONE_UC_8_REG_ADDR ((uint16_t)(0x7FUL << MXC_F_AFE_ADC_ONE_UC_8_REG_ADDR_POS)) |
| |
| #define | MXC_F_AFE_ADC_ONE_UC_9_REG_DATA_POS 0 |
| |
| #define | MXC_F_AFE_ADC_ONE_UC_9_REG_DATA ((uint16_t)(0xFFUL << MXC_F_AFE_ADC_ONE_UC_9_REG_DATA_POS)) |
| |
| #define | MXC_F_AFE_ADC_ONE_UC_9_REG_ADDR_POS 8 |
| |
| #define | MXC_F_AFE_ADC_ONE_UC_9_REG_ADDR ((uint16_t)(0x7FUL << MXC_F_AFE_ADC_ONE_UC_9_REG_ADDR_POS)) |
| |
| #define | MXC_F_AFE_ADC_ONE_UC_10_REG_DATA_POS 0 |
| |
| #define | MXC_F_AFE_ADC_ONE_UC_10_REG_DATA ((uint16_t)(0xFFUL << MXC_F_AFE_ADC_ONE_UC_10_REG_DATA_POS)) |
| |
| #define | MXC_F_AFE_ADC_ONE_UC_10_REG_ADDR_POS 8 |
| |
| #define | MXC_F_AFE_ADC_ONE_UC_10_REG_ADDR ((uint16_t)(0x7FUL << MXC_F_AFE_ADC_ONE_UC_10_REG_ADDR_POS)) |
| |
| #define | MXC_F_AFE_ADC_ONE_UC_11_REG_DATA_POS 0 |
| |
| #define | MXC_F_AFE_ADC_ONE_UC_11_REG_DATA ((uint16_t)(0xFFUL << MXC_F_AFE_ADC_ONE_UC_11_REG_DATA_POS)) |
| |
| #define | MXC_F_AFE_ADC_ONE_UC_11_REG_ADDR_POS 8 |
| |
| #define | MXC_F_AFE_ADC_ONE_UC_11_REG_ADDR ((uint16_t)(0x7FUL << MXC_F_AFE_ADC_ONE_UC_11_REG_ADDR_POS)) |
| |
| #define | MXC_F_AFE_ADC_ONE_UC_12_REG_DATA_POS 0 |
| |
| #define | MXC_F_AFE_ADC_ONE_UC_12_REG_DATA ((uint16_t)(0xFFUL << MXC_F_AFE_ADC_ONE_UC_12_REG_DATA_POS)) |
| |
| #define | MXC_F_AFE_ADC_ONE_UC_12_REG_ADDR_POS 8 |
| |
| #define | MXC_F_AFE_ADC_ONE_UC_12_REG_ADDR ((uint16_t)(0x7FUL << MXC_F_AFE_ADC_ONE_UC_12_REG_ADDR_POS)) |
| |
| #define | MXC_F_AFE_ADC_ONE_UC_13_REG_DATA_POS 0 |
| |
| #define | MXC_F_AFE_ADC_ONE_UC_13_REG_DATA ((uint16_t)(0xFFUL << MXC_F_AFE_ADC_ONE_UC_13_REG_DATA_POS)) |
| |
| #define | MXC_F_AFE_ADC_ONE_UC_13_REG_ADDR_POS 8 |
| |
| #define | MXC_F_AFE_ADC_ONE_UC_13_REG_ADDR ((uint16_t)(0x7FUL << MXC_F_AFE_ADC_ONE_UC_13_REG_ADDR_POS)) |
| |
| #define | MXC_F_AFE_ADC_ONE_UC_14_REG_DATA_POS 0 |
| |
| #define | MXC_F_AFE_ADC_ONE_UC_14_REG_DATA ((uint16_t)(0xFFUL << MXC_F_AFE_ADC_ONE_UC_14_REG_DATA_POS)) |
| |
| #define | MXC_F_AFE_ADC_ONE_UC_14_REG_ADDR_POS 8 |
| |
| #define | MXC_F_AFE_ADC_ONE_UC_14_REG_ADDR ((uint16_t)(0x7FUL << MXC_F_AFE_ADC_ONE_UC_14_REG_ADDR_POS)) |
| |
| #define | MXC_F_AFE_ADC_ONE_UC_15_REG_DATA_POS 0 |
| |
| #define | MXC_F_AFE_ADC_ONE_UC_15_REG_DATA ((uint16_t)(0xFFUL << MXC_F_AFE_ADC_ONE_UC_15_REG_DATA_POS)) |
| |
| #define | MXC_F_AFE_ADC_ONE_UC_15_REG_ADDR_POS 8 |
| |
| #define | MXC_F_AFE_ADC_ONE_UC_15_REG_ADDR ((uint16_t)(0x7FUL << MXC_F_AFE_ADC_ONE_UC_15_REG_ADDR_POS)) |
| |
| #define | MXC_F_AFE_ADC_ONE_UC_16_REG_DATA_POS 0 |
| |
| #define | MXC_F_AFE_ADC_ONE_UC_16_REG_DATA ((uint16_t)(0xFFUL << MXC_F_AFE_ADC_ONE_UC_16_REG_DATA_POS)) |
| |
| #define | MXC_F_AFE_ADC_ONE_UC_16_REG_ADDR_POS 8 |
| |
| #define | MXC_F_AFE_ADC_ONE_UC_16_REG_ADDR ((uint16_t)(0x7FUL << MXC_F_AFE_ADC_ONE_UC_16_REG_ADDR_POS)) |
| |
| #define | MXC_F_AFE_ADC_ONE_UC_17_REG_DATA_POS 0 |
| |
| #define | MXC_F_AFE_ADC_ONE_UC_17_REG_DATA ((uint16_t)(0xFFUL << MXC_F_AFE_ADC_ONE_UC_17_REG_DATA_POS)) |
| |
| #define | MXC_F_AFE_ADC_ONE_UC_17_REG_ADDR_POS 8 |
| |
| #define | MXC_F_AFE_ADC_ONE_UC_17_REG_ADDR ((uint16_t)(0x7FUL << MXC_F_AFE_ADC_ONE_UC_17_REG_ADDR_POS)) |
| |
| #define | MXC_F_AFE_ADC_ONE_UC_18_REG_DATA_POS 0 |
| |
| #define | MXC_F_AFE_ADC_ONE_UC_18_REG_DATA ((uint16_t)(0xFFUL << MXC_F_AFE_ADC_ONE_UC_18_REG_DATA_POS)) |
| |
| #define | MXC_F_AFE_ADC_ONE_UC_18_REG_ADDR_POS 8 |
| |
| #define | MXC_F_AFE_ADC_ONE_UC_18_REG_ADDR ((uint16_t)(0x7FUL << MXC_F_AFE_ADC_ONE_UC_18_REG_ADDR_POS)) |
| |
| #define | MXC_F_AFE_ADC_ONE_UC_19_REG_DATA_POS 0 |
| |
| #define | MXC_F_AFE_ADC_ONE_UC_19_REG_DATA ((uint16_t)(0xFFUL << MXC_F_AFE_ADC_ONE_UC_19_REG_DATA_POS)) |
| |
| #define | MXC_F_AFE_ADC_ONE_UC_19_REG_ADDR_POS 8 |
| |
| #define | MXC_F_AFE_ADC_ONE_UC_19_REG_ADDR ((uint16_t)(0x7FUL << MXC_F_AFE_ADC_ONE_UC_19_REG_ADDR_POS)) |
| |
| #define | MXC_F_AFE_ADC_ONE_UC_20_REG_DATA_POS 0 |
| |
| #define | MXC_F_AFE_ADC_ONE_UC_20_REG_DATA ((uint16_t)(0xFFUL << MXC_F_AFE_ADC_ONE_UC_20_REG_DATA_POS)) |
| |
| #define | MXC_F_AFE_ADC_ONE_UC_20_REG_ADDR_POS 8 |
| |
| #define | MXC_F_AFE_ADC_ONE_UC_20_REG_ADDR ((uint16_t)(0x7FUL << MXC_F_AFE_ADC_ONE_UC_20_REG_ADDR_POS)) |
| |
| #define | MXC_F_AFE_ADC_ONE_UC_21_REG_DATA_POS 0 |
| |
| #define | MXC_F_AFE_ADC_ONE_UC_21_REG_DATA ((uint16_t)(0xFFUL << MXC_F_AFE_ADC_ONE_UC_21_REG_DATA_POS)) |
| |
| #define | MXC_F_AFE_ADC_ONE_UC_21_REG_ADDR_POS 8 |
| |
| #define | MXC_F_AFE_ADC_ONE_UC_21_REG_ADDR ((uint16_t)(0x7FUL << MXC_F_AFE_ADC_ONE_UC_21_REG_ADDR_POS)) |
| |
| #define | MXC_F_AFE_ADC_ONE_UC_22_REG_DATA_POS 0 |
| |
| #define | MXC_F_AFE_ADC_ONE_UC_22_REG_DATA ((uint16_t)(0xFFUL << MXC_F_AFE_ADC_ONE_UC_22_REG_DATA_POS)) |
| |
| #define | MXC_F_AFE_ADC_ONE_UC_22_REG_ADDR_POS 8 |
| |
| #define | MXC_F_AFE_ADC_ONE_UC_22_REG_ADDR ((uint16_t)(0x7FUL << MXC_F_AFE_ADC_ONE_UC_22_REG_ADDR_POS)) |
| |
| #define | MXC_F_AFE_ADC_ONE_UC_23_REG_DATA_POS 0 |
| |
| #define | MXC_F_AFE_ADC_ONE_UC_23_REG_DATA ((uint16_t)(0xFFUL << MXC_F_AFE_ADC_ONE_UC_23_REG_DATA_POS)) |
| |
| #define | MXC_F_AFE_ADC_ONE_UC_23_REG_ADDR_POS 8 |
| |
| #define | MXC_F_AFE_ADC_ONE_UC_23_REG_ADDR ((uint16_t)(0x7FUL << MXC_F_AFE_ADC_ONE_UC_23_REG_ADDR_POS)) |
| |
| #define | MXC_F_AFE_ADC_ONE_UC_24_REG_DATA_POS 0 |
| |
| #define | MXC_F_AFE_ADC_ONE_UC_24_REG_DATA ((uint16_t)(0xFFUL << MXC_F_AFE_ADC_ONE_UC_24_REG_DATA_POS)) |
| |
| #define | MXC_F_AFE_ADC_ONE_UC_24_REG_ADDR_POS 8 |
| |
| #define | MXC_F_AFE_ADC_ONE_UC_24_REG_ADDR ((uint16_t)(0x7FUL << MXC_F_AFE_ADC_ONE_UC_24_REG_ADDR_POS)) |
| |
| #define | MXC_F_AFE_ADC_ONE_UC_25_REG_DATA_POS 0 |
| |
| #define | MXC_F_AFE_ADC_ONE_UC_25_REG_DATA ((uint16_t)(0xFFUL << MXC_F_AFE_ADC_ONE_UC_25_REG_DATA_POS)) |
| |
| #define | MXC_F_AFE_ADC_ONE_UC_25_REG_ADDR_POS 8 |
| |
| #define | MXC_F_AFE_ADC_ONE_UC_25_REG_ADDR ((uint16_t)(0x7FUL << MXC_F_AFE_ADC_ONE_UC_25_REG_ADDR_POS)) |
| |
| #define | MXC_F_AFE_ADC_ONE_UC_26_REG_DATA_POS 0 |
| |
| #define | MXC_F_AFE_ADC_ONE_UC_26_REG_DATA ((uint16_t)(0xFFUL << MXC_F_AFE_ADC_ONE_UC_26_REG_DATA_POS)) |
| |
| #define | MXC_F_AFE_ADC_ONE_UC_26_REG_ADDR_POS 8 |
| |
| #define | MXC_F_AFE_ADC_ONE_UC_26_REG_ADDR ((uint16_t)(0x7FUL << MXC_F_AFE_ADC_ONE_UC_26_REG_ADDR_POS)) |
| |
| #define | MXC_F_AFE_ADC_ONE_UC_27_REG_DATA_POS 0 |
| |
| #define | MXC_F_AFE_ADC_ONE_UC_27_REG_DATA ((uint16_t)(0xFFUL << MXC_F_AFE_ADC_ONE_UC_27_REG_DATA_POS)) |
| |
| #define | MXC_F_AFE_ADC_ONE_UC_27_REG_ADDR_POS 8 |
| |
| #define | MXC_F_AFE_ADC_ONE_UC_27_REG_ADDR ((uint16_t)(0x7FUL << MXC_F_AFE_ADC_ONE_UC_27_REG_ADDR_POS)) |
| |
| #define | MXC_F_AFE_ADC_ONE_UC_28_REG_DATA_POS 0 |
| |
| #define | MXC_F_AFE_ADC_ONE_UC_28_REG_DATA ((uint16_t)(0xFFUL << MXC_F_AFE_ADC_ONE_UC_28_REG_DATA_POS)) |
| |
| #define | MXC_F_AFE_ADC_ONE_UC_28_REG_ADDR_POS 8 |
| |
| #define | MXC_F_AFE_ADC_ONE_UC_28_REG_ADDR ((uint16_t)(0x7FUL << MXC_F_AFE_ADC_ONE_UC_28_REG_ADDR_POS)) |
| |
| #define | MXC_F_AFE_ADC_ONE_UC_29_REG_DATA_POS 0 |
| |
| #define | MXC_F_AFE_ADC_ONE_UC_29_REG_DATA ((uint16_t)(0xFFUL << MXC_F_AFE_ADC_ONE_UC_29_REG_DATA_POS)) |
| |
| #define | MXC_F_AFE_ADC_ONE_UC_29_REG_ADDR_POS 8 |
| |
| #define | MXC_F_AFE_ADC_ONE_UC_29_REG_ADDR ((uint16_t)(0x7FUL << MXC_F_AFE_ADC_ONE_UC_29_REG_ADDR_POS)) |
| |
| #define | MXC_F_AFE_ADC_ONE_UC_30_REG_DATA_POS 0 |
| |
| #define | MXC_F_AFE_ADC_ONE_UC_30_REG_DATA ((uint16_t)(0xFFUL << MXC_F_AFE_ADC_ONE_UC_30_REG_DATA_POS)) |
| |
| #define | MXC_F_AFE_ADC_ONE_UC_30_REG_ADDR_POS 8 |
| |
| #define | MXC_F_AFE_ADC_ONE_UC_30_REG_ADDR ((uint16_t)(0x7FUL << MXC_F_AFE_ADC_ONE_UC_30_REG_ADDR_POS)) |
| |
| #define | MXC_F_AFE_ADC_ONE_UC_31_REG_DATA_POS 0 |
| |
| #define | MXC_F_AFE_ADC_ONE_UC_31_REG_DATA ((uint16_t)(0xFFUL << MXC_F_AFE_ADC_ONE_UC_31_REG_DATA_POS)) |
| |
| #define | MXC_F_AFE_ADC_ONE_UC_31_REG_ADDR_POS 8 |
| |
| #define | MXC_F_AFE_ADC_ONE_UC_31_REG_ADDR ((uint16_t)(0x7FUL << MXC_F_AFE_ADC_ONE_UC_31_REG_ADDR_POS)) |
| |
| #define | MXC_F_AFE_ADC_ONE_UC_32_REG_DATA_POS 0 |
| |
| #define | MXC_F_AFE_ADC_ONE_UC_32_REG_DATA ((uint16_t)(0xFFUL << MXC_F_AFE_ADC_ONE_UC_32_REG_DATA_POS)) |
| |
| #define | MXC_F_AFE_ADC_ONE_UC_32_REG_ADDR_POS 8 |
| |
| #define | MXC_F_AFE_ADC_ONE_UC_32_REG_ADDR ((uint16_t)(0x7FUL << MXC_F_AFE_ADC_ONE_UC_32_REG_ADDR_POS)) |
| |
| #define | MXC_F_AFE_ADC_ONE_UC_33_REG_DATA_POS 0 |
| |
| #define | MXC_F_AFE_ADC_ONE_UC_33_REG_DATA ((uint16_t)(0xFFUL << MXC_F_AFE_ADC_ONE_UC_33_REG_DATA_POS)) |
| |
| #define | MXC_F_AFE_ADC_ONE_UC_33_REG_ADDR_POS 8 |
| |
| #define | MXC_F_AFE_ADC_ONE_UC_33_REG_ADDR ((uint16_t)(0x7FUL << MXC_F_AFE_ADC_ONE_UC_33_REG_ADDR_POS)) |
| |
| #define | MXC_F_AFE_ADC_ONE_UC_34_REG_DATA_POS 0 |
| |
| #define | MXC_F_AFE_ADC_ONE_UC_34_REG_DATA ((uint16_t)(0xFFUL << MXC_F_AFE_ADC_ONE_UC_34_REG_DATA_POS)) |
| |
| #define | MXC_F_AFE_ADC_ONE_UC_34_REG_ADDR_POS 8 |
| |
| #define | MXC_F_AFE_ADC_ONE_UC_34_REG_ADDR ((uint16_t)(0x7FUL << MXC_F_AFE_ADC_ONE_UC_34_REG_ADDR_POS)) |
| |
| #define | MXC_F_AFE_ADC_ONE_UC_35_REG_DATA_POS 0 |
| |
| #define | MXC_F_AFE_ADC_ONE_UC_35_REG_DATA ((uint16_t)(0xFFUL << MXC_F_AFE_ADC_ONE_UC_35_REG_DATA_POS)) |
| |
| #define | MXC_F_AFE_ADC_ONE_UC_35_REG_ADDR_POS 8 |
| |
| #define | MXC_F_AFE_ADC_ONE_UC_35_REG_ADDR ((uint16_t)(0x7FUL << MXC_F_AFE_ADC_ONE_UC_35_REG_ADDR_POS)) |
| |
| #define | MXC_F_AFE_ADC_ONE_UC_36_REG_DATA_POS 0 |
| |
| #define | MXC_F_AFE_ADC_ONE_UC_36_REG_DATA ((uint16_t)(0xFFUL << MXC_F_AFE_ADC_ONE_UC_36_REG_DATA_POS)) |
| |
| #define | MXC_F_AFE_ADC_ONE_UC_36_REG_ADDR_POS 8 |
| |
| #define | MXC_F_AFE_ADC_ONE_UC_36_REG_ADDR ((uint16_t)(0x7FUL << MXC_F_AFE_ADC_ONE_UC_36_REG_ADDR_POS)) |
| |
| #define | MXC_F_AFE_ADC_ONE_UC_37_REG_DATA_POS 0 |
| |
| #define | MXC_F_AFE_ADC_ONE_UC_37_REG_DATA ((uint16_t)(0xFFUL << MXC_F_AFE_ADC_ONE_UC_37_REG_DATA_POS)) |
| |
| #define | MXC_F_AFE_ADC_ONE_UC_37_REG_ADDR_POS 8 |
| |
| #define | MXC_F_AFE_ADC_ONE_UC_37_REG_ADDR ((uint16_t)(0x7FUL << MXC_F_AFE_ADC_ONE_UC_37_REG_ADDR_POS)) |
| |
| #define | MXC_F_AFE_ADC_ONE_UC_38_REG_DATA_POS 0 |
| |
| #define | MXC_F_AFE_ADC_ONE_UC_38_REG_DATA ((uint16_t)(0xFFUL << MXC_F_AFE_ADC_ONE_UC_38_REG_DATA_POS)) |
| |
| #define | MXC_F_AFE_ADC_ONE_UC_38_REG_ADDR_POS 8 |
| |
| #define | MXC_F_AFE_ADC_ONE_UC_38_REG_ADDR ((uint16_t)(0x7FUL << MXC_F_AFE_ADC_ONE_UC_38_REG_ADDR_POS)) |
| |
| #define | MXC_F_AFE_ADC_ONE_UC_39_REG_DATA_POS 0 |
| |
| #define | MXC_F_AFE_ADC_ONE_UC_39_REG_DATA ((uint16_t)(0xFFUL << MXC_F_AFE_ADC_ONE_UC_39_REG_DATA_POS)) |
| |
| #define | MXC_F_AFE_ADC_ONE_UC_39_REG_ADDR_POS 8 |
| |
| #define | MXC_F_AFE_ADC_ONE_UC_39_REG_ADDR ((uint16_t)(0x7FUL << MXC_F_AFE_ADC_ONE_UC_39_REG_ADDR_POS)) |
| |
| #define | MXC_F_AFE_ADC_ONE_UC_40_REG_DATA_POS 0 |
| |
| #define | MXC_F_AFE_ADC_ONE_UC_40_REG_DATA ((uint16_t)(0xFFUL << MXC_F_AFE_ADC_ONE_UC_40_REG_DATA_POS)) |
| |
| #define | MXC_F_AFE_ADC_ONE_UC_40_REG_ADDR_POS 8 |
| |
| #define | MXC_F_AFE_ADC_ONE_UC_40_REG_ADDR ((uint16_t)(0x7FUL << MXC_F_AFE_ADC_ONE_UC_40_REG_ADDR_POS)) |
| |
| #define | MXC_F_AFE_ADC_ONE_UC_41_REG_DATA_POS 0 |
| |
| #define | MXC_F_AFE_ADC_ONE_UC_41_REG_DATA ((uint16_t)(0xFFUL << MXC_F_AFE_ADC_ONE_UC_41_REG_DATA_POS)) |
| |
| #define | MXC_F_AFE_ADC_ONE_UC_41_REG_ADDR_POS 8 |
| |
| #define | MXC_F_AFE_ADC_ONE_UC_41_REG_ADDR ((uint16_t)(0x7FUL << MXC_F_AFE_ADC_ONE_UC_41_REG_ADDR_POS)) |
| |
| #define | MXC_F_AFE_ADC_ONE_UC_42_REG_DATA_POS 0 |
| |
| #define | MXC_F_AFE_ADC_ONE_UC_42_REG_DATA ((uint16_t)(0xFFUL << MXC_F_AFE_ADC_ONE_UC_42_REG_DATA_POS)) |
| |
| #define | MXC_F_AFE_ADC_ONE_UC_42_REG_ADDR_POS 8 |
| |
| #define | MXC_F_AFE_ADC_ONE_UC_42_REG_ADDR ((uint16_t)(0x7FUL << MXC_F_AFE_ADC_ONE_UC_42_REG_ADDR_POS)) |
| |
| #define | MXC_F_AFE_ADC_ONE_UC_43_REG_DATA_POS 0 |
| |
| #define | MXC_F_AFE_ADC_ONE_UC_43_REG_DATA ((uint16_t)(0xFFUL << MXC_F_AFE_ADC_ONE_UC_43_REG_DATA_POS)) |
| |
| #define | MXC_F_AFE_ADC_ONE_UC_43_REG_ADDR_POS 8 |
| |
| #define | MXC_F_AFE_ADC_ONE_UC_43_REG_ADDR ((uint16_t)(0x7FUL << MXC_F_AFE_ADC_ONE_UC_43_REG_ADDR_POS)) |
| |
| #define | MXC_F_AFE_ADC_ONE_UC_44_REG_DATA_POS 0 |
| |
| #define | MXC_F_AFE_ADC_ONE_UC_44_REG_DATA ((uint16_t)(0xFFUL << MXC_F_AFE_ADC_ONE_UC_44_REG_DATA_POS)) |
| |
| #define | MXC_F_AFE_ADC_ONE_UC_44_REG_ADDR_POS 8 |
| |
| #define | MXC_F_AFE_ADC_ONE_UC_44_REG_ADDR ((uint16_t)(0x7FUL << MXC_F_AFE_ADC_ONE_UC_44_REG_ADDR_POS)) |
| |
| #define | MXC_F_AFE_ADC_ONE_UC_45_REG_DATA_POS 0 |
| |
| #define | MXC_F_AFE_ADC_ONE_UC_45_REG_DATA ((uint16_t)(0xFFUL << MXC_F_AFE_ADC_ONE_UC_45_REG_DATA_POS)) |
| |
| #define | MXC_F_AFE_ADC_ONE_UC_45_REG_ADDR_POS 8 |
| |
| #define | MXC_F_AFE_ADC_ONE_UC_45_REG_ADDR ((uint16_t)(0x7FUL << MXC_F_AFE_ADC_ONE_UC_45_REG_ADDR_POS)) |
| |
| #define | MXC_F_AFE_ADC_ONE_UC_46_REG_DATA_POS 0 |
| |
| #define | MXC_F_AFE_ADC_ONE_UC_46_REG_DATA ((uint16_t)(0xFFUL << MXC_F_AFE_ADC_ONE_UC_46_REG_DATA_POS)) |
| |
| #define | MXC_F_AFE_ADC_ONE_UC_46_REG_ADDR_POS 8 |
| |
| #define | MXC_F_AFE_ADC_ONE_UC_46_REG_ADDR ((uint16_t)(0x7FUL << MXC_F_AFE_ADC_ONE_UC_46_REG_ADDR_POS)) |
| |
| #define | MXC_F_AFE_ADC_ONE_UC_47_REG_DATA_POS 0 |
| |
| #define | MXC_F_AFE_ADC_ONE_UC_47_REG_DATA ((uint16_t)(0xFFUL << MXC_F_AFE_ADC_ONE_UC_47_REG_DATA_POS)) |
| |
| #define | MXC_F_AFE_ADC_ONE_UC_47_REG_ADDR_POS 8 |
| |
| #define | MXC_F_AFE_ADC_ONE_UC_47_REG_ADDR ((uint16_t)(0x7FUL << MXC_F_AFE_ADC_ONE_UC_47_REG_ADDR_POS)) |
| |
| #define | MXC_F_AFE_ADC_ONE_UC_48_REG_DATA_POS 0 |
| |
| #define | MXC_F_AFE_ADC_ONE_UC_48_REG_DATA ((uint16_t)(0xFFUL << MXC_F_AFE_ADC_ONE_UC_48_REG_DATA_POS)) |
| |
| #define | MXC_F_AFE_ADC_ONE_UC_48_REG_ADDR_POS 8 |
| |
| #define | MXC_F_AFE_ADC_ONE_UC_48_REG_ADDR ((uint16_t)(0x7FUL << MXC_F_AFE_ADC_ONE_UC_48_REG_ADDR_POS)) |
| |
| #define | MXC_F_AFE_ADC_ONE_UC_49_REG_DATA_POS 0 |
| |
| #define | MXC_F_AFE_ADC_ONE_UC_49_REG_DATA ((uint16_t)(0xFFUL << MXC_F_AFE_ADC_ONE_UC_49_REG_DATA_POS)) |
| |
| #define | MXC_F_AFE_ADC_ONE_UC_49_REG_ADDR_POS 8 |
| |
| #define | MXC_F_AFE_ADC_ONE_UC_49_REG_ADDR ((uint16_t)(0x7FUL << MXC_F_AFE_ADC_ONE_UC_49_REG_ADDR_POS)) |
| |
| #define | MXC_F_AFE_ADC_ONE_UC_50_REG_DATA_POS 0 |
| |
| #define | MXC_F_AFE_ADC_ONE_UC_50_REG_DATA ((uint16_t)(0xFFUL << MXC_F_AFE_ADC_ONE_UC_50_REG_DATA_POS)) |
| |
| #define | MXC_F_AFE_ADC_ONE_UC_50_REG_ADDR_POS 8 |
| |
| #define | MXC_F_AFE_ADC_ONE_UC_50_REG_ADDR ((uint16_t)(0x7FUL << MXC_F_AFE_ADC_ONE_UC_50_REG_ADDR_POS)) |
| |
| #define | MXC_F_AFE_ADC_ONE_UC_51_REG_DATA_POS 0 |
| |
| #define | MXC_F_AFE_ADC_ONE_UC_51_REG_DATA ((uint16_t)(0xFFUL << MXC_F_AFE_ADC_ONE_UC_51_REG_DATA_POS)) |
| |
| #define | MXC_F_AFE_ADC_ONE_UC_51_REG_ADDR_POS 8 |
| |
| #define | MXC_F_AFE_ADC_ONE_UC_51_REG_ADDR ((uint16_t)(0x7FUL << MXC_F_AFE_ADC_ONE_UC_51_REG_ADDR_POS)) |
| |
| #define | MXC_F_AFE_ADC_ONE_UC_52_REG_DATA_POS 0 |
| |
| #define | MXC_F_AFE_ADC_ONE_UC_52_REG_DATA ((uint16_t)(0xFFUL << MXC_F_AFE_ADC_ONE_UC_52_REG_DATA_POS)) |
| |
| #define | MXC_F_AFE_ADC_ONE_UC_52_REG_ADDR_POS 8 |
| |
| #define | MXC_F_AFE_ADC_ONE_UC_52_REG_ADDR ((uint16_t)(0x7FUL << MXC_F_AFE_ADC_ONE_UC_52_REG_ADDR_POS)) |
| |
| #define | MXC_F_AFE_ADC_ONE_UCADDR_UCADDR_POS 0 |
| |
| #define | MXC_F_AFE_ADC_ONE_UCADDR_UCADDR ((uint8_t)(0x7FUL << MXC_F_AFE_ADC_ONE_UCADDR_UCADDR_POS)) |
| |
| #define | MXC_F_AFE_ADC_ONE_FT_PWORD_FT_PWORD_POS 0 |
| |
| #define | MXC_F_AFE_ADC_ONE_FT_PWORD_FT_PWORD ((uint8_t)(0x7FUL << MXC_F_AFE_ADC_ONE_FT_PWORD_FT_PWORD_POS)) |
| |
| #define | MXC_V_AFE_ADC_ONE_FT_PWORD_FT_PWORD_PWORD_1 ((uint8_t)0x48UL) |
| |
| #define | MXC_S_AFE_ADC_ONE_FT_PWORD_FT_PWORD_PWORD_1 (MXC_V_AFE_ADC_ONE_FT_PWORD_FT_PWORD_PWORD_1 << MXC_F_AFE_ADC_ONE_FT_PWORD_FT_PWORD_POS) |
| |
| #define | MXC_V_AFE_ADC_ONE_FT_PWORD_FT_PWORD_PWORD_2 ((uint8_t)0x7BUL) |
| |
| #define | MXC_S_AFE_ADC_ONE_FT_PWORD_FT_PWORD_PWORD_2 (MXC_V_AFE_ADC_ONE_FT_PWORD_FT_PWORD_PWORD_2 << MXC_F_AFE_ADC_ONE_FT_PWORD_FT_PWORD_POS) |
| |
| #define | MXC_F_AFE_ADC_ONE_ADC_TRIM0_VGB_TRIM_POS 0 |
| |
| #define | MXC_F_AFE_ADC_ONE_ADC_TRIM0_VGB_TRIM ((uint32_t)(0x3FUL << MXC_F_AFE_ADC_ONE_ADC_TRIM0_VGB_TRIM_POS)) |
| |
| #define | MXC_F_AFE_ADC_ONE_ADC_TRIM0_IP_TRIM_POS 6 |
| |
| #define | MXC_F_AFE_ADC_ONE_ADC_TRIM0_IP_TRIM ((uint32_t)(0x1FUL << MXC_F_AFE_ADC_ONE_ADC_TRIM0_IP_TRIM_POS)) |
| |
| #define | MXC_F_AFE_ADC_ONE_ADC_TRIM0_IB_TRIM_POS 11 |
| |
| #define | MXC_F_AFE_ADC_ONE_ADC_TRIM0_IB_TRIM ((uint32_t)(0x3FUL << MXC_F_AFE_ADC_ONE_ADC_TRIM0_IB_TRIM_POS)) |
| |
| #define | MXC_F_AFE_ADC_ONE_ADC_TRIM0_CLKSKEW_POS 17 |
| |
| #define | MXC_F_AFE_ADC_ONE_ADC_TRIM0_CLKSKEW ((uint32_t)(0x3UL << MXC_F_AFE_ADC_ONE_ADC_TRIM0_CLKSKEW_POS)) |
| |
| #define | MXC_F_AFE_ADC_ONE_ADC_TRIM1_IDAC0_TRIM_POS 0 |
| |
| #define | MXC_F_AFE_ADC_ONE_ADC_TRIM1_IDAC0_TRIM ((uint16_t)(0x7FUL << MXC_F_AFE_ADC_ONE_ADC_TRIM1_IDAC0_TRIM_POS)) |
| |
| #define | MXC_F_AFE_ADC_ONE_ADC_TRIM1_IDAC1_TRIM_POS 7 |
| |
| #define | MXC_F_AFE_ADC_ONE_ADC_TRIM1_IDAC1_TRIM ((uint16_t)(0x7FUL << MXC_F_AFE_ADC_ONE_ADC_TRIM1_IDAC1_TRIM_POS)) |
| |
| #define | MXC_F_AFE_ADC_ONE_ANA_TRIM_LDO_TRIM_POS 0 |
| |
| #define | MXC_F_AFE_ADC_ONE_ANA_TRIM_LDO_TRIM ((uint16_t)(0xFUL << MXC_F_AFE_ADC_ONE_ANA_TRIM_LDO_TRIM_POS)) |
| |
| #define | MXC_F_AFE_ADC_ONE_ANA_TRIM_OSC_TRIM_POS 4 |
| |
| #define | MXC_F_AFE_ADC_ONE_ANA_TRIM_OSC_TRIM ((uint16_t)(0x3FUL << MXC_F_AFE_ADC_ONE_ANA_TRIM_OSC_TRIM_POS)) |
| |
| #define | MXC_F_AFE_ADC_ONE_ANA_TRIM_OSC_FSEL_POS 10 |
| |
| #define | MXC_F_AFE_ADC_ONE_ANA_TRIM_OSC_FSEL ((uint16_t)(0x3UL << MXC_F_AFE_ADC_ONE_ANA_TRIM_OSC_FSEL_POS)) |
| |
| #define | MXC_F_AFE_ADC_ONE_ANA_TRIM_PKG_TRIM_POS 12 |
| |
| #define | MXC_F_AFE_ADC_ONE_ANA_TRIM_PKG_TRIM ((uint16_t)(0x3UL << MXC_F_AFE_ADC_ONE_ANA_TRIM_PKG_TRIM_POS)) |
| |
| #define | MXC_F_AFE_ADC_ONE_ANA_TRIM_RES_TRIM_POS 14 |
| |
| #define | MXC_F_AFE_ADC_ONE_ANA_TRIM_RES_TRIM ((uint16_t)(0x1UL << MXC_F_AFE_ADC_ONE_ANA_TRIM_RES_TRIM_POS)) |
| |
| #define | MXC_F_AFE_ADC_ONE_SYS_CTRL_ANA_SRC_SEL_POS 0 |
| |
| #define | MXC_F_AFE_ADC_ONE_SYS_CTRL_ANA_SRC_SEL ((uint8_t)(0x3UL << MXC_F_AFE_ADC_ONE_SYS_CTRL_ANA_SRC_SEL_POS)) |
| |
| #define | MXC_V_AFE_ADC_ONE_SYS_CTRL_ANA_SRC_SEL_ADC0_BANK ((uint8_t)0x0UL) |
| |
| #define | MXC_S_AFE_ADC_ONE_SYS_CTRL_ANA_SRC_SEL_ADC0_BANK (MXC_V_AFE_ADC_ONE_SYS_CTRL_ANA_SRC_SEL_ADC0_BANK << MXC_F_AFE_ADC_ONE_SYS_CTRL_ANA_SRC_SEL_POS) |
| |
| #define | MXC_V_AFE_ADC_ONE_SYS_CTRL_ANA_SRC_SEL_ADC1_BANK ((uint8_t)0x1UL) |
| |
| #define | MXC_S_AFE_ADC_ONE_SYS_CTRL_ANA_SRC_SEL_ADC1_BANK (MXC_V_AFE_ADC_ONE_SYS_CTRL_ANA_SRC_SEL_ADC1_BANK << MXC_F_AFE_ADC_ONE_SYS_CTRL_ANA_SRC_SEL_POS) |
| |
| #define | MXC_V_AFE_ADC_ONE_SYS_CTRL_ANA_SRC_SEL_DAC12_BANK ((uint8_t)0x2UL) |
| |
| #define | MXC_S_AFE_ADC_ONE_SYS_CTRL_ANA_SRC_SEL_DAC12_BANK (MXC_V_AFE_ADC_ONE_SYS_CTRL_ANA_SRC_SEL_DAC12_BANK << MXC_F_AFE_ADC_ONE_SYS_CTRL_ANA_SRC_SEL_POS) |
| |
| #define | MXC_V_AFE_ADC_ONE_SYS_CTRL_ANA_SRC_SEL_HART_BANK ((uint8_t)0x3UL) |
| |
| #define | MXC_S_AFE_ADC_ONE_SYS_CTRL_ANA_SRC_SEL_HART_BANK (MXC_V_AFE_ADC_ONE_SYS_CTRL_ANA_SRC_SEL_HART_BANK << MXC_F_AFE_ADC_ONE_SYS_CTRL_ANA_SRC_SEL_POS) |
| |
| #define | MXC_F_AFE_ADC_ONE_SYS_CTRL_CRC5_POS 2 |
| |
| #define | MXC_F_AFE_ADC_ONE_SYS_CTRL_CRC5 ((uint8_t)(0x1UL << MXC_F_AFE_ADC_ONE_SYS_CTRL_CRC5_POS)) |
| |
| #define | MXC_F_AFE_ADC_ONE_SYS_CTRL_ST_DIS_POS 3 |
| |
| #define | MXC_F_AFE_ADC_ONE_SYS_CTRL_ST_DIS ((uint8_t)(0x1UL << MXC_F_AFE_ADC_ONE_SYS_CTRL_ST_DIS_POS)) |
| |
| #define | MXC_F_AFE_ADC_ONE_SYS_CTRL_HART_EN_POS 4 |
| |
| #define | MXC_F_AFE_ADC_ONE_SYS_CTRL_HART_EN ((uint8_t)(0x1UL << MXC_F_AFE_ADC_ONE_SYS_CTRL_HART_EN_POS)) |
| |
| #define | MXC_F_AFE_ADC_ONE_SYS_CTRL_SPI_ABORT_DIS_POS 5 |
| |
| #define | MXC_F_AFE_ADC_ONE_SYS_CTRL_SPI_ABORT_DIS ((uint8_t)(0x1UL << MXC_F_AFE_ADC_ONE_SYS_CTRL_SPI_ABORT_DIS_POS)) |
| |
| #define | MXC_F_AFE_ADC_ONE_SYS_CTRL_POR_FLAG_POS 6 |
| |
| #define | MXC_F_AFE_ADC_ONE_SYS_CTRL_POR_FLAG ((uint8_t)(0x1UL << MXC_F_AFE_ADC_ONE_SYS_CTRL_POR_FLAG_POS)) |
| |
| #define | MXC_F_AFE_ADC_ONE_SYS_CTRL_CRC_INV_POS 7 |
| |
| #define | MXC_F_AFE_ADC_ONE_SYS_CTRL_CRC_INV ((uint8_t)(0x1UL << MXC_F_AFE_ADC_ONE_SYS_CTRL_CRC_INV_POS)) |
| |
1.9.4