MAX32680 Peripheral Driver API
Peripheral Driver API for the MAX32680
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spi.h
1
6/******************************************************************************
7 *
8 * Copyright (C) 2022-2023 Maxim Integrated Products, Inc. (now owned by
9 * Analog Devices, Inc.),
10 * Copyright (C) 2023-2024 Analog Devices, Inc.
11 *
12 * Licensed under the Apache License, Version 2.0 (the "License");
13 * you may not use this file except in compliance with the License.
14 * You may obtain a copy of the License at
15 *
16 * http://www.apache.org/licenses/LICENSE-2.0
17 *
18 * Unless required by applicable law or agreed to in writing, software
19 * distributed under the License is distributed on an "AS IS" BASIS,
20 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
21 * See the License for the specific language governing permissions and
22 * limitations under the License.
23 *
24 ******************************************************************************/
25#ifndef LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32680_SPI_H_
26#define LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32680_SPI_H_
27
28/***** includes *******/
29#include <stdbool.h>
30#include "spi_regs.h"
31#include "mxc_sys.h"
32#include "mxc_assert.h"
33#include "gpio.h"
34#include "mxc_pins.h"
35#include "mxc_lock.h"
36
37#ifdef __cplusplus
38extern "C" {
39#endif
40
47/***** Definitions *****/
48
69typedef enum {
75
87typedef enum {
93
94typedef struct _mxc_spi_pins_t mxc_spi_pins_t;
95
104 bool clock;
105 bool ss0;
106 bool ss1;
107 bool ss2;
108 bool miso;
109 bool mosi;
110 bool sdio2;
111 bool sdio3;
112 bool vddioh;
113};
114
115typedef struct _mxc_spi_req_t mxc_spi_req_t;
122typedef void (*spi_complete_cb_t)(void *req, int result);
123
132 int ssIdx;
134 uint8_t *txData;
138 uint8_t *rxData;
142 uint32_t txLen;
143 uint32_t rxLen;
144 uint32_t txCnt;
145 uint32_t rxCnt;
146
148};
149
150/* ************************************************************************* */
151/* Control/Configuration functions */
152/* ************************************************************************* */
153
190int MXC_SPI_Init(mxc_spi_regs_t *spi, int masterMode, int quadModeUsed, int numSlaves,
191 unsigned ssPolarity, unsigned int hz, mxc_spi_pins_t pins);
192
201
215
224
236int MXC_SPI_SetFrequency(mxc_spi_regs_t *spi, unsigned int hz);
237
248
257int MXC_SPI_SetDataSize(mxc_spi_regs_t *spi, int dataSize);
258
267
268/* ************************************************************************* */
269/* Low-level functions */
270/* ************************************************************************* */
271
282int MXC_SPI_SetSlave(mxc_spi_regs_t *spi, int ssIdx);
283
294
304
313
323
332
346
357
368
378unsigned int MXC_SPI_ReadRXFIFO(mxc_spi_regs_t *spi, unsigned char *bytes, unsigned int len);
379
388
398unsigned int MXC_SPI_WriteTXFIFO(mxc_spi_regs_t *spi, unsigned char *bytes, unsigned int len);
399
408
415
422
440int MXC_SPI_SetRXThreshold(mxc_spi_regs_t *spi, unsigned int numBytes);
441
450
468int MXC_SPI_SetTXThreshold(mxc_spi_regs_t *spi, unsigned int numBytes);
469
478
490
501
511void MXC_SPI_EnableInt(mxc_spi_regs_t *spi, unsigned int intEn);
512
522void MXC_SPI_DisableInt(mxc_spi_regs_t *spi, unsigned int intDis);
523
524/* ************************************************************************* */
525/* Transaction level functions */
526/* ************************************************************************* */
527
551int MXC_SPI_MasterTransaction(mxc_spi_req_t *req);
552
563int MXC_SPI_MasterTransactionAsync(mxc_spi_req_t *req);
564
580int MXC_SPI_MasterTransactionDMA(mxc_spi_req_t *req);
581
597int MXC_SPI_SlaveTransaction(mxc_spi_req_t *req);
598
609int MXC_SPI_SlaveTransactionAsync(mxc_spi_req_t *req);
610
626int MXC_SPI_SlaveTransactionDMA(mxc_spi_req_t *req);
627
639int MXC_SPI_SetDefaultTXData(mxc_spi_regs_t *spi, unsigned int defaultTXData);
640
651
662
674
677#ifdef __cplusplus
678}
679#endif
680
681#endif // LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32680_SPI_H_
Definition: spi_regs.h:76
uint8_t * txData
Definition: spi.h:134
uint32_t rxLen
Number of bytes to be stored in rxData.
Definition: spi.h:143
bool sdio2
SDIO2 pin.
Definition: spi.h:110
bool ss0
Slave select pin 0.
Definition: spi.h:105
bool vddioh
VDDIOH Select.
Definition: spi.h:112
uint32_t rxCnt
Number of bytes stored in rxData.
Definition: spi.h:145
int ssIdx
Slave select line to use (Master only, ignored in slave mode)
Definition: spi.h:132
bool sdio3
SDIO3 pin.
Definition: spi.h:111
mxc_spi_regs_t * spi
Point to SPI registers.
Definition: spi.h:131
bool miso
miso pin
Definition: spi.h:108
bool clock
Clock pin.
Definition: spi.h:104
bool mosi
mosi pin
Definition: spi.h:109
spi_complete_cb_t completeCB
Pointer to function called when transaction is complete.
Definition: spi.h:147
uint32_t txCnt
Number of bytes actually transmitted from txData.
Definition: spi.h:144
uint8_t * rxData
Definition: spi.h:138
uint32_t txLen
Number of bytes to be sent from txData.
Definition: spi.h:142
int ssDeassert
1 - Deassert SS at end of transaction, 0 - leave SS asserted
Definition: spi.h:133
bool ss2
Slave select pin 2.
Definition: spi.h:107
bool ss1
Slave select pin 1.
Definition: spi.h:106
int MXC_SPI_SetFrequency(mxc_spi_regs_t *spi, unsigned int hz)
Set the frequency of the SPI interface.
unsigned int MXC_SPI_GetFlags(mxc_spi_regs_t *spi)
Gets the interrupt flags that are currently set.
int MXC_SPI_GetSlave(mxc_spi_regs_t *spi)
Gets the slave select (SS) line used for transmissions.
unsigned int MXC_SPI_GetTXFIFOAvailable(mxc_spi_regs_t *spi)
Get the amount of free space available in the transmit FIFO.
void MXC_SPI_EnableInt(mxc_spi_regs_t *spi, unsigned int intEn)
Enables specific interrupts.
void MXC_SPI_ClearFlags(mxc_spi_regs_t *spi)
Clears the interrupt flags that are currently set.
unsigned int MXC_SPI_ReadRXFIFO(mxc_spi_regs_t *spi, unsigned char *bytes, unsigned int len)
Unloads bytes from the receive FIFO.
int MXC_SPI_SetRXThreshold(mxc_spi_regs_t *spi, unsigned int numBytes)
Set the receive threshold level.
int MXC_SPI_SetWidth(mxc_spi_regs_t *spi, mxc_spi_width_t spiWidth)
Sets the SPI width used for transmissions.
int MXC_SPI_SetSlave(mxc_spi_regs_t *spi, int ssIdx)
Sets the slave select (SS) line used for transmissions.
int MXC_SPI_GetDataSize(mxc_spi_regs_t *spi)
Gets the number of bits per character.
unsigned int MXC_SPI_GetTXThreshold(mxc_spi_regs_t *spi)
Get the current transmit threshold level.
int MXC_SPI_GetPeripheralClock(mxc_spi_regs_t *spi)
Returns the frequency of the clock used as the bit rate generator for a given SPI instance.
int MXC_SPI_SetDataSize(mxc_spi_regs_t *spi, int dataSize)
Sets the number of bits per character.
int MXC_SPI_ReadyForSleep(mxc_spi_regs_t *spi)
Checks if the given SPI bus can be placed in sleep mode.
mxc_spi_mode_t MXC_SPI_GetMode(mxc_spi_regs_t *spi)
Gets the spi mode.
unsigned int MXC_SPI_GetRXFIFOAvailable(mxc_spi_regs_t *spi)
Get the number of bytes currently available in the receive FIFO.
mxc_spi_mode_t
The list of SPI modes.
Definition: spi.h:87
int MXC_SPI_SlaveTransactionAsync(mxc_spi_req_t *req)
Setup an interrupt-driven SPI transaction.
unsigned int MXC_SPI_GetFrequency(mxc_spi_regs_t *spi)
Get the frequency of the SPI interface.
void MXC_SPI_ClearTXFIFO(mxc_spi_regs_t *spi)
Removes and discards all bytes currently in the transmit FIFO.
int MXC_SPI_MasterTransactionAsync(mxc_spi_req_t *req)
Setup an interrupt-driven SPI transaction.
mxc_spi_width_t
The list of SPI Widths supported.
Definition: spi.h:69
int MXC_SPI_SetTXThreshold(mxc_spi_regs_t *spi, unsigned int numBytes)
Set the transmit threshold level.
int MXC_SPI_Init(mxc_spi_regs_t *spi, int masterMode, int quadModeUsed, int numSlaves, unsigned ssPolarity, unsigned int hz, mxc_spi_pins_t pins)
Initialize and enable SPI peripheral.
int MXC_SPI_Shutdown(mxc_spi_regs_t *spi)
Disable and shutdown SPI peripheral.
int MXC_SPI_SlaveTransactionDMA(mxc_spi_req_t *req)
Setup a DMA driven SPI transaction.
mxc_spi_width_t MXC_SPI_GetWidth(mxc_spi_regs_t *spi)
Gets the SPI width used for transmissions.
int MXC_SPI_SlaveTransaction(mxc_spi_req_t *req)
Performs a blocking SPI transaction.
int MXC_SPI_SetMode(mxc_spi_regs_t *spi, mxc_spi_mode_t spiMode)
Sets the spi mode using clock polarity and clock phase.
void MXC_SPI_AsyncHandler(mxc_spi_regs_t *spi)
The processing function for asynchronous transactions.
int MXC_SPI_GetActive(mxc_spi_regs_t *spi)
Checks the SPI Peripheral for an ongoing transmission.
void MXC_SPI_ClearRXFIFO(mxc_spi_regs_t *spi)
Removes and discards all bytes currently in the receive FIFO.
int MXC_SPI_AbortTransmission(mxc_spi_regs_t *spi)
Aborts an ongoing SPI Transmission.
void MXC_SPI_DisableInt(mxc_spi_regs_t *spi, unsigned int intDis)
Disables specific interrupts.
unsigned int MXC_SPI_WriteTXFIFO(mxc_spi_regs_t *spi, unsigned char *bytes, unsigned int len)
Loads bytes into the transmit FIFO.
int MXC_SPI_SetDefaultTXData(mxc_spi_regs_t *spi, unsigned int defaultTXData)
Sets the TX data to transmit as a 'dummy' byte.
void MXC_SPI_AbortAsync(mxc_spi_regs_t *spi)
Abort any asynchronous requests in progress.
unsigned int MXC_SPI_GetRXThreshold(mxc_spi_regs_t *spi)
Get the current receive threshold level.
int MXC_SPI_StartTransmission(mxc_spi_regs_t *spi)
Starts a SPI Transmission.
int MXC_SPI_MasterTransactionDMA(mxc_spi_req_t *req)
Setup a DMA driven SPI transaction.
int MXC_SPI_MasterTransaction(mxc_spi_req_t *req)
Performs a blocking SPI transaction.
void(* spi_complete_cb_t)(void *req, int result)
The callback routine used to indicate the transaction has terminated.
Definition: spi.h:122
void MXC_SPI_HWSSControl(mxc_spi_regs_t *spi, int state)
Enable/Disable HW CS control feature.
@ SPI_MODE_0
clock phase = 0, clock polarity = 0
Definition: spi.h:88
@ SPI_MODE_2
clock phase = 1, clock polarity = 0
Definition: spi.h:90
@ SPI_MODE_1
clock phase = 0, clock polarity = 1
Definition: spi.h:89
@ SPI_MODE_3
clock phase = 1, clock polarity = 1
Definition: spi.h:91
@ SPI_WIDTH_QUAD
4 Data lines, half duplex
Definition: spi.h:73
@ SPI_WIDTH_STANDARD
MISO/MOSI, full duplex.
Definition: spi.h:71
@ SPI_WIDTH_3WIRE
1 Data line, half duplex
Definition: spi.h:70
@ SPI_WIDTH_DUAL
2 Data lines, half duplex
Definition: spi.h:72
Structure used to initialize SPI pins.
Definition: spi.h:103
The information required to perform a complete SPI transaction.
Definition: spi.h:130
Registers, Bit Masks and Bit Positions for the SPI Peripheral Module.