ADC_INTEN

Macros
#define	MXC_F_ADC_INTEN_READY_POS   0
#define	MXC_F_ADC_INTEN_READY   ((uint32_t)(0x1UL << MXC_F_ADC_INTEN_READY_POS))
#define	MXC_F_ADC_INTEN_ABORT_POS   2
#define	MXC_F_ADC_INTEN_ABORT   ((uint32_t)(0x1UL << MXC_F_ADC_INTEN_ABORT_POS))
#define	MXC_F_ADC_INTEN_START_DET_POS   3
#define	MXC_F_ADC_INTEN_START_DET   ((uint32_t)(0x1UL << MXC_F_ADC_INTEN_START_DET_POS))
#define	MXC_F_ADC_INTEN_SEQ_STARTED_POS   4
#define	MXC_F_ADC_INTEN_SEQ_STARTED   ((uint32_t)(0x1UL << MXC_F_ADC_INTEN_SEQ_STARTED_POS))
#define	MXC_F_ADC_INTEN_SEQ_DONE_POS   5
#define	MXC_F_ADC_INTEN_SEQ_DONE   ((uint32_t)(0x1UL << MXC_F_ADC_INTEN_SEQ_DONE_POS))
#define	MXC_F_ADC_INTEN_CONV_DONE_POS   6
#define	MXC_F_ADC_INTEN_CONV_DONE   ((uint32_t)(0x1UL << MXC_F_ADC_INTEN_CONV_DONE_POS))
#define	MXC_F_ADC_INTEN_CLIPPED_POS   7
#define	MXC_F_ADC_INTEN_CLIPPED   ((uint32_t)(0x1UL << MXC_F_ADC_INTEN_CLIPPED_POS))
#define	MXC_F_ADC_INTEN_FIFO_LVL_POS   8
#define	MXC_F_ADC_INTEN_FIFO_LVL   ((uint32_t)(0x1UL << MXC_F_ADC_INTEN_FIFO_LVL_POS))
#define	MXC_F_ADC_INTEN_FIFO_UFL_POS   9
#define	MXC_F_ADC_INTEN_FIFO_UFL   ((uint32_t)(0x1UL << MXC_F_ADC_INTEN_FIFO_UFL_POS))
#define	MXC_F_ADC_INTEN_FIFO_OFL_POS   10
#define	MXC_F_ADC_INTEN_FIFO_OFL   ((uint32_t)(0x1UL << MXC_F_ADC_INTEN_FIFO_OFL_POS))

Detailed Description

Interrupt Enable Register.

Macro Definition Documentation

MXC_F_ADC_INTEN_ABORT

#define MXC_F_ADC_INTEN_ABORT   ((uint32_t)(0x1UL << MXC_F_ADC_INTEN_ABORT_POS))

INTEN_ABORT Mask

MXC_F_ADC_INTEN_ABORT_POS

#define MXC_F_ADC_INTEN_ABORT_POS   2

INTEN_ABORT Position

MXC_F_ADC_INTEN_CLIPPED

#define MXC_F_ADC_INTEN_CLIPPED   ((uint32_t)(0x1UL << MXC_F_ADC_INTEN_CLIPPED_POS))

INTEN_CLIPPED Mask

MXC_F_ADC_INTEN_CLIPPED_POS

#define MXC_F_ADC_INTEN_CLIPPED_POS   7

INTEN_CLIPPED Position

MXC_F_ADC_INTEN_CONV_DONE

#define MXC_F_ADC_INTEN_CONV_DONE   ((uint32_t)(0x1UL << MXC_F_ADC_INTEN_CONV_DONE_POS))

INTEN_CONV_DONE Mask

MXC_F_ADC_INTEN_CONV_DONE_POS

#define MXC_F_ADC_INTEN_CONV_DONE_POS   6

INTEN_CONV_DONE Position

MXC_F_ADC_INTEN_FIFO_LVL

#define MXC_F_ADC_INTEN_FIFO_LVL   ((uint32_t)(0x1UL << MXC_F_ADC_INTEN_FIFO_LVL_POS))

INTEN_FIFO_LVL Mask

MXC_F_ADC_INTEN_FIFO_LVL_POS

#define MXC_F_ADC_INTEN_FIFO_LVL_POS   8

INTEN_FIFO_LVL Position

MXC_F_ADC_INTEN_FIFO_OFL

#define MXC_F_ADC_INTEN_FIFO_OFL   ((uint32_t)(0x1UL << MXC_F_ADC_INTEN_FIFO_OFL_POS))

INTEN_FIFO_OFL Mask

MXC_F_ADC_INTEN_FIFO_OFL_POS

#define MXC_F_ADC_INTEN_FIFO_OFL_POS   10

INTEN_FIFO_OFL Position

MXC_F_ADC_INTEN_FIFO_UFL

#define MXC_F_ADC_INTEN_FIFO_UFL   ((uint32_t)(0x1UL << MXC_F_ADC_INTEN_FIFO_UFL_POS))

INTEN_FIFO_UFL Mask

MXC_F_ADC_INTEN_FIFO_UFL_POS

#define MXC_F_ADC_INTEN_FIFO_UFL_POS   9

INTEN_FIFO_UFL Position

MXC_F_ADC_INTEN_READY

#define MXC_F_ADC_INTEN_READY   ((uint32_t)(0x1UL << MXC_F_ADC_INTEN_READY_POS))

INTEN_READY Mask

MXC_F_ADC_INTEN_READY_POS

#define MXC_F_ADC_INTEN_READY_POS   0

INTEN_READY Position

MXC_F_ADC_INTEN_SEQ_DONE

#define MXC_F_ADC_INTEN_SEQ_DONE   ((uint32_t)(0x1UL << MXC_F_ADC_INTEN_SEQ_DONE_POS))

INTEN_SEQ_DONE Mask

MXC_F_ADC_INTEN_SEQ_DONE_POS

#define MXC_F_ADC_INTEN_SEQ_DONE_POS   5

INTEN_SEQ_DONE Position

MXC_F_ADC_INTEN_SEQ_STARTED

#define MXC_F_ADC_INTEN_SEQ_STARTED   ((uint32_t)(0x1UL << MXC_F_ADC_INTEN_SEQ_STARTED_POS))

INTEN_SEQ_STARTED Mask

MXC_F_ADC_INTEN_SEQ_STARTED_POS

#define MXC_F_ADC_INTEN_SEQ_STARTED_POS   4

INTEN_SEQ_STARTED Position

MXC_F_ADC_INTEN_START_DET

#define MXC_F_ADC_INTEN_START_DET   ((uint32_t)(0x1UL << MXC_F_ADC_INTEN_START_DET_POS))

INTEN_START_DET Mask

MXC_F_ADC_INTEN_START_DET_POS

#define MXC_F_ADC_INTEN_START_DET_POS   3

INTEN_START_DET Position