CAN_INTEN

Macros
#define	MXC_F_CAN_INTEN_DOR_POS   0
#define	MXC_F_CAN_INTEN_DOR   ((uint8_t)(0x1UL << MXC_F_CAN_INTEN_DOR_POS))
#define	MXC_F_CAN_INTEN_BERR_POS   1
#define	MXC_F_CAN_INTEN_BERR   ((uint8_t)(0x1UL << MXC_F_CAN_INTEN_BERR_POS))
#define	MXC_F_CAN_INTEN_TX_POS   2
#define	MXC_F_CAN_INTEN_TX   ((uint8_t)(0x1UL << MXC_F_CAN_INTEN_TX_POS))
#define	MXC_F_CAN_INTEN_RX_POS   3
#define	MXC_F_CAN_INTEN_RX   ((uint8_t)(0x1UL << MXC_F_CAN_INTEN_RX_POS))
#define	MXC_F_CAN_INTEN_ERPSV_POS   4
#define	MXC_F_CAN_INTEN_ERPSV   ((uint8_t)(0x1UL << MXC_F_CAN_INTEN_ERPSV_POS))
#define	MXC_F_CAN_INTEN_ERWARN_POS   5
#define	MXC_F_CAN_INTEN_ERWARN   ((uint8_t)(0x1UL << MXC_F_CAN_INTEN_ERWARN_POS))
#define	MXC_F_CAN_INTEN_AL_POS   6
#define	MXC_F_CAN_INTEN_AL   ((uint8_t)(0x1UL << MXC_F_CAN_INTEN_AL_POS))
#define	MXC_F_CAN_INTEN_WU_POS   7
#define	MXC_F_CAN_INTEN_WU   ((uint8_t)(0x1UL << MXC_F_CAN_INTEN_WU_POS))

Detailed Description

Interrupt Enable Register.

Macro Definition Documentation

MXC_F_CAN_INTEN_AL

#define MXC_F_CAN_INTEN_AL   ((uint8_t)(0x1UL << MXC_F_CAN_INTEN_AL_POS))

INTEN_AL Mask

MXC_F_CAN_INTEN_AL_POS

#define MXC_F_CAN_INTEN_AL_POS   6

INTEN_AL Position

MXC_F_CAN_INTEN_BERR

#define MXC_F_CAN_INTEN_BERR   ((uint8_t)(0x1UL << MXC_F_CAN_INTEN_BERR_POS))

INTEN_BERR Mask

MXC_F_CAN_INTEN_BERR_POS

#define MXC_F_CAN_INTEN_BERR_POS   1

INTEN_BERR Position

MXC_F_CAN_INTEN_DOR

#define MXC_F_CAN_INTEN_DOR   ((uint8_t)(0x1UL << MXC_F_CAN_INTEN_DOR_POS))

INTEN_DOR Mask

MXC_F_CAN_INTEN_DOR_POS

#define MXC_F_CAN_INTEN_DOR_POS   0

INTEN_DOR Position

MXC_F_CAN_INTEN_ERPSV

#define MXC_F_CAN_INTEN_ERPSV   ((uint8_t)(0x1UL << MXC_F_CAN_INTEN_ERPSV_POS))

INTEN_ERPSV Mask

MXC_F_CAN_INTEN_ERPSV_POS

#define MXC_F_CAN_INTEN_ERPSV_POS   4

INTEN_ERPSV Position

MXC_F_CAN_INTEN_ERWARN

#define MXC_F_CAN_INTEN_ERWARN   ((uint8_t)(0x1UL << MXC_F_CAN_INTEN_ERWARN_POS))

INTEN_ERWARN Mask

MXC_F_CAN_INTEN_ERWARN_POS

#define MXC_F_CAN_INTEN_ERWARN_POS   5

INTEN_ERWARN Position

MXC_F_CAN_INTEN_RX

#define MXC_F_CAN_INTEN_RX   ((uint8_t)(0x1UL << MXC_F_CAN_INTEN_RX_POS))

INTEN_RX Mask

MXC_F_CAN_INTEN_RX_POS

#define MXC_F_CAN_INTEN_RX_POS   3

INTEN_RX Position

MXC_F_CAN_INTEN_TX

#define MXC_F_CAN_INTEN_TX   ((uint8_t)(0x1UL << MXC_F_CAN_INTEN_TX_POS))

INTEN_TX Mask

MXC_F_CAN_INTEN_TX_POS

#define MXC_F_CAN_INTEN_TX_POS   2

INTEN_TX Position

MXC_F_CAN_INTEN_WU

#define MXC_F_CAN_INTEN_WU   ((uint8_t)(0x1UL << MXC_F_CAN_INTEN_WU_POS))

INTEN_WU Mask

MXC_F_CAN_INTEN_WU_POS

#define MXC_F_CAN_INTEN_WU_POS   7

INTEN_WU Position