FCR_FCTRL0

Macros
#define	MXC_F_FCR_FCTRL0_RDSGCSEL_POS   0
#define	MXC_F_FCR_FCTRL0_RDSGCSEL   ((uint32_t)(0x3FUL << MXC_F_FCR_FCTRL0_RDSGCSEL_POS))
#define	MXC_F_FCR_FCTRL0_RDSGCSET_POS   6
#define	MXC_F_FCR_FCTRL0_RDSGCSET   ((uint32_t)(0x1UL << MXC_F_FCR_FCTRL0_RDSGCSET_POS))
#define	MXC_F_FCR_FCTRL0_HYPERCGDLY_POS   8
#define	MXC_F_FCR_FCTRL0_HYPERCGDLY   ((uint32_t)(0x3FUL << MXC_F_FCR_FCTRL0_HYPERCGDLY_POS))
#define	MXC_F_FCR_FCTRL0_USBCLKSEL_POS   16
#define	MXC_F_FCR_FCTRL0_USBCLKSEL   ((uint32_t)(0x3UL << MXC_F_FCR_FCTRL0_USBCLKSEL_POS))
#define	MXC_F_FCR_FCTRL0_I2C0DGEN0_POS   20
#define	MXC_F_FCR_FCTRL0_I2C0DGEN0   ((uint32_t)(0x1UL << MXC_F_FCR_FCTRL0_I2C0DGEN0_POS))
#define	MXC_F_FCR_FCTRL0_I2C0DGEN1_POS   21
#define	MXC_F_FCR_FCTRL0_I2C0DGEN1   ((uint32_t)(0x1UL << MXC_F_FCR_FCTRL0_I2C0DGEN1_POS))
#define	MXC_F_FCR_FCTRL0_I2C1DGEN0_POS   22
#define	MXC_F_FCR_FCTRL0_I2C1DGEN0   ((uint32_t)(0x1UL << MXC_F_FCR_FCTRL0_I2C1DGEN0_POS))
#define	MXC_F_FCR_FCTRL0_I2C1DGEN1_POS   23
#define	MXC_F_FCR_FCTRL0_I2C1DGEN1   ((uint32_t)(0x1UL << MXC_F_FCR_FCTRL0_I2C1DGEN1_POS))
#define	MXC_F_FCR_FCTRL0_I2C2DGEN0_POS   24
#define	MXC_F_FCR_FCTRL0_I2C2DGEN0   ((uint32_t)(0x1UL << MXC_F_FCR_FCTRL0_I2C2DGEN0_POS))
#define	MXC_F_FCR_FCTRL0_I2C2DGEN1_POS   25
#define	MXC_F_FCR_FCTRL0_I2C2DGEN1   ((uint32_t)(0x1UL << MXC_F_FCR_FCTRL0_I2C2DGEN1_POS))

Detailed Description

Function Control 0.

Macro Definition Documentation

MXC_F_FCR_FCTRL0_HYPERCGDLY

#define MXC_F_FCR_FCTRL0_HYPERCGDLY   ((uint32_t)(0x3FUL << MXC_F_FCR_FCTRL0_HYPERCGDLY_POS))

FCTRL0_HYPERCGDLY Mask

MXC_F_FCR_FCTRL0_HYPERCGDLY_POS

#define MXC_F_FCR_FCTRL0_HYPERCGDLY_POS   8

FCTRL0_HYPERCGDLY Position

MXC_F_FCR_FCTRL0_I2C0DGEN0

#define MXC_F_FCR_FCTRL0_I2C0DGEN0   ((uint32_t)(0x1UL << MXC_F_FCR_FCTRL0_I2C0DGEN0_POS))

FCTRL0_I2C0DGEN0 Mask

MXC_F_FCR_FCTRL0_I2C0DGEN0_POS

#define MXC_F_FCR_FCTRL0_I2C0DGEN0_POS   20

FCTRL0_I2C0DGEN0 Position

MXC_F_FCR_FCTRL0_I2C0DGEN1

#define MXC_F_FCR_FCTRL0_I2C0DGEN1   ((uint32_t)(0x1UL << MXC_F_FCR_FCTRL0_I2C0DGEN1_POS))

FCTRL0_I2C0DGEN1 Mask

MXC_F_FCR_FCTRL0_I2C0DGEN1_POS

#define MXC_F_FCR_FCTRL0_I2C0DGEN1_POS   21

FCTRL0_I2C0DGEN1 Position

MXC_F_FCR_FCTRL0_I2C1DGEN0

#define MXC_F_FCR_FCTRL0_I2C1DGEN0   ((uint32_t)(0x1UL << MXC_F_FCR_FCTRL0_I2C1DGEN0_POS))

FCTRL0_I2C1DGEN0 Mask

MXC_F_FCR_FCTRL0_I2C1DGEN0_POS

#define MXC_F_FCR_FCTRL0_I2C1DGEN0_POS   22

FCTRL0_I2C1DGEN0 Position

MXC_F_FCR_FCTRL0_I2C1DGEN1

#define MXC_F_FCR_FCTRL0_I2C1DGEN1   ((uint32_t)(0x1UL << MXC_F_FCR_FCTRL0_I2C1DGEN1_POS))

FCTRL0_I2C1DGEN1 Mask

MXC_F_FCR_FCTRL0_I2C1DGEN1_POS

#define MXC_F_FCR_FCTRL0_I2C1DGEN1_POS   23

FCTRL0_I2C1DGEN1 Position

MXC_F_FCR_FCTRL0_I2C2DGEN0

#define MXC_F_FCR_FCTRL0_I2C2DGEN0   ((uint32_t)(0x1UL << MXC_F_FCR_FCTRL0_I2C2DGEN0_POS))

FCTRL0_I2C2DGEN0 Mask

MXC_F_FCR_FCTRL0_I2C2DGEN0_POS

#define MXC_F_FCR_FCTRL0_I2C2DGEN0_POS   24

FCTRL0_I2C2DGEN0 Position

MXC_F_FCR_FCTRL0_I2C2DGEN1

#define MXC_F_FCR_FCTRL0_I2C2DGEN1   ((uint32_t)(0x1UL << MXC_F_FCR_FCTRL0_I2C2DGEN1_POS))

FCTRL0_I2C2DGEN1 Mask

MXC_F_FCR_FCTRL0_I2C2DGEN1_POS

#define MXC_F_FCR_FCTRL0_I2C2DGEN1_POS   25

FCTRL0_I2C2DGEN1 Position

MXC_F_FCR_FCTRL0_RDSGCSEL

#define MXC_F_FCR_FCTRL0_RDSGCSEL   ((uint32_t)(0x3FUL << MXC_F_FCR_FCTRL0_RDSGCSEL_POS))

FCTRL0_RDSGCSEL Mask

MXC_F_FCR_FCTRL0_RDSGCSEL_POS

#define MXC_F_FCR_FCTRL0_RDSGCSEL_POS   0

FCTRL0_RDSGCSEL Position

MXC_F_FCR_FCTRL0_RDSGCSET

#define MXC_F_FCR_FCTRL0_RDSGCSET   ((uint32_t)(0x1UL << MXC_F_FCR_FCTRL0_RDSGCSET_POS))

FCTRL0_RDSGCSET Mask

MXC_F_FCR_FCTRL0_RDSGCSET_POS

#define MXC_F_FCR_FCTRL0_RDSGCSET_POS   6

FCTRL0_RDSGCSET Position

MXC_F_FCR_FCTRL0_USBCLKSEL

#define MXC_F_FCR_FCTRL0_USBCLKSEL   ((uint32_t)(0x3UL << MXC_F_FCR_FCTRL0_USBCLKSEL_POS))

FCTRL0_USBCLKSEL Mask

MXC_F_FCR_FCTRL0_USBCLKSEL_POS

#define MXC_F_FCR_FCTRL0_USBCLKSEL_POS   16

FCTRL0_USBCLKSEL Position