GCR_RST1

Macros
#define	MXC_F_GCR_RST1_I2C1_POS   0
#define	MXC_F_GCR_RST1_I2C1   ((uint32_t)(0x1UL << MXC_F_GCR_RST1_I2C1_POS))
#define	MXC_F_GCR_RST1_PT_POS   1
#define	MXC_F_GCR_RST1_PT   ((uint32_t)(0x1UL << MXC_F_GCR_RST1_PT_POS))
#define	MXC_F_GCR_RST1_SPIXIP_POS   3
#define	MXC_F_GCR_RST1_SPIXIP   ((uint32_t)(0x1UL << MXC_F_GCR_RST1_SPIXIP_POS))
#define	MXC_F_GCR_RST1_SPIXIPM_POS   4
#define	MXC_F_GCR_RST1_SPIXIPM   ((uint32_t)(0x1UL << MXC_F_GCR_RST1_SPIXIPM_POS))
#define	MXC_F_GCR_RST1_OWM_POS   7
#define	MXC_F_GCR_RST1_OWM   ((uint32_t)(0x1UL << MXC_F_GCR_RST1_OWM_POS))
#define	MXC_F_GCR_RST1_SPI3_POS   11
#define	MXC_F_GCR_RST1_SPI3   ((uint32_t)(0x1UL << MXC_F_GCR_RST1_SPI3_POS))
#define	MXC_F_GCR_RST1_SPI4_POS   13
#define	MXC_F_GCR_RST1_SPI4   ((uint32_t)(0x1UL << MXC_F_GCR_RST1_SPI4_POS))
#define	MXC_F_GCR_RST1_SMPHR_POS   16
#define	MXC_F_GCR_RST1_SMPHR   ((uint32_t)(0x1UL << MXC_F_GCR_RST1_SMPHR_POS))
#define	MXC_F_GCR_RST1_BTLE_POS   18
#define	MXC_F_GCR_RST1_BTLE   ((uint32_t)(0x1UL << MXC_F_GCR_RST1_BTLE_POS))
#define	MXC_F_GCR_RST1_I2S_POS   19
#define	MXC_F_GCR_RST1_I2S   ((uint32_t)(0x1UL << MXC_F_GCR_RST1_I2S_POS))
#define	MXC_F_GCR_RST1_I2C2_POS   20
#define	MXC_F_GCR_RST1_I2C2   ((uint32_t)(0x1UL << MXC_F_GCR_RST1_I2C2_POS))
#define	MXC_F_GCR_RST1_PUF_POS   28
#define	MXC_F_GCR_RST1_PUF   ((uint32_t)(0x1UL << MXC_F_GCR_RST1_PUF_POS))
#define	MXC_F_GCR_RST1_CPU1_POS   31
#define	MXC_F_GCR_RST1_CPU1   ((uint32_t)(0x1UL << MXC_F_GCR_RST1_CPU1_POS))

Detailed Description

Reset 1.

Macro Definition Documentation

MXC_F_GCR_RST1_BTLE

#define MXC_F_GCR_RST1_BTLE   ((uint32_t)(0x1UL << MXC_F_GCR_RST1_BTLE_POS))

RST1_BTLE Mask

MXC_F_GCR_RST1_BTLE_POS

#define MXC_F_GCR_RST1_BTLE_POS   18

RST1_BTLE Position

MXC_F_GCR_RST1_CPU1

#define MXC_F_GCR_RST1_CPU1   ((uint32_t)(0x1UL << MXC_F_GCR_RST1_CPU1_POS))

RST1_CPU1 Mask

MXC_F_GCR_RST1_CPU1_POS

#define MXC_F_GCR_RST1_CPU1_POS   31

RST1_CPU1 Position

MXC_F_GCR_RST1_I2C1

#define MXC_F_GCR_RST1_I2C1   ((uint32_t)(0x1UL << MXC_F_GCR_RST1_I2C1_POS))

RST1_I2C1 Mask

MXC_F_GCR_RST1_I2C1_POS

#define MXC_F_GCR_RST1_I2C1_POS   0

RST1_I2C1 Position

MXC_F_GCR_RST1_I2C2

#define MXC_F_GCR_RST1_I2C2   ((uint32_t)(0x1UL << MXC_F_GCR_RST1_I2C2_POS))

RST1_I2C2 Mask

MXC_F_GCR_RST1_I2C2_POS

#define MXC_F_GCR_RST1_I2C2_POS   20

RST1_I2C2 Position

MXC_F_GCR_RST1_I2S

#define MXC_F_GCR_RST1_I2S   ((uint32_t)(0x1UL << MXC_F_GCR_RST1_I2S_POS))

RST1_I2S Mask

MXC_F_GCR_RST1_I2S_POS

#define MXC_F_GCR_RST1_I2S_POS   19

RST1_I2S Position

MXC_F_GCR_RST1_OWM

#define MXC_F_GCR_RST1_OWM   ((uint32_t)(0x1UL << MXC_F_GCR_RST1_OWM_POS))

RST1_OWM Mask

MXC_F_GCR_RST1_OWM_POS

#define MXC_F_GCR_RST1_OWM_POS   7

RST1_OWM Position

MXC_F_GCR_RST1_PT

#define MXC_F_GCR_RST1_PT   ((uint32_t)(0x1UL << MXC_F_GCR_RST1_PT_POS))

RST1_PT Mask

MXC_F_GCR_RST1_PT_POS

#define MXC_F_GCR_RST1_PT_POS   1

RST1_PT Position

MXC_F_GCR_RST1_PUF

#define MXC_F_GCR_RST1_PUF   ((uint32_t)(0x1UL << MXC_F_GCR_RST1_PUF_POS))

RST1_PUF Mask

MXC_F_GCR_RST1_PUF_POS

#define MXC_F_GCR_RST1_PUF_POS   28

RST1_PUF Position

MXC_F_GCR_RST1_SMPHR

#define MXC_F_GCR_RST1_SMPHR   ((uint32_t)(0x1UL << MXC_F_GCR_RST1_SMPHR_POS))

RST1_SMPHR Mask

MXC_F_GCR_RST1_SMPHR_POS

#define MXC_F_GCR_RST1_SMPHR_POS   16

RST1_SMPHR Position

MXC_F_GCR_RST1_SPI3

#define MXC_F_GCR_RST1_SPI3   ((uint32_t)(0x1UL << MXC_F_GCR_RST1_SPI3_POS))

RST1_SPI3 Mask

MXC_F_GCR_RST1_SPI3_POS

#define MXC_F_GCR_RST1_SPI3_POS   11

RST1_SPI3 Position

MXC_F_GCR_RST1_SPI4

#define MXC_F_GCR_RST1_SPI4   ((uint32_t)(0x1UL << MXC_F_GCR_RST1_SPI4_POS))

RST1_SPI4 Mask

MXC_F_GCR_RST1_SPI4_POS

#define MXC_F_GCR_RST1_SPI4_POS   13

RST1_SPI4 Position

MXC_F_GCR_RST1_SPIXIP

#define MXC_F_GCR_RST1_SPIXIP   ((uint32_t)(0x1UL << MXC_F_GCR_RST1_SPIXIP_POS))

RST1_SPIXIP Mask

MXC_F_GCR_RST1_SPIXIP_POS

#define MXC_F_GCR_RST1_SPIXIP_POS   3

RST1_SPIXIP Position

MXC_F_GCR_RST1_SPIXIPM

#define MXC_F_GCR_RST1_SPIXIPM   ((uint32_t)(0x1UL << MXC_F_GCR_RST1_SPIXIPM_POS))

RST1_SPIXIPM Mask

MXC_F_GCR_RST1_SPIXIPM_POS

#define MXC_F_GCR_RST1_SPIXIPM_POS   4

RST1_SPIXIPM Position