Macros
#define	MXC_R_GCR_SYSCTRL ((uint32_t)0x00000000UL)

#define	MXC_R_GCR_RST0 ((uint32_t)0x00000004UL)

#define	MXC_R_GCR_CLKCTRL ((uint32_t)0x00000008UL)

#define	MXC_R_GCR_PM ((uint32_t)0x0000000CUL)

#define	MXC_R_GCR_PCLKDIV ((uint32_t)0x00000018UL)

#define	MXC_R_GCR_PCLKDIS0 ((uint32_t)0x00000024UL)

#define	MXC_R_GCR_MEMCTRL ((uint32_t)0x00000028UL)

#define	MXC_R_GCR_MEMZ ((uint32_t)0x0000002CUL)

#define	MXC_R_GCR_SYSST ((uint32_t)0x00000040UL)

#define	MXC_R_GCR_RST1 ((uint32_t)0x00000044UL)

#define	MXC_R_GCR_PCLKDIS1 ((uint32_t)0x00000048UL)

#define	MXC_R_GCR_EVENTEN ((uint32_t)0x0000004CUL)

#define	MXC_R_GCR_REVISION ((uint32_t)0x00000050UL)

#define	MXC_R_GCR_SYSIE ((uint32_t)0x00000054UL)

#define	MXC_R_GCR_ECCERR ((uint32_t)0x00000064UL)

#define	MXC_R_GCR_ECCCED ((uint32_t)0x00000068UL)

#define	MXC_R_GCR_ECCIE ((uint32_t)0x0000006CUL)

#define	MXC_R_GCR_ECCADDR ((uint32_t)0x00000070UL)

#define	MXC_R_GCR_BTLELDOCTRL ((uint32_t)0x00000074UL)

#define	MXC_R_GCR_BTLELDODLY ((uint32_t)0x00000078UL)

#define	MXC_R_GCR_GPR0 ((uint32_t)0x00000080UL)

Detailed Description

GCR Peripheral Register Offsets from the GCR Base Peripheral Address.

Macro Definition Documentation

◆ MXC_R_GCR_BTLELDOCTRL

#define MXC_R_GCR_BTLELDOCTRL ((uint32_t)0x00000074UL)

Offset from GCR Base Address: 0x0074

◆ MXC_R_GCR_BTLELDODLY

#define MXC_R_GCR_BTLELDODLY ((uint32_t)0x00000078UL)

Offset from GCR Base Address: 0x0078

◆ MXC_R_GCR_CLKCTRL

#define MXC_R_GCR_CLKCTRL ((uint32_t)0x00000008UL)

Offset from GCR Base Address: 0x0008

◆ MXC_R_GCR_ECCADDR

#define MXC_R_GCR_ECCADDR ((uint32_t)0x00000070UL)

Offset from GCR Base Address: 0x0070

◆ MXC_R_GCR_ECCCED

#define MXC_R_GCR_ECCCED ((uint32_t)0x00000068UL)

Offset from GCR Base Address: 0x0068

◆ MXC_R_GCR_ECCERR

#define MXC_R_GCR_ECCERR ((uint32_t)0x00000064UL)

Offset from GCR Base Address: 0x0064

◆ MXC_R_GCR_ECCIE

#define MXC_R_GCR_ECCIE ((uint32_t)0x0000006CUL)

Offset from GCR Base Address: 0x006C

◆ MXC_R_GCR_EVENTEN

#define MXC_R_GCR_EVENTEN ((uint32_t)0x0000004CUL)

Offset from GCR Base Address: 0x004C

◆ MXC_R_GCR_GPR0

#define MXC_R_GCR_GPR0 ((uint32_t)0x00000080UL)

Offset from GCR Base Address: 0x0080

◆ MXC_R_GCR_MEMCTRL

#define MXC_R_GCR_MEMCTRL ((uint32_t)0x00000028UL)

Offset from GCR Base Address: 0x0028

◆ MXC_R_GCR_MEMZ

#define MXC_R_GCR_MEMZ ((uint32_t)0x0000002CUL)

Offset from GCR Base Address: 0x002C

◆ MXC_R_GCR_PCLKDIS0

#define MXC_R_GCR_PCLKDIS0 ((uint32_t)0x00000024UL)

Offset from GCR Base Address: 0x0024

◆ MXC_R_GCR_PCLKDIS1

#define MXC_R_GCR_PCLKDIS1 ((uint32_t)0x00000048UL)

Offset from GCR Base Address: 0x0048

◆ MXC_R_GCR_PCLKDIV

#define MXC_R_GCR_PCLKDIV ((uint32_t)0x00000018UL)

Offset from GCR Base Address: 0x0018

◆ MXC_R_GCR_PM

#define MXC_R_GCR_PM ((uint32_t)0x0000000CUL)

Offset from GCR Base Address: 0x000C

◆ MXC_R_GCR_REVISION

#define MXC_R_GCR_REVISION ((uint32_t)0x00000050UL)

Offset from GCR Base Address: 0x0050

◆ MXC_R_GCR_RST0

#define MXC_R_GCR_RST0 ((uint32_t)0x00000004UL)

Offset from GCR Base Address: 0x0004

◆ MXC_R_GCR_RST1

#define MXC_R_GCR_RST1 ((uint32_t)0x00000044UL)

Offset from GCR Base Address: 0x0044

◆ MXC_R_GCR_SYSCTRL

#define MXC_R_GCR_SYSCTRL ((uint32_t)0x00000000UL)

Offset from GCR Base Address: 0x0000

◆ MXC_R_GCR_SYSIE

#define MXC_R_GCR_SYSIE ((uint32_t)0x00000054UL)

Offset from GCR Base Address: 0x0054

◆ MXC_R_GCR_SYSST

#define MXC_R_GCR_SYSST ((uint32_t)0x00000040UL)

Offset from GCR Base Address: 0x0040

Macros