Macros
#define	MXC_F_I2C_INTEN0_DONE_POS 0

#define	MXC_F_I2C_INTEN0_DONE ((uint32_t)(0x1UL << MXC_F_I2C_INTEN0_DONE_POS))

#define	MXC_F_I2C_INTEN0_IRXM_POS 1

#define	MXC_F_I2C_INTEN0_IRXM ((uint32_t)(0x1UL << MXC_F_I2C_INTEN0_IRXM_POS))

#define	MXC_F_I2C_INTEN0_GC_ADDR_MATCH_POS 2

#define	MXC_F_I2C_INTEN0_GC_ADDR_MATCH ((uint32_t)(0x1UL << MXC_F_I2C_INTEN0_GC_ADDR_MATCH_POS))

#define	MXC_F_I2C_INTEN0_ADDR_MATCH_POS 3

#define	MXC_F_I2C_INTEN0_ADDR_MATCH ((uint32_t)(0x1UL << MXC_F_I2C_INTEN0_ADDR_MATCH_POS))

#define	MXC_F_I2C_INTEN0_RX_THD_POS 4

#define	MXC_F_I2C_INTEN0_RX_THD ((uint32_t)(0x1UL << MXC_F_I2C_INTEN0_RX_THD_POS))

#define	MXC_F_I2C_INTEN0_TX_THD_POS 5

#define	MXC_F_I2C_INTEN0_TX_THD ((uint32_t)(0x1UL << MXC_F_I2C_INTEN0_TX_THD_POS))

#define	MXC_F_I2C_INTEN0_STOP_POS 6

#define	MXC_F_I2C_INTEN0_STOP ((uint32_t)(0x1UL << MXC_F_I2C_INTEN0_STOP_POS))

#define	MXC_F_I2C_INTEN0_ADDR_ACK_POS 7

#define	MXC_F_I2C_INTEN0_ADDR_ACK ((uint32_t)(0x1UL << MXC_F_I2C_INTEN0_ADDR_ACK_POS))

#define	MXC_F_I2C_INTEN0_ARB_ERR_POS 8

#define	MXC_F_I2C_INTEN0_ARB_ERR ((uint32_t)(0x1UL << MXC_F_I2C_INTEN0_ARB_ERR_POS))

#define	MXC_F_I2C_INTEN0_TO_ERR_POS 9

#define	MXC_F_I2C_INTEN0_TO_ERR ((uint32_t)(0x1UL << MXC_F_I2C_INTEN0_TO_ERR_POS))

#define	MXC_F_I2C_INTEN0_ADDR_NACK_ERR_POS 10

#define	MXC_F_I2C_INTEN0_ADDR_NACK_ERR ((uint32_t)(0x1UL << MXC_F_I2C_INTEN0_ADDR_NACK_ERR_POS))

#define	MXC_F_I2C_INTEN0_DATA_ERR_POS 11

#define	MXC_F_I2C_INTEN0_DATA_ERR ((uint32_t)(0x1UL << MXC_F_I2C_INTEN0_DATA_ERR_POS))

#define	MXC_F_I2C_INTEN0_DNR_ERR_POS 12

#define	MXC_F_I2C_INTEN0_DNR_ERR ((uint32_t)(0x1UL << MXC_F_I2C_INTEN0_DNR_ERR_POS))

#define	MXC_F_I2C_INTEN0_START_ERR_POS 13

#define	MXC_F_I2C_INTEN0_START_ERR ((uint32_t)(0x1UL << MXC_F_I2C_INTEN0_START_ERR_POS))

#define	MXC_F_I2C_INTEN0_STOP_ERR_POS 14

#define	MXC_F_I2C_INTEN0_STOP_ERR ((uint32_t)(0x1UL << MXC_F_I2C_INTEN0_STOP_ERR_POS))

#define	MXC_F_I2C_INTEN0_TX_LOCKOUT_POS 15

#define	MXC_F_I2C_INTEN0_TX_LOCKOUT ((uint32_t)(0x1UL << MXC_F_I2C_INTEN0_TX_LOCKOUT_POS))

#define	MXC_F_I2C_INTEN0_MAMI_POS 16

#define	MXC_F_I2C_INTEN0_MAMI ((uint32_t)(0x3FUL << MXC_F_I2C_INTEN0_MAMI_POS))

#define	MXC_F_I2C_INTEN0_RD_ADDR_MATCH_POS 22

#define	MXC_F_I2C_INTEN0_RD_ADDR_MATCH ((uint32_t)(0x1UL << MXC_F_I2C_INTEN0_RD_ADDR_MATCH_POS))

#define	MXC_F_I2C_INTEN0_WR_ADDR_MATCH_POS 23

#define	MXC_F_I2C_INTEN0_WR_ADDR_MATCH ((uint32_t)(0x1UL << MXC_F_I2C_INTEN0_WR_ADDR_MATCH_POS))

Detailed Description

Interrupt Enable Register.

Macro Definition Documentation

◆ MXC_F_I2C_INTEN0_ADDR_ACK

#define MXC_F_I2C_INTEN0_ADDR_ACK ((uint32_t)(0x1UL << MXC_F_I2C_INTEN0_ADDR_ACK_POS))

INTEN0_ADDR_ACK Mask

◆ MXC_F_I2C_INTEN0_ADDR_ACK_POS

#define MXC_F_I2C_INTEN0_ADDR_ACK_POS 7

INTEN0_ADDR_ACK Position

◆ MXC_F_I2C_INTEN0_ADDR_MATCH

#define MXC_F_I2C_INTEN0_ADDR_MATCH ((uint32_t)(0x1UL << MXC_F_I2C_INTEN0_ADDR_MATCH_POS))

INTEN0_ADDR_MATCH Mask

◆ MXC_F_I2C_INTEN0_ADDR_MATCH_POS

#define MXC_F_I2C_INTEN0_ADDR_MATCH_POS 3

INTEN0_ADDR_MATCH Position

◆ MXC_F_I2C_INTEN0_ADDR_NACK_ERR

#define MXC_F_I2C_INTEN0_ADDR_NACK_ERR ((uint32_t)(0x1UL << MXC_F_I2C_INTEN0_ADDR_NACK_ERR_POS))

INTEN0_ADDR_NACK_ERR Mask

◆ MXC_F_I2C_INTEN0_ADDR_NACK_ERR_POS

#define MXC_F_I2C_INTEN0_ADDR_NACK_ERR_POS 10

INTEN0_ADDR_NACK_ERR Position

◆ MXC_F_I2C_INTEN0_ARB_ERR

#define MXC_F_I2C_INTEN0_ARB_ERR ((uint32_t)(0x1UL << MXC_F_I2C_INTEN0_ARB_ERR_POS))

INTEN0_ARB_ERR Mask

◆ MXC_F_I2C_INTEN0_ARB_ERR_POS

#define MXC_F_I2C_INTEN0_ARB_ERR_POS 8

INTEN0_ARB_ERR Position

◆ MXC_F_I2C_INTEN0_DATA_ERR

#define MXC_F_I2C_INTEN0_DATA_ERR ((uint32_t)(0x1UL << MXC_F_I2C_INTEN0_DATA_ERR_POS))

INTEN0_DATA_ERR Mask

◆ MXC_F_I2C_INTEN0_DATA_ERR_POS

#define MXC_F_I2C_INTEN0_DATA_ERR_POS 11

INTEN0_DATA_ERR Position

◆ MXC_F_I2C_INTEN0_DNR_ERR

#define MXC_F_I2C_INTEN0_DNR_ERR ((uint32_t)(0x1UL << MXC_F_I2C_INTEN0_DNR_ERR_POS))

INTEN0_DNR_ERR Mask

◆ MXC_F_I2C_INTEN0_DNR_ERR_POS

#define MXC_F_I2C_INTEN0_DNR_ERR_POS 12

INTEN0_DNR_ERR Position

◆ MXC_F_I2C_INTEN0_DONE

#define MXC_F_I2C_INTEN0_DONE ((uint32_t)(0x1UL << MXC_F_I2C_INTEN0_DONE_POS))

INTEN0_DONE Mask

◆ MXC_F_I2C_INTEN0_DONE_POS

#define MXC_F_I2C_INTEN0_DONE_POS 0

INTEN0_DONE Position

◆ MXC_F_I2C_INTEN0_GC_ADDR_MATCH

#define MXC_F_I2C_INTEN0_GC_ADDR_MATCH ((uint32_t)(0x1UL << MXC_F_I2C_INTEN0_GC_ADDR_MATCH_POS))

INTEN0_GC_ADDR_MATCH Mask

◆ MXC_F_I2C_INTEN0_GC_ADDR_MATCH_POS

#define MXC_F_I2C_INTEN0_GC_ADDR_MATCH_POS 2

INTEN0_GC_ADDR_MATCH Position

◆ MXC_F_I2C_INTEN0_IRXM

#define MXC_F_I2C_INTEN0_IRXM ((uint32_t)(0x1UL << MXC_F_I2C_INTEN0_IRXM_POS))

INTEN0_IRXM Mask

◆ MXC_F_I2C_INTEN0_IRXM_POS

#define MXC_F_I2C_INTEN0_IRXM_POS 1

INTEN0_IRXM Position

◆ MXC_F_I2C_INTEN0_MAMI

#define MXC_F_I2C_INTEN0_MAMI ((uint32_t)(0x3FUL << MXC_F_I2C_INTEN0_MAMI_POS))

INTEN0_MAMI Mask

◆ MXC_F_I2C_INTEN0_MAMI_POS

#define MXC_F_I2C_INTEN0_MAMI_POS 16

INTEN0_MAMI Position

◆ MXC_F_I2C_INTEN0_RD_ADDR_MATCH

#define MXC_F_I2C_INTEN0_RD_ADDR_MATCH ((uint32_t)(0x1UL << MXC_F_I2C_INTEN0_RD_ADDR_MATCH_POS))

INTEN0_RD_ADDR_MATCH Mask

◆ MXC_F_I2C_INTEN0_RD_ADDR_MATCH_POS

#define MXC_F_I2C_INTEN0_RD_ADDR_MATCH_POS 22

INTEN0_RD_ADDR_MATCH Position

◆ MXC_F_I2C_INTEN0_RX_THD

#define MXC_F_I2C_INTEN0_RX_THD ((uint32_t)(0x1UL << MXC_F_I2C_INTEN0_RX_THD_POS))

INTEN0_RX_THD Mask

◆ MXC_F_I2C_INTEN0_RX_THD_POS

#define MXC_F_I2C_INTEN0_RX_THD_POS 4

INTEN0_RX_THD Position

◆ MXC_F_I2C_INTEN0_START_ERR

#define MXC_F_I2C_INTEN0_START_ERR ((uint32_t)(0x1UL << MXC_F_I2C_INTEN0_START_ERR_POS))

INTEN0_START_ERR Mask

◆ MXC_F_I2C_INTEN0_START_ERR_POS

#define MXC_F_I2C_INTEN0_START_ERR_POS 13

INTEN0_START_ERR Position

◆ MXC_F_I2C_INTEN0_STOP

#define MXC_F_I2C_INTEN0_STOP ((uint32_t)(0x1UL << MXC_F_I2C_INTEN0_STOP_POS))

INTEN0_STOP Mask

◆ MXC_F_I2C_INTEN0_STOP_ERR

#define MXC_F_I2C_INTEN0_STOP_ERR ((uint32_t)(0x1UL << MXC_F_I2C_INTEN0_STOP_ERR_POS))

INTEN0_STOP_ERR Mask

◆ MXC_F_I2C_INTEN0_STOP_ERR_POS

#define MXC_F_I2C_INTEN0_STOP_ERR_POS 14

INTEN0_STOP_ERR Position

◆ MXC_F_I2C_INTEN0_STOP_POS

#define MXC_F_I2C_INTEN0_STOP_POS 6

INTEN0_STOP Position

◆ MXC_F_I2C_INTEN0_TO_ERR

#define MXC_F_I2C_INTEN0_TO_ERR ((uint32_t)(0x1UL << MXC_F_I2C_INTEN0_TO_ERR_POS))

INTEN0_TO_ERR Mask

◆ MXC_F_I2C_INTEN0_TO_ERR_POS

#define MXC_F_I2C_INTEN0_TO_ERR_POS 9

INTEN0_TO_ERR Position

◆ MXC_F_I2C_INTEN0_TX_LOCKOUT

#define MXC_F_I2C_INTEN0_TX_LOCKOUT ((uint32_t)(0x1UL << MXC_F_I2C_INTEN0_TX_LOCKOUT_POS))

INTEN0_TX_LOCKOUT Mask

◆ MXC_F_I2C_INTEN0_TX_LOCKOUT_POS

#define MXC_F_I2C_INTEN0_TX_LOCKOUT_POS 15

INTEN0_TX_LOCKOUT Position

◆ MXC_F_I2C_INTEN0_TX_THD

#define MXC_F_I2C_INTEN0_TX_THD ((uint32_t)(0x1UL << MXC_F_I2C_INTEN0_TX_THD_POS))

INTEN0_TX_THD Mask

◆ MXC_F_I2C_INTEN0_TX_THD_POS

#define MXC_F_I2C_INTEN0_TX_THD_POS 5

INTEN0_TX_THD Position

◆ MXC_F_I2C_INTEN0_WR_ADDR_MATCH

#define MXC_F_I2C_INTEN0_WR_ADDR_MATCH ((uint32_t)(0x1UL << MXC_F_I2C_INTEN0_WR_ADDR_MATCH_POS))

INTEN0_WR_ADDR_MATCH Mask

◆ MXC_F_I2C_INTEN0_WR_ADDR_MATCH_POS

#define MXC_F_I2C_INTEN0_WR_ADDR_MATCH_POS 23

INTEN0_WR_ADDR_MATCH Position

Macros