SPI_CTRL0

Macros
#define	MXC_F_SPI_CTRL0_EN_POS   0
#define	MXC_F_SPI_CTRL0_EN   ((uint32_t)(0x1UL << MXC_F_SPI_CTRL0_EN_POS))
#define	MXC_F_SPI_CTRL0_MST_MODE_POS   1
#define	MXC_F_SPI_CTRL0_MST_MODE   ((uint32_t)(0x1UL << MXC_F_SPI_CTRL0_MST_MODE_POS))
#define	MXC_F_SPI_CTRL0_SS_IO_POS   4
#define	MXC_F_SPI_CTRL0_SS_IO   ((uint32_t)(0x1UL << MXC_F_SPI_CTRL0_SS_IO_POS))
#define	MXC_F_SPI_CTRL0_START_POS   5
#define	MXC_F_SPI_CTRL0_START   ((uint32_t)(0x1UL << MXC_F_SPI_CTRL0_START_POS))
#define	MXC_F_SPI_CTRL0_SS_CTRL_POS   8
#define	MXC_F_SPI_CTRL0_SS_CTRL   ((uint32_t)(0x1UL << MXC_F_SPI_CTRL0_SS_CTRL_POS))
#define	MXC_F_SPI_CTRL0_SS_ACTIVE_POS   16
#define	MXC_F_SPI_CTRL0_SS_ACTIVE   ((uint32_t)(0xFUL << MXC_F_SPI_CTRL0_SS_ACTIVE_POS))
#define	MXC_V_SPI_CTRL0_SS_ACTIVE_SS0   ((uint32_t)0x1UL)
#define	MXC_S_SPI_CTRL0_SS_ACTIVE_SS0   (MXC_V_SPI_CTRL0_SS_ACTIVE_SS0 << MXC_F_SPI_CTRL0_SS_ACTIVE_POS)
#define	MXC_V_SPI_CTRL0_SS_ACTIVE_SS1   ((uint32_t)0x2UL)
#define	MXC_S_SPI_CTRL0_SS_ACTIVE_SS1   (MXC_V_SPI_CTRL0_SS_ACTIVE_SS1 << MXC_F_SPI_CTRL0_SS_ACTIVE_POS)
#define	MXC_V_SPI_CTRL0_SS_ACTIVE_SS2   ((uint32_t)0x4UL)
#define	MXC_S_SPI_CTRL0_SS_ACTIVE_SS2   (MXC_V_SPI_CTRL0_SS_ACTIVE_SS2 << MXC_F_SPI_CTRL0_SS_ACTIVE_POS)
#define	MXC_V_SPI_CTRL0_SS_ACTIVE_SS3   ((uint32_t)0x8UL)
#define	MXC_S_SPI_CTRL0_SS_ACTIVE_SS3   (MXC_V_SPI_CTRL0_SS_ACTIVE_SS3 << MXC_F_SPI_CTRL0_SS_ACTIVE_POS)

Detailed Description

Register for controlling SPI peripheral.

Macro Definition Documentation

MXC_F_SPI_CTRL0_EN

#define MXC_F_SPI_CTRL0_EN   ((uint32_t)(0x1UL << MXC_F_SPI_CTRL0_EN_POS))

CTRL0_EN Mask

MXC_F_SPI_CTRL0_EN_POS

#define MXC_F_SPI_CTRL0_EN_POS   0

CTRL0_EN Position

MXC_F_SPI_CTRL0_MST_MODE

#define MXC_F_SPI_CTRL0_MST_MODE   ((uint32_t)(0x1UL << MXC_F_SPI_CTRL0_MST_MODE_POS))

CTRL0_MST_MODE Mask

MXC_F_SPI_CTRL0_MST_MODE_POS

#define MXC_F_SPI_CTRL0_MST_MODE_POS   1

CTRL0_MST_MODE Position

MXC_F_SPI_CTRL0_SS_ACTIVE

#define MXC_F_SPI_CTRL0_SS_ACTIVE   ((uint32_t)(0xFUL << MXC_F_SPI_CTRL0_SS_ACTIVE_POS))

CTRL0_SS_ACTIVE Mask

MXC_F_SPI_CTRL0_SS_ACTIVE_POS

#define MXC_F_SPI_CTRL0_SS_ACTIVE_POS   16

CTRL0_SS_ACTIVE Position

MXC_F_SPI_CTRL0_SS_CTRL

#define MXC_F_SPI_CTRL0_SS_CTRL   ((uint32_t)(0x1UL << MXC_F_SPI_CTRL0_SS_CTRL_POS))

CTRL0_SS_CTRL Mask

MXC_F_SPI_CTRL0_SS_CTRL_POS

#define MXC_F_SPI_CTRL0_SS_CTRL_POS   8

CTRL0_SS_CTRL Position

MXC_F_SPI_CTRL0_SS_IO

#define MXC_F_SPI_CTRL0_SS_IO   ((uint32_t)(0x1UL << MXC_F_SPI_CTRL0_SS_IO_POS))

CTRL0_SS_IO Mask

MXC_F_SPI_CTRL0_SS_IO_POS

#define MXC_F_SPI_CTRL0_SS_IO_POS   4

CTRL0_SS_IO Position

MXC_F_SPI_CTRL0_START

#define MXC_F_SPI_CTRL0_START   ((uint32_t)(0x1UL << MXC_F_SPI_CTRL0_START_POS))

CTRL0_START Mask

MXC_F_SPI_CTRL0_START_POS

#define MXC_F_SPI_CTRL0_START_POS   5

CTRL0_START Position

MXC_S_SPI_CTRL0_SS_ACTIVE_SS0

#define MXC_S_SPI_CTRL0_SS_ACTIVE_SS0   (MXC_V_SPI_CTRL0_SS_ACTIVE_SS0 << MXC_F_SPI_CTRL0_SS_ACTIVE_POS)

CTRL0_SS_ACTIVE_SS0 Setting

MXC_S_SPI_CTRL0_SS_ACTIVE_SS1

#define MXC_S_SPI_CTRL0_SS_ACTIVE_SS1   (MXC_V_SPI_CTRL0_SS_ACTIVE_SS1 << MXC_F_SPI_CTRL0_SS_ACTIVE_POS)

CTRL0_SS_ACTIVE_SS1 Setting

MXC_S_SPI_CTRL0_SS_ACTIVE_SS2

#define MXC_S_SPI_CTRL0_SS_ACTIVE_SS2   (MXC_V_SPI_CTRL0_SS_ACTIVE_SS2 << MXC_F_SPI_CTRL0_SS_ACTIVE_POS)

CTRL0_SS_ACTIVE_SS2 Setting

MXC_S_SPI_CTRL0_SS_ACTIVE_SS3

#define MXC_S_SPI_CTRL0_SS_ACTIVE_SS3   (MXC_V_SPI_CTRL0_SS_ACTIVE_SS3 << MXC_F_SPI_CTRL0_SS_ACTIVE_POS)

CTRL0_SS_ACTIVE_SS3 Setting

MXC_V_SPI_CTRL0_SS_ACTIVE_SS0

#define MXC_V_SPI_CTRL0_SS_ACTIVE_SS0   ((uint32_t)0x1UL)

CTRL0_SS_ACTIVE_SS0 Value

MXC_V_SPI_CTRL0_SS_ACTIVE_SS1

#define MXC_V_SPI_CTRL0_SS_ACTIVE_SS1   ((uint32_t)0x2UL)

CTRL0_SS_ACTIVE_SS1 Value

MXC_V_SPI_CTRL0_SS_ACTIVE_SS2

#define MXC_V_SPI_CTRL0_SS_ACTIVE_SS2   ((uint32_t)0x4UL)

CTRL0_SS_ACTIVE_SS2 Value

MXC_V_SPI_CTRL0_SS_ACTIVE_SS3

#define MXC_V_SPI_CTRL0_SS_ACTIVE_SS3   ((uint32_t)0x8UL)

CTRL0_SS_ACTIVE_SS3 Value