SPIXR_DMA

Macros
#define	MXC_F_SPIXR_DMA_TX_FIFO_LVL_POS   0
#define	MXC_F_SPIXR_DMA_TX_FIFO_LVL   ((uint32_t)(0x3FUL << MXC_F_SPIXR_DMA_TX_FIFO_LVL_POS))
#define	MXC_F_SPIXR_DMA_TX_FIFO_EN_POS   6
#define	MXC_F_SPIXR_DMA_TX_FIFO_EN   ((uint32_t)(0x1UL << MXC_F_SPIXR_DMA_TX_FIFO_EN_POS))
#define	MXC_F_SPIXR_DMA_TX_FIFO_CLEAR_POS   7
#define	MXC_F_SPIXR_DMA_TX_FIFO_CLEAR   ((uint32_t)(0x1UL << MXC_F_SPIXR_DMA_TX_FIFO_CLEAR_POS))
#define	MXC_F_SPIXR_DMA_TX_FIFO_CNT_POS   8
#define	MXC_F_SPIXR_DMA_TX_FIFO_CNT   ((uint32_t)(0x1FUL << MXC_F_SPIXR_DMA_TX_FIFO_CNT_POS))
#define	MXC_F_SPIXR_DMA_DMA_TX_EN_POS   15
#define	MXC_F_SPIXR_DMA_DMA_TX_EN   ((uint32_t)(0x1UL << MXC_F_SPIXR_DMA_DMA_TX_EN_POS))
#define	MXC_F_SPIXR_DMA_RX_FIFO_LVL_POS   16
#define	MXC_F_SPIXR_DMA_RX_FIFO_LVL   ((uint32_t)(0x3FUL << MXC_F_SPIXR_DMA_RX_FIFO_LVL_POS))
#define	MXC_F_SPIXR_DMA_RX_FIFO_EN_POS   22
#define	MXC_F_SPIXR_DMA_RX_FIFO_EN   ((uint32_t)(0x1UL << MXC_F_SPIXR_DMA_RX_FIFO_EN_POS))
#define	MXC_F_SPIXR_DMA_RX_FIFO_CLR_POS   23
#define	MXC_F_SPIXR_DMA_RX_FIFO_CLR   ((uint32_t)(0x1UL << MXC_F_SPIXR_DMA_RX_FIFO_CLR_POS))
#define	MXC_F_SPIXR_DMA_RX_FIFO_CNT_POS   24
#define	MXC_F_SPIXR_DMA_RX_FIFO_CNT   ((uint32_t)(0x3FUL << MXC_F_SPIXR_DMA_RX_FIFO_CNT_POS))
#define	MXC_F_SPIXR_DMA_DMA_RX_EN_POS   31
#define	MXC_F_SPIXR_DMA_DMA_RX_EN   ((uint32_t)(0x1UL << MXC_F_SPIXR_DMA_DMA_RX_EN_POS))

Detailed Description

Register for controlling DMA.

Macro Definition Documentation

MXC_F_SPIXR_DMA_DMA_RX_EN

#define MXC_F_SPIXR_DMA_DMA_RX_EN   ((uint32_t)(0x1UL << MXC_F_SPIXR_DMA_DMA_RX_EN_POS))

DMA_DMA_RX_EN Mask

MXC_F_SPIXR_DMA_DMA_RX_EN_POS

#define MXC_F_SPIXR_DMA_DMA_RX_EN_POS   31

DMA_DMA_RX_EN Position

MXC_F_SPIXR_DMA_DMA_TX_EN

#define MXC_F_SPIXR_DMA_DMA_TX_EN   ((uint32_t)(0x1UL << MXC_F_SPIXR_DMA_DMA_TX_EN_POS))

DMA_DMA_TX_EN Mask

MXC_F_SPIXR_DMA_DMA_TX_EN_POS

#define MXC_F_SPIXR_DMA_DMA_TX_EN_POS   15

DMA_DMA_TX_EN Position

MXC_F_SPIXR_DMA_RX_FIFO_CLR

#define MXC_F_SPIXR_DMA_RX_FIFO_CLR   ((uint32_t)(0x1UL << MXC_F_SPIXR_DMA_RX_FIFO_CLR_POS))

DMA_RX_FIFO_CLR Mask

MXC_F_SPIXR_DMA_RX_FIFO_CLR_POS

#define MXC_F_SPIXR_DMA_RX_FIFO_CLR_POS   23

DMA_RX_FIFO_CLR Position

MXC_F_SPIXR_DMA_RX_FIFO_CNT

#define MXC_F_SPIXR_DMA_RX_FIFO_CNT   ((uint32_t)(0x3FUL << MXC_F_SPIXR_DMA_RX_FIFO_CNT_POS))

DMA_RX_FIFO_CNT Mask

MXC_F_SPIXR_DMA_RX_FIFO_CNT_POS

#define MXC_F_SPIXR_DMA_RX_FIFO_CNT_POS   24

DMA_RX_FIFO_CNT Position

MXC_F_SPIXR_DMA_RX_FIFO_EN

#define MXC_F_SPIXR_DMA_RX_FIFO_EN   ((uint32_t)(0x1UL << MXC_F_SPIXR_DMA_RX_FIFO_EN_POS))

DMA_RX_FIFO_EN Mask

MXC_F_SPIXR_DMA_RX_FIFO_EN_POS

#define MXC_F_SPIXR_DMA_RX_FIFO_EN_POS   22

DMA_RX_FIFO_EN Position

MXC_F_SPIXR_DMA_RX_FIFO_LVL

#define MXC_F_SPIXR_DMA_RX_FIFO_LVL   ((uint32_t)(0x3FUL << MXC_F_SPIXR_DMA_RX_FIFO_LVL_POS))

DMA_RX_FIFO_LVL Mask

MXC_F_SPIXR_DMA_RX_FIFO_LVL_POS

#define MXC_F_SPIXR_DMA_RX_FIFO_LVL_POS   16

DMA_RX_FIFO_LVL Position

MXC_F_SPIXR_DMA_TX_FIFO_CLEAR

#define MXC_F_SPIXR_DMA_TX_FIFO_CLEAR   ((uint32_t)(0x1UL << MXC_F_SPIXR_DMA_TX_FIFO_CLEAR_POS))

DMA_TX_FIFO_CLEAR Mask

MXC_F_SPIXR_DMA_TX_FIFO_CLEAR_POS

#define MXC_F_SPIXR_DMA_TX_FIFO_CLEAR_POS   7

DMA_TX_FIFO_CLEAR Position

MXC_F_SPIXR_DMA_TX_FIFO_CNT

#define MXC_F_SPIXR_DMA_TX_FIFO_CNT   ((uint32_t)(0x1FUL << MXC_F_SPIXR_DMA_TX_FIFO_CNT_POS))

DMA_TX_FIFO_CNT Mask

MXC_F_SPIXR_DMA_TX_FIFO_CNT_POS

#define MXC_F_SPIXR_DMA_TX_FIFO_CNT_POS   8

DMA_TX_FIFO_CNT Position

MXC_F_SPIXR_DMA_TX_FIFO_EN

#define MXC_F_SPIXR_DMA_TX_FIFO_EN   ((uint32_t)(0x1UL << MXC_F_SPIXR_DMA_TX_FIFO_EN_POS))

DMA_TX_FIFO_EN Mask

MXC_F_SPIXR_DMA_TX_FIFO_EN_POS

#define MXC_F_SPIXR_DMA_TX_FIFO_EN_POS   6

DMA_TX_FIFO_EN Position

MXC_F_SPIXR_DMA_TX_FIFO_LVL

#define MXC_F_SPIXR_DMA_TX_FIFO_LVL   ((uint32_t)(0x3FUL << MXC_F_SPIXR_DMA_TX_FIFO_LVL_POS))

DMA_TX_FIFO_LVL Mask

MXC_F_SPIXR_DMA_TX_FIFO_LVL_POS

#define MXC_F_SPIXR_DMA_TX_FIFO_LVL_POS   0

DMA_TX_FIFO_LVL Position