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#define	MXC_F_TMR_CTRL1_CLKSEL_A_POS 0

#define	MXC_F_TMR_CTRL1_CLKSEL_A ((uint32_t)(0x3UL << MXC_F_TMR_CTRL1_CLKSEL_A_POS))

#define	MXC_F_TMR_CTRL1_CLKEN_A_POS 2

#define	MXC_F_TMR_CTRL1_CLKEN_A ((uint32_t)(0x1UL << MXC_F_TMR_CTRL1_CLKEN_A_POS))

#define	MXC_F_TMR_CTRL1_CLKRDY_A_POS 3

#define	MXC_F_TMR_CTRL1_CLKRDY_A ((uint32_t)(0x1UL << MXC_F_TMR_CTRL1_CLKRDY_A_POS))

#define	MXC_F_TMR_CTRL1_EVENT_SEL_A_POS 4

#define	MXC_F_TMR_CTRL1_EVENT_SEL_A ((uint32_t)(0x7UL << MXC_F_TMR_CTRL1_EVENT_SEL_A_POS))

#define	MXC_F_TMR_CTRL1_NEGTRIG_A_POS 7

#define	MXC_F_TMR_CTRL1_NEGTRIG_A ((uint32_t)(0x1UL << MXC_F_TMR_CTRL1_NEGTRIG_A_POS))

#define	MXC_F_TMR_CTRL1_IE_A_POS 8

#define	MXC_F_TMR_CTRL1_IE_A ((uint32_t)(0x1UL << MXC_F_TMR_CTRL1_IE_A_POS))

#define	MXC_F_TMR_CTRL1_CAPEVENT_SEL_A_POS 9

#define	MXC_F_TMR_CTRL1_CAPEVENT_SEL_A ((uint32_t)(0x3UL << MXC_F_TMR_CTRL1_CAPEVENT_SEL_A_POS))

#define	MXC_F_TMR_CTRL1_SW_CAPEVENT_A_POS 11

#define	MXC_F_TMR_CTRL1_SW_CAPEVENT_A ((uint32_t)(0x1UL << MXC_F_TMR_CTRL1_SW_CAPEVENT_A_POS))

#define	MXC_F_TMR_CTRL1_WE_A_POS 12

#define	MXC_F_TMR_CTRL1_WE_A ((uint32_t)(0x1UL << MXC_F_TMR_CTRL1_WE_A_POS))

#define	MXC_F_TMR_CTRL1_OUTEN_A_POS 13

#define	MXC_F_TMR_CTRL1_OUTEN_A ((uint32_t)(0x1UL << MXC_F_TMR_CTRL1_OUTEN_A_POS))

#define	MXC_F_TMR_CTRL1_OUTBEN_A_POS 14

#define	MXC_F_TMR_CTRL1_OUTBEN_A ((uint32_t)(0x1UL << MXC_F_TMR_CTRL1_OUTBEN_A_POS))

#define	MXC_F_TMR_CTRL1_CLKSEL_B_POS 16

#define	MXC_F_TMR_CTRL1_CLKSEL_B ((uint32_t)(0x3UL << MXC_F_TMR_CTRL1_CLKSEL_B_POS))

#define	MXC_F_TMR_CTRL1_CLKEN_B_POS 18

#define	MXC_F_TMR_CTRL1_CLKEN_B ((uint32_t)(0x1UL << MXC_F_TMR_CTRL1_CLKEN_B_POS))

#define	MXC_F_TMR_CTRL1_CLKRDY_B_POS 19

#define	MXC_F_TMR_CTRL1_CLKRDY_B ((uint32_t)(0x1UL << MXC_F_TMR_CTRL1_CLKRDY_B_POS))

#define	MXC_F_TMR_CTRL1_EVENT_SEL_B_POS 20

#define	MXC_F_TMR_CTRL1_EVENT_SEL_B ((uint32_t)(0x7UL << MXC_F_TMR_CTRL1_EVENT_SEL_B_POS))

#define	MXC_F_TMR_CTRL1_NEGTRIG_B_POS 23

#define	MXC_F_TMR_CTRL1_NEGTRIG_B ((uint32_t)(0x1UL << MXC_F_TMR_CTRL1_NEGTRIG_B_POS))

#define	MXC_F_TMR_CTRL1_IE_B_POS 24

#define	MXC_F_TMR_CTRL1_IE_B ((uint32_t)(0x1UL << MXC_F_TMR_CTRL1_IE_B_POS))

#define	MXC_F_TMR_CTRL1_CAPEVENT_SEL_B_POS 25

#define	MXC_F_TMR_CTRL1_CAPEVENT_SEL_B ((uint32_t)(0x3UL << MXC_F_TMR_CTRL1_CAPEVENT_SEL_B_POS))

#define	MXC_F_TMR_CTRL1_SW_CAPEVENT_B_POS 27

#define	MXC_F_TMR_CTRL1_SW_CAPEVENT_B ((uint32_t)(0x1UL << MXC_F_TMR_CTRL1_SW_CAPEVENT_B_POS))

#define	MXC_F_TMR_CTRL1_WE_B_POS 28

#define	MXC_F_TMR_CTRL1_WE_B ((uint32_t)(0x1UL << MXC_F_TMR_CTRL1_WE_B_POS))

#define	MXC_F_TMR_CTRL1_CASCADE_POS 31

#define	MXC_F_TMR_CTRL1_CASCADE ((uint32_t)(0x1UL << MXC_F_TMR_CTRL1_CASCADE_POS))

Detailed Description

Timer Configuration Register.

Macro Definition Documentation

◆ MXC_F_TMR_CTRL1_CAPEVENT_SEL_A

#define MXC_F_TMR_CTRL1_CAPEVENT_SEL_A ((uint32_t)(0x3UL << MXC_F_TMR_CTRL1_CAPEVENT_SEL_A_POS))

CTRL1_CAPEVENT_SEL_A Mask

◆ MXC_F_TMR_CTRL1_CAPEVENT_SEL_A_POS

#define MXC_F_TMR_CTRL1_CAPEVENT_SEL_A_POS 9

CTRL1_CAPEVENT_SEL_A Position

◆ MXC_F_TMR_CTRL1_CAPEVENT_SEL_B

#define MXC_F_TMR_CTRL1_CAPEVENT_SEL_B ((uint32_t)(0x3UL << MXC_F_TMR_CTRL1_CAPEVENT_SEL_B_POS))

CTRL1_CAPEVENT_SEL_B Mask

◆ MXC_F_TMR_CTRL1_CAPEVENT_SEL_B_POS

#define MXC_F_TMR_CTRL1_CAPEVENT_SEL_B_POS 25

CTRL1_CAPEVENT_SEL_B Position

◆ MXC_F_TMR_CTRL1_CASCADE

#define MXC_F_TMR_CTRL1_CASCADE ((uint32_t)(0x1UL << MXC_F_TMR_CTRL1_CASCADE_POS))

CTRL1_CASCADE Mask

◆ MXC_F_TMR_CTRL1_CASCADE_POS

#define MXC_F_TMR_CTRL1_CASCADE_POS 31

CTRL1_CASCADE Position

◆ MXC_F_TMR_CTRL1_CLKEN_A

#define MXC_F_TMR_CTRL1_CLKEN_A ((uint32_t)(0x1UL << MXC_F_TMR_CTRL1_CLKEN_A_POS))

CTRL1_CLKEN_A Mask

◆ MXC_F_TMR_CTRL1_CLKEN_A_POS

#define MXC_F_TMR_CTRL1_CLKEN_A_POS 2

CTRL1_CLKEN_A Position

◆ MXC_F_TMR_CTRL1_CLKEN_B

#define MXC_F_TMR_CTRL1_CLKEN_B ((uint32_t)(0x1UL << MXC_F_TMR_CTRL1_CLKEN_B_POS))

CTRL1_CLKEN_B Mask

◆ MXC_F_TMR_CTRL1_CLKEN_B_POS

#define MXC_F_TMR_CTRL1_CLKEN_B_POS 18

CTRL1_CLKEN_B Position

◆ MXC_F_TMR_CTRL1_CLKRDY_A

#define MXC_F_TMR_CTRL1_CLKRDY_A ((uint32_t)(0x1UL << MXC_F_TMR_CTRL1_CLKRDY_A_POS))

CTRL1_CLKRDY_A Mask

◆ MXC_F_TMR_CTRL1_CLKRDY_A_POS

#define MXC_F_TMR_CTRL1_CLKRDY_A_POS 3

CTRL1_CLKRDY_A Position

◆ MXC_F_TMR_CTRL1_CLKRDY_B

#define MXC_F_TMR_CTRL1_CLKRDY_B ((uint32_t)(0x1UL << MXC_F_TMR_CTRL1_CLKRDY_B_POS))

CTRL1_CLKRDY_B Mask

◆ MXC_F_TMR_CTRL1_CLKRDY_B_POS

#define MXC_F_TMR_CTRL1_CLKRDY_B_POS 19

CTRL1_CLKRDY_B Position

◆ MXC_F_TMR_CTRL1_CLKSEL_A

#define MXC_F_TMR_CTRL1_CLKSEL_A ((uint32_t)(0x3UL << MXC_F_TMR_CTRL1_CLKSEL_A_POS))

CTRL1_CLKSEL_A Mask

◆ MXC_F_TMR_CTRL1_CLKSEL_A_POS

#define MXC_F_TMR_CTRL1_CLKSEL_A_POS 0

CTRL1_CLKSEL_A Position

◆ MXC_F_TMR_CTRL1_CLKSEL_B

#define MXC_F_TMR_CTRL1_CLKSEL_B ((uint32_t)(0x3UL << MXC_F_TMR_CTRL1_CLKSEL_B_POS))

CTRL1_CLKSEL_B Mask

◆ MXC_F_TMR_CTRL1_CLKSEL_B_POS

#define MXC_F_TMR_CTRL1_CLKSEL_B_POS 16

CTRL1_CLKSEL_B Position

◆ MXC_F_TMR_CTRL1_EVENT_SEL_A

#define MXC_F_TMR_CTRL1_EVENT_SEL_A ((uint32_t)(0x7UL << MXC_F_TMR_CTRL1_EVENT_SEL_A_POS))

CTRL1_EVENT_SEL_A Mask

◆ MXC_F_TMR_CTRL1_EVENT_SEL_A_POS

#define MXC_F_TMR_CTRL1_EVENT_SEL_A_POS 4

CTRL1_EVENT_SEL_A Position

◆ MXC_F_TMR_CTRL1_EVENT_SEL_B

#define MXC_F_TMR_CTRL1_EVENT_SEL_B ((uint32_t)(0x7UL << MXC_F_TMR_CTRL1_EVENT_SEL_B_POS))

CTRL1_EVENT_SEL_B Mask

◆ MXC_F_TMR_CTRL1_EVENT_SEL_B_POS

#define MXC_F_TMR_CTRL1_EVENT_SEL_B_POS 20

CTRL1_EVENT_SEL_B Position

◆ MXC_F_TMR_CTRL1_IE_A

#define MXC_F_TMR_CTRL1_IE_A ((uint32_t)(0x1UL << MXC_F_TMR_CTRL1_IE_A_POS))

CTRL1_IE_A Mask

◆ MXC_F_TMR_CTRL1_IE_A_POS

#define MXC_F_TMR_CTRL1_IE_A_POS 8

CTRL1_IE_A Position

◆ MXC_F_TMR_CTRL1_IE_B

#define MXC_F_TMR_CTRL1_IE_B ((uint32_t)(0x1UL << MXC_F_TMR_CTRL1_IE_B_POS))

CTRL1_IE_B Mask

◆ MXC_F_TMR_CTRL1_IE_B_POS

#define MXC_F_TMR_CTRL1_IE_B_POS 24

CTRL1_IE_B Position

◆ MXC_F_TMR_CTRL1_NEGTRIG_A

#define MXC_F_TMR_CTRL1_NEGTRIG_A ((uint32_t)(0x1UL << MXC_F_TMR_CTRL1_NEGTRIG_A_POS))

CTRL1_NEGTRIG_A Mask

◆ MXC_F_TMR_CTRL1_NEGTRIG_A_POS

#define MXC_F_TMR_CTRL1_NEGTRIG_A_POS 7

CTRL1_NEGTRIG_A Position

◆ MXC_F_TMR_CTRL1_NEGTRIG_B

#define MXC_F_TMR_CTRL1_NEGTRIG_B ((uint32_t)(0x1UL << MXC_F_TMR_CTRL1_NEGTRIG_B_POS))

CTRL1_NEGTRIG_B Mask

◆ MXC_F_TMR_CTRL1_NEGTRIG_B_POS

#define MXC_F_TMR_CTRL1_NEGTRIG_B_POS 23

CTRL1_NEGTRIG_B Position

◆ MXC_F_TMR_CTRL1_OUTBEN_A

#define MXC_F_TMR_CTRL1_OUTBEN_A ((uint32_t)(0x1UL << MXC_F_TMR_CTRL1_OUTBEN_A_POS))

CTRL1_OUTBEN_A Mask

◆ MXC_F_TMR_CTRL1_OUTBEN_A_POS

#define MXC_F_TMR_CTRL1_OUTBEN_A_POS 14

CTRL1_OUTBEN_A Position

◆ MXC_F_TMR_CTRL1_OUTEN_A

#define MXC_F_TMR_CTRL1_OUTEN_A ((uint32_t)(0x1UL << MXC_F_TMR_CTRL1_OUTEN_A_POS))

CTRL1_OUTEN_A Mask

◆ MXC_F_TMR_CTRL1_OUTEN_A_POS

#define MXC_F_TMR_CTRL1_OUTEN_A_POS 13

CTRL1_OUTEN_A Position

◆ MXC_F_TMR_CTRL1_SW_CAPEVENT_A

#define MXC_F_TMR_CTRL1_SW_CAPEVENT_A ((uint32_t)(0x1UL << MXC_F_TMR_CTRL1_SW_CAPEVENT_A_POS))

CTRL1_SW_CAPEVENT_A Mask

◆ MXC_F_TMR_CTRL1_SW_CAPEVENT_A_POS

#define MXC_F_TMR_CTRL1_SW_CAPEVENT_A_POS 11

CTRL1_SW_CAPEVENT_A Position

◆ MXC_F_TMR_CTRL1_SW_CAPEVENT_B

#define MXC_F_TMR_CTRL1_SW_CAPEVENT_B ((uint32_t)(0x1UL << MXC_F_TMR_CTRL1_SW_CAPEVENT_B_POS))

CTRL1_SW_CAPEVENT_B Mask

◆ MXC_F_TMR_CTRL1_SW_CAPEVENT_B_POS

#define MXC_F_TMR_CTRL1_SW_CAPEVENT_B_POS 27

CTRL1_SW_CAPEVENT_B Position

◆ MXC_F_TMR_CTRL1_WE_A

#define MXC_F_TMR_CTRL1_WE_A ((uint32_t)(0x1UL << MXC_F_TMR_CTRL1_WE_A_POS))

CTRL1_WE_A Mask

◆ MXC_F_TMR_CTRL1_WE_A_POS

#define MXC_F_TMR_CTRL1_WE_A_POS 12

CTRL1_WE_A Position

◆ MXC_F_TMR_CTRL1_WE_B

#define MXC_F_TMR_CTRL1_WE_B ((uint32_t)(0x1UL << MXC_F_TMR_CTRL1_WE_B_POS))

CTRL1_WE_B Mask

◆ MXC_F_TMR_CTRL1_WE_B_POS

#define MXC_F_TMR_CTRL1_WE_B_POS 28

CTRL1_WE_B Position

Macros