HyperBus (HPB)

Modules
	HPB_Registers

Data Structures
struct	mxc_hpb_cfg_reg_val_t
struct	mxc_hpb_mem_config_t

Enumerations
enum	mxc_hpb_cs_high_t
enum	mxc_hpb_cs_setup_hold_t
enum	mxc_hpb_latency_t
enum	mxc_hpb_device_t

Functions
void	MXC_HPB_RegRead8 (mxc_hpb_cfg_reg_val_t *cfg_reg_val, uint32_t base_addr, unsigned int index)
void	MXC_HPB_RegWrite8 (mxc_hpb_cfg_reg_val_t *cfg_reg_val, uint32_t base_addr, unsigned int index)
void	MXC_HPB_RegRead16 (mxc_hpb_cfg_reg_val_t *cfg_reg_val, uint32_t base_addr, unsigned int index)
void	MXC_HPB_RegWrite16 (mxc_hpb_cfg_reg_val_t *cfg_reg_val, uint32_t base_addr, unsigned int index)
int	MXC_HPB_Init (mxc_hpb_mem_config_t *mem0, mxc_hpb_mem_config_t *mem1)
uint32_t	MXC_HPB_GetStatus (void)
void	MXC_HPB_EnableInt (unsigned polarity)
unsigned	MXC_HPB_GetFlag (void)

Detailed Description

---

Data Structure Documentation

mxc_hpb_cfg_reg_val_t

struct mxc_hpb_cfg_reg_val_t

Structure type containing register offset-value pairs.

Data Fields
uint32_t	addr

Field Documentation

addr

uint32_t addr

Offset from port base

mxc_hpb_mem_config_t

struct mxc_hpb_mem_config_t

Structure type to configure the HPB controller.

Data Fields
uint32_t	base_addr
mxc_hpb_device_t	device_type
mxc_hpb_cfg_reg_val_t *	cfg_reg_val
unsigned int	cfg_reg_val_len
mxc_hpb_cs_high_t	read_cs_high
mxc_hpb_cs_high_t	write_cs_high
mxc_hpb_cs_setup_hold_t	read_cs_setup
mxc_hpb_cs_setup_hold_t	write_cs_setup
mxc_hpb_cs_setup_hold_t	read_cs_hold
mxc_hpb_cs_setup_hold_t	write_cs_hold
mxc_hpb_latency_t	latency_cycle

Field Documentation

base_addr

uint32_t base_addr

The base address for memory space

cfg_reg_val

mxc_hpb_cfg_reg_val_t* cfg_reg_val

Pointer to array of address offset/value pairs

cfg_reg_val_len

unsigned int cfg_reg_val_len

number of configuration pairs

device_type

mxc_hpb_device_t device_type

Type of device attached to controller

latency_cycle

mxc_hpb_latency_t latency_cycle

Latency Cycle for HyperRAM mode, ignored when the connected device is HyperFlash

read_cs_high

mxc_hpb_cs_high_t read_cs_high

Before the read access, this setting inserts the CK cycles to the chip select high period.

read_cs_hold

mxc_hpb_cs_setup_hold_t read_cs_hold

In the read access, this setting inserts the CK cycles, between the falling edge of last CK and the rising edge of chip select.

read_cs_setup

mxc_hpb_cs_setup_hold_t read_cs_setup

In the read access, this setting inserts the CK cycles, between the falling edge of chip select and the rising edge of first CK.

write_cs_high

mxc_hpb_cs_high_t write_cs_high

Before the write access, this setting inserts the CK cycles to the chip select high period.

write_cs_hold

mxc_hpb_cs_setup_hold_t write_cs_hold

In the write access, this setting inserts the CK cycles, between the falling edge of last CK and the rising edge of chip select

write_cs_setup

mxc_hpb_cs_setup_hold_t write_cs_setup

In the write access, this setting inserts the CK cycles, between the falling edge of chip select and the rising edge of first CK.

Enumeration Type Documentation

mxc_hpb_cs_high_t

enum mxc_hpb_cs_high_t

Enumeration type to select the number of cycles CS is high.

Enumerator
MXC_HPB_CS_HIGH_1_5	CS High 1.5 clock cycles
MXC_HPB_CS_HIGH_2_5	CS High 2.5 clock cycles
MXC_HPB_CS_HIGH_3_5	CS High 3.5 clock cycles
MXC_HPB_CS_HIGH_4_5	CS High 4.5 clock cycles
MXC_HPB_CS_HIGH_5_5	CS High 5.5 clock cycles
MXC_HPB_CS_HIGH_6_5	CS High 6.5 clock cycles
MXC_HPB_CS_HIGH_7_5	CS High 7.5 clock cycles
MXC_HPB_CS_HIGH_8_5	CS High 8.5 clock cycles
MXC_HPB_CS_HIGH_9_5	CS High 9.5 clock cycles
MXC_HPB_CS_HIGH_10_5	CS High 10.5 clock cycles
MXC_HPB_CS_HIGH_11_5	CS High 11.5 clock cycles
MXC_HPB_CS_HIGH_12_5	CS High 12.5 clock cycles
MXC_HPB_CS_HIGH_13_5	CS High 13.5 clock cycles
MXC_HPB_CS_HIGH_14_5	CS High 14.5 clock cycles
MXC_HPB_CS_HIGH_15_5	CS High 15.5 clock cycles
MXC_HPB_CS_HIGH_16_5	CS High 16.5 clock cycles

mxc_hpb_cs_setup_hold_t

enum mxc_hpb_cs_setup_hold_t

Enumeration type to select the number of clock cycles between asserting the CS signal and the first clock cycle.

Enumerator
MXC_HPB_CS_SETUP_HOLD_1	CS Setup/Hold 1 clock cycles
MXC_HPB_CS_SETUP_HOLD_2	CS Setup/Hold 2 clock cycles
MXC_HPB_CS_SETUP_HOLD_3	CS Setup/Hold 3 clock cycles
MXC_HPB_CS_SETUP_HOLD_4	CS Setup/Hold 4 clock cycles
MXC_HPB_CS_SETUP_HOLD_5	CS Setup/Hold 5 clock cycles
MXC_HPB_CS_SETUP_HOLD_6	CS Setup/Hold 6 clock cycles
MXC_HPB_CS_SETUP_HOLD_7	CS Setup/Hold 7 clock cycles
MXC_HPB_CS_SETUP_HOLD_8	CS Setup/Hold 8 clock cycles
MXC_HPB_CS_SETUP_HOLD_9	CS Setup/Hold 9 clock cycles
MXC_HPB_CS_SETUP_HOLD_10	CS Setup/Hold 10 clock cycles
MXC_HPB_CS_SETUP_HOLD_11	CS Setup/Hold 11 clock cycles
MXC_HPB_CS_SETUP_HOLD_12	CS Setup/Hold 12 clock cycles
MXC_HPB_CS_SETUP_HOLD_13	CS Setup/Hold 13 clock cycles
MXC_HPB_CS_SETUP_HOLD_14	CS Setup/Hold 14 clock cycles
MXC_HPB_CS_SETUP_HOLD_15	CS Setup/Hold 15 clock cycles
MXC_HPB_CS_SETUP_HOLD_16	CS Setup/Hold 16 clock cycles

mxc_hpb_device_t

enum mxc_hpb_device_t

Enumeration type to select the type of device connected to the HPB controller.

mxc_hpb_latency_t

enum mxc_hpb_latency_t

Enumeration type to select the number of clock cycles for the latency of RAM operations.

Enumerator
MXC_HPB_LAT_5	5 clock latency for RAM
MXC_HPB_LAT_6	6 clock latency for RAM
MXC_HPB_LAT_3	3 clock latency for RAM
MXC_HPB_LAT_4	4 clock latency for RAM

Function Documentation

MXC_HPB_EnableInt()

void MXC_HPB_EnableInt

(

unsigned

polarity

)

Enable HPB interrupt.

Parameters

polarity

1 to use active high, 0 to use active low.

MXC_HPB_GetFlag()

unsigned MXC_HPB_GetFlag

(

void

)

Get HPB interrupt status.

Returns

1 if flag is set, 0 if not.

MXC_HPB_GetStatus()

uint32_t MXC_HPB_GetStatus

(

void

)

Returns the contents of the status register.

Note

Use MXC_F_HPB_CSR macros to filter out specific status bits.

Returns

HPB status register.

MXC_HPB_Init()

int MXC_HPB_Init	(	mxc_hpb_mem_config_t *	mem0,
		mxc_hpb_mem_config_t *	mem1
	)

Configure the HyperBus peripheral.

Parameters

mem0	Pointer to configuration struct for mem0 (may be NULL if this memory not used)
mem1	Pointer to configuration struct for mem1 (may be NULL if this memory not used)

Returns

E_BAD_PARAM if configuration error, E_NO_ERROR otherwise

MXC_HPB_RegRead16()

void MXC_HPB_RegRead16	(	mxc_hpb_cfg_reg_val_t *	cfg_reg_val,
		uint32_t	base_addr,
		unsigned int	index
	)

Read a variable.

Parameters

cfg_reg_val	Pointer to configuration struct to read a variable
base_addr	Base address
index	0 or 1 to determine which configuration settings

MXC_HPB_RegRead8()

void MXC_HPB_RegRead8	(	mxc_hpb_cfg_reg_val_t *	cfg_reg_val,
		uint32_t	base_addr,
		unsigned int	index
	)

Read a variable.

Parameters

cfg_reg_val	Pointer to configuration struct to read a variable
base_addr	Base address
index	0 or 1 to determine which configuration settings

MXC_HPB_RegWrite16()

void MXC_HPB_RegWrite16	(	mxc_hpb_cfg_reg_val_t *	cfg_reg_val,
		uint32_t	base_addr,
		unsigned int	index
	)

Read a variable.

Parameters

cfg_reg_val	Pointer to configuration struct to read a variable
base_addr	Base address
index	0 or 1 to determine which configuration settings

MXC_HPB_RegWrite8()

void MXC_HPB_RegWrite8	(	mxc_hpb_cfg_reg_val_t *	cfg_reg_val,
		uint32_t	base_addr,
		unsigned int	index
	)

Read a variable.

Parameters

cfg_reg_val	Pointer to configuration struct to read a variable
base_addr	Base address
index	0 or 1 to determine which configuration settings