MAX32690 Peripheral Driver API
Peripheral Driver API for the MAX32690
hpb_regs.h
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1
8/******************************************************************************
9 *
10 * Copyright (C) 2022-2023 Maxim Integrated Products, Inc. (now owned by
11 * Analog Devices, Inc.),
12 * Copyright (C) 2023-2024 Analog Devices, Inc.
13 *
14 * Licensed under the Apache License, Version 2.0 (the "License");
15 * you may not use this file except in compliance with the License.
16 * You may obtain a copy of the License at
17 *
18 * http://www.apache.org/licenses/LICENSE-2.0
19 *
20 * Unless required by applicable law or agreed to in writing, software
21 * distributed under the License is distributed on an "AS IS" BASIS,
22 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
23 * See the License for the specific language governing permissions and
24 * limitations under the License.
25 *
26 ******************************************************************************/
27
28#ifndef LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32690_INCLUDE_HPB_REGS_H_
29#define LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32690_INCLUDE_HPB_REGS_H_
30
31/* **** Includes **** */
32#include <stdint.h>
33
34#ifdef __cplusplus
35extern "C" {
36#endif
37
38#if defined (__ICCARM__)
39 #pragma system_include
40#endif
41
42#if defined (__CC_ARM)
43 #pragma anon_unions
44#endif
46/*
47 If types are not defined elsewhere (CMSIS) define them here
48*/
49#ifndef __IO
50#define __IO volatile
51#endif
52#ifndef __I
53#define __I volatile const
54#endif
55#ifndef __O
56#define __O volatile
57#endif
58#ifndef __R
59#define __R volatile const
60#endif
62
63/* **** Definitions **** */
64
76typedef struct {
77 __IO uint32_t stat;
78 __IO uint32_t inten;
79 __IO uint32_t intfl;
80 __R uint32_t rsv_0xc;
81 __IO uint32_t membaddr[2];
82 __R uint32_t rsv_0x18_0x1f[2];
83 __IO uint32_t memctrl[2];
84 __R uint32_t rsv_0x28_0x2f[2];
85 __IO uint32_t memtim[2];
86} mxc_hpb_regs_t;
87
88/* Register offsets for module HPB */
95#define MXC_R_HPB_STAT ((uint32_t)0x00000000UL)
96#define MXC_R_HPB_INTEN ((uint32_t)0x00000004UL)
97#define MXC_R_HPB_INTFL ((uint32_t)0x00000008UL)
98#define MXC_R_HPB_MEMBADDR ((uint32_t)0x00000010UL)
99#define MXC_R_HPB_MEMCTRL ((uint32_t)0x00000020UL)
100#define MXC_R_HPB_MEMTIM ((uint32_t)0x00000030UL)
109#define MXC_F_HPB_STAT_RDTXN_POS 0
110#define MXC_F_HPB_STAT_RDTXN ((uint32_t)(0x1UL << MXC_F_HPB_STAT_RDTXN_POS))
112#define MXC_F_HPB_STAT_RDADDRERR_POS 8
113#define MXC_F_HPB_STAT_RDADDRERR ((uint32_t)(0x1UL << MXC_F_HPB_STAT_RDADDRERR_POS))
115#define MXC_F_HPB_STAT_RDSLVST_POS 9
116#define MXC_F_HPB_STAT_RDSLVST ((uint32_t)(0x1UL << MXC_F_HPB_STAT_RDSLVST_POS))
118#define MXC_F_HPB_STAT_RDRSTERR_POS 10
119#define MXC_F_HPB_STAT_RDRSTERR ((uint32_t)(0x1UL << MXC_F_HPB_STAT_RDRSTERR_POS))
121#define MXC_F_HPB_STAT_RDSTALL_POS 11
122#define MXC_F_HPB_STAT_RDSTALL ((uint32_t)(0x1UL << MXC_F_HPB_STAT_RDSTALL_POS))
124#define MXC_F_HPB_STAT_WRTXN_POS 16
125#define MXC_F_HPB_STAT_WRTXN ((uint32_t)(0x1UL << MXC_F_HPB_STAT_WRTXN_POS))
127#define MXC_F_HPB_STAT_WRADDRERR_POS 24
128#define MXC_F_HPB_STAT_WRADDRERR ((uint32_t)(0x1UL << MXC_F_HPB_STAT_WRADDRERR_POS))
130#define MXC_F_HPB_STAT_WRRSTERR_POS 26
131#define MXC_F_HPB_STAT_WRRSTERR ((uint32_t)(0x1UL << MXC_F_HPB_STAT_WRRSTERR_POS))
141#define MXC_F_HPB_INTEN_MEM_POS 0
142#define MXC_F_HPB_INTEN_MEM ((uint32_t)(0x1UL << MXC_F_HPB_INTEN_MEM_POS))
144#define MXC_F_HPB_INTEN_ERR_POS 1
145#define MXC_F_HPB_INTEN_ERR ((uint32_t)(0x1UL << MXC_F_HPB_INTEN_ERR_POS))
155#define MXC_F_HPB_INTFL_MEM_POS 0
156#define MXC_F_HPB_INTFL_MEM ((uint32_t)(0x1UL << MXC_F_HPB_INTFL_MEM_POS))
158#define MXC_F_HPB_INTFL_ERR_POS 1
159#define MXC_F_HPB_INTFL_ERR ((uint32_t)(0x1UL << MXC_F_HPB_INTFL_ERR_POS))
169#define MXC_F_HPB_MEMBADDR_ADDR_POS 0
170#define MXC_F_HPB_MEMBADDR_ADDR ((uint32_t)(0xFFFFFFFFUL << MXC_F_HPB_MEMBADDR_ADDR_POS))
180#define MXC_F_HPB_MEMCTRL_WRAPSIZE_POS 0
181#define MXC_F_HPB_MEMCTRL_WRAPSIZE ((uint32_t)(0x3UL << MXC_F_HPB_MEMCTRL_WRAPSIZE_POS))
182#define MXC_V_HPB_MEMCTRL_WRAPSIZE_64B ((uint32_t)0x1UL)
183#define MXC_S_HPB_MEMCTRL_WRAPSIZE_64B (MXC_V_HPB_MEMCTRL_WRAPSIZE_64B << MXC_F_HPB_MEMCTRL_WRAPSIZE_POS)
184#define MXC_V_HPB_MEMCTRL_WRAPSIZE_16B ((uint32_t)0x2UL)
185#define MXC_S_HPB_MEMCTRL_WRAPSIZE_16B (MXC_V_HPB_MEMCTRL_WRAPSIZE_16B << MXC_F_HPB_MEMCTRL_WRAPSIZE_POS)
186#define MXC_V_HPB_MEMCTRL_WRAPSIZE_32B ((uint32_t)0x3UL)
187#define MXC_S_HPB_MEMCTRL_WRAPSIZE_32B (MXC_V_HPB_MEMCTRL_WRAPSIZE_32B << MXC_F_HPB_MEMCTRL_WRAPSIZE_POS)
189#define MXC_F_HPB_MEMCTRL_DEVTYPE_POS 3
190#define MXC_F_HPB_MEMCTRL_DEVTYPE ((uint32_t)(0x3UL << MXC_F_HPB_MEMCTRL_DEVTYPE_POS))
191#define MXC_V_HPB_MEMCTRL_DEVTYPE_HYPERFLASH ((uint32_t)0x0UL)
192#define MXC_S_HPB_MEMCTRL_DEVTYPE_HYPERFLASH (MXC_V_HPB_MEMCTRL_DEVTYPE_HYPERFLASH << MXC_F_HPB_MEMCTRL_DEVTYPE_POS)
193#define MXC_V_HPB_MEMCTRL_DEVTYPE_XCCELA_PSRAM ((uint32_t)0x1UL)
194#define MXC_S_HPB_MEMCTRL_DEVTYPE_XCCELA_PSRAM (MXC_V_HPB_MEMCTRL_DEVTYPE_XCCELA_PSRAM << MXC_F_HPB_MEMCTRL_DEVTYPE_POS)
195#define MXC_V_HPB_MEMCTRL_DEVTYPE_HYPERRAM ((uint32_t)0x2UL)
196#define MXC_S_HPB_MEMCTRL_DEVTYPE_HYPERRAM (MXC_V_HPB_MEMCTRL_DEVTYPE_HYPERRAM << MXC_F_HPB_MEMCTRL_DEVTYPE_POS)
198#define MXC_F_HPB_MEMCTRL_CRT_POS 5
199#define MXC_F_HPB_MEMCTRL_CRT ((uint32_t)(0x1UL << MXC_F_HPB_MEMCTRL_CRT_POS))
201#define MXC_F_HPB_MEMCTRL_RDLAT_EN_POS 6
202#define MXC_F_HPB_MEMCTRL_RDLAT_EN ((uint32_t)(0x1UL << MXC_F_HPB_MEMCTRL_RDLAT_EN_POS))
204#define MXC_F_HPB_MEMCTRL_HSE_POS 7
205#define MXC_F_HPB_MEMCTRL_HSE ((uint32_t)(0x1UL << MXC_F_HPB_MEMCTRL_HSE_POS))
207#define MXC_F_HPB_MEMCTRL_MAXLEN_POS 18
208#define MXC_F_HPB_MEMCTRL_MAXLEN ((uint32_t)(0x1FFUL << MXC_F_HPB_MEMCTRL_MAXLEN_POS))
210#define MXC_F_HPB_MEMCTRL_MAX_EN_POS 31
211#define MXC_F_HPB_MEMCTRL_MAX_EN ((uint32_t)(0x1UL << MXC_F_HPB_MEMCTRL_MAX_EN_POS))
221#define MXC_F_HPB_MEMTIM_LAT_POS 0
222#define MXC_F_HPB_MEMTIM_LAT ((uint32_t)(0xFUL << MXC_F_HPB_MEMTIM_LAT_POS))
223#define MXC_V_HPB_MEMTIM_LAT_5CLK ((uint32_t)0x0UL)
224#define MXC_S_HPB_MEMTIM_LAT_5CLK (MXC_V_HPB_MEMTIM_LAT_5CLK << MXC_F_HPB_MEMTIM_LAT_POS)
225#define MXC_V_HPB_MEMTIM_LAT_6CLK ((uint32_t)0x1UL)
226#define MXC_S_HPB_MEMTIM_LAT_6CLK (MXC_V_HPB_MEMTIM_LAT_6CLK << MXC_F_HPB_MEMTIM_LAT_POS)
227#define MXC_V_HPB_MEMTIM_LAT_3CLK ((uint32_t)0xEUL)
228#define MXC_S_HPB_MEMTIM_LAT_3CLK (MXC_V_HPB_MEMTIM_LAT_3CLK << MXC_F_HPB_MEMTIM_LAT_POS)
229#define MXC_V_HPB_MEMTIM_LAT_4CLK ((uint32_t)0xFUL)
230#define MXC_S_HPB_MEMTIM_LAT_4CLK (MXC_V_HPB_MEMTIM_LAT_4CLK << MXC_F_HPB_MEMTIM_LAT_POS)
232#define MXC_F_HPB_MEMTIM_WRCSHD_POS 8
233#define MXC_F_HPB_MEMTIM_WRCSHD ((uint32_t)(0xFUL << MXC_F_HPB_MEMTIM_WRCSHD_POS))
235#define MXC_F_HPB_MEMTIM_RDCSHD_POS 12
236#define MXC_F_HPB_MEMTIM_RDCSHD ((uint32_t)(0xFUL << MXC_F_HPB_MEMTIM_RDCSHD_POS))
238#define MXC_F_HPB_MEMTIM_WRCSST_POS 16
239#define MXC_F_HPB_MEMTIM_WRCSST ((uint32_t)(0xFUL << MXC_F_HPB_MEMTIM_WRCSST_POS))
241#define MXC_F_HPB_MEMTIM_RDCSST_POS 20
242#define MXC_F_HPB_MEMTIM_RDCSST ((uint32_t)(0xFUL << MXC_F_HPB_MEMTIM_RDCSST_POS))
244#define MXC_F_HPB_MEMTIM_WRCSHI_POS 24
245#define MXC_F_HPB_MEMTIM_WRCSHI ((uint32_t)(0xFUL << MXC_F_HPB_MEMTIM_WRCSHI_POS))
247#define MXC_F_HPB_MEMTIM_RDCSHI_POS 28
248#define MXC_F_HPB_MEMTIM_RDCSHI ((uint32_t)(0xFUL << MXC_F_HPB_MEMTIM_RDCSHI_POS))
252#ifdef __cplusplus
253}
254#endif
255
256#endif // LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32690_INCLUDE_HPB_REGS_H_
mxc_hpb_regs_t::intfl
__IO uint32_t intfl
Definition: hpb_regs.h:79
mxc_hpb_regs_t::stat
__IO uint32_t stat
Definition: hpb_regs.h:77
mxc_hpb_regs_t::inten
__IO uint32_t inten
Definition: hpb_regs.h:78
mxc_hpb_regs_t
Definition: hpb_regs.h:76