DMA_SRC

Macros
#define	MXC_F_DMA_SRC_ADDR_POS   0
#define	MXC_F_DMA_SRC_ADDR   ((uint32_t)(0xFFFFFFFFUL << MXC_F_DMA_SRC_ADDR_POS))

Detailed Description

Source Device Address. If SRCINC=1, the counter bits are incremented by 1,2, or 4, depending on the data width of each AHB cycle. For peripheral transfers, some or all of the actual address bits are fixed. If SRCINC=0, this register remains constant. In the case where a count-to-zero condition occurs while RLDEN=1, the register is reloaded with the contents of DMA_SRC_RLD.

Macro Definition Documentation

MXC_F_DMA_SRC_ADDR

#define MXC_F_DMA_SRC_ADDR   ((uint32_t)(0xFFFFFFFFUL << MXC_F_DMA_SRC_ADDR_POS))

SRC_ADDR Mask

MXC_F_DMA_SRC_ADDR_POS

#define MXC_F_DMA_SRC_ADDR_POS   0

SRC_ADDR Position