ADC_CHSEL2

Macros
#define	MXC_F_ADC_CHSEL2_SLOT8_ID_POS   0
#define	MXC_F_ADC_CHSEL2_SLOT8_ID   ((uint32_t)(0x1FUL << MXC_F_ADC_CHSEL2_SLOT8_ID_POS))
#define	MXC_F_ADC_CHSEL2_SLOT9_ID_POS   8
#define	MXC_F_ADC_CHSEL2_SLOT9_ID   ((uint32_t)(0x1FUL << MXC_F_ADC_CHSEL2_SLOT9_ID_POS))
#define	MXC_F_ADC_CHSEL2_SLOT10_ID_POS   16
#define	MXC_F_ADC_CHSEL2_SLOT10_ID   ((uint32_t)(0x1FUL << MXC_F_ADC_CHSEL2_SLOT10_ID_POS))
#define	MXC_F_ADC_CHSEL2_SLOT11_ID_POS   24
#define	MXC_F_ADC_CHSEL2_SLOT11_ID   ((uint32_t)(0x1FUL << MXC_F_ADC_CHSEL2_SLOT11_ID_POS))

Detailed Description

Channel Select Register 2.

Macro Definition Documentation

MXC_F_ADC_CHSEL2_SLOT10_ID

#define MXC_F_ADC_CHSEL2_SLOT10_ID   ((uint32_t)(0x1FUL << MXC_F_ADC_CHSEL2_SLOT10_ID_POS))

CHSEL2_SLOT10_ID Mask

MXC_F_ADC_CHSEL2_SLOT10_ID_POS

#define MXC_F_ADC_CHSEL2_SLOT10_ID_POS   16

CHSEL2_SLOT10_ID Position

MXC_F_ADC_CHSEL2_SLOT11_ID

#define MXC_F_ADC_CHSEL2_SLOT11_ID   ((uint32_t)(0x1FUL << MXC_F_ADC_CHSEL2_SLOT11_ID_POS))

CHSEL2_SLOT11_ID Mask

MXC_F_ADC_CHSEL2_SLOT11_ID_POS

#define MXC_F_ADC_CHSEL2_SLOT11_ID_POS   24

CHSEL2_SLOT11_ID Position

MXC_F_ADC_CHSEL2_SLOT8_ID

#define MXC_F_ADC_CHSEL2_SLOT8_ID   ((uint32_t)(0x1FUL << MXC_F_ADC_CHSEL2_SLOT8_ID_POS))

CHSEL2_SLOT8_ID Mask

MXC_F_ADC_CHSEL2_SLOT8_ID_POS

#define MXC_F_ADC_CHSEL2_SLOT8_ID_POS   0

CHSEL2_SLOT8_ID Position

MXC_F_ADC_CHSEL2_SLOT9_ID

#define MXC_F_ADC_CHSEL2_SLOT9_ID   ((uint32_t)(0x1FUL << MXC_F_ADC_CHSEL2_SLOT9_ID_POS))

CHSEL2_SLOT9_ID Mask

MXC_F_ADC_CHSEL2_SLOT9_ID_POS

#define MXC_F_ADC_CHSEL2_SLOT9_ID_POS   8

CHSEL2_SLOT9_ID Position