ADC_CTRL1

Macros
#define	MXC_F_ADC_CTRL1_START_POS   0
#define	MXC_F_ADC_CTRL1_START   ((uint32_t)(0x1UL << MXC_F_ADC_CTRL1_START_POS))
#define	MXC_F_ADC_CTRL1_TRIG_MODE_POS   1
#define	MXC_F_ADC_CTRL1_TRIG_MODE   ((uint32_t)(0x1UL << MXC_F_ADC_CTRL1_TRIG_MODE_POS))
#define	MXC_F_ADC_CTRL1_CNV_MODE_POS   2
#define	MXC_F_ADC_CTRL1_CNV_MODE   ((uint32_t)(0x1UL << MXC_F_ADC_CTRL1_CNV_MODE_POS))
#define	MXC_F_ADC_CTRL1_SAMP_CK_OFF_POS   3
#define	MXC_F_ADC_CTRL1_SAMP_CK_OFF   ((uint32_t)(0x1UL << MXC_F_ADC_CTRL1_SAMP_CK_OFF_POS))
#define	MXC_F_ADC_CTRL1_TRIG_SEL_POS   4
#define	MXC_F_ADC_CTRL1_TRIG_SEL   ((uint32_t)(0x7UL << MXC_F_ADC_CTRL1_TRIG_SEL_POS))
#define	MXC_F_ADC_CTRL1_TS_SEL_POS   7
#define	MXC_F_ADC_CTRL1_TS_SEL   ((uint32_t)(0x1UL << MXC_F_ADC_CTRL1_TS_SEL_POS))
#define	MXC_F_ADC_CTRL1_AVG_POS   8
#define	MXC_F_ADC_CTRL1_AVG   ((uint32_t)(0x7UL << MXC_F_ADC_CTRL1_AVG_POS))
#define	MXC_V_ADC_CTRL1_AVG_AVG1   ((uint32_t)0x0UL)
#define	MXC_S_ADC_CTRL1_AVG_AVG1   (MXC_V_ADC_CTRL1_AVG_AVG1 << MXC_F_ADC_CTRL1_AVG_POS)
#define	MXC_V_ADC_CTRL1_AVG_AVG2   ((uint32_t)0x1UL)
#define	MXC_S_ADC_CTRL1_AVG_AVG2   (MXC_V_ADC_CTRL1_AVG_AVG2 << MXC_F_ADC_CTRL1_AVG_POS)
#define	MXC_V_ADC_CTRL1_AVG_AVG4   ((uint32_t)0x2UL)
#define	MXC_S_ADC_CTRL1_AVG_AVG4   (MXC_V_ADC_CTRL1_AVG_AVG4 << MXC_F_ADC_CTRL1_AVG_POS)
#define	MXC_V_ADC_CTRL1_AVG_AVG8   ((uint32_t)0x3UL)
#define	MXC_S_ADC_CTRL1_AVG_AVG8   (MXC_V_ADC_CTRL1_AVG_AVG8 << MXC_F_ADC_CTRL1_AVG_POS)
#define	MXC_V_ADC_CTRL1_AVG_AVG16   ((uint32_t)0x4UL)
#define	MXC_S_ADC_CTRL1_AVG_AVG16   (MXC_V_ADC_CTRL1_AVG_AVG16 << MXC_F_ADC_CTRL1_AVG_POS)
#define	MXC_V_ADC_CTRL1_AVG_AVG32   ((uint32_t)0x5UL)
#define	MXC_S_ADC_CTRL1_AVG_AVG32   (MXC_V_ADC_CTRL1_AVG_AVG32 << MXC_F_ADC_CTRL1_AVG_POS)
#define	MXC_F_ADC_CTRL1_NUM_SLOTS_POS   16
#define	MXC_F_ADC_CTRL1_NUM_SLOTS   ((uint32_t)(0x1FUL << MXC_F_ADC_CTRL1_NUM_SLOTS_POS))

Detailed Description

Control Register 1.

Macro Definition Documentation

MXC_F_ADC_CTRL1_AVG

#define MXC_F_ADC_CTRL1_AVG   ((uint32_t)(0x7UL << MXC_F_ADC_CTRL1_AVG_POS))

CTRL1_AVG Mask

MXC_F_ADC_CTRL1_AVG_POS

#define MXC_F_ADC_CTRL1_AVG_POS   8

CTRL1_AVG Position

MXC_F_ADC_CTRL1_CNV_MODE

#define MXC_F_ADC_CTRL1_CNV_MODE   ((uint32_t)(0x1UL << MXC_F_ADC_CTRL1_CNV_MODE_POS))

CTRL1_CNV_MODE Mask

MXC_F_ADC_CTRL1_CNV_MODE_POS

#define MXC_F_ADC_CTRL1_CNV_MODE_POS   2

CTRL1_CNV_MODE Position

MXC_F_ADC_CTRL1_NUM_SLOTS

#define MXC_F_ADC_CTRL1_NUM_SLOTS   ((uint32_t)(0x1FUL << MXC_F_ADC_CTRL1_NUM_SLOTS_POS))

CTRL1_NUM_SLOTS Mask

MXC_F_ADC_CTRL1_NUM_SLOTS_POS

#define MXC_F_ADC_CTRL1_NUM_SLOTS_POS   16

CTRL1_NUM_SLOTS Position

MXC_F_ADC_CTRL1_SAMP_CK_OFF

#define MXC_F_ADC_CTRL1_SAMP_CK_OFF   ((uint32_t)(0x1UL << MXC_F_ADC_CTRL1_SAMP_CK_OFF_POS))

CTRL1_SAMP_CK_OFF Mask

MXC_F_ADC_CTRL1_SAMP_CK_OFF_POS

#define MXC_F_ADC_CTRL1_SAMP_CK_OFF_POS   3

CTRL1_SAMP_CK_OFF Position

MXC_F_ADC_CTRL1_START

#define MXC_F_ADC_CTRL1_START   ((uint32_t)(0x1UL << MXC_F_ADC_CTRL1_START_POS))

CTRL1_START Mask

MXC_F_ADC_CTRL1_START_POS

#define MXC_F_ADC_CTRL1_START_POS   0

CTRL1_START Position

MXC_F_ADC_CTRL1_TRIG_MODE

#define MXC_F_ADC_CTRL1_TRIG_MODE   ((uint32_t)(0x1UL << MXC_F_ADC_CTRL1_TRIG_MODE_POS))

CTRL1_TRIG_MODE Mask

MXC_F_ADC_CTRL1_TRIG_MODE_POS

#define MXC_F_ADC_CTRL1_TRIG_MODE_POS   1

CTRL1_TRIG_MODE Position

MXC_F_ADC_CTRL1_TRIG_SEL

#define MXC_F_ADC_CTRL1_TRIG_SEL   ((uint32_t)(0x7UL << MXC_F_ADC_CTRL1_TRIG_SEL_POS))

CTRL1_TRIG_SEL Mask

MXC_F_ADC_CTRL1_TRIG_SEL_POS

#define MXC_F_ADC_CTRL1_TRIG_SEL_POS   4

CTRL1_TRIG_SEL Position

MXC_F_ADC_CTRL1_TS_SEL

#define MXC_F_ADC_CTRL1_TS_SEL   ((uint32_t)(0x1UL << MXC_F_ADC_CTRL1_TS_SEL_POS))

CTRL1_TS_SEL Mask

MXC_F_ADC_CTRL1_TS_SEL_POS

#define MXC_F_ADC_CTRL1_TS_SEL_POS   7

CTRL1_TS_SEL Position

MXC_S_ADC_CTRL1_AVG_AVG1

#define MXC_S_ADC_CTRL1_AVG_AVG1   (MXC_V_ADC_CTRL1_AVG_AVG1 << MXC_F_ADC_CTRL1_AVG_POS)

CTRL1_AVG_AVG1 Setting

MXC_S_ADC_CTRL1_AVG_AVG16

#define MXC_S_ADC_CTRL1_AVG_AVG16   (MXC_V_ADC_CTRL1_AVG_AVG16 << MXC_F_ADC_CTRL1_AVG_POS)

CTRL1_AVG_AVG16 Setting

MXC_S_ADC_CTRL1_AVG_AVG2

#define MXC_S_ADC_CTRL1_AVG_AVG2   (MXC_V_ADC_CTRL1_AVG_AVG2 << MXC_F_ADC_CTRL1_AVG_POS)

CTRL1_AVG_AVG2 Setting

MXC_S_ADC_CTRL1_AVG_AVG32

#define MXC_S_ADC_CTRL1_AVG_AVG32   (MXC_V_ADC_CTRL1_AVG_AVG32 << MXC_F_ADC_CTRL1_AVG_POS)

CTRL1_AVG_AVG32 Setting

MXC_S_ADC_CTRL1_AVG_AVG4

#define MXC_S_ADC_CTRL1_AVG_AVG4   (MXC_V_ADC_CTRL1_AVG_AVG4 << MXC_F_ADC_CTRL1_AVG_POS)

CTRL1_AVG_AVG4 Setting

MXC_S_ADC_CTRL1_AVG_AVG8

#define MXC_S_ADC_CTRL1_AVG_AVG8   (MXC_V_ADC_CTRL1_AVG_AVG8 << MXC_F_ADC_CTRL1_AVG_POS)

CTRL1_AVG_AVG8 Setting

MXC_V_ADC_CTRL1_AVG_AVG1

#define MXC_V_ADC_CTRL1_AVG_AVG1   ((uint32_t)0x0UL)

CTRL1_AVG_AVG1 Value

MXC_V_ADC_CTRL1_AVG_AVG16

#define MXC_V_ADC_CTRL1_AVG_AVG16   ((uint32_t)0x4UL)

CTRL1_AVG_AVG16 Value

MXC_V_ADC_CTRL1_AVG_AVG2

#define MXC_V_ADC_CTRL1_AVG_AVG2   ((uint32_t)0x1UL)

CTRL1_AVG_AVG2 Value

MXC_V_ADC_CTRL1_AVG_AVG32

#define MXC_V_ADC_CTRL1_AVG_AVG32   ((uint32_t)0x5UL)

CTRL1_AVG_AVG32 Value

MXC_V_ADC_CTRL1_AVG_AVG4

#define MXC_V_ADC_CTRL1_AVG_AVG4   ((uint32_t)0x2UL)

CTRL1_AVG_AVG4 Value

MXC_V_ADC_CTRL1_AVG_AVG8

#define MXC_V_ADC_CTRL1_AVG_AVG8   ((uint32_t)0x3UL)

CTRL1_AVG_AVG8 Value