Macros
#define	MXC_R_CSI2_CFG_NUM_LANES ((uint32_t)0x00000000UL)

#define	MXC_R_CSI2_CFG_CLK_LANE_EN ((uint32_t)0x00000004UL)

#define	MXC_R_CSI2_CFG_DATA_LANE_EN ((uint32_t)0x00000008UL)

#define	MXC_R_CSI2_CFG_FLUSH_COUNT ((uint32_t)0x0000000CUL)

#define	MXC_R_CSI2_CFG_BIT_ERR ((uint32_t)0x00000010UL)

#define	MXC_R_CSI2_IRQ_STATUS ((uint32_t)0x00000014UL)

#define	MXC_R_CSI2_IRQ_ENABLE ((uint32_t)0x00000018UL)

#define	MXC_R_CSI2_IRQ_CLR ((uint32_t)0x0000001CUL)

#define	MXC_R_CSI2_ULPS_CLK_STATUS ((uint32_t)0x00000020UL)

#define	MXC_R_CSI2_ULPS_STATUS ((uint32_t)0x00000024UL)

#define	MXC_R_CSI2_ULPS_CLK_MARK_STATUS ((uint32_t)0x00000028UL)

#define	MXC_R_CSI2_ULPS_MARK_STATUS ((uint32_t)0x0000002CUL)

#define	MXC_R_CSI2_PPI_ERRSOT_HS ((uint32_t)0x00000030UL)

#define	MXC_R_CSI2_PPI_ERRSOTSYNC_HS ((uint32_t)0x00000034UL)

#define	MXC_R_CSI2_PPI_ERRESC ((uint32_t)0x00000038UL)

#define	MXC_R_CSI2_PPI_ERRSYNCESC ((uint32_t)0x0000003CUL)

#define	MXC_R_CSI2_PPI_ERRCONTROL ((uint32_t)0x00000040UL)

#define	MXC_R_CSI2_CFG_CPHY_EN ((uint32_t)0x00000044UL)

#define	MXC_R_CSI2_CFG_PPI_16_EN ((uint32_t)0x00000048UL)

#define	MXC_R_CSI2_CFG_PACKET_INTERFACE_EN ((uint32_t)0x0000004CUL)

#define	MXC_R_CSI2_CFG_VCX_EN ((uint32_t)0x00000050UL)

#define	MXC_R_CSI2_CFG_BYTE_DATA_FORMAT ((uint32_t)0x00000054UL)

#define	MXC_R_CSI2_CFG_DISABLE_PAYLOAD_0 ((uint32_t)0x00000058UL)

#define	MXC_R_CSI2_CFG_DISABLE_PAYLOAD_1 ((uint32_t)0x0000005CUL)

#define	MXC_R_CSI2_CFG_VID_IGNORE_VC ((uint32_t)0x00000080UL)

#define	MXC_R_CSI2_CFG_VID_VC ((uint32_t)0x00000084UL)

#define	MXC_R_CSI2_CFG_P_FIFO_SEND_LEVEL ((uint32_t)0x00000088UL)

#define	MXC_R_CSI2_CFG_VID_VSYNC ((uint32_t)0x0000008CUL)

#define	MXC_R_CSI2_CFG_VID_HSYNC_FP ((uint32_t)0x00000090UL)

#define	MXC_R_CSI2_CFG_VID_HSYNC ((uint32_t)0x00000094UL)

#define	MXC_R_CSI2_CFG_VID_HSYNC_BP ((uint32_t)0x00000098UL)

#define	MXC_R_CSI2_CFG_DATABUS16_SEL ((uint32_t)0x00000400UL)

#define	MXC_R_CSI2_CFG_D0_SWAP_SEL ((uint32_t)0x00000404UL)

#define	MXC_R_CSI2_CFG_D1_SWAP_SEL ((uint32_t)0x00000408UL)

#define	MXC_R_CSI2_CFG_D2_SWAP_SEL ((uint32_t)0x0000040CUL)

#define	MXC_R_CSI2_CFG_D3_SWAP_SEL ((uint32_t)0x00000410UL)

#define	MXC_R_CSI2_CFG_C0_SWAP_SEL ((uint32_t)0x00000414UL)

#define	MXC_R_CSI2_CFG_DPDN_SWAP ((uint32_t)0x00000418UL)

#define	MXC_R_CSI2_RG_CFGCLK_1US_CNT ((uint32_t)0x0000041CUL)

#define	MXC_R_CSI2_RG_HSRX_CLK_PRE_TIME_GRP0 ((uint32_t)0x00000420UL)

#define	MXC_R_CSI2_RG_HSRX_DATA_PRE_TIME_GRP0 ((uint32_t)0x00000424UL)

#define	MXC_R_CSI2_RESET_DESKEW ((uint32_t)0x00000428UL)

#define	MXC_R_CSI2_PMA_RDY ((uint32_t)0x0000042CUL)

#define	MXC_R_CSI2_XCFGI_DW00 ((uint32_t)0x00000430UL)

#define	MXC_R_CSI2_XCFGI_DW01 ((uint32_t)0x00000434UL)

#define	MXC_R_CSI2_XCFGI_DW02 ((uint32_t)0x00000438UL)

#define	MXC_R_CSI2_XCFGI_DW03 ((uint32_t)0x0000043CUL)

#define	MXC_R_CSI2_XCFGI_DW04 ((uint32_t)0x00000440UL)

#define	MXC_R_CSI2_XCFGI_DW05 ((uint32_t)0x00000444UL)

#define	MXC_R_CSI2_XCFGI_DW06 ((uint32_t)0x00000448UL)

#define	MXC_R_CSI2_XCFGI_DW07 ((uint32_t)0x0000044CUL)

#define	MXC_R_CSI2_XCFGI_DW08 ((uint32_t)0x00000450UL)

#define	MXC_R_CSI2_XCFGI_DW09 ((uint32_t)0x00000454UL)

#define	MXC_R_CSI2_XCFGI_DW0A ((uint32_t)0x00000458UL)

#define	MXC_R_CSI2_XCFGI_DW0B ((uint32_t)0x0000045CUL)

#define	MXC_R_CSI2_XCFGI_DW0C ((uint32_t)0x00000460UL)

#define	MXC_R_CSI2_XCFGI_DW0D ((uint32_t)0x00000464UL)

#define	MXC_R_CSI2_GPIO_MODE ((uint32_t)0x00000468UL)

#define	MXC_R_CSI2_GPIO_DP_IE ((uint32_t)0x0000046CUL)

#define	MXC_R_CSI2_GPIO_DN_IE ((uint32_t)0x00000470UL)

#define	MXC_R_CSI2_GPIO_DP_C ((uint32_t)0x00000474UL)

#define	MXC_R_CSI2_GPIO_DN_C ((uint32_t)0x00000478UL)

#define	MXC_R_CSI2_VCONTROL ((uint32_t)0x0000047CUL)

#define	MXC_R_CSI2_MPSOV1 ((uint32_t)0x00000480UL)

#define	MXC_R_CSI2_MPSOV2 ((uint32_t)0x00000484UL)

#define	MXC_R_CSI2_MPSOV3 ((uint32_t)0x00000488UL)

#define	MXC_R_CSI2_RG_CDRX_DSIRX_EN ((uint32_t)0x00000490UL)

#define	MXC_R_CSI2_RG_CDRX_L012_SUBLVDS_EN ((uint32_t)0x00000494UL)

#define	MXC_R_CSI2_RG_CDRX_L012_HSRT_CTRL ((uint32_t)0x00000498UL)

#define	MXC_R_CSI2_RG_CDRX_BISTHS_PLL_EN ((uint32_t)0x0000049CUL)

#define	MXC_R_CSI2_RG_CDRX_BISTHS_PLL_PRE_DIV2 ((uint32_t)0x000004A0UL)

#define	MXC_R_CSI2_RG_CDRX_BISTHS_PLL_FBK_INT ((uint32_t)0x000004A4UL)

#define	MXC_R_CSI2_DBG1_MUX_SEL ((uint32_t)0x000004A8UL)

#define	MXC_R_CSI2_DBG2_MUX_SEL ((uint32_t)0x000004ACUL)

#define	MXC_R_CSI2_DBG1_MUX_DOUT ((uint32_t)0x000004B0UL)

#define	MXC_R_CSI2_DBG2_MUX_DOUT ((uint32_t)0x000004B4UL)

#define	MXC_R_CSI2_AON_POWER_READY_N ((uint32_t)0x000004B8UL)

#define	MXC_R_CSI2_DPHY_RST_N ((uint32_t)0x000004BCUL)

#define	MXC_R_CSI2_RXBYTECLKHS_INV ((uint32_t)0x000004C0UL)

#define	MXC_R_CSI2_VFIFO_CFG0 ((uint32_t)0x00000500UL)

#define	MXC_R_CSI2_VFIFO_CFG1 ((uint32_t)0x00000504UL)

#define	MXC_R_CSI2_VFIFO_CTRL ((uint32_t)0x00000508UL)

#define	MXC_R_CSI2_VFIFO_STS ((uint32_t)0x0000050CUL)

#define	MXC_R_CSI2_VFIFO_LINE_NUM ((uint32_t)0x00000510UL)

#define	MXC_R_CSI2_VFIFO_PIXEL_NUM ((uint32_t)0x00000514UL)

#define	MXC_R_CSI2_VFIFO_LINE_CNT ((uint32_t)0x00000518UL)

#define	MXC_R_CSI2_VFIFO_PIXEL_CNT ((uint32_t)0x0000051CUL)

#define	MXC_R_CSI2_VFIFO_FRAME_STS ((uint32_t)0x00000520UL)

#define	MXC_R_CSI2_VFIFO_RAW_CTRL ((uint32_t)0x00000524UL)

#define	MXC_R_CSI2_VFIFO_RAW_BUF0_ADDR ((uint32_t)0x00000528UL)

#define	MXC_R_CSI2_VFIFO_RAW_BUF1_ADDR ((uint32_t)0x0000052CUL)

#define	MXC_R_CSI2_VFIFO_AHBM_CTRL ((uint32_t)0x00000530UL)

#define	MXC_R_CSI2_VFIFO_AHBM_STS ((uint32_t)0x00000534UL)

#define	MXC_R_CSI2_VFIFO_AHBM_START_ADDR ((uint32_t)0x00000538UL)

#define	MXC_R_CSI2_VFIFO_AHBM_ADDR_RANGE ((uint32_t)0x0000053CUL)

#define	MXC_R_CSI2_VFIFO_AHBM_MAX_TRANS ((uint32_t)0x00000540UL)

#define	MXC_R_CSI2_VFIFO_AHBM_TRANS_CNT ((uint32_t)0x00000544UL)

#define	MXC_R_CSI2_RX_EINT_VFF_IE ((uint32_t)0x00000600UL)

#define	MXC_R_CSI2_RX_EINT_VFF_IF ((uint32_t)0x00000604UL)

#define	MXC_R_CSI2_RX_EINT_PPI_IE ((uint32_t)0x00000608UL)

#define	MXC_R_CSI2_RX_EINT_PPI_IF ((uint32_t)0x0000060CUL)

#define	MXC_R_CSI2_RX_EINT_CTRL_IE ((uint32_t)0x00000610UL)

#define	MXC_R_CSI2_RX_EINT_CTRL_IF ((uint32_t)0x00000614UL)

#define	MXC_R_CSI2_PPI_STOPSTATE ((uint32_t)0x00000700UL)

#define	MXC_R_CSI2_PPI_TURNAROUND_CFG ((uint32_t)0x00000704UL)

Detailed Description

CSI2 Peripheral Register Offsets from the CSI2 Base Peripheral Address.

Macro Definition Documentation

◆ MXC_R_CSI2_AON_POWER_READY_N

#define MXC_R_CSI2_AON_POWER_READY_N ((uint32_t)0x000004B8UL)

Offset from CSI2 Base Address: 0x04B8

◆ MXC_R_CSI2_CFG_BIT_ERR

#define MXC_R_CSI2_CFG_BIT_ERR ((uint32_t)0x00000010UL)

Offset from CSI2 Base Address: 0x0010

◆ MXC_R_CSI2_CFG_BYTE_DATA_FORMAT

#define MXC_R_CSI2_CFG_BYTE_DATA_FORMAT ((uint32_t)0x00000054UL)

Offset from CSI2 Base Address: 0x0054

◆ MXC_R_CSI2_CFG_C0_SWAP_SEL

#define MXC_R_CSI2_CFG_C0_SWAP_SEL ((uint32_t)0x00000414UL)

Offset from CSI2 Base Address: 0x0414

◆ MXC_R_CSI2_CFG_CLK_LANE_EN

#define MXC_R_CSI2_CFG_CLK_LANE_EN ((uint32_t)0x00000004UL)

Offset from CSI2 Base Address: 0x0004

◆ MXC_R_CSI2_CFG_CPHY_EN

#define MXC_R_CSI2_CFG_CPHY_EN ((uint32_t)0x00000044UL)

Offset from CSI2 Base Address: 0x0044

◆ MXC_R_CSI2_CFG_D0_SWAP_SEL

#define MXC_R_CSI2_CFG_D0_SWAP_SEL ((uint32_t)0x00000404UL)

Offset from CSI2 Base Address: 0x0404

◆ MXC_R_CSI2_CFG_D1_SWAP_SEL

#define MXC_R_CSI2_CFG_D1_SWAP_SEL ((uint32_t)0x00000408UL)

Offset from CSI2 Base Address: 0x0408

◆ MXC_R_CSI2_CFG_D2_SWAP_SEL

#define MXC_R_CSI2_CFG_D2_SWAP_SEL ((uint32_t)0x0000040CUL)

Offset from CSI2 Base Address: 0x040C

◆ MXC_R_CSI2_CFG_D3_SWAP_SEL

#define MXC_R_CSI2_CFG_D3_SWAP_SEL ((uint32_t)0x00000410UL)

Offset from CSI2 Base Address: 0x0410

◆ MXC_R_CSI2_CFG_DATA_LANE_EN

#define MXC_R_CSI2_CFG_DATA_LANE_EN ((uint32_t)0x00000008UL)

Offset from CSI2 Base Address: 0x0008

◆ MXC_R_CSI2_CFG_DATABUS16_SEL

#define MXC_R_CSI2_CFG_DATABUS16_SEL ((uint32_t)0x00000400UL)

Offset from CSI2 Base Address: 0x0400

◆ MXC_R_CSI2_CFG_DISABLE_PAYLOAD_0

#define MXC_R_CSI2_CFG_DISABLE_PAYLOAD_0 ((uint32_t)0x00000058UL)

Offset from CSI2 Base Address: 0x0058

◆ MXC_R_CSI2_CFG_DISABLE_PAYLOAD_1

#define MXC_R_CSI2_CFG_DISABLE_PAYLOAD_1 ((uint32_t)0x0000005CUL)

Offset from CSI2 Base Address: 0x005C

◆ MXC_R_CSI2_CFG_DPDN_SWAP

#define MXC_R_CSI2_CFG_DPDN_SWAP ((uint32_t)0x00000418UL)

Offset from CSI2 Base Address: 0x0418

◆ MXC_R_CSI2_CFG_FLUSH_COUNT

#define MXC_R_CSI2_CFG_FLUSH_COUNT ((uint32_t)0x0000000CUL)

Offset from CSI2 Base Address: 0x000C

◆ MXC_R_CSI2_CFG_NUM_LANES

#define MXC_R_CSI2_CFG_NUM_LANES ((uint32_t)0x00000000UL)

Offset from CSI2 Base Address: 0x0000

◆ MXC_R_CSI2_CFG_P_FIFO_SEND_LEVEL

#define MXC_R_CSI2_CFG_P_FIFO_SEND_LEVEL ((uint32_t)0x00000088UL)

Offset from CSI2 Base Address: 0x0088

◆ MXC_R_CSI2_CFG_PACKET_INTERFACE_EN

#define MXC_R_CSI2_CFG_PACKET_INTERFACE_EN ((uint32_t)0x0000004CUL)

Offset from CSI2 Base Address: 0x004C

◆ MXC_R_CSI2_CFG_PPI_16_EN

#define MXC_R_CSI2_CFG_PPI_16_EN ((uint32_t)0x00000048UL)

Offset from CSI2 Base Address: 0x0048

◆ MXC_R_CSI2_CFG_VCX_EN

#define MXC_R_CSI2_CFG_VCX_EN ((uint32_t)0x00000050UL)

Offset from CSI2 Base Address: 0x0050

◆ MXC_R_CSI2_CFG_VID_HSYNC

#define MXC_R_CSI2_CFG_VID_HSYNC ((uint32_t)0x00000094UL)

Offset from CSI2 Base Address: 0x0094

◆ MXC_R_CSI2_CFG_VID_HSYNC_BP

#define MXC_R_CSI2_CFG_VID_HSYNC_BP ((uint32_t)0x00000098UL)

Offset from CSI2 Base Address: 0x0098

◆ MXC_R_CSI2_CFG_VID_HSYNC_FP

#define MXC_R_CSI2_CFG_VID_HSYNC_FP ((uint32_t)0x00000090UL)

Offset from CSI2 Base Address: 0x0090

◆ MXC_R_CSI2_CFG_VID_IGNORE_VC

#define MXC_R_CSI2_CFG_VID_IGNORE_VC ((uint32_t)0x00000080UL)

Offset from CSI2 Base Address: 0x0080

◆ MXC_R_CSI2_CFG_VID_VC

#define MXC_R_CSI2_CFG_VID_VC ((uint32_t)0x00000084UL)

Offset from CSI2 Base Address: 0x0084

◆ MXC_R_CSI2_CFG_VID_VSYNC

#define MXC_R_CSI2_CFG_VID_VSYNC ((uint32_t)0x0000008CUL)

Offset from CSI2 Base Address: 0x008C

◆ MXC_R_CSI2_DBG1_MUX_DOUT

#define MXC_R_CSI2_DBG1_MUX_DOUT ((uint32_t)0x000004B0UL)

Offset from CSI2 Base Address: 0x04B0

◆ MXC_R_CSI2_DBG1_MUX_SEL

#define MXC_R_CSI2_DBG1_MUX_SEL ((uint32_t)0x000004A8UL)

Offset from CSI2 Base Address: 0x04A8

◆ MXC_R_CSI2_DBG2_MUX_DOUT

#define MXC_R_CSI2_DBG2_MUX_DOUT ((uint32_t)0x000004B4UL)

Offset from CSI2 Base Address: 0x04B4

◆ MXC_R_CSI2_DBG2_MUX_SEL

#define MXC_R_CSI2_DBG2_MUX_SEL ((uint32_t)0x000004ACUL)

Offset from CSI2 Base Address: 0x04AC

◆ MXC_R_CSI2_DPHY_RST_N

#define MXC_R_CSI2_DPHY_RST_N ((uint32_t)0x000004BCUL)

Offset from CSI2 Base Address: 0x04BC

◆ MXC_R_CSI2_GPIO_DN_C

#define MXC_R_CSI2_GPIO_DN_C ((uint32_t)0x00000478UL)

Offset from CSI2 Base Address: 0x0478

◆ MXC_R_CSI2_GPIO_DN_IE

#define MXC_R_CSI2_GPIO_DN_IE ((uint32_t)0x00000470UL)

Offset from CSI2 Base Address: 0x0470

◆ MXC_R_CSI2_GPIO_DP_C

#define MXC_R_CSI2_GPIO_DP_C ((uint32_t)0x00000474UL)

Offset from CSI2 Base Address: 0x0474

◆ MXC_R_CSI2_GPIO_DP_IE

#define MXC_R_CSI2_GPIO_DP_IE ((uint32_t)0x0000046CUL)

Offset from CSI2 Base Address: 0x046C

◆ MXC_R_CSI2_GPIO_MODE

#define MXC_R_CSI2_GPIO_MODE ((uint32_t)0x00000468UL)

Offset from CSI2 Base Address: 0x0468

◆ MXC_R_CSI2_IRQ_CLR

#define MXC_R_CSI2_IRQ_CLR ((uint32_t)0x0000001CUL)

Offset from CSI2 Base Address: 0x001C

◆ MXC_R_CSI2_IRQ_ENABLE

#define MXC_R_CSI2_IRQ_ENABLE ((uint32_t)0x00000018UL)

Offset from CSI2 Base Address: 0x0018

◆ MXC_R_CSI2_IRQ_STATUS

#define MXC_R_CSI2_IRQ_STATUS ((uint32_t)0x00000014UL)

Offset from CSI2 Base Address: 0x0014

◆ MXC_R_CSI2_MPSOV1

#define MXC_R_CSI2_MPSOV1 ((uint32_t)0x00000480UL)

Offset from CSI2 Base Address: 0x0480

◆ MXC_R_CSI2_MPSOV2

#define MXC_R_CSI2_MPSOV2 ((uint32_t)0x00000484UL)

Offset from CSI2 Base Address: 0x0484

◆ MXC_R_CSI2_MPSOV3

#define MXC_R_CSI2_MPSOV3 ((uint32_t)0x00000488UL)

Offset from CSI2 Base Address: 0x0488

◆ MXC_R_CSI2_PMA_RDY

#define MXC_R_CSI2_PMA_RDY ((uint32_t)0x0000042CUL)

Offset from CSI2 Base Address: 0x042C

◆ MXC_R_CSI2_PPI_ERRCONTROL

#define MXC_R_CSI2_PPI_ERRCONTROL ((uint32_t)0x00000040UL)

Offset from CSI2 Base Address: 0x0040

◆ MXC_R_CSI2_PPI_ERRESC

#define MXC_R_CSI2_PPI_ERRESC ((uint32_t)0x00000038UL)

Offset from CSI2 Base Address: 0x0038

◆ MXC_R_CSI2_PPI_ERRSOT_HS

#define MXC_R_CSI2_PPI_ERRSOT_HS ((uint32_t)0x00000030UL)

Offset from CSI2 Base Address: 0x0030

◆ MXC_R_CSI2_PPI_ERRSOTSYNC_HS

#define MXC_R_CSI2_PPI_ERRSOTSYNC_HS ((uint32_t)0x00000034UL)

Offset from CSI2 Base Address: 0x0034

◆ MXC_R_CSI2_PPI_ERRSYNCESC

#define MXC_R_CSI2_PPI_ERRSYNCESC ((uint32_t)0x0000003CUL)

Offset from CSI2 Base Address: 0x003C

◆ MXC_R_CSI2_PPI_STOPSTATE

#define MXC_R_CSI2_PPI_STOPSTATE ((uint32_t)0x00000700UL)

Offset from CSI2 Base Address: 0x0700

◆ MXC_R_CSI2_PPI_TURNAROUND_CFG

#define MXC_R_CSI2_PPI_TURNAROUND_CFG ((uint32_t)0x00000704UL)

Offset from CSI2 Base Address: 0x0704

◆ MXC_R_CSI2_RESET_DESKEW

#define MXC_R_CSI2_RESET_DESKEW ((uint32_t)0x00000428UL)

Offset from CSI2 Base Address: 0x0428

◆ MXC_R_CSI2_RG_CDRX_BISTHS_PLL_EN

#define MXC_R_CSI2_RG_CDRX_BISTHS_PLL_EN ((uint32_t)0x0000049CUL)

Offset from CSI2 Base Address: 0x049C

◆ MXC_R_CSI2_RG_CDRX_BISTHS_PLL_FBK_INT

#define MXC_R_CSI2_RG_CDRX_BISTHS_PLL_FBK_INT ((uint32_t)0x000004A4UL)

Offset from CSI2 Base Address: 0x04A4

◆ MXC_R_CSI2_RG_CDRX_BISTHS_PLL_PRE_DIV2

#define MXC_R_CSI2_RG_CDRX_BISTHS_PLL_PRE_DIV2 ((uint32_t)0x000004A0UL)

Offset from CSI2 Base Address: 0x04A0

◆ MXC_R_CSI2_RG_CDRX_DSIRX_EN

#define MXC_R_CSI2_RG_CDRX_DSIRX_EN ((uint32_t)0x00000490UL)

Offset from CSI2 Base Address: 0x0490

◆ MXC_R_CSI2_RG_CDRX_L012_HSRT_CTRL

#define MXC_R_CSI2_RG_CDRX_L012_HSRT_CTRL ((uint32_t)0x00000498UL)

Offset from CSI2 Base Address: 0x0498

◆ MXC_R_CSI2_RG_CDRX_L012_SUBLVDS_EN

#define MXC_R_CSI2_RG_CDRX_L012_SUBLVDS_EN ((uint32_t)0x00000494UL)

Offset from CSI2 Base Address: 0x0494

◆ MXC_R_CSI2_RG_CFGCLK_1US_CNT

#define MXC_R_CSI2_RG_CFGCLK_1US_CNT ((uint32_t)0x0000041CUL)

Offset from CSI2 Base Address: 0x041C

◆ MXC_R_CSI2_RG_HSRX_CLK_PRE_TIME_GRP0

#define MXC_R_CSI2_RG_HSRX_CLK_PRE_TIME_GRP0 ((uint32_t)0x00000420UL)

Offset from CSI2 Base Address: 0x0420

◆ MXC_R_CSI2_RG_HSRX_DATA_PRE_TIME_GRP0

#define MXC_R_CSI2_RG_HSRX_DATA_PRE_TIME_GRP0 ((uint32_t)0x00000424UL)

Offset from CSI2 Base Address: 0x0424

◆ MXC_R_CSI2_RX_EINT_CTRL_IE

#define MXC_R_CSI2_RX_EINT_CTRL_IE ((uint32_t)0x00000610UL)

Offset from CSI2 Base Address: 0x0610

◆ MXC_R_CSI2_RX_EINT_CTRL_IF

#define MXC_R_CSI2_RX_EINT_CTRL_IF ((uint32_t)0x00000614UL)

Offset from CSI2 Base Address: 0x0614

◆ MXC_R_CSI2_RX_EINT_PPI_IE

#define MXC_R_CSI2_RX_EINT_PPI_IE ((uint32_t)0x00000608UL)

Offset from CSI2 Base Address: 0x0608

◆ MXC_R_CSI2_RX_EINT_PPI_IF

#define MXC_R_CSI2_RX_EINT_PPI_IF ((uint32_t)0x0000060CUL)

Offset from CSI2 Base Address: 0x060C

◆ MXC_R_CSI2_RX_EINT_VFF_IE

#define MXC_R_CSI2_RX_EINT_VFF_IE ((uint32_t)0x00000600UL)

Offset from CSI2 Base Address: 0x0600

◆ MXC_R_CSI2_RX_EINT_VFF_IF

#define MXC_R_CSI2_RX_EINT_VFF_IF ((uint32_t)0x00000604UL)

Offset from CSI2 Base Address: 0x0604

◆ MXC_R_CSI2_RXBYTECLKHS_INV

#define MXC_R_CSI2_RXBYTECLKHS_INV ((uint32_t)0x000004C0UL)

Offset from CSI2 Base Address: 0x04C0

◆ MXC_R_CSI2_ULPS_CLK_MARK_STATUS

#define MXC_R_CSI2_ULPS_CLK_MARK_STATUS ((uint32_t)0x00000028UL)

Offset from CSI2 Base Address: 0x0028

◆ MXC_R_CSI2_ULPS_CLK_STATUS

#define MXC_R_CSI2_ULPS_CLK_STATUS ((uint32_t)0x00000020UL)

Offset from CSI2 Base Address: 0x0020

◆ MXC_R_CSI2_ULPS_MARK_STATUS

#define MXC_R_CSI2_ULPS_MARK_STATUS ((uint32_t)0x0000002CUL)

Offset from CSI2 Base Address: 0x002C

◆ MXC_R_CSI2_ULPS_STATUS

#define MXC_R_CSI2_ULPS_STATUS ((uint32_t)0x00000024UL)

Offset from CSI2 Base Address: 0x0024

◆ MXC_R_CSI2_VCONTROL

#define MXC_R_CSI2_VCONTROL ((uint32_t)0x0000047CUL)

Offset from CSI2 Base Address: 0x047C

◆ MXC_R_CSI2_VFIFO_AHBM_ADDR_RANGE

#define MXC_R_CSI2_VFIFO_AHBM_ADDR_RANGE ((uint32_t)0x0000053CUL)

Offset from CSI2 Base Address: 0x053C

◆ MXC_R_CSI2_VFIFO_AHBM_CTRL

#define MXC_R_CSI2_VFIFO_AHBM_CTRL ((uint32_t)0x00000530UL)

Offset from CSI2 Base Address: 0x0530

◆ MXC_R_CSI2_VFIFO_AHBM_MAX_TRANS

#define MXC_R_CSI2_VFIFO_AHBM_MAX_TRANS ((uint32_t)0x00000540UL)

Offset from CSI2 Base Address: 0x0540

◆ MXC_R_CSI2_VFIFO_AHBM_START_ADDR

#define MXC_R_CSI2_VFIFO_AHBM_START_ADDR ((uint32_t)0x00000538UL)

Offset from CSI2 Base Address: 0x0538

◆ MXC_R_CSI2_VFIFO_AHBM_STS

#define MXC_R_CSI2_VFIFO_AHBM_STS ((uint32_t)0x00000534UL)

Offset from CSI2 Base Address: 0x0534

◆ MXC_R_CSI2_VFIFO_AHBM_TRANS_CNT

#define MXC_R_CSI2_VFIFO_AHBM_TRANS_CNT ((uint32_t)0x00000544UL)

Offset from CSI2 Base Address: 0x0544

◆ MXC_R_CSI2_VFIFO_CFG0

#define MXC_R_CSI2_VFIFO_CFG0 ((uint32_t)0x00000500UL)

Offset from CSI2 Base Address: 0x0500

◆ MXC_R_CSI2_VFIFO_CFG1

#define MXC_R_CSI2_VFIFO_CFG1 ((uint32_t)0x00000504UL)

Offset from CSI2 Base Address: 0x0504

◆ MXC_R_CSI2_VFIFO_CTRL

#define MXC_R_CSI2_VFIFO_CTRL ((uint32_t)0x00000508UL)

Offset from CSI2 Base Address: 0x0508

◆ MXC_R_CSI2_VFIFO_FRAME_STS

#define MXC_R_CSI2_VFIFO_FRAME_STS ((uint32_t)0x00000520UL)

Offset from CSI2 Base Address: 0x0520

◆ MXC_R_CSI2_VFIFO_LINE_CNT

#define MXC_R_CSI2_VFIFO_LINE_CNT ((uint32_t)0x00000518UL)

Offset from CSI2 Base Address: 0x0518

◆ MXC_R_CSI2_VFIFO_LINE_NUM

#define MXC_R_CSI2_VFIFO_LINE_NUM ((uint32_t)0x00000510UL)

Offset from CSI2 Base Address: 0x0510

◆ MXC_R_CSI2_VFIFO_PIXEL_CNT

#define MXC_R_CSI2_VFIFO_PIXEL_CNT ((uint32_t)0x0000051CUL)

Offset from CSI2 Base Address: 0x051C

◆ MXC_R_CSI2_VFIFO_PIXEL_NUM

#define MXC_R_CSI2_VFIFO_PIXEL_NUM ((uint32_t)0x00000514UL)

Offset from CSI2 Base Address: 0x0514

◆ MXC_R_CSI2_VFIFO_RAW_BUF0_ADDR

#define MXC_R_CSI2_VFIFO_RAW_BUF0_ADDR ((uint32_t)0x00000528UL)

Offset from CSI2 Base Address: 0x0528

◆ MXC_R_CSI2_VFIFO_RAW_BUF1_ADDR

#define MXC_R_CSI2_VFIFO_RAW_BUF1_ADDR ((uint32_t)0x0000052CUL)

Offset from CSI2 Base Address: 0x052C

◆ MXC_R_CSI2_VFIFO_RAW_CTRL

#define MXC_R_CSI2_VFIFO_RAW_CTRL ((uint32_t)0x00000524UL)

Offset from CSI2 Base Address: 0x0524

◆ MXC_R_CSI2_VFIFO_STS

#define MXC_R_CSI2_VFIFO_STS ((uint32_t)0x0000050CUL)

Offset from CSI2 Base Address: 0x050C

◆ MXC_R_CSI2_XCFGI_DW00

#define MXC_R_CSI2_XCFGI_DW00 ((uint32_t)0x00000430UL)

Offset from CSI2 Base Address: 0x0430

◆ MXC_R_CSI2_XCFGI_DW01

#define MXC_R_CSI2_XCFGI_DW01 ((uint32_t)0x00000434UL)

Offset from CSI2 Base Address: 0x0434

◆ MXC_R_CSI2_XCFGI_DW02

#define MXC_R_CSI2_XCFGI_DW02 ((uint32_t)0x00000438UL)

Offset from CSI2 Base Address: 0x0438

◆ MXC_R_CSI2_XCFGI_DW03

#define MXC_R_CSI2_XCFGI_DW03 ((uint32_t)0x0000043CUL)

Offset from CSI2 Base Address: 0x043C

◆ MXC_R_CSI2_XCFGI_DW04

#define MXC_R_CSI2_XCFGI_DW04 ((uint32_t)0x00000440UL)

Offset from CSI2 Base Address: 0x0440

◆ MXC_R_CSI2_XCFGI_DW05

#define MXC_R_CSI2_XCFGI_DW05 ((uint32_t)0x00000444UL)

Offset from CSI2 Base Address: 0x0444

◆ MXC_R_CSI2_XCFGI_DW06

#define MXC_R_CSI2_XCFGI_DW06 ((uint32_t)0x00000448UL)

Offset from CSI2 Base Address: 0x0448

◆ MXC_R_CSI2_XCFGI_DW07

#define MXC_R_CSI2_XCFGI_DW07 ((uint32_t)0x0000044CUL)

Offset from CSI2 Base Address: 0x044C

◆ MXC_R_CSI2_XCFGI_DW08

#define MXC_R_CSI2_XCFGI_DW08 ((uint32_t)0x00000450UL)

Offset from CSI2 Base Address: 0x0450

◆ MXC_R_CSI2_XCFGI_DW09

#define MXC_R_CSI2_XCFGI_DW09 ((uint32_t)0x00000454UL)

Offset from CSI2 Base Address: 0x0454

◆ MXC_R_CSI2_XCFGI_DW0A

#define MXC_R_CSI2_XCFGI_DW0A ((uint32_t)0x00000458UL)

Offset from CSI2 Base Address: 0x0458

◆ MXC_R_CSI2_XCFGI_DW0B

#define MXC_R_CSI2_XCFGI_DW0B ((uint32_t)0x0000045CUL)

Offset from CSI2 Base Address: 0x045C

◆ MXC_R_CSI2_XCFGI_DW0C

#define MXC_R_CSI2_XCFGI_DW0C ((uint32_t)0x00000460UL)

Offset from CSI2 Base Address: 0x0460

◆ MXC_R_CSI2_XCFGI_DW0D

#define MXC_R_CSI2_XCFGI_DW0D ((uint32_t)0x00000464UL)

Offset from CSI2 Base Address: 0x0464

Macros