GCR_MEMZ

Macros
#define	MXC_F_GCR_MEMZ_RAM0_POS   0
#define	MXC_F_GCR_MEMZ_RAM0   ((uint32_t)(0x1UL << MXC_F_GCR_MEMZ_RAM0_POS))
#define	MXC_F_GCR_MEMZ_RAM1_POS   1
#define	MXC_F_GCR_MEMZ_RAM1   ((uint32_t)(0x1UL << MXC_F_GCR_MEMZ_RAM1_POS))
#define	MXC_F_GCR_MEMZ_RAM2_POS   2
#define	MXC_F_GCR_MEMZ_RAM2   ((uint32_t)(0x1UL << MXC_F_GCR_MEMZ_RAM2_POS))
#define	MXC_F_GCR_MEMZ_RAM3_POS   3
#define	MXC_F_GCR_MEMZ_RAM3   ((uint32_t)(0x1UL << MXC_F_GCR_MEMZ_RAM3_POS))
#define	MXC_F_GCR_MEMZ_RAM4_POS   4
#define	MXC_F_GCR_MEMZ_RAM4   ((uint32_t)(0x1UL << MXC_F_GCR_MEMZ_RAM4_POS))
#define	MXC_F_GCR_MEMZ_RAM5_POS   5
#define	MXC_F_GCR_MEMZ_RAM5   ((uint32_t)(0x1UL << MXC_F_GCR_MEMZ_RAM5_POS))
#define	MXC_F_GCR_MEMZ_RAM6_POS   6
#define	MXC_F_GCR_MEMZ_RAM6   ((uint32_t)(0x1UL << MXC_F_GCR_MEMZ_RAM6_POS))
#define	MXC_F_GCR_MEMZ_RAM7_POS   7
#define	MXC_F_GCR_MEMZ_RAM7   ((uint32_t)(0x1UL << MXC_F_GCR_MEMZ_RAM7_POS))
#define	MXC_F_GCR_MEMZ_RAM0ECC_POS   8
#define	MXC_F_GCR_MEMZ_RAM0ECC   ((uint32_t)(0x1UL << MXC_F_GCR_MEMZ_RAM0ECC_POS))
#define	MXC_F_GCR_MEMZ_ICC0_POS   9
#define	MXC_F_GCR_MEMZ_ICC0   ((uint32_t)(0x1UL << MXC_F_GCR_MEMZ_ICC0_POS))
#define	MXC_F_GCR_MEMZ_ICC1_POS   10
#define	MXC_F_GCR_MEMZ_ICC1   ((uint32_t)(0x1UL << MXC_F_GCR_MEMZ_ICC1_POS))
#define	MXC_F_GCR_MEMZ_USBFIFO_POS   11
#define	MXC_F_GCR_MEMZ_USBFIFO   ((uint32_t)(0x1UL << MXC_F_GCR_MEMZ_USBFIFO_POS))

Detailed Description

Memory Zeroize Control.

Macro Definition Documentation

MXC_F_GCR_MEMZ_ICC0

#define MXC_F_GCR_MEMZ_ICC0   ((uint32_t)(0x1UL << MXC_F_GCR_MEMZ_ICC0_POS))

MEMZ_ICC0 Mask

MXC_F_GCR_MEMZ_ICC0_POS

#define MXC_F_GCR_MEMZ_ICC0_POS   9

MEMZ_ICC0 Position

MXC_F_GCR_MEMZ_ICC1

#define MXC_F_GCR_MEMZ_ICC1   ((uint32_t)(0x1UL << MXC_F_GCR_MEMZ_ICC1_POS))

MEMZ_ICC1 Mask

MXC_F_GCR_MEMZ_ICC1_POS

#define MXC_F_GCR_MEMZ_ICC1_POS   10

MEMZ_ICC1 Position

MXC_F_GCR_MEMZ_RAM0

#define MXC_F_GCR_MEMZ_RAM0   ((uint32_t)(0x1UL << MXC_F_GCR_MEMZ_RAM0_POS))

MEMZ_RAM0 Mask

MXC_F_GCR_MEMZ_RAM0_POS

#define MXC_F_GCR_MEMZ_RAM0_POS   0

MEMZ_RAM0 Position

MXC_F_GCR_MEMZ_RAM0ECC

#define MXC_F_GCR_MEMZ_RAM0ECC   ((uint32_t)(0x1UL << MXC_F_GCR_MEMZ_RAM0ECC_POS))

MEMZ_RAM0ECC Mask

MXC_F_GCR_MEMZ_RAM0ECC_POS

#define MXC_F_GCR_MEMZ_RAM0ECC_POS   8

MEMZ_RAM0ECC Position

MXC_F_GCR_MEMZ_RAM1

#define MXC_F_GCR_MEMZ_RAM1   ((uint32_t)(0x1UL << MXC_F_GCR_MEMZ_RAM1_POS))

MEMZ_RAM1 Mask

MXC_F_GCR_MEMZ_RAM1_POS

#define MXC_F_GCR_MEMZ_RAM1_POS   1

MEMZ_RAM1 Position

MXC_F_GCR_MEMZ_RAM2

#define MXC_F_GCR_MEMZ_RAM2   ((uint32_t)(0x1UL << MXC_F_GCR_MEMZ_RAM2_POS))

MEMZ_RAM2 Mask

MXC_F_GCR_MEMZ_RAM2_POS

#define MXC_F_GCR_MEMZ_RAM2_POS   2

MEMZ_RAM2 Position

MXC_F_GCR_MEMZ_RAM3

#define MXC_F_GCR_MEMZ_RAM3   ((uint32_t)(0x1UL << MXC_F_GCR_MEMZ_RAM3_POS))

MEMZ_RAM3 Mask

MXC_F_GCR_MEMZ_RAM3_POS

#define MXC_F_GCR_MEMZ_RAM3_POS   3

MEMZ_RAM3 Position

MXC_F_GCR_MEMZ_RAM4

#define MXC_F_GCR_MEMZ_RAM4   ((uint32_t)(0x1UL << MXC_F_GCR_MEMZ_RAM4_POS))

MEMZ_RAM4 Mask

MXC_F_GCR_MEMZ_RAM4_POS

#define MXC_F_GCR_MEMZ_RAM4_POS   4

MEMZ_RAM4 Position

MXC_F_GCR_MEMZ_RAM5

#define MXC_F_GCR_MEMZ_RAM5   ((uint32_t)(0x1UL << MXC_F_GCR_MEMZ_RAM5_POS))

MEMZ_RAM5 Mask

MXC_F_GCR_MEMZ_RAM5_POS

#define MXC_F_GCR_MEMZ_RAM5_POS   5

MEMZ_RAM5 Position

MXC_F_GCR_MEMZ_RAM6

#define MXC_F_GCR_MEMZ_RAM6   ((uint32_t)(0x1UL << MXC_F_GCR_MEMZ_RAM6_POS))

MEMZ_RAM6 Mask

MXC_F_GCR_MEMZ_RAM6_POS

#define MXC_F_GCR_MEMZ_RAM6_POS   6

MEMZ_RAM6 Position

MXC_F_GCR_MEMZ_RAM7

#define MXC_F_GCR_MEMZ_RAM7   ((uint32_t)(0x1UL << MXC_F_GCR_MEMZ_RAM7_POS))

MEMZ_RAM7 Mask

MXC_F_GCR_MEMZ_RAM7_POS

#define MXC_F_GCR_MEMZ_RAM7_POS   7

MEMZ_RAM7 Position

MXC_F_GCR_MEMZ_USBFIFO

#define MXC_F_GCR_MEMZ_USBFIFO   ((uint32_t)(0x1UL << MXC_F_GCR_MEMZ_USBFIFO_POS))

MEMZ_USBFIFO Mask

MXC_F_GCR_MEMZ_USBFIFO_POS

#define MXC_F_GCR_MEMZ_USBFIFO_POS   11

MEMZ_USBFIFO Position