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#define	MXC_F_I2C_TXCTRL0_PRELOAD_MODE_POS 0

#define	MXC_F_I2C_TXCTRL0_PRELOAD_MODE ((uint32_t)(0x1UL << MXC_F_I2C_TXCTRL0_PRELOAD_MODE_POS))

#define	MXC_F_I2C_TXCTRL0_TX_READY_MODE_POS 1

#define	MXC_F_I2C_TXCTRL0_TX_READY_MODE ((uint32_t)(0x1UL << MXC_F_I2C_TXCTRL0_TX_READY_MODE_POS))

#define	MXC_F_I2C_TXCTRL0_GC_ADDR_FLUSH_DIS_POS 2

#define	MXC_F_I2C_TXCTRL0_GC_ADDR_FLUSH_DIS ((uint32_t)(0x1UL << MXC_F_I2C_TXCTRL0_GC_ADDR_FLUSH_DIS_POS))

#define	MXC_F_I2C_TXCTRL0_WR_ADDR_FLUSH_DIS_POS 3

#define	MXC_F_I2C_TXCTRL0_WR_ADDR_FLUSH_DIS ((uint32_t)(0x1UL << MXC_F_I2C_TXCTRL0_WR_ADDR_FLUSH_DIS_POS))

#define	MXC_F_I2C_TXCTRL0_RD_ADDR_FLUSH_DIS_POS 4

#define	MXC_F_I2C_TXCTRL0_RD_ADDR_FLUSH_DIS ((uint32_t)(0x1UL << MXC_F_I2C_TXCTRL0_RD_ADDR_FLUSH_DIS_POS))

#define	MXC_F_I2C_TXCTRL0_NACK_FLUSH_DIS_POS 5

#define	MXC_F_I2C_TXCTRL0_NACK_FLUSH_DIS ((uint32_t)(0x1UL << MXC_F_I2C_TXCTRL0_NACK_FLUSH_DIS_POS))

#define	MXC_F_I2C_TXCTRL0_FLUSH_POS 7

#define	MXC_F_I2C_TXCTRL0_FLUSH ((uint32_t)(0x1UL << MXC_F_I2C_TXCTRL0_FLUSH_POS))

#define	MXC_F_I2C_TXCTRL0_THD_VAL_POS 8

#define	MXC_F_I2C_TXCTRL0_THD_VAL ((uint32_t)(0xFUL << MXC_F_I2C_TXCTRL0_THD_VAL_POS))

Detailed Description

Transmit Control Register 0.

Macro Definition Documentation

◆ MXC_F_I2C_TXCTRL0_FLUSH

#define MXC_F_I2C_TXCTRL0_FLUSH ((uint32_t)(0x1UL << MXC_F_I2C_TXCTRL0_FLUSH_POS))

TXCTRL0_FLUSH Mask

◆ MXC_F_I2C_TXCTRL0_FLUSH_POS

#define MXC_F_I2C_TXCTRL0_FLUSH_POS 7

TXCTRL0_FLUSH Position

◆ MXC_F_I2C_TXCTRL0_GC_ADDR_FLUSH_DIS

#define MXC_F_I2C_TXCTRL0_GC_ADDR_FLUSH_DIS ((uint32_t)(0x1UL << MXC_F_I2C_TXCTRL0_GC_ADDR_FLUSH_DIS_POS))

TXCTRL0_GC_ADDR_FLUSH_DIS Mask

◆ MXC_F_I2C_TXCTRL0_GC_ADDR_FLUSH_DIS_POS

#define MXC_F_I2C_TXCTRL0_GC_ADDR_FLUSH_DIS_POS 2

TXCTRL0_GC_ADDR_FLUSH_DIS Position

◆ MXC_F_I2C_TXCTRL0_NACK_FLUSH_DIS

#define MXC_F_I2C_TXCTRL0_NACK_FLUSH_DIS ((uint32_t)(0x1UL << MXC_F_I2C_TXCTRL0_NACK_FLUSH_DIS_POS))

TXCTRL0_NACK_FLUSH_DIS Mask

◆ MXC_F_I2C_TXCTRL0_NACK_FLUSH_DIS_POS

#define MXC_F_I2C_TXCTRL0_NACK_FLUSH_DIS_POS 5

TXCTRL0_NACK_FLUSH_DIS Position

◆ MXC_F_I2C_TXCTRL0_PRELOAD_MODE

#define MXC_F_I2C_TXCTRL0_PRELOAD_MODE ((uint32_t)(0x1UL << MXC_F_I2C_TXCTRL0_PRELOAD_MODE_POS))

TXCTRL0_PRELOAD_MODE Mask

◆ MXC_F_I2C_TXCTRL0_PRELOAD_MODE_POS

#define MXC_F_I2C_TXCTRL0_PRELOAD_MODE_POS 0

TXCTRL0_PRELOAD_MODE Position

◆ MXC_F_I2C_TXCTRL0_RD_ADDR_FLUSH_DIS

#define MXC_F_I2C_TXCTRL0_RD_ADDR_FLUSH_DIS ((uint32_t)(0x1UL << MXC_F_I2C_TXCTRL0_RD_ADDR_FLUSH_DIS_POS))

TXCTRL0_RD_ADDR_FLUSH_DIS Mask

◆ MXC_F_I2C_TXCTRL0_RD_ADDR_FLUSH_DIS_POS

#define MXC_F_I2C_TXCTRL0_RD_ADDR_FLUSH_DIS_POS 4

TXCTRL0_RD_ADDR_FLUSH_DIS Position

◆ MXC_F_I2C_TXCTRL0_THD_VAL

#define MXC_F_I2C_TXCTRL0_THD_VAL ((uint32_t)(0xFUL << MXC_F_I2C_TXCTRL0_THD_VAL_POS))

TXCTRL0_THD_VAL Mask

◆ MXC_F_I2C_TXCTRL0_THD_VAL_POS

#define MXC_F_I2C_TXCTRL0_THD_VAL_POS 8

TXCTRL0_THD_VAL Position

◆ MXC_F_I2C_TXCTRL0_TX_READY_MODE

#define MXC_F_I2C_TXCTRL0_TX_READY_MODE ((uint32_t)(0x1UL << MXC_F_I2C_TXCTRL0_TX_READY_MODE_POS))

TXCTRL0_TX_READY_MODE Mask

◆ MXC_F_I2C_TXCTRL0_TX_READY_MODE_POS

#define MXC_F_I2C_TXCTRL0_TX_READY_MODE_POS 1

TXCTRL0_TX_READY_MODE Position

◆ MXC_F_I2C_TXCTRL0_WR_ADDR_FLUSH_DIS

#define MXC_F_I2C_TXCTRL0_WR_ADDR_FLUSH_DIS ((uint32_t)(0x1UL << MXC_F_I2C_TXCTRL0_WR_ADDR_FLUSH_DIS_POS))

TXCTRL0_WR_ADDR_FLUSH_DIS Mask

◆ MXC_F_I2C_TXCTRL0_WR_ADDR_FLUSH_DIS_POS

#define MXC_F_I2C_TXCTRL0_WR_ADDR_FLUSH_DIS_POS 3

TXCTRL0_WR_ADDR_FLUSH_DIS Position

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