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MAX78002 Peripheral Driver API
Peripheral Driver API for the MAX78002
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Macros | |
| #define | MXC_R_MCR_ECCEN ((uint32_t)0x00000000UL) |
| #define | MXC_R_MCR_IPO_MTRIM ((uint32_t)0x00000004UL) |
| #define | MXC_R_MCR_OUTEN ((uint32_t)0x00000008UL) |
| #define | MXC_R_MCR_CMP_CTRL ((uint32_t)0x0000000CUL) |
| #define | MXC_R_MCR_CTRL ((uint32_t)0x00000010UL) |
| #define | MXC_R_MCR_GPIO3_CTRL ((uint32_t)0x00000020UL) |
| #define | MXC_R_MCR_CWD0 ((uint32_t)0x00000040UL) |
| #define | MXC_R_MCR_CWD1 ((uint32_t)0x00000044UL) |
| #define | MXC_R_MCR_ADCCFG0 ((uint32_t)0x00000050UL) |
| #define | MXC_R_MCR_ADCCFG1 ((uint32_t)0x00000054UL) |
| #define | MXC_R_MCR_ADCCFG2 ((uint32_t)0x00000058UL) |
| #define | MXC_R_MCR_LDOCTRL ((uint32_t)0x00000060UL) |
MCR Peripheral Register Offsets from the MCR Base Peripheral Address.
| #define MXC_R_MCR_ADCCFG0 ((uint32_t)0x00000050UL) |
Offset from MCR Base Address: 0x0050
| #define MXC_R_MCR_ADCCFG1 ((uint32_t)0x00000054UL) |
Offset from MCR Base Address: 0x0054
| #define MXC_R_MCR_ADCCFG2 ((uint32_t)0x00000058UL) |
Offset from MCR Base Address: 0x0058
| #define MXC_R_MCR_CMP_CTRL ((uint32_t)0x0000000CUL) |
Offset from MCR Base Address: 0x000C
| #define MXC_R_MCR_CTRL ((uint32_t)0x00000010UL) |
Offset from MCR Base Address: 0x0010
| #define MXC_R_MCR_CWD0 ((uint32_t)0x00000040UL) |
Offset from MCR Base Address: 0x0040
| #define MXC_R_MCR_CWD1 ((uint32_t)0x00000044UL) |
Offset from MCR Base Address: 0x0044
| #define MXC_R_MCR_ECCEN ((uint32_t)0x00000000UL) |
Offset from MCR Base Address: 0x0000
| #define MXC_R_MCR_GPIO3_CTRL ((uint32_t)0x00000020UL) |
Offset from MCR Base Address: 0x0020
| #define MXC_R_MCR_IPO_MTRIM ((uint32_t)0x00000004UL) |
Offset from MCR Base Address: 0x0004
| #define MXC_R_MCR_LDOCTRL ((uint32_t)0x00000060UL) |
Offset from MCR Base Address: 0x0060
| #define MXC_R_MCR_OUTEN ((uint32_t)0x00000008UL) |
Offset from MCR Base Address: 0x0008