Macros
#define	MXC_F_TMR_CTRL0_MODE_A_POS 0

#define	MXC_F_TMR_CTRL0_MODE_A ((uint32_t)(0xFUL << MXC_F_TMR_CTRL0_MODE_A_POS))

#define	MXC_V_TMR_CTRL0_MODE_A_ONE_SHOT ((uint32_t)0x0UL)

#define	MXC_S_TMR_CTRL0_MODE_A_ONE_SHOT (MXC_V_TMR_CTRL0_MODE_A_ONE_SHOT << MXC_F_TMR_CTRL0_MODE_A_POS)

#define	MXC_V_TMR_CTRL0_MODE_A_CONTINUOUS ((uint32_t)0x1UL)

#define	MXC_S_TMR_CTRL0_MODE_A_CONTINUOUS (MXC_V_TMR_CTRL0_MODE_A_CONTINUOUS << MXC_F_TMR_CTRL0_MODE_A_POS)

#define	MXC_V_TMR_CTRL0_MODE_A_COUNTER ((uint32_t)0x2UL)

#define	MXC_S_TMR_CTRL0_MODE_A_COUNTER (MXC_V_TMR_CTRL0_MODE_A_COUNTER << MXC_F_TMR_CTRL0_MODE_A_POS)

#define	MXC_V_TMR_CTRL0_MODE_A_PWM ((uint32_t)0x3UL)

#define	MXC_S_TMR_CTRL0_MODE_A_PWM (MXC_V_TMR_CTRL0_MODE_A_PWM << MXC_F_TMR_CTRL0_MODE_A_POS)

#define	MXC_V_TMR_CTRL0_MODE_A_CAPTURE ((uint32_t)0x4UL)

#define	MXC_S_TMR_CTRL0_MODE_A_CAPTURE (MXC_V_TMR_CTRL0_MODE_A_CAPTURE << MXC_F_TMR_CTRL0_MODE_A_POS)

#define	MXC_V_TMR_CTRL0_MODE_A_COMPARE ((uint32_t)0x5UL)

#define	MXC_S_TMR_CTRL0_MODE_A_COMPARE (MXC_V_TMR_CTRL0_MODE_A_COMPARE << MXC_F_TMR_CTRL0_MODE_A_POS)

#define	MXC_V_TMR_CTRL0_MODE_A_GATED ((uint32_t)0x6UL)

#define	MXC_S_TMR_CTRL0_MODE_A_GATED (MXC_V_TMR_CTRL0_MODE_A_GATED << MXC_F_TMR_CTRL0_MODE_A_POS)

#define	MXC_V_TMR_CTRL0_MODE_A_CAPCOMP ((uint32_t)0x7UL)

#define	MXC_S_TMR_CTRL0_MODE_A_CAPCOMP (MXC_V_TMR_CTRL0_MODE_A_CAPCOMP << MXC_F_TMR_CTRL0_MODE_A_POS)

#define	MXC_V_TMR_CTRL0_MODE_A_DUAL_EDGE ((uint32_t)0x8UL)

#define	MXC_S_TMR_CTRL0_MODE_A_DUAL_EDGE (MXC_V_TMR_CTRL0_MODE_A_DUAL_EDGE << MXC_F_TMR_CTRL0_MODE_A_POS)

#define	MXC_V_TMR_CTRL0_MODE_A_IGATED ((uint32_t)0xEUL)

#define	MXC_S_TMR_CTRL0_MODE_A_IGATED (MXC_V_TMR_CTRL0_MODE_A_IGATED << MXC_F_TMR_CTRL0_MODE_A_POS)

#define	MXC_F_TMR_CTRL0_CLKDIV_A_POS 4

#define	MXC_F_TMR_CTRL0_CLKDIV_A ((uint32_t)(0xFUL << MXC_F_TMR_CTRL0_CLKDIV_A_POS))

#define	MXC_V_TMR_CTRL0_CLKDIV_A_DIV_BY_1 ((uint32_t)0x0UL)

#define	MXC_S_TMR_CTRL0_CLKDIV_A_DIV_BY_1 (MXC_V_TMR_CTRL0_CLKDIV_A_DIV_BY_1 << MXC_F_TMR_CTRL0_CLKDIV_A_POS)

#define	MXC_V_TMR_CTRL0_CLKDIV_A_DIV_BY_2 ((uint32_t)0x1UL)

#define	MXC_S_TMR_CTRL0_CLKDIV_A_DIV_BY_2 (MXC_V_TMR_CTRL0_CLKDIV_A_DIV_BY_2 << MXC_F_TMR_CTRL0_CLKDIV_A_POS)

#define	MXC_V_TMR_CTRL0_CLKDIV_A_DIV_BY_4 ((uint32_t)0x2UL)

#define	MXC_S_TMR_CTRL0_CLKDIV_A_DIV_BY_4 (MXC_V_TMR_CTRL0_CLKDIV_A_DIV_BY_4 << MXC_F_TMR_CTRL0_CLKDIV_A_POS)

#define	MXC_V_TMR_CTRL0_CLKDIV_A_DIV_BY_8 ((uint32_t)0x3UL)

#define	MXC_S_TMR_CTRL0_CLKDIV_A_DIV_BY_8 (MXC_V_TMR_CTRL0_CLKDIV_A_DIV_BY_8 << MXC_F_TMR_CTRL0_CLKDIV_A_POS)

#define	MXC_V_TMR_CTRL0_CLKDIV_A_DIV_BY_16 ((uint32_t)0x4UL)

#define	MXC_S_TMR_CTRL0_CLKDIV_A_DIV_BY_16 (MXC_V_TMR_CTRL0_CLKDIV_A_DIV_BY_16 << MXC_F_TMR_CTRL0_CLKDIV_A_POS)

#define	MXC_V_TMR_CTRL0_CLKDIV_A_DIV_BY_32 ((uint32_t)0x5UL)

#define	MXC_S_TMR_CTRL0_CLKDIV_A_DIV_BY_32 (MXC_V_TMR_CTRL0_CLKDIV_A_DIV_BY_32 << MXC_F_TMR_CTRL0_CLKDIV_A_POS)

#define	MXC_V_TMR_CTRL0_CLKDIV_A_DIV_BY_64 ((uint32_t)0x6UL)

#define	MXC_S_TMR_CTRL0_CLKDIV_A_DIV_BY_64 (MXC_V_TMR_CTRL0_CLKDIV_A_DIV_BY_64 << MXC_F_TMR_CTRL0_CLKDIV_A_POS)

#define	MXC_V_TMR_CTRL0_CLKDIV_A_DIV_BY_128 ((uint32_t)0x7UL)

#define	MXC_S_TMR_CTRL0_CLKDIV_A_DIV_BY_128 (MXC_V_TMR_CTRL0_CLKDIV_A_DIV_BY_128 << MXC_F_TMR_CTRL0_CLKDIV_A_POS)

#define	MXC_V_TMR_CTRL0_CLKDIV_A_DIV_BY_256 ((uint32_t)0x8UL)

#define	MXC_S_TMR_CTRL0_CLKDIV_A_DIV_BY_256 (MXC_V_TMR_CTRL0_CLKDIV_A_DIV_BY_256 << MXC_F_TMR_CTRL0_CLKDIV_A_POS)

#define	MXC_V_TMR_CTRL0_CLKDIV_A_DIV_BY_512 ((uint32_t)0x9UL)

#define	MXC_S_TMR_CTRL0_CLKDIV_A_DIV_BY_512 (MXC_V_TMR_CTRL0_CLKDIV_A_DIV_BY_512 << MXC_F_TMR_CTRL0_CLKDIV_A_POS)

#define	MXC_V_TMR_CTRL0_CLKDIV_A_DIV_BY_1024 ((uint32_t)0xAUL)

#define	MXC_S_TMR_CTRL0_CLKDIV_A_DIV_BY_1024 (MXC_V_TMR_CTRL0_CLKDIV_A_DIV_BY_1024 << MXC_F_TMR_CTRL0_CLKDIV_A_POS)

#define	MXC_V_TMR_CTRL0_CLKDIV_A_DIV_BY_2048 ((uint32_t)0xBUL)

#define	MXC_S_TMR_CTRL0_CLKDIV_A_DIV_BY_2048 (MXC_V_TMR_CTRL0_CLKDIV_A_DIV_BY_2048 << MXC_F_TMR_CTRL0_CLKDIV_A_POS)

#define	MXC_V_TMR_CTRL0_CLKDIV_A_DIV_BY_4096 ((uint32_t)0xCUL)

#define	MXC_S_TMR_CTRL0_CLKDIV_A_DIV_BY_4096 (MXC_V_TMR_CTRL0_CLKDIV_A_DIV_BY_4096 << MXC_F_TMR_CTRL0_CLKDIV_A_POS)

#define	MXC_F_TMR_CTRL0_POL_A_POS 8

#define	MXC_F_TMR_CTRL0_POL_A ((uint32_t)(0x1UL << MXC_F_TMR_CTRL0_POL_A_POS))

#define	MXC_F_TMR_CTRL0_PWMSYNC_A_POS 9

#define	MXC_F_TMR_CTRL0_PWMSYNC_A ((uint32_t)(0x1UL << MXC_F_TMR_CTRL0_PWMSYNC_A_POS))

#define	MXC_F_TMR_CTRL0_NOLHPOL_A_POS 10

#define	MXC_F_TMR_CTRL0_NOLHPOL_A ((uint32_t)(0x1UL << MXC_F_TMR_CTRL0_NOLHPOL_A_POS))

#define	MXC_F_TMR_CTRL0_NOLLPOL_A_POS 11

#define	MXC_F_TMR_CTRL0_NOLLPOL_A ((uint32_t)(0x1UL << MXC_F_TMR_CTRL0_NOLLPOL_A_POS))

#define	MXC_F_TMR_CTRL0_PWMCKBD_A_POS 12

#define	MXC_F_TMR_CTRL0_PWMCKBD_A ((uint32_t)(0x1UL << MXC_F_TMR_CTRL0_PWMCKBD_A_POS))

#define	MXC_F_TMR_CTRL0_RST_A_POS 13

#define	MXC_F_TMR_CTRL0_RST_A ((uint32_t)(0x1UL << MXC_F_TMR_CTRL0_RST_A_POS))

#define	MXC_F_TMR_CTRL0_CLKEN_A_POS 14

#define	MXC_F_TMR_CTRL0_CLKEN_A ((uint32_t)(0x1UL << MXC_F_TMR_CTRL0_CLKEN_A_POS))

#define	MXC_F_TMR_CTRL0_EN_A_POS 15

#define	MXC_F_TMR_CTRL0_EN_A ((uint32_t)(0x1UL << MXC_F_TMR_CTRL0_EN_A_POS))

#define	MXC_F_TMR_CTRL0_MODE_B_POS 16

#define	MXC_F_TMR_CTRL0_MODE_B ((uint32_t)(0xFUL << MXC_F_TMR_CTRL0_MODE_B_POS))

#define	MXC_V_TMR_CTRL0_MODE_B_ONE_SHOT ((uint32_t)0x0UL)

#define	MXC_S_TMR_CTRL0_MODE_B_ONE_SHOT (MXC_V_TMR_CTRL0_MODE_B_ONE_SHOT << MXC_F_TMR_CTRL0_MODE_B_POS)

#define	MXC_V_TMR_CTRL0_MODE_B_CONTINUOUS ((uint32_t)0x1UL)

#define	MXC_S_TMR_CTRL0_MODE_B_CONTINUOUS (MXC_V_TMR_CTRL0_MODE_B_CONTINUOUS << MXC_F_TMR_CTRL0_MODE_B_POS)

#define	MXC_V_TMR_CTRL0_MODE_B_COUNTER ((uint32_t)0x2UL)

#define	MXC_S_TMR_CTRL0_MODE_B_COUNTER (MXC_V_TMR_CTRL0_MODE_B_COUNTER << MXC_F_TMR_CTRL0_MODE_B_POS)

#define	MXC_V_TMR_CTRL0_MODE_B_PWM ((uint32_t)0x3UL)

#define	MXC_S_TMR_CTRL0_MODE_B_PWM (MXC_V_TMR_CTRL0_MODE_B_PWM << MXC_F_TMR_CTRL0_MODE_B_POS)

#define	MXC_V_TMR_CTRL0_MODE_B_CAPTURE ((uint32_t)0x4UL)

#define	MXC_S_TMR_CTRL0_MODE_B_CAPTURE (MXC_V_TMR_CTRL0_MODE_B_CAPTURE << MXC_F_TMR_CTRL0_MODE_B_POS)

#define	MXC_V_TMR_CTRL0_MODE_B_COMPARE ((uint32_t)0x5UL)

#define	MXC_S_TMR_CTRL0_MODE_B_COMPARE (MXC_V_TMR_CTRL0_MODE_B_COMPARE << MXC_F_TMR_CTRL0_MODE_B_POS)

#define	MXC_V_TMR_CTRL0_MODE_B_GATED ((uint32_t)0x6UL)

#define	MXC_S_TMR_CTRL0_MODE_B_GATED (MXC_V_TMR_CTRL0_MODE_B_GATED << MXC_F_TMR_CTRL0_MODE_B_POS)

#define	MXC_V_TMR_CTRL0_MODE_B_CAPCOMP ((uint32_t)0x7UL)

#define	MXC_S_TMR_CTRL0_MODE_B_CAPCOMP (MXC_V_TMR_CTRL0_MODE_B_CAPCOMP << MXC_F_TMR_CTRL0_MODE_B_POS)

#define	MXC_V_TMR_CTRL0_MODE_B_DUAL_EDGE ((uint32_t)0x8UL)

#define	MXC_S_TMR_CTRL0_MODE_B_DUAL_EDGE (MXC_V_TMR_CTRL0_MODE_B_DUAL_EDGE << MXC_F_TMR_CTRL0_MODE_B_POS)

#define	MXC_V_TMR_CTRL0_MODE_B_IGATED ((uint32_t)0xEUL)

#define	MXC_S_TMR_CTRL0_MODE_B_IGATED (MXC_V_TMR_CTRL0_MODE_B_IGATED << MXC_F_TMR_CTRL0_MODE_B_POS)

#define	MXC_F_TMR_CTRL0_CLKDIV_B_POS 20

#define	MXC_F_TMR_CTRL0_CLKDIV_B ((uint32_t)(0xFUL << MXC_F_TMR_CTRL0_CLKDIV_B_POS))

#define	MXC_V_TMR_CTRL0_CLKDIV_B_DIV_BY_1 ((uint32_t)0x0UL)

#define	MXC_S_TMR_CTRL0_CLKDIV_B_DIV_BY_1 (MXC_V_TMR_CTRL0_CLKDIV_B_DIV_BY_1 << MXC_F_TMR_CTRL0_CLKDIV_B_POS)

#define	MXC_V_TMR_CTRL0_CLKDIV_B_DIV_BY_2 ((uint32_t)0x1UL)

#define	MXC_S_TMR_CTRL0_CLKDIV_B_DIV_BY_2 (MXC_V_TMR_CTRL0_CLKDIV_B_DIV_BY_2 << MXC_F_TMR_CTRL0_CLKDIV_B_POS)

#define	MXC_V_TMR_CTRL0_CLKDIV_B_DIV_BY_4 ((uint32_t)0x2UL)

#define	MXC_S_TMR_CTRL0_CLKDIV_B_DIV_BY_4 (MXC_V_TMR_CTRL0_CLKDIV_B_DIV_BY_4 << MXC_F_TMR_CTRL0_CLKDIV_B_POS)

#define	MXC_V_TMR_CTRL0_CLKDIV_B_DIV_BY_8 ((uint32_t)0x3UL)

#define	MXC_S_TMR_CTRL0_CLKDIV_B_DIV_BY_8 (MXC_V_TMR_CTRL0_CLKDIV_B_DIV_BY_8 << MXC_F_TMR_CTRL0_CLKDIV_B_POS)

#define	MXC_V_TMR_CTRL0_CLKDIV_B_DIV_BY_16 ((uint32_t)0x4UL)

#define	MXC_S_TMR_CTRL0_CLKDIV_B_DIV_BY_16 (MXC_V_TMR_CTRL0_CLKDIV_B_DIV_BY_16 << MXC_F_TMR_CTRL0_CLKDIV_B_POS)

#define	MXC_V_TMR_CTRL0_CLKDIV_B_DIV_BY_32 ((uint32_t)0x5UL)

#define	MXC_S_TMR_CTRL0_CLKDIV_B_DIV_BY_32 (MXC_V_TMR_CTRL0_CLKDIV_B_DIV_BY_32 << MXC_F_TMR_CTRL0_CLKDIV_B_POS)

#define	MXC_V_TMR_CTRL0_CLKDIV_B_DIV_BY_64 ((uint32_t)0x6UL)

#define	MXC_S_TMR_CTRL0_CLKDIV_B_DIV_BY_64 (MXC_V_TMR_CTRL0_CLKDIV_B_DIV_BY_64 << MXC_F_TMR_CTRL0_CLKDIV_B_POS)

#define	MXC_V_TMR_CTRL0_CLKDIV_B_DIV_BY_128 ((uint32_t)0x7UL)

#define	MXC_S_TMR_CTRL0_CLKDIV_B_DIV_BY_128 (MXC_V_TMR_CTRL0_CLKDIV_B_DIV_BY_128 << MXC_F_TMR_CTRL0_CLKDIV_B_POS)

#define	MXC_V_TMR_CTRL0_CLKDIV_B_DIV_BY_256 ((uint32_t)0x8UL)

#define	MXC_S_TMR_CTRL0_CLKDIV_B_DIV_BY_256 (MXC_V_TMR_CTRL0_CLKDIV_B_DIV_BY_256 << MXC_F_TMR_CTRL0_CLKDIV_B_POS)

#define	MXC_V_TMR_CTRL0_CLKDIV_B_DIV_BY_512 ((uint32_t)0x9UL)

#define	MXC_S_TMR_CTRL0_CLKDIV_B_DIV_BY_512 (MXC_V_TMR_CTRL0_CLKDIV_B_DIV_BY_512 << MXC_F_TMR_CTRL0_CLKDIV_B_POS)

#define	MXC_V_TMR_CTRL0_CLKDIV_B_DIV_BY_1024 ((uint32_t)0xAUL)

#define	MXC_S_TMR_CTRL0_CLKDIV_B_DIV_BY_1024 (MXC_V_TMR_CTRL0_CLKDIV_B_DIV_BY_1024 << MXC_F_TMR_CTRL0_CLKDIV_B_POS)

#define	MXC_V_TMR_CTRL0_CLKDIV_B_DIV_BY_2048 ((uint32_t)0xBUL)

#define	MXC_S_TMR_CTRL0_CLKDIV_B_DIV_BY_2048 (MXC_V_TMR_CTRL0_CLKDIV_B_DIV_BY_2048 << MXC_F_TMR_CTRL0_CLKDIV_B_POS)

#define	MXC_V_TMR_CTRL0_CLKDIV_B_DIV_BY_4096 ((uint32_t)0xCUL)

#define	MXC_S_TMR_CTRL0_CLKDIV_B_DIV_BY_4096 (MXC_V_TMR_CTRL0_CLKDIV_B_DIV_BY_4096 << MXC_F_TMR_CTRL0_CLKDIV_B_POS)

#define	MXC_F_TMR_CTRL0_POL_B_POS 24

#define	MXC_F_TMR_CTRL0_POL_B ((uint32_t)(0x1UL << MXC_F_TMR_CTRL0_POL_B_POS))

#define	MXC_F_TMR_CTRL0_PWMSYNC_B_POS 25

#define	MXC_F_TMR_CTRL0_PWMSYNC_B ((uint32_t)(0x1UL << MXC_F_TMR_CTRL0_PWMSYNC_B_POS))

#define	MXC_F_TMR_CTRL0_NOLHPOL_B_POS 26

#define	MXC_F_TMR_CTRL0_NOLHPOL_B ((uint32_t)(0x1UL << MXC_F_TMR_CTRL0_NOLHPOL_B_POS))

#define	MXC_F_TMR_CTRL0_NOLLPOL_B_POS 27

#define	MXC_F_TMR_CTRL0_NOLLPOL_B ((uint32_t)(0x1UL << MXC_F_TMR_CTRL0_NOLLPOL_B_POS))

#define	MXC_F_TMR_CTRL0_PWMCKBD_B_POS 28

#define	MXC_F_TMR_CTRL0_PWMCKBD_B ((uint32_t)(0x1UL << MXC_F_TMR_CTRL0_PWMCKBD_B_POS))

#define	MXC_F_TMR_CTRL0_RST_B_POS 29

#define	MXC_F_TMR_CTRL0_RST_B ((uint32_t)(0x1UL << MXC_F_TMR_CTRL0_RST_B_POS))

#define	MXC_F_TMR_CTRL0_CLKEN_B_POS 30

#define	MXC_F_TMR_CTRL0_CLKEN_B ((uint32_t)(0x1UL << MXC_F_TMR_CTRL0_CLKEN_B_POS))

#define	MXC_F_TMR_CTRL0_EN_B_POS 31

#define	MXC_F_TMR_CTRL0_EN_B ((uint32_t)(0x1UL << MXC_F_TMR_CTRL0_EN_B_POS))

Detailed Description

Timer Control Register.

Macro Definition Documentation

◆ MXC_F_TMR_CTRL0_CLKDIV_A

#define MXC_F_TMR_CTRL0_CLKDIV_A ((uint32_t)(0xFUL << MXC_F_TMR_CTRL0_CLKDIV_A_POS))

CTRL0_CLKDIV_A Mask

◆ MXC_F_TMR_CTRL0_CLKDIV_A_POS

#define MXC_F_TMR_CTRL0_CLKDIV_A_POS 4

CTRL0_CLKDIV_A Position

◆ MXC_F_TMR_CTRL0_CLKDIV_B

#define MXC_F_TMR_CTRL0_CLKDIV_B ((uint32_t)(0xFUL << MXC_F_TMR_CTRL0_CLKDIV_B_POS))

CTRL0_CLKDIV_B Mask

◆ MXC_F_TMR_CTRL0_CLKDIV_B_POS

#define MXC_F_TMR_CTRL0_CLKDIV_B_POS 20

CTRL0_CLKDIV_B Position

◆ MXC_F_TMR_CTRL0_CLKEN_A

#define MXC_F_TMR_CTRL0_CLKEN_A ((uint32_t)(0x1UL << MXC_F_TMR_CTRL0_CLKEN_A_POS))

CTRL0_CLKEN_A Mask

◆ MXC_F_TMR_CTRL0_CLKEN_A_POS

#define MXC_F_TMR_CTRL0_CLKEN_A_POS 14

CTRL0_CLKEN_A Position

◆ MXC_F_TMR_CTRL0_CLKEN_B

#define MXC_F_TMR_CTRL0_CLKEN_B ((uint32_t)(0x1UL << MXC_F_TMR_CTRL0_CLKEN_B_POS))

CTRL0_CLKEN_B Mask

◆ MXC_F_TMR_CTRL0_CLKEN_B_POS

#define MXC_F_TMR_CTRL0_CLKEN_B_POS 30

CTRL0_CLKEN_B Position

◆ MXC_F_TMR_CTRL0_EN_A

#define MXC_F_TMR_CTRL0_EN_A ((uint32_t)(0x1UL << MXC_F_TMR_CTRL0_EN_A_POS))

CTRL0_EN_A Mask

◆ MXC_F_TMR_CTRL0_EN_A_POS

#define MXC_F_TMR_CTRL0_EN_A_POS 15

CTRL0_EN_A Position

◆ MXC_F_TMR_CTRL0_EN_B

#define MXC_F_TMR_CTRL0_EN_B ((uint32_t)(0x1UL << MXC_F_TMR_CTRL0_EN_B_POS))

CTRL0_EN_B Mask

◆ MXC_F_TMR_CTRL0_EN_B_POS

#define MXC_F_TMR_CTRL0_EN_B_POS 31

CTRL0_EN_B Position

◆ MXC_F_TMR_CTRL0_MODE_A

#define MXC_F_TMR_CTRL0_MODE_A ((uint32_t)(0xFUL << MXC_F_TMR_CTRL0_MODE_A_POS))

CTRL0_MODE_A Mask

◆ MXC_F_TMR_CTRL0_MODE_A_POS

#define MXC_F_TMR_CTRL0_MODE_A_POS 0

CTRL0_MODE_A Position

◆ MXC_F_TMR_CTRL0_MODE_B

#define MXC_F_TMR_CTRL0_MODE_B ((uint32_t)(0xFUL << MXC_F_TMR_CTRL0_MODE_B_POS))

CTRL0_MODE_B Mask

◆ MXC_F_TMR_CTRL0_MODE_B_POS

#define MXC_F_TMR_CTRL0_MODE_B_POS 16

CTRL0_MODE_B Position

◆ MXC_F_TMR_CTRL0_NOLHPOL_A

#define MXC_F_TMR_CTRL0_NOLHPOL_A ((uint32_t)(0x1UL << MXC_F_TMR_CTRL0_NOLHPOL_A_POS))

CTRL0_NOLHPOL_A Mask

◆ MXC_F_TMR_CTRL0_NOLHPOL_A_POS

#define MXC_F_TMR_CTRL0_NOLHPOL_A_POS 10

CTRL0_NOLHPOL_A Position

◆ MXC_F_TMR_CTRL0_NOLHPOL_B

#define MXC_F_TMR_CTRL0_NOLHPOL_B ((uint32_t)(0x1UL << MXC_F_TMR_CTRL0_NOLHPOL_B_POS))

CTRL0_NOLHPOL_B Mask

◆ MXC_F_TMR_CTRL0_NOLHPOL_B_POS

#define MXC_F_TMR_CTRL0_NOLHPOL_B_POS 26

CTRL0_NOLHPOL_B Position

◆ MXC_F_TMR_CTRL0_NOLLPOL_A

#define MXC_F_TMR_CTRL0_NOLLPOL_A ((uint32_t)(0x1UL << MXC_F_TMR_CTRL0_NOLLPOL_A_POS))

CTRL0_NOLLPOL_A Mask

◆ MXC_F_TMR_CTRL0_NOLLPOL_A_POS

#define MXC_F_TMR_CTRL0_NOLLPOL_A_POS 11

CTRL0_NOLLPOL_A Position

◆ MXC_F_TMR_CTRL0_NOLLPOL_B

#define MXC_F_TMR_CTRL0_NOLLPOL_B ((uint32_t)(0x1UL << MXC_F_TMR_CTRL0_NOLLPOL_B_POS))

CTRL0_NOLLPOL_B Mask

◆ MXC_F_TMR_CTRL0_NOLLPOL_B_POS

#define MXC_F_TMR_CTRL0_NOLLPOL_B_POS 27

CTRL0_NOLLPOL_B Position

◆ MXC_F_TMR_CTRL0_POL_A

#define MXC_F_TMR_CTRL0_POL_A ((uint32_t)(0x1UL << MXC_F_TMR_CTRL0_POL_A_POS))

CTRL0_POL_A Mask

◆ MXC_F_TMR_CTRL0_POL_A_POS

#define MXC_F_TMR_CTRL0_POL_A_POS 8

CTRL0_POL_A Position

◆ MXC_F_TMR_CTRL0_POL_B

#define MXC_F_TMR_CTRL0_POL_B ((uint32_t)(0x1UL << MXC_F_TMR_CTRL0_POL_B_POS))

CTRL0_POL_B Mask

◆ MXC_F_TMR_CTRL0_POL_B_POS

#define MXC_F_TMR_CTRL0_POL_B_POS 24

CTRL0_POL_B Position

◆ MXC_F_TMR_CTRL0_PWMCKBD_A

#define MXC_F_TMR_CTRL0_PWMCKBD_A ((uint32_t)(0x1UL << MXC_F_TMR_CTRL0_PWMCKBD_A_POS))

CTRL0_PWMCKBD_A Mask

◆ MXC_F_TMR_CTRL0_PWMCKBD_A_POS

#define MXC_F_TMR_CTRL0_PWMCKBD_A_POS 12

CTRL0_PWMCKBD_A Position

◆ MXC_F_TMR_CTRL0_PWMCKBD_B

#define MXC_F_TMR_CTRL0_PWMCKBD_B ((uint32_t)(0x1UL << MXC_F_TMR_CTRL0_PWMCKBD_B_POS))

CTRL0_PWMCKBD_B Mask

◆ MXC_F_TMR_CTRL0_PWMCKBD_B_POS

#define MXC_F_TMR_CTRL0_PWMCKBD_B_POS 28

CTRL0_PWMCKBD_B Position

◆ MXC_F_TMR_CTRL0_PWMSYNC_A

#define MXC_F_TMR_CTRL0_PWMSYNC_A ((uint32_t)(0x1UL << MXC_F_TMR_CTRL0_PWMSYNC_A_POS))

CTRL0_PWMSYNC_A Mask

◆ MXC_F_TMR_CTRL0_PWMSYNC_A_POS

#define MXC_F_TMR_CTRL0_PWMSYNC_A_POS 9

CTRL0_PWMSYNC_A Position

◆ MXC_F_TMR_CTRL0_PWMSYNC_B

#define MXC_F_TMR_CTRL0_PWMSYNC_B ((uint32_t)(0x1UL << MXC_F_TMR_CTRL0_PWMSYNC_B_POS))

CTRL0_PWMSYNC_B Mask

◆ MXC_F_TMR_CTRL0_PWMSYNC_B_POS

#define MXC_F_TMR_CTRL0_PWMSYNC_B_POS 25

CTRL0_PWMSYNC_B Position

◆ MXC_F_TMR_CTRL0_RST_A

#define MXC_F_TMR_CTRL0_RST_A ((uint32_t)(0x1UL << MXC_F_TMR_CTRL0_RST_A_POS))

CTRL0_RST_A Mask

◆ MXC_F_TMR_CTRL0_RST_A_POS

#define MXC_F_TMR_CTRL0_RST_A_POS 13

CTRL0_RST_A Position

◆ MXC_F_TMR_CTRL0_RST_B

#define MXC_F_TMR_CTRL0_RST_B ((uint32_t)(0x1UL << MXC_F_TMR_CTRL0_RST_B_POS))

CTRL0_RST_B Mask

◆ MXC_F_TMR_CTRL0_RST_B_POS

#define MXC_F_TMR_CTRL0_RST_B_POS 29

CTRL0_RST_B Position

◆ MXC_S_TMR_CTRL0_CLKDIV_A_DIV_BY_1

#define MXC_S_TMR_CTRL0_CLKDIV_A_DIV_BY_1 (MXC_V_TMR_CTRL0_CLKDIV_A_DIV_BY_1 << MXC_F_TMR_CTRL0_CLKDIV_A_POS)

CTRL0_CLKDIV_A_DIV_BY_1 Setting

◆ MXC_S_TMR_CTRL0_CLKDIV_A_DIV_BY_1024

#define MXC_S_TMR_CTRL0_CLKDIV_A_DIV_BY_1024 (MXC_V_TMR_CTRL0_CLKDIV_A_DIV_BY_1024 << MXC_F_TMR_CTRL0_CLKDIV_A_POS)

CTRL0_CLKDIV_A_DIV_BY_1024 Setting

◆ MXC_S_TMR_CTRL0_CLKDIV_A_DIV_BY_128

#define MXC_S_TMR_CTRL0_CLKDIV_A_DIV_BY_128 (MXC_V_TMR_CTRL0_CLKDIV_A_DIV_BY_128 << MXC_F_TMR_CTRL0_CLKDIV_A_POS)

CTRL0_CLKDIV_A_DIV_BY_128 Setting

◆ MXC_S_TMR_CTRL0_CLKDIV_A_DIV_BY_16

#define MXC_S_TMR_CTRL0_CLKDIV_A_DIV_BY_16 (MXC_V_TMR_CTRL0_CLKDIV_A_DIV_BY_16 << MXC_F_TMR_CTRL0_CLKDIV_A_POS)

CTRL0_CLKDIV_A_DIV_BY_16 Setting

◆ MXC_S_TMR_CTRL0_CLKDIV_A_DIV_BY_2

#define MXC_S_TMR_CTRL0_CLKDIV_A_DIV_BY_2 (MXC_V_TMR_CTRL0_CLKDIV_A_DIV_BY_2 << MXC_F_TMR_CTRL0_CLKDIV_A_POS)

CTRL0_CLKDIV_A_DIV_BY_2 Setting

◆ MXC_S_TMR_CTRL0_CLKDIV_A_DIV_BY_2048

#define MXC_S_TMR_CTRL0_CLKDIV_A_DIV_BY_2048 (MXC_V_TMR_CTRL0_CLKDIV_A_DIV_BY_2048 << MXC_F_TMR_CTRL0_CLKDIV_A_POS)

CTRL0_CLKDIV_A_DIV_BY_2048 Setting

◆ MXC_S_TMR_CTRL0_CLKDIV_A_DIV_BY_256

#define MXC_S_TMR_CTRL0_CLKDIV_A_DIV_BY_256 (MXC_V_TMR_CTRL0_CLKDIV_A_DIV_BY_256 << MXC_F_TMR_CTRL0_CLKDIV_A_POS)

CTRL0_CLKDIV_A_DIV_BY_256 Setting

◆ MXC_S_TMR_CTRL0_CLKDIV_A_DIV_BY_32

#define MXC_S_TMR_CTRL0_CLKDIV_A_DIV_BY_32 (MXC_V_TMR_CTRL0_CLKDIV_A_DIV_BY_32 << MXC_F_TMR_CTRL0_CLKDIV_A_POS)

CTRL0_CLKDIV_A_DIV_BY_32 Setting

◆ MXC_S_TMR_CTRL0_CLKDIV_A_DIV_BY_4

#define MXC_S_TMR_CTRL0_CLKDIV_A_DIV_BY_4 (MXC_V_TMR_CTRL0_CLKDIV_A_DIV_BY_4 << MXC_F_TMR_CTRL0_CLKDIV_A_POS)

CTRL0_CLKDIV_A_DIV_BY_4 Setting

◆ MXC_S_TMR_CTRL0_CLKDIV_A_DIV_BY_4096

#define MXC_S_TMR_CTRL0_CLKDIV_A_DIV_BY_4096 (MXC_V_TMR_CTRL0_CLKDIV_A_DIV_BY_4096 << MXC_F_TMR_CTRL0_CLKDIV_A_POS)

CTRL0_CLKDIV_A_DIV_BY_4096 Setting

◆ MXC_S_TMR_CTRL0_CLKDIV_A_DIV_BY_512

#define MXC_S_TMR_CTRL0_CLKDIV_A_DIV_BY_512 (MXC_V_TMR_CTRL0_CLKDIV_A_DIV_BY_512 << MXC_F_TMR_CTRL0_CLKDIV_A_POS)

CTRL0_CLKDIV_A_DIV_BY_512 Setting

◆ MXC_S_TMR_CTRL0_CLKDIV_A_DIV_BY_64

#define MXC_S_TMR_CTRL0_CLKDIV_A_DIV_BY_64 (MXC_V_TMR_CTRL0_CLKDIV_A_DIV_BY_64 << MXC_F_TMR_CTRL0_CLKDIV_A_POS)

CTRL0_CLKDIV_A_DIV_BY_64 Setting

◆ MXC_S_TMR_CTRL0_CLKDIV_A_DIV_BY_8

#define MXC_S_TMR_CTRL0_CLKDIV_A_DIV_BY_8 (MXC_V_TMR_CTRL0_CLKDIV_A_DIV_BY_8 << MXC_F_TMR_CTRL0_CLKDIV_A_POS)

CTRL0_CLKDIV_A_DIV_BY_8 Setting

◆ MXC_S_TMR_CTRL0_CLKDIV_B_DIV_BY_1

#define MXC_S_TMR_CTRL0_CLKDIV_B_DIV_BY_1 (MXC_V_TMR_CTRL0_CLKDIV_B_DIV_BY_1 << MXC_F_TMR_CTRL0_CLKDIV_B_POS)

CTRL0_CLKDIV_B_DIV_BY_1 Setting

◆ MXC_S_TMR_CTRL0_CLKDIV_B_DIV_BY_1024

#define MXC_S_TMR_CTRL0_CLKDIV_B_DIV_BY_1024 (MXC_V_TMR_CTRL0_CLKDIV_B_DIV_BY_1024 << MXC_F_TMR_CTRL0_CLKDIV_B_POS)

CTRL0_CLKDIV_B_DIV_BY_1024 Setting

◆ MXC_S_TMR_CTRL0_CLKDIV_B_DIV_BY_128

#define MXC_S_TMR_CTRL0_CLKDIV_B_DIV_BY_128 (MXC_V_TMR_CTRL0_CLKDIV_B_DIV_BY_128 << MXC_F_TMR_CTRL0_CLKDIV_B_POS)

CTRL0_CLKDIV_B_DIV_BY_128 Setting

◆ MXC_S_TMR_CTRL0_CLKDIV_B_DIV_BY_16

#define MXC_S_TMR_CTRL0_CLKDIV_B_DIV_BY_16 (MXC_V_TMR_CTRL0_CLKDIV_B_DIV_BY_16 << MXC_F_TMR_CTRL0_CLKDIV_B_POS)

CTRL0_CLKDIV_B_DIV_BY_16 Setting

◆ MXC_S_TMR_CTRL0_CLKDIV_B_DIV_BY_2

#define MXC_S_TMR_CTRL0_CLKDIV_B_DIV_BY_2 (MXC_V_TMR_CTRL0_CLKDIV_B_DIV_BY_2 << MXC_F_TMR_CTRL0_CLKDIV_B_POS)

CTRL0_CLKDIV_B_DIV_BY_2 Setting

◆ MXC_S_TMR_CTRL0_CLKDIV_B_DIV_BY_2048

#define MXC_S_TMR_CTRL0_CLKDIV_B_DIV_BY_2048 (MXC_V_TMR_CTRL0_CLKDIV_B_DIV_BY_2048 << MXC_F_TMR_CTRL0_CLKDIV_B_POS)

CTRL0_CLKDIV_B_DIV_BY_2048 Setting

◆ MXC_S_TMR_CTRL0_CLKDIV_B_DIV_BY_256

#define MXC_S_TMR_CTRL0_CLKDIV_B_DIV_BY_256 (MXC_V_TMR_CTRL0_CLKDIV_B_DIV_BY_256 << MXC_F_TMR_CTRL0_CLKDIV_B_POS)

CTRL0_CLKDIV_B_DIV_BY_256 Setting

◆ MXC_S_TMR_CTRL0_CLKDIV_B_DIV_BY_32

#define MXC_S_TMR_CTRL0_CLKDIV_B_DIV_BY_32 (MXC_V_TMR_CTRL0_CLKDIV_B_DIV_BY_32 << MXC_F_TMR_CTRL0_CLKDIV_B_POS)

CTRL0_CLKDIV_B_DIV_BY_32 Setting

◆ MXC_S_TMR_CTRL0_CLKDIV_B_DIV_BY_4

#define MXC_S_TMR_CTRL0_CLKDIV_B_DIV_BY_4 (MXC_V_TMR_CTRL0_CLKDIV_B_DIV_BY_4 << MXC_F_TMR_CTRL0_CLKDIV_B_POS)

CTRL0_CLKDIV_B_DIV_BY_4 Setting

◆ MXC_S_TMR_CTRL0_CLKDIV_B_DIV_BY_4096

#define MXC_S_TMR_CTRL0_CLKDIV_B_DIV_BY_4096 (MXC_V_TMR_CTRL0_CLKDIV_B_DIV_BY_4096 << MXC_F_TMR_CTRL0_CLKDIV_B_POS)

CTRL0_CLKDIV_B_DIV_BY_4096 Setting

◆ MXC_S_TMR_CTRL0_CLKDIV_B_DIV_BY_512

#define MXC_S_TMR_CTRL0_CLKDIV_B_DIV_BY_512 (MXC_V_TMR_CTRL0_CLKDIV_B_DIV_BY_512 << MXC_F_TMR_CTRL0_CLKDIV_B_POS)

CTRL0_CLKDIV_B_DIV_BY_512 Setting

◆ MXC_S_TMR_CTRL0_CLKDIV_B_DIV_BY_64

#define MXC_S_TMR_CTRL0_CLKDIV_B_DIV_BY_64 (MXC_V_TMR_CTRL0_CLKDIV_B_DIV_BY_64 << MXC_F_TMR_CTRL0_CLKDIV_B_POS)

CTRL0_CLKDIV_B_DIV_BY_64 Setting

◆ MXC_S_TMR_CTRL0_CLKDIV_B_DIV_BY_8

#define MXC_S_TMR_CTRL0_CLKDIV_B_DIV_BY_8 (MXC_V_TMR_CTRL0_CLKDIV_B_DIV_BY_8 << MXC_F_TMR_CTRL0_CLKDIV_B_POS)

CTRL0_CLKDIV_B_DIV_BY_8 Setting

◆ MXC_S_TMR_CTRL0_MODE_A_CAPCOMP

#define MXC_S_TMR_CTRL0_MODE_A_CAPCOMP (MXC_V_TMR_CTRL0_MODE_A_CAPCOMP << MXC_F_TMR_CTRL0_MODE_A_POS)

CTRL0_MODE_A_CAPCOMP Setting

◆ MXC_S_TMR_CTRL0_MODE_A_CAPTURE

#define MXC_S_TMR_CTRL0_MODE_A_CAPTURE (MXC_V_TMR_CTRL0_MODE_A_CAPTURE << MXC_F_TMR_CTRL0_MODE_A_POS)

CTRL0_MODE_A_CAPTURE Setting

◆ MXC_S_TMR_CTRL0_MODE_A_COMPARE

#define MXC_S_TMR_CTRL0_MODE_A_COMPARE (MXC_V_TMR_CTRL0_MODE_A_COMPARE << MXC_F_TMR_CTRL0_MODE_A_POS)

CTRL0_MODE_A_COMPARE Setting

◆ MXC_S_TMR_CTRL0_MODE_A_CONTINUOUS

#define MXC_S_TMR_CTRL0_MODE_A_CONTINUOUS (MXC_V_TMR_CTRL0_MODE_A_CONTINUOUS << MXC_F_TMR_CTRL0_MODE_A_POS)

CTRL0_MODE_A_CONTINUOUS Setting

◆ MXC_S_TMR_CTRL0_MODE_A_COUNTER

#define MXC_S_TMR_CTRL0_MODE_A_COUNTER (MXC_V_TMR_CTRL0_MODE_A_COUNTER << MXC_F_TMR_CTRL0_MODE_A_POS)

CTRL0_MODE_A_COUNTER Setting

◆ MXC_S_TMR_CTRL0_MODE_A_DUAL_EDGE

#define MXC_S_TMR_CTRL0_MODE_A_DUAL_EDGE (MXC_V_TMR_CTRL0_MODE_A_DUAL_EDGE << MXC_F_TMR_CTRL0_MODE_A_POS)

CTRL0_MODE_A_DUAL_EDGE Setting

◆ MXC_S_TMR_CTRL0_MODE_A_GATED

#define MXC_S_TMR_CTRL0_MODE_A_GATED (MXC_V_TMR_CTRL0_MODE_A_GATED << MXC_F_TMR_CTRL0_MODE_A_POS)

CTRL0_MODE_A_GATED Setting

◆ MXC_S_TMR_CTRL0_MODE_A_IGATED

#define MXC_S_TMR_CTRL0_MODE_A_IGATED (MXC_V_TMR_CTRL0_MODE_A_IGATED << MXC_F_TMR_CTRL0_MODE_A_POS)

CTRL0_MODE_A_IGATED Setting

◆ MXC_S_TMR_CTRL0_MODE_A_ONE_SHOT

#define MXC_S_TMR_CTRL0_MODE_A_ONE_SHOT (MXC_V_TMR_CTRL0_MODE_A_ONE_SHOT << MXC_F_TMR_CTRL0_MODE_A_POS)

CTRL0_MODE_A_ONE_SHOT Setting

◆ MXC_S_TMR_CTRL0_MODE_A_PWM

#define MXC_S_TMR_CTRL0_MODE_A_PWM (MXC_V_TMR_CTRL0_MODE_A_PWM << MXC_F_TMR_CTRL0_MODE_A_POS)

CTRL0_MODE_A_PWM Setting

◆ MXC_S_TMR_CTRL0_MODE_B_CAPCOMP

#define MXC_S_TMR_CTRL0_MODE_B_CAPCOMP (MXC_V_TMR_CTRL0_MODE_B_CAPCOMP << MXC_F_TMR_CTRL0_MODE_B_POS)

CTRL0_MODE_B_CAPCOMP Setting

◆ MXC_S_TMR_CTRL0_MODE_B_CAPTURE

#define MXC_S_TMR_CTRL0_MODE_B_CAPTURE (MXC_V_TMR_CTRL0_MODE_B_CAPTURE << MXC_F_TMR_CTRL0_MODE_B_POS)

CTRL0_MODE_B_CAPTURE Setting

◆ MXC_S_TMR_CTRL0_MODE_B_COMPARE

#define MXC_S_TMR_CTRL0_MODE_B_COMPARE (MXC_V_TMR_CTRL0_MODE_B_COMPARE << MXC_F_TMR_CTRL0_MODE_B_POS)

CTRL0_MODE_B_COMPARE Setting

◆ MXC_S_TMR_CTRL0_MODE_B_CONTINUOUS

#define MXC_S_TMR_CTRL0_MODE_B_CONTINUOUS (MXC_V_TMR_CTRL0_MODE_B_CONTINUOUS << MXC_F_TMR_CTRL0_MODE_B_POS)

CTRL0_MODE_B_CONTINUOUS Setting

◆ MXC_S_TMR_CTRL0_MODE_B_COUNTER

#define MXC_S_TMR_CTRL0_MODE_B_COUNTER (MXC_V_TMR_CTRL0_MODE_B_COUNTER << MXC_F_TMR_CTRL0_MODE_B_POS)

CTRL0_MODE_B_COUNTER Setting

◆ MXC_S_TMR_CTRL0_MODE_B_DUAL_EDGE

#define MXC_S_TMR_CTRL0_MODE_B_DUAL_EDGE (MXC_V_TMR_CTRL0_MODE_B_DUAL_EDGE << MXC_F_TMR_CTRL0_MODE_B_POS)

CTRL0_MODE_B_DUAL_EDGE Setting

◆ MXC_S_TMR_CTRL0_MODE_B_GATED

#define MXC_S_TMR_CTRL0_MODE_B_GATED (MXC_V_TMR_CTRL0_MODE_B_GATED << MXC_F_TMR_CTRL0_MODE_B_POS)

CTRL0_MODE_B_GATED Setting

◆ MXC_S_TMR_CTRL0_MODE_B_IGATED

#define MXC_S_TMR_CTRL0_MODE_B_IGATED (MXC_V_TMR_CTRL0_MODE_B_IGATED << MXC_F_TMR_CTRL0_MODE_B_POS)

CTRL0_MODE_B_IGATED Setting

◆ MXC_S_TMR_CTRL0_MODE_B_ONE_SHOT

#define MXC_S_TMR_CTRL0_MODE_B_ONE_SHOT (MXC_V_TMR_CTRL0_MODE_B_ONE_SHOT << MXC_F_TMR_CTRL0_MODE_B_POS)

CTRL0_MODE_B_ONE_SHOT Setting

◆ MXC_S_TMR_CTRL0_MODE_B_PWM

#define MXC_S_TMR_CTRL0_MODE_B_PWM (MXC_V_TMR_CTRL0_MODE_B_PWM << MXC_F_TMR_CTRL0_MODE_B_POS)

CTRL0_MODE_B_PWM Setting

◆ MXC_V_TMR_CTRL0_CLKDIV_A_DIV_BY_1

#define MXC_V_TMR_CTRL0_CLKDIV_A_DIV_BY_1 ((uint32_t)0x0UL)

CTRL0_CLKDIV_A_DIV_BY_1 Value

◆ MXC_V_TMR_CTRL0_CLKDIV_A_DIV_BY_1024

#define MXC_V_TMR_CTRL0_CLKDIV_A_DIV_BY_1024 ((uint32_t)0xAUL)

CTRL0_CLKDIV_A_DIV_BY_1024 Value

◆ MXC_V_TMR_CTRL0_CLKDIV_A_DIV_BY_128

#define MXC_V_TMR_CTRL0_CLKDIV_A_DIV_BY_128 ((uint32_t)0x7UL)

CTRL0_CLKDIV_A_DIV_BY_128 Value

◆ MXC_V_TMR_CTRL0_CLKDIV_A_DIV_BY_16

#define MXC_V_TMR_CTRL0_CLKDIV_A_DIV_BY_16 ((uint32_t)0x4UL)

CTRL0_CLKDIV_A_DIV_BY_16 Value

◆ MXC_V_TMR_CTRL0_CLKDIV_A_DIV_BY_2

#define MXC_V_TMR_CTRL0_CLKDIV_A_DIV_BY_2 ((uint32_t)0x1UL)

CTRL0_CLKDIV_A_DIV_BY_2 Value

◆ MXC_V_TMR_CTRL0_CLKDIV_A_DIV_BY_2048

#define MXC_V_TMR_CTRL0_CLKDIV_A_DIV_BY_2048 ((uint32_t)0xBUL)

CTRL0_CLKDIV_A_DIV_BY_2048 Value

◆ MXC_V_TMR_CTRL0_CLKDIV_A_DIV_BY_256

#define MXC_V_TMR_CTRL0_CLKDIV_A_DIV_BY_256 ((uint32_t)0x8UL)

CTRL0_CLKDIV_A_DIV_BY_256 Value

◆ MXC_V_TMR_CTRL0_CLKDIV_A_DIV_BY_32

#define MXC_V_TMR_CTRL0_CLKDIV_A_DIV_BY_32 ((uint32_t)0x5UL)

CTRL0_CLKDIV_A_DIV_BY_32 Value

◆ MXC_V_TMR_CTRL0_CLKDIV_A_DIV_BY_4

#define MXC_V_TMR_CTRL0_CLKDIV_A_DIV_BY_4 ((uint32_t)0x2UL)

CTRL0_CLKDIV_A_DIV_BY_4 Value

◆ MXC_V_TMR_CTRL0_CLKDIV_A_DIV_BY_4096

#define MXC_V_TMR_CTRL0_CLKDIV_A_DIV_BY_4096 ((uint32_t)0xCUL)

CTRL0_CLKDIV_A_DIV_BY_4096 Value

◆ MXC_V_TMR_CTRL0_CLKDIV_A_DIV_BY_512

#define MXC_V_TMR_CTRL0_CLKDIV_A_DIV_BY_512 ((uint32_t)0x9UL)

CTRL0_CLKDIV_A_DIV_BY_512 Value

◆ MXC_V_TMR_CTRL0_CLKDIV_A_DIV_BY_64

#define MXC_V_TMR_CTRL0_CLKDIV_A_DIV_BY_64 ((uint32_t)0x6UL)

CTRL0_CLKDIV_A_DIV_BY_64 Value

◆ MXC_V_TMR_CTRL0_CLKDIV_A_DIV_BY_8

#define MXC_V_TMR_CTRL0_CLKDIV_A_DIV_BY_8 ((uint32_t)0x3UL)

CTRL0_CLKDIV_A_DIV_BY_8 Value

◆ MXC_V_TMR_CTRL0_CLKDIV_B_DIV_BY_1

#define MXC_V_TMR_CTRL0_CLKDIV_B_DIV_BY_1 ((uint32_t)0x0UL)

CTRL0_CLKDIV_B_DIV_BY_1 Value

◆ MXC_V_TMR_CTRL0_CLKDIV_B_DIV_BY_1024

#define MXC_V_TMR_CTRL0_CLKDIV_B_DIV_BY_1024 ((uint32_t)0xAUL)

CTRL0_CLKDIV_B_DIV_BY_1024 Value

◆ MXC_V_TMR_CTRL0_CLKDIV_B_DIV_BY_128

#define MXC_V_TMR_CTRL0_CLKDIV_B_DIV_BY_128 ((uint32_t)0x7UL)

CTRL0_CLKDIV_B_DIV_BY_128 Value

◆ MXC_V_TMR_CTRL0_CLKDIV_B_DIV_BY_16

#define MXC_V_TMR_CTRL0_CLKDIV_B_DIV_BY_16 ((uint32_t)0x4UL)

CTRL0_CLKDIV_B_DIV_BY_16 Value

◆ MXC_V_TMR_CTRL0_CLKDIV_B_DIV_BY_2

#define MXC_V_TMR_CTRL0_CLKDIV_B_DIV_BY_2 ((uint32_t)0x1UL)

CTRL0_CLKDIV_B_DIV_BY_2 Value

◆ MXC_V_TMR_CTRL0_CLKDIV_B_DIV_BY_2048

#define MXC_V_TMR_CTRL0_CLKDIV_B_DIV_BY_2048 ((uint32_t)0xBUL)

CTRL0_CLKDIV_B_DIV_BY_2048 Value

◆ MXC_V_TMR_CTRL0_CLKDIV_B_DIV_BY_256

#define MXC_V_TMR_CTRL0_CLKDIV_B_DIV_BY_256 ((uint32_t)0x8UL)

CTRL0_CLKDIV_B_DIV_BY_256 Value

◆ MXC_V_TMR_CTRL0_CLKDIV_B_DIV_BY_32

#define MXC_V_TMR_CTRL0_CLKDIV_B_DIV_BY_32 ((uint32_t)0x5UL)

CTRL0_CLKDIV_B_DIV_BY_32 Value

◆ MXC_V_TMR_CTRL0_CLKDIV_B_DIV_BY_4

#define MXC_V_TMR_CTRL0_CLKDIV_B_DIV_BY_4 ((uint32_t)0x2UL)

CTRL0_CLKDIV_B_DIV_BY_4 Value

◆ MXC_V_TMR_CTRL0_CLKDIV_B_DIV_BY_4096

#define MXC_V_TMR_CTRL0_CLKDIV_B_DIV_BY_4096 ((uint32_t)0xCUL)

CTRL0_CLKDIV_B_DIV_BY_4096 Value

◆ MXC_V_TMR_CTRL0_CLKDIV_B_DIV_BY_512

#define MXC_V_TMR_CTRL0_CLKDIV_B_DIV_BY_512 ((uint32_t)0x9UL)

CTRL0_CLKDIV_B_DIV_BY_512 Value

◆ MXC_V_TMR_CTRL0_CLKDIV_B_DIV_BY_64

#define MXC_V_TMR_CTRL0_CLKDIV_B_DIV_BY_64 ((uint32_t)0x6UL)

CTRL0_CLKDIV_B_DIV_BY_64 Value

◆ MXC_V_TMR_CTRL0_CLKDIV_B_DIV_BY_8

#define MXC_V_TMR_CTRL0_CLKDIV_B_DIV_BY_8 ((uint32_t)0x3UL)

CTRL0_CLKDIV_B_DIV_BY_8 Value

◆ MXC_V_TMR_CTRL0_MODE_A_CAPCOMP

#define MXC_V_TMR_CTRL0_MODE_A_CAPCOMP ((uint32_t)0x7UL)

CTRL0_MODE_A_CAPCOMP Value

◆ MXC_V_TMR_CTRL0_MODE_A_CAPTURE

#define MXC_V_TMR_CTRL0_MODE_A_CAPTURE ((uint32_t)0x4UL)

CTRL0_MODE_A_CAPTURE Value

◆ MXC_V_TMR_CTRL0_MODE_A_COMPARE

#define MXC_V_TMR_CTRL0_MODE_A_COMPARE ((uint32_t)0x5UL)

CTRL0_MODE_A_COMPARE Value

◆ MXC_V_TMR_CTRL0_MODE_A_CONTINUOUS

#define MXC_V_TMR_CTRL0_MODE_A_CONTINUOUS ((uint32_t)0x1UL)

CTRL0_MODE_A_CONTINUOUS Value

◆ MXC_V_TMR_CTRL0_MODE_A_COUNTER

#define MXC_V_TMR_CTRL0_MODE_A_COUNTER ((uint32_t)0x2UL)

CTRL0_MODE_A_COUNTER Value

◆ MXC_V_TMR_CTRL0_MODE_A_DUAL_EDGE

#define MXC_V_TMR_CTRL0_MODE_A_DUAL_EDGE ((uint32_t)0x8UL)

CTRL0_MODE_A_DUAL_EDGE Value

◆ MXC_V_TMR_CTRL0_MODE_A_GATED

#define MXC_V_TMR_CTRL0_MODE_A_GATED ((uint32_t)0x6UL)

CTRL0_MODE_A_GATED Value

◆ MXC_V_TMR_CTRL0_MODE_A_IGATED

#define MXC_V_TMR_CTRL0_MODE_A_IGATED ((uint32_t)0xEUL)

CTRL0_MODE_A_IGATED Value

◆ MXC_V_TMR_CTRL0_MODE_A_ONE_SHOT

#define MXC_V_TMR_CTRL0_MODE_A_ONE_SHOT ((uint32_t)0x0UL)

CTRL0_MODE_A_ONE_SHOT Value

◆ MXC_V_TMR_CTRL0_MODE_A_PWM

#define MXC_V_TMR_CTRL0_MODE_A_PWM ((uint32_t)0x3UL)

CTRL0_MODE_A_PWM Value

◆ MXC_V_TMR_CTRL0_MODE_B_CAPCOMP

#define MXC_V_TMR_CTRL0_MODE_B_CAPCOMP ((uint32_t)0x7UL)

CTRL0_MODE_B_CAPCOMP Value

◆ MXC_V_TMR_CTRL0_MODE_B_CAPTURE

#define MXC_V_TMR_CTRL0_MODE_B_CAPTURE ((uint32_t)0x4UL)

CTRL0_MODE_B_CAPTURE Value

◆ MXC_V_TMR_CTRL0_MODE_B_COMPARE

#define MXC_V_TMR_CTRL0_MODE_B_COMPARE ((uint32_t)0x5UL)

CTRL0_MODE_B_COMPARE Value

◆ MXC_V_TMR_CTRL0_MODE_B_CONTINUOUS

#define MXC_V_TMR_CTRL0_MODE_B_CONTINUOUS ((uint32_t)0x1UL)

CTRL0_MODE_B_CONTINUOUS Value

◆ MXC_V_TMR_CTRL0_MODE_B_COUNTER

#define MXC_V_TMR_CTRL0_MODE_B_COUNTER ((uint32_t)0x2UL)

CTRL0_MODE_B_COUNTER Value

◆ MXC_V_TMR_CTRL0_MODE_B_DUAL_EDGE

#define MXC_V_TMR_CTRL0_MODE_B_DUAL_EDGE ((uint32_t)0x8UL)

CTRL0_MODE_B_DUAL_EDGE Value

◆ MXC_V_TMR_CTRL0_MODE_B_GATED

#define MXC_V_TMR_CTRL0_MODE_B_GATED ((uint32_t)0x6UL)

CTRL0_MODE_B_GATED Value

◆ MXC_V_TMR_CTRL0_MODE_B_IGATED

#define MXC_V_TMR_CTRL0_MODE_B_IGATED ((uint32_t)0xEUL)

CTRL0_MODE_B_IGATED Value

◆ MXC_V_TMR_CTRL0_MODE_B_ONE_SHOT

#define MXC_V_TMR_CTRL0_MODE_B_ONE_SHOT ((uint32_t)0x0UL)

CTRL0_MODE_B_ONE_SHOT Value

◆ MXC_V_TMR_CTRL0_MODE_B_PWM

#define MXC_V_TMR_CTRL0_MODE_B_PWM ((uint32_t)0x3UL)

CTRL0_MODE_B_PWM Value

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