MAX78002 Peripheral Driver API
Peripheral Driver API for the MAX78002
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mcr_regs.h
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1
8/******************************************************************************
9 *
10 * Copyright (C) 2022-2023 Maxim Integrated Products, Inc. (now owned by
11 * Analog Devices, Inc.),
12 * Copyright (C) 2023-2024 Analog Devices, Inc.
13 *
14 * Licensed under the Apache License, Version 2.0 (the "License");
15 * you may not use this file except in compliance with the License.
16 * You may obtain a copy of the License at
17 *
18 * http://www.apache.org/licenses/LICENSE-2.0
19 *
20 * Unless required by applicable law or agreed to in writing, software
21 * distributed under the License is distributed on an "AS IS" BASIS,
22 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
23 * See the License for the specific language governing permissions and
24 * limitations under the License.
25 *
26 ******************************************************************************/
27
28#ifndef LIBRARIES_CMSIS_DEVICE_MAXIM_MAX78002_INCLUDE_MCR_REGS_H_
29#define LIBRARIES_CMSIS_DEVICE_MAXIM_MAX78002_INCLUDE_MCR_REGS_H_
30
31/* **** Includes **** */
32#include <stdint.h>
33
34#ifdef __cplusplus
35extern "C" {
36#endif
37
38#if defined (__ICCARM__)
39 #pragma system_include
40#endif
41
42#if defined (__CC_ARM)
43 #pragma anon_unions
44#endif
46/*
47 If types are not defined elsewhere (CMSIS) define them here
48*/
49#ifndef __IO
50#define __IO volatile
51#endif
52#ifndef __I
53#define __I volatile const
54#endif
55#ifndef __O
56#define __O volatile
57#endif
58#ifndef __R
59#define __R volatile const
60#endif
62
63/* **** Definitions **** */
64
76typedef struct {
77 __IO uint32_t eccen;
78 __IO uint32_t ipo_mtrim;
79 __IO uint32_t outen;
80 __IO uint32_t cmp_ctrl;
81 __IO uint32_t ctrl;
82 __R uint32_t rsv_0x14_0x1f[3];
83 __IO uint32_t gpio3_ctrl;
84 __R uint32_t rsv_0x24_0x3f[7];
85 __IO uint32_t cwd0;
86 __IO uint32_t cwd1;
87 __R uint32_t rsv_0x48_0x4f[2];
88 __IO uint32_t adccfg0;
89 __IO uint32_t adccfg1;
90 __IO uint32_t adccfg2;
91 __R uint32_t rsv_0x5c;
92 __IO uint32_t ldoctrl;
93} mxc_mcr_regs_t;
94
95/* Register offsets for module MCR */
102#define MXC_R_MCR_ECCEN ((uint32_t)0x00000000UL)
103#define MXC_R_MCR_IPO_MTRIM ((uint32_t)0x00000004UL)
104#define MXC_R_MCR_OUTEN ((uint32_t)0x00000008UL)
105#define MXC_R_MCR_CMP_CTRL ((uint32_t)0x0000000CUL)
106#define MXC_R_MCR_CTRL ((uint32_t)0x00000010UL)
107#define MXC_R_MCR_GPIO3_CTRL ((uint32_t)0x00000020UL)
108#define MXC_R_MCR_CWD0 ((uint32_t)0x00000040UL)
109#define MXC_R_MCR_CWD1 ((uint32_t)0x00000044UL)
110#define MXC_R_MCR_ADCCFG0 ((uint32_t)0x00000050UL)
111#define MXC_R_MCR_ADCCFG1 ((uint32_t)0x00000054UL)
112#define MXC_R_MCR_ADCCFG2 ((uint32_t)0x00000058UL)
113#define MXC_R_MCR_LDOCTRL ((uint32_t)0x00000060UL)
122#define MXC_F_MCR_ECCEN_RAM0_POS 0
123#define MXC_F_MCR_ECCEN_RAM0 ((uint32_t)(0x1UL << MXC_F_MCR_ECCEN_RAM0_POS))
133#define MXC_F_MCR_IPO_MTRIM_MTRIM_POS 0
134#define MXC_F_MCR_IPO_MTRIM_MTRIM ((uint32_t)(0xFFUL << MXC_F_MCR_IPO_MTRIM_MTRIM_POS))
136#define MXC_F_MCR_IPO_MTRIM_TRIM_RANGE_POS 8
137#define MXC_F_MCR_IPO_MTRIM_TRIM_RANGE ((uint32_t)(0x1UL << MXC_F_MCR_IPO_MTRIM_TRIM_RANGE_POS))
147#define MXC_F_MCR_OUTEN_SQWOUT_EN_POS 0
148#define MXC_F_MCR_OUTEN_SQWOUT_EN ((uint32_t)(0x1UL << MXC_F_MCR_OUTEN_SQWOUT_EN_POS))
150#define MXC_F_MCR_OUTEN_PDOWN_OUT_EN_POS 1
151#define MXC_F_MCR_OUTEN_PDOWN_OUT_EN ((uint32_t)(0x1UL << MXC_F_MCR_OUTEN_PDOWN_OUT_EN_POS))
161#define MXC_F_MCR_CMP_CTRL_EN_POS 0
162#define MXC_F_MCR_CMP_CTRL_EN ((uint32_t)(0x1UL << MXC_F_MCR_CMP_CTRL_EN_POS))
164#define MXC_F_MCR_CMP_CTRL_POL_POS 5
165#define MXC_F_MCR_CMP_CTRL_POL ((uint32_t)(0x1UL << MXC_F_MCR_CMP_CTRL_POL_POS))
167#define MXC_F_MCR_CMP_CTRL_INT_EN_POS 6
168#define MXC_F_MCR_CMP_CTRL_INT_EN ((uint32_t)(0x1UL << MXC_F_MCR_CMP_CTRL_INT_EN_POS))
170#define MXC_F_MCR_CMP_CTRL_OUT_POS 14
171#define MXC_F_MCR_CMP_CTRL_OUT ((uint32_t)(0x1UL << MXC_F_MCR_CMP_CTRL_OUT_POS))
173#define MXC_F_MCR_CMP_CTRL_INT_FL_POS 15
174#define MXC_F_MCR_CMP_CTRL_INT_FL ((uint32_t)(0x1UL << MXC_F_MCR_CMP_CTRL_INT_FL_POS))
184#define MXC_F_MCR_CTRL_CMPHYST_POS 0
185#define MXC_F_MCR_CTRL_CMPHYST ((uint32_t)(0x3UL << MXC_F_MCR_CTRL_CMPHYST_POS))
187#define MXC_F_MCR_CTRL_INRO_EN_POS 2
188#define MXC_F_MCR_CTRL_INRO_EN ((uint32_t)(0x1UL << MXC_F_MCR_CTRL_INRO_EN_POS))
190#define MXC_F_MCR_CTRL_ERTCO_EN_POS 3
191#define MXC_F_MCR_CTRL_ERTCO_EN ((uint32_t)(0x1UL << MXC_F_MCR_CTRL_ERTCO_EN_POS))
193#define MXC_F_MCR_CTRL_IBRO_EN_POS 4
194#define MXC_F_MCR_CTRL_IBRO_EN ((uint32_t)(0x1UL << MXC_F_MCR_CTRL_IBRO_EN_POS))
196#define MXC_F_MCR_CTRL_SIMO_CLKSCL_EN_POS 8
197#define MXC_F_MCR_CTRL_SIMO_CLKSCL_EN ((uint32_t)(0x1UL << MXC_F_MCR_CTRL_SIMO_CLKSCL_EN_POS))
199#define MXC_F_MCR_CTRL_SIMO_RSTD_POS 9
200#define MXC_F_MCR_CTRL_SIMO_RSTD ((uint32_t)(0x1UL << MXC_F_MCR_CTRL_SIMO_RSTD_POS))
210#define MXC_F_MCR_GPIO3_CTRL_P30_DO_POS 0
211#define MXC_F_MCR_GPIO3_CTRL_P30_DO ((uint32_t)(0x1UL << MXC_F_MCR_GPIO3_CTRL_P30_DO_POS))
213#define MXC_F_MCR_GPIO3_CTRL_P30_OE_POS 1
214#define MXC_F_MCR_GPIO3_CTRL_P30_OE ((uint32_t)(0x1UL << MXC_F_MCR_GPIO3_CTRL_P30_OE_POS))
216#define MXC_F_MCR_GPIO3_CTRL_P30_PE_POS 2
217#define MXC_F_MCR_GPIO3_CTRL_P30_PE ((uint32_t)(0x1UL << MXC_F_MCR_GPIO3_CTRL_P30_PE_POS))
219#define MXC_F_MCR_GPIO3_CTRL_P30_IN_POS 3
220#define MXC_F_MCR_GPIO3_CTRL_P30_IN ((uint32_t)(0x1UL << MXC_F_MCR_GPIO3_CTRL_P30_IN_POS))
222#define MXC_F_MCR_GPIO3_CTRL_P31_DO_POS 4
223#define MXC_F_MCR_GPIO3_CTRL_P31_DO ((uint32_t)(0x1UL << MXC_F_MCR_GPIO3_CTRL_P31_DO_POS))
225#define MXC_F_MCR_GPIO3_CTRL_P31_OE_POS 5
226#define MXC_F_MCR_GPIO3_CTRL_P31_OE ((uint32_t)(0x1UL << MXC_F_MCR_GPIO3_CTRL_P31_OE_POS))
228#define MXC_F_MCR_GPIO3_CTRL_P31_PE_POS 6
229#define MXC_F_MCR_GPIO3_CTRL_P31_PE ((uint32_t)(0x1UL << MXC_F_MCR_GPIO3_CTRL_P31_PE_POS))
231#define MXC_F_MCR_GPIO3_CTRL_P31_IN_POS 7
232#define MXC_F_MCR_GPIO3_CTRL_P31_IN ((uint32_t)(0x1UL << MXC_F_MCR_GPIO3_CTRL_P31_IN_POS))
242#define MXC_F_MCR_CWD0_DATA_POS 0
243#define MXC_F_MCR_CWD0_DATA ((uint32_t)(0xFFFFFFFFUL << MXC_F_MCR_CWD0_DATA_POS))
253#define MXC_F_MCR_CWD1_DATA_POS 0
254#define MXC_F_MCR_CWD1_DATA ((uint32_t)(0xFFFFFFFFUL << MXC_F_MCR_CWD1_DATA_POS))
264#define MXC_F_MCR_ADCCFG0_LP_5K_DIS_POS 0
265#define MXC_F_MCR_ADCCFG0_LP_5K_DIS ((uint32_t)(0x1UL << MXC_F_MCR_ADCCFG0_LP_5K_DIS_POS))
267#define MXC_F_MCR_ADCCFG0_LP_50K_DIS_POS 1
268#define MXC_F_MCR_ADCCFG0_LP_50K_DIS ((uint32_t)(0x1UL << MXC_F_MCR_ADCCFG0_LP_50K_DIS_POS))
270#define MXC_F_MCR_ADCCFG0_EXT_REF_POS 2
271#define MXC_F_MCR_ADCCFG0_EXT_REF ((uint32_t)(0x1UL << MXC_F_MCR_ADCCFG0_EXT_REF_POS))
273#define MXC_F_MCR_ADCCFG0_REF_SEL_POS 3
274#define MXC_F_MCR_ADCCFG0_REF_SEL ((uint32_t)(0x1UL << MXC_F_MCR_ADCCFG0_REF_SEL_POS))
284#define MXC_F_MCR_ADCCFG1_CHX_PU_DYN_POS 0
285#define MXC_F_MCR_ADCCFG1_CHX_PU_DYN ((uint32_t)(0x1FFFUL << MXC_F_MCR_ADCCFG1_CHX_PU_DYN_POS))
295#define MXC_F_MCR_ADCCFG2_CH0_POS 0
296#define MXC_F_MCR_ADCCFG2_CH0 ((uint32_t)(0x3UL << MXC_F_MCR_ADCCFG2_CH0_POS))
297#define MXC_V_MCR_ADCCFG2_CH0_DIV1 ((uint32_t)0x0UL)
298#define MXC_S_MCR_ADCCFG2_CH0_DIV1 (MXC_V_MCR_ADCCFG2_CH0_DIV1 << MXC_F_MCR_ADCCFG2_CH0_POS)
299#define MXC_V_MCR_ADCCFG2_CH0_DIV2_5K ((uint32_t)0x1UL)
300#define MXC_S_MCR_ADCCFG2_CH0_DIV2_5K (MXC_V_MCR_ADCCFG2_CH0_DIV2_5K << MXC_F_MCR_ADCCFG2_CH0_POS)
301#define MXC_V_MCR_ADCCFG2_CH0_DIV2_50K ((uint32_t)0x2UL)
302#define MXC_S_MCR_ADCCFG2_CH0_DIV2_50K (MXC_V_MCR_ADCCFG2_CH0_DIV2_50K << MXC_F_MCR_ADCCFG2_CH0_POS)
304#define MXC_F_MCR_ADCCFG2_CH1_POS 2
305#define MXC_F_MCR_ADCCFG2_CH1 ((uint32_t)(0x3UL << MXC_F_MCR_ADCCFG2_CH1_POS))
307#define MXC_F_MCR_ADCCFG2_CH2_POS 4
308#define MXC_F_MCR_ADCCFG2_CH2 ((uint32_t)(0x3UL << MXC_F_MCR_ADCCFG2_CH2_POS))
310#define MXC_F_MCR_ADCCFG2_CH3_POS 6
311#define MXC_F_MCR_ADCCFG2_CH3 ((uint32_t)(0x3UL << MXC_F_MCR_ADCCFG2_CH3_POS))
313#define MXC_F_MCR_ADCCFG2_CH4_POS 8
314#define MXC_F_MCR_ADCCFG2_CH4 ((uint32_t)(0x3UL << MXC_F_MCR_ADCCFG2_CH4_POS))
316#define MXC_F_MCR_ADCCFG2_CH5_POS 10
317#define MXC_F_MCR_ADCCFG2_CH5 ((uint32_t)(0x3UL << MXC_F_MCR_ADCCFG2_CH5_POS))
319#define MXC_F_MCR_ADCCFG2_CH6_POS 12
320#define MXC_F_MCR_ADCCFG2_CH6 ((uint32_t)(0x3UL << MXC_F_MCR_ADCCFG2_CH6_POS))
322#define MXC_F_MCR_ADCCFG2_CH7_POS 14
323#define MXC_F_MCR_ADCCFG2_CH7 ((uint32_t)(0x3UL << MXC_F_MCR_ADCCFG2_CH7_POS))
333#define MXC_F_MCR_LDOCTRL_0P9EN_POS 0
334#define MXC_F_MCR_LDOCTRL_0P9EN ((uint32_t)(0x1UL << MXC_F_MCR_LDOCTRL_0P9EN_POS))
336#define MXC_F_MCR_LDOCTRL_2P5EN_POS 1
337#define MXC_F_MCR_LDOCTRL_2P5EN ((uint32_t)(0x1UL << MXC_F_MCR_LDOCTRL_2P5EN_POS))
341#ifdef __cplusplus
342}
343#endif
344
345#endif // LIBRARIES_CMSIS_DEVICE_MAXIM_MAX78002_INCLUDE_MCR_REGS_H_
mxc_mcr_regs_t::adccfg0
__IO uint32_t adccfg0
Definition: mcr_regs.h:88
mxc_mcr_regs_t::cwd1
__IO uint32_t cwd1
Definition: mcr_regs.h:86
mxc_mcr_regs_t::ctrl
__IO uint32_t ctrl
Definition: mcr_regs.h:81
mxc_mcr_regs_t::adccfg2
__IO uint32_t adccfg2
Definition: mcr_regs.h:90
mxc_mcr_regs_t::outen
__IO uint32_t outen
Definition: mcr_regs.h:79
mxc_mcr_regs_t::ldoctrl
__IO uint32_t ldoctrl
Definition: mcr_regs.h:92
mxc_mcr_regs_t::cmp_ctrl
__IO uint32_t cmp_ctrl
Definition: mcr_regs.h:80
mxc_mcr_regs_t::cwd0
__IO uint32_t cwd0
Definition: mcr_regs.h:85
mxc_mcr_regs_t::ipo_mtrim
__IO uint32_t ipo_mtrim
Definition: mcr_regs.h:78
mxc_mcr_regs_t::eccen
__IO uint32_t eccen
Definition: mcr_regs.h:77
mxc_mcr_regs_t::adccfg1
__IO uint32_t adccfg1
Definition: mcr_regs.h:89
mxc_mcr_regs_t::gpio3_ctrl
__IO uint32_t gpio3_ctrl
Definition: mcr_regs.h:83
mxc_mcr_regs_t
Definition: mcr_regs.h:76