Go to the documentation of this file.
57 #define AD463X_REG_INTERFACE_CONFIG_A 0x00
58 #define AD463X_REG_INTERFACE_CONFIG_B 0x01
59 #define AD463X_REG_DEVICE_CONFIG 0x02
60 #define AD463X_REG_CHIP_TYPE 0x03
61 #define AD463X_REG_PRODUCT_ID_L 0x04
62 #define AD463X_REG_PRODUCT_ID_H 0x05
63 #define AD463X_REG_CHIP_GRADE 0x06
64 #define AD463X_REG_SCRATCH_PAD 0x0A
65 #define AD463X_REG_SPI_REVISION 0x0B
66 #define AD463X_REG_VENDOR_L 0x0C
67 #define AD463X_REG_VENDOR_H 0x0D
68 #define AD463X_REG_STREAM_MODE 0x0E
69 #define AD463X_REG_EXIT_CFG_MODE 0x14
70 #define AD463X_REG_AVG 0x15
71 #define AD463X_REG_OFFSET_BASE 0x16
72 #define AD463X_REG_OFFSET_X0_0 0x16
73 #define AD463X_REG_OFFSET_X0_1 0x17
74 #define AD463X_REG_OFFSET_X0_2 0x18
75 #define AD463X_REG_OFFSET_X1_0 0x19
76 #define AD463X_REG_OFFSET_X1_1 0x1A
77 #define AD463X_REG_OFFSET_X1_2 0x1B
78 #define AD463X_REG_GAIN_BASE 0x1C
79 #define AD463X_REG_GAIN_X0_LSB 0x1C
80 #define AD463X_REG_GAIN_X0_MSB 0x1D
81 #define AD463X_REG_GAIN_X1_LSB 0x1E
82 #define AD463X_REG_GAIN_X1_MSB 0x1F
83 #define AD463X_REG_MODES 0x20
84 #define AD463X_REG_OSCILATOR 0x21
85 #define AD463X_REG_IO 0x22
86 #define AD463X_REG_PAT0 0x23
87 #define AD463X_REG_PAT1 0x24
88 #define AD463X_REG_PAT2 0x25
89 #define AD463X_REG_PAT3 0x26
90 #define AD463X_REG_DIG_DIAG 0x34
91 #define AD463X_REG_DIG_ERR 0x35
93 #define AD463X_CFG_SW_RESET (NO_OS_BIT(7) | NO_OS_BIT(0))
94 #define AD463X_CFG_SDO_ENABLE NO_OS_BIT(4)
96 #define AD463X_SW_RESET_MSK (NO_OS_BIT(7) | NO_OS_BIT(0))
97 #define AD463X_LANE_MODE_MSK (NO_OS_BIT(7) | NO_OS_BIT(6))
98 #define AD463X_CLK_MODE_MSK (NO_OS_BIT(5) | NO_OS_BIT(4))
99 #define AD463X_DDR_MODE_MSK NO_OS_BIT(3)
100 #define AD463X_SDR_MODE 0x00
101 #define AD463X_DDR_MODE NO_OS_BIT(3)
102 #define AD463X_OUT_DATA_MODE_MSK (NO_OS_BIT(2) | NO_OS_BIT(1) | NO_OS_BIT(0))
103 #define AD463X_24_DIFF 0x00
104 #define AD463X_16_DIFF_8_COM 0x01
105 #define AD463X_24_DIFF_8_COM 0x02
106 #define AD463X_30_AVERAGED_DIFF 0x03
107 #define AD463X_32_PATTERN 0x04
109 #define AD463X_EXIT_CFG_MODE NO_OS_BIT(0)
111 #define AD463X_CHANNEL_0 0x00
112 #define AD463X_CHANNEL_1 0x01
114 #define AD463X_OFFSET_0 0x00
115 #define AD463X_OFFSET_1 0x01
116 #define AD463X_OFFSET_2 0x02
118 #define AD463X_GAIN_LSB 0x00
119 #define AD463X_GAIN_MSB 0x01
121 #define AD463X_ONE_LANE_PER_CH 0x00
122 #define AD463X_TWO_LANES_PER_CH NO_OS_BIT(6)
123 #define AD463X_FOUR_LANES_PER_CH NO_OS_BIT(7)
124 #define AD463X_SHARED_TWO_CH (NO_OS_BIT(6) | NO_OS_BIT(7))
126 #define AD463X_SPI_COMPATIBLE_MODE 0x00
127 #define AD463X_ECHO_CLOCK_MODE NO_OS_BIT(4)
128 #define AD463X_CLOCK_MASTER_MODE NO_OS_BIT(5)
130 #define AD463X_NORMAL_MODE 0x00
131 #define AD463X_LOW_POWER_MODE (NO_OS_BIT(1) | NO_OS_BIT(0))
133 #define AD463X_AVG_FILTER_RESET NO_OS_BIT(7)
134 #define AD463X_CONFIG_TIMING 0x2000
135 #define AD463X_REG_READ_DUMMY 0x00
136 #define AD463X_REG_WRITE 0x00
137 #define AD463X_REG_READ NO_OS_BIT(7)
138 #define AD463X_REG_CHAN_OFFSET(ch, pos) (AD463X_REG_OFFSET_BASE + (3 * ch) + pos)
139 #define AD463X_REG_CHAN_GAIN(ch, pos) (AD463X_REG_GAIN_BASE + (2 * ch) + pos)
141 #define AD463X_DRIVER_STRENGTH_MASK NO_OS_BIT(0)
142 #define AD463X_NORMAL_OUTPUT_STRENGTH 0x00
143 #define AD463X_DOUBLE_OUTPUT_STRENGTH NO_OS_BIT(1)
145 #define AD463X_OUT_DATA_PAT 0x5A5A0F0F
147 #define AD463X_TRIGGER_PULSE_WIDTH_NS 0x0A
149 #define AD463X_GAIN_MAX_VAL_SCALED 19997
const char * name
Definition: clk_axi_clkgen.h:57
#define MILLI
Definition: no_os_units.h:54
int32_t ad463x_set_drive_strength(struct ad463x_dev *dev, uint8_t mode)
Set drive strength.
Definition: ad463x.c:251
Structure holding the parameters for GPIO initialization.
Definition: no_os_gpio.h:85
ad463x_id
Device type.
Definition: ad463x.h:155
uint32_t no_commands
Definition: spi_engine.h:167
Structure containing the init parameters needed by the PWM generator.
Definition: no_os_pwm.h:72
int32_t scale_table[4][2]
Definition: ad463x.h:272
int32_t ad463x_set_ch_gain(struct ad463x_dev *dev, uint8_t ch_idx, uint64_t gain)
Set channel gain.
Definition: ad463x.c:293
int64_t no_os_div_s64_rem(int64_t dividend, int32_t divisor, int32_t *remainder)
int32_t ad463x_set_avg_frame_len(struct ad463x_dev *dev, uint8_t mode)
Set average frame length.
Definition: ad463x.c:214
uint8_t reg_data_width
Definition: ad463x.h:219
#define AD463x_TEST_DATA
Definition: ad463x.c:55
uint8_t pgia_idx
Definition: ad463x.h:270
struct no_os_spi_init_param * spi_init
Definition: ad463x.h:201
uint8_t clock_mode
Definition: ad463x.h:223
int32_t ad463x_set_avg_frame_len(struct ad463x_dev *dev, uint8_t mode)
Set average frame length.
Definition: ad463x.c:214
uint8_t data_rate
Definition: ad463x.h:225
int32_t no_os_spi_write_and_read(struct no_os_spi_desc *desc, uint8_t *data, uint16_t bytes_number)
Write and read data to/from SPI.
Definition: no_os_spi.c:165
@ AD463X_GAIN_0_56
Definition: ad463x.h:188
#define AD463X_REG_READ_DUMMY
Definition: ad463x.h:135
int32_t ad463x_calc_pgia_gain(int32_t gain_int, int32_t gain_fract, int32_t vref, int32_t precision, enum ad463x_pgia_gain *gain_idx)
Calculate the PGIA gain.
Definition: ad463x.c:673
#define CS_LOW
Definition: spi_engine.h:79
#define AD463X_REG_DEVICE_CONFIG
Definition: ad463x.h:59
#define AD463X_EXIT_CFG_MODE
Definition: ad463x.h:109
uint8_t lane_mode
Definition: ad463x.h:262
#define AD463X_DDR_MODE
Definition: ad463x.h:101
#define ADAQ4224_GAIN_MAX_NANO
Definition: ad463x.c:57
@ ID_AD4631_16
Definition: ad463x.h:167
uint32_t axi_clkgen_rate
Definition: ad463x.h:213
int32_t spi_engine_offload_init(struct no_os_spi_desc *desc, const struct spi_engine_offload_init_param *param)
Initialize the SPI engine's offload module.
Definition: spi_engine.c:759
int32_t ad463x_spi_reg_read(struct ad463x_dev *dev, uint16_t reg_addr, uint8_t *reg_data)
Read device register.
Definition: ad463x.c:87
int32_t no_os_pwm_remove(struct no_os_pwm_desc *desc)
Free the resources allocated by no_os_pwm_init().
Definition: no_os_pwm.c:85
Driver for the Analog Devices AXI CLKGEN.
int32_t ad463x_spi_reg_write(struct ad463x_dev *dev, uint16_t reg_addr, uint8_t reg_data)
Write device register.
Definition: ad463x.c:111
#define pr_err(fmt, args...)
Definition: no_os_print_log.h:94
uint32_t * commands_data
Definition: spi_engine.h:169
int32_t ad463x_exit_reg_cfg_mode(struct ad463x_dev *dev)
Exit register configuration mode.
Definition: ad463x.c:266
int32_t vref
Definition: ad463x.h:227
#define AD463X_CLK_MODE_MSK
Definition: ad463x.h:98
uint8_t output_mode
Definition: ad463x.h:229
Header file of Delay functions.
Definition: clk_axi_clkgen.h:56
struct no_os_gpio_desc * gpio_pgia_a0
Definition: ad463x.h:243
int32_t axi_clkgen_set_rate(struct axi_clkgen *clkgen, uint32_t rate)
axi_clkgen_set_rate
Definition: clk_axi_clkgen.c:419
#define NO_OS_DIV_ROUND_CLOSEST_ULL(x, y)
Definition: no_os_util.h:60
struct no_os_gpio_desc * gpio_resetn
Definition: ad463x.h:242
struct spi_engine_offload_init_param * offload_init_param
Definition: ad463x.h:209
@ ID_ADAQ4224
Definition: ad463x.h:177
Structure representing an offload message.
Definition: spi_engine.h:160
int32_t ad463x_spi_reg_read_masked(struct ad463x_dev *dev, uint16_t reg_addr, uint8_t mask, uint8_t *data)
SPI read device register using a mask.
Definition: ad463x.c:151
Definition: ad9361_util.h:75
@ NO_OS_GPIO_HIGH
Definition: no_os_gpio.h:123
#define AD463X_OFFSET_1
Definition: ad463x.h:115
enum ad463x_id device_id
Definition: ad463x.h:217
#define AD463X_CONFIG_TIMING
Definition: ad463x.h:134
struct no_os_pwm_desc * trigger_pwm_desc
Definition: ad463x.h:246
#define AD463X_DOUBLE_OUTPUT_STRENGTH
Definition: ad463x.h:143
uint32_t no_os_find_closest(int32_t val, const int32_t *array, uint32_t size)
uint8_t data_rate
Definition: ad463x.h:266
#define AD463X_TWO_LANES_PER_CH
Definition: ad463x.h:122
int32_t axi_clkgen_init(struct axi_clkgen **clk, const struct axi_clkgen_init *init)
axi_clkgen_init
Definition: clk_axi_clkgen.c:525
@ ID_AD4630_16
Definition: ad463x.h:161
Definition: clk_axi_clkgen.h:50
#define NO_OS_ARRAY_SIZE(x)
Definition: no_os_util.h:53
#define AD463X_FOUR_LANES_PER_CH
Definition: ad463x.h:123
@ ID_AD4631_20
Definition: ad463x.h:165
#define AD463X_GAIN_LSB
Definition: ad463x.h:118
int32_t ad463x_set_ch_gain(struct ad463x_dev *dev, uint8_t ch_idx, uint64_t gain)
Set channel gain.
Definition: ad463x.c:293
#define MICRO
Definition: no_os_units.h:55
struct no_os_gpio_init_param * gpio_pgia_a1
Definition: ad463x.h:205
int32_t ad463x_spi_reg_write_masked(struct ad463x_dev *dev, uint16_t reg_addr, uint8_t mask, uint8_t data)
SPI write device register using a mask.
Definition: ad463x.c:176
@ NO_OS_GPIO_LOW
Definition: no_os_gpio.h:121
#define AD463X_32_PATTERN
Definition: ad463x.h:107
struct no_os_pwm_init_param * trigger_pwm_init
Definition: ad463x.h:207
#define AD463X_SHARED_TWO_CH
Definition: ad463x.h:124
uint32_t reg_access_speed
Definition: ad7616.h:218
uint8_t reg_data_width
Definition: ad463x.h:256
void no_os_mdelay(uint32_t msecs)
Wait until msecs milliseconds passed.
Definition: aducm3029_delay.c:132
uint8_t real_bits_precision
Definition: ad463x.h:276
int32_t ad463x_set_pwr_mode(struct ad463x_dev *dev, uint8_t mode)
Set power mode.
Definition: ad463x.c:200
@ ID_AD4631_24
Definition: ad463x.h:163
#define CS_HIGH
Definition: spi_engine.h:78
void spi_engine_set_speed(struct no_os_spi_desc *desc, uint32_t speed_hz)
Set SPI engine clock frequency.
Definition: spi_engine.c:152
#define AD463X_ONE_LANE_PER_CH
Definition: ad463x.h:121
int32_t no_os_pwm_enable(struct no_os_pwm_desc *desc)
Enable PWM signal generation.
Definition: no_os_pwm.c:104
#define AD463X_REG_MODES
Definition: ad463x.h:83
int32_t spi_engine_set_transfer_width(struct no_os_spi_desc *desc, uint8_t data_wdith)
Set width of the transfered word over SPI.
Definition: spi_engine.c:131
@ ID_AD4632_24
Definition: ad463x.h:169
@ ID_AD4632_16
Definition: ad463x.h:173
#define AD463X_OFFSET_0
Definition: ad463x.h:114
struct spi_engine_offload_init_param * offload_init_param
Definition: ad7616.h:211
Header file of AD463x Driver.
struct no_os_pwm_init_param * trigger_pwm_init
Definition: ad7616.h:213
@ AD463X_GAIN_6_67
Definition: ad463x.h:192
int32_t ad463x_set_ch_offset(struct ad463x_dev *dev, uint8_t ch_idx, uint32_t offset)
Set channel offset.
Definition: ad463x.c:322
int32_t ad463x_spi_reg_write_masked(struct ad463x_dev *dev, uint16_t reg_addr, uint8_t mask, uint8_t data)
SPI write device register using a mask.
Definition: ad463x.c:176
int32_t ad463x_read_data(struct ad463x_dev *dev, uint32_t *buf, uint16_t samples)
Read from device. Enter register mode to read/write registers.
Definition: ad463x.c:410
#define AD463X_24_DIFF
Definition: ad463x.h:103
#define AD463X_REG_EXIT_CFG_MODE
Definition: ad463x.h:69
#define AD463X_REG_AVG
Definition: ad463x.h:70
uint32_t reg_access_speed
Definition: ad463x.h:252
uint32_t reg_access_speed
Definition: ad463x.h:215
struct no_os_spi_desc * spi_desc
Definition: ad463x.h:240
void(* dcache_invalidate_range)(uint32_t address, uint32_t bytes_count)
Definition: ad463x.h:280
int32_t ad463x_calc_pgia_gain(int32_t gain_int, int32_t gain_fract, int32_t vref, int32_t precision, enum ad463x_pgia_gain *gain_idx)
Calculate the PGIA gain.
Definition: ad463x.c:673
#define AD463X_NORMAL_MODE
Definition: ad463x.h:130
int32_t ad463x_enter_config_mode(struct ad463x_dev *dev)
Enter register configuration mode.
Definition: ad463x.c:129
int32_t ad463x_spi_reg_read_masked(struct ad463x_dev *dev, uint16_t reg_addr, uint8_t mask, uint8_t *data)
SPI read device register using a mask.
Definition: ad463x.c:151
uint8_t lane_mode
Definition: ad463x.h:221
int32_t ad463x_set_pgia_gain(struct ad463x_dev *dev, enum ad463x_pgia_gain gain_idx)
Set the PGIA gain.
Definition: ad463x.c:701
int32_t no_os_gpio_remove(struct no_os_gpio_desc *desc)
Free the resources allocated by no_os_gpio_get().
Definition: no_os_gpio.c:110
Structure holding SPI descriptor.
Definition: no_os_spi.h:177
#define AD463X_REG_SCRATCH_PAD
Definition: ad463x.h:64
int32_t ad463x_enter_config_mode(struct ad463x_dev *dev)
Enter register configuration mode.
Definition: ad463x.c:129
ad463x_pgia_gain
Available pgia gains.
Definition: ad463x.h:184
uint8_t capture_data_width
Definition: ad463x.h:260
int32_t ad463x_remove(struct ad463x_dev *dev)
Free the memory allocated by ad463x_init().
Definition: ad463x.c:731
Structure holding the GPIO descriptor.
Definition: no_os_gpio.h:102
#define AD463X_16_DIFF_8_COM
Definition: ad463x.h:104
int32_t ad463x_init(struct ad463x_dev **device, struct ad463x_init_param *init_param)
Initialize the device.
Definition: ad463x.c:485
#define AD463X_REG_READ
Definition: ad463x.h:137
int32_t vref
Definition: ad463x.h:268
int32_t ad463x_set_drive_strength(struct ad463x_dev *dev, uint8_t mode)
Set drive strength.
Definition: ad463x.c:251
uint8_t clock_mode
Definition: ad463x.h:264
uint32_t * commands
Definition: spi_engine.h:165
#define AD463X_AVG_FILTER_RESET
Definition: ad463x.h:133
Structure representing an PWM generator device.
Definition: no_os_pwm.h:99
#define AD463X_REG_CHAN_GAIN(ch, pos)
Definition: ad463x.h:139
int32_t ad463x_read_data(struct ad463x_dev *dev, uint32_t *buf, uint16_t samples)
Read from device. Enter register mode to read/write registers.
Definition: ad463x.c:410
int32_t no_os_pwm_init(struct no_os_pwm_desc **desc, const struct no_os_pwm_init_param *param)
Initialize the PWM peripheral.
Definition: no_os_pwm.c:57
@ ID_AD4630_24
Definition: ad463x.h:157
void(* dcache_invalidate_range)(uint32_t address, uint32_t bytes_count)
Definition: ad7616.h:236
@ AD463X_GAIN_0_33
Definition: ad463x.h:186
uint32_t axi_clkgen_rate
Definition: ad7616.h:217
int32_t ad463x_remove(struct ad463x_dev *dev)
Free the memory allocated by ad463x_init().
Definition: ad463x.c:731
int32_t ad463x_spi_reg_write(struct ad463x_dev *dev, uint16_t reg_addr, uint8_t reg_data)
Write device register.
Definition: ad463x.c:111
void * no_os_malloc(size_t size)
Allocate memory and return a pointer to it.
Definition: chibios_alloc.c:49
Header file of PWM Interface.
uint32_t no_os_field_get(uint32_t mask, uint32_t word)
@ AD463X_GAIN_2_22
Definition: ad463x.h:190
#define NO_OS_BIT(x)
Definition: no_os_util.h:51
void no_os_free(void *ptr)
Deallocate memory previously allocated by a call to no_os_calloc or no_os_malloc.
Definition: chibios_alloc.c:75
struct axi_clkgen * clkgen
Definition: ad463x.h:250
uint8_t output_mode
Definition: ad463x.h:274
#define AD463X_REG_CHAN_OFFSET(ch, pos)
Definition: ad463x.h:138
#define AD463X_DDR_MODE_MSK
Definition: ad463x.h:99
#define AD463X_OUT_DATA_MODE_MSK
Definition: ad463x.h:102
#define AD463X_LOW_POWER_MODE
Definition: ad463x.h:131
int32_t no_os_gpio_set_value(struct no_os_gpio_desc *desc, uint8_t value)
Set the value of the specified GPIO.
Definition: no_os_gpio.c:203
#define no_os_shift_right(x, s)
Definition: no_os_util.h:117
struct ad7616_init_param init_param
Definition: ad7616_sdz.c:119
struct axi_clkgen_init * clkgen_init
Definition: ad7616.h:215
int32_t ad463x_set_pgia_gain(struct ad463x_dev *dev, enum ad463x_pgia_gain gain_idx)
Set the PGIA gain.
Definition: ad463x.c:701
struct no_os_gpio_init_param * gpio_pgia_a0
Definition: ad463x.h:204
Device initialization parameters.
Definition: ad463x.h:238
#define AD463X_24_DIFF_8_COM
Definition: ad463x.h:105
#define AD463X_30_AVERAGED_DIFF
Definition: ad463x.h:106
void(* dcache_invalidate_range)(uint32_t address, uint32_t bytes_count)
Definition: ad463x.h:231
uint8_t read_bytes_no
Definition: ad463x.h:258
int32_t spi_engine_offload_transfer(struct no_os_spi_desc *desc, struct spi_engine_offload_message msg, uint32_t no_samples)
Initiate a SPI transfer in offload mode.
Definition: spi_engine.c:805
struct axi_clkgen_init * clkgen_init
Definition: ad463x.h:211
int32_t ad463x_init(struct ad463x_dev **device, struct ad463x_init_param *init_param)
Initialize the device.
Definition: ad463x.c:485
#define AD463X_GAIN_MAX_VAL_SCALED
Definition: ad463x.h:149
int32_t no_os_spi_remove(struct no_os_spi_desc *desc)
Free the resources allocated by no_os_spi_init().
Definition: no_os_spi.c:122
Structure containing the init parameters needed by the offload module.
Definition: spi_engine.h:145
Header file of GPIO Interface.
@ ID_AD4030
Definition: ad463x.h:175
#define AD463X_REG_IO
Definition: ad463x.h:85
enum ad463x_id device_id
Definition: ad463x.h:254
#define AD463X_GAIN_MSB
Definition: ad463x.h:119
uint32_t max_speed_hz
Definition: no_os_spi.h:183
#define NANO
Definition: no_os_units.h:56
int32_t no_os_spi_init(struct no_os_spi_desc **desc, const struct no_os_spi_init_param *param)
Initialize the SPI communication peripheral.
Definition: no_os_spi.c:58
#define AD463X_NORMAL_OUTPUT_STRENGTH
Definition: ad463x.h:142
int32_t axi_clkgen_remove(struct axi_clkgen *clkgen)
axi_clkgen_remove
Definition: clk_axi_clkgen.c:546
Header file of utility functions.
struct spi_engine_offload_init_param * offload_init_param
Definition: ad463x.h:248
int32_t ad463x_set_ch_offset(struct ad463x_dev *dev, uint8_t ch_idx, uint32_t offset)
Set channel offset.
Definition: ad463x.c:322
#define AD463X_DRIVER_STRENGTH_MASK
Definition: ad463x.h:141
@ ID_AD4630_20
Definition: ad463x.h:159
uint32_t rx_addr
Definition: spi_engine.h:173
int32_t no_os_gpio_direction_output(struct no_os_gpio_desc *desc, uint8_t value)
Enable the output direction of the specified GPIO.
Definition: no_os_gpio.c:153
#define AD463X_LANE_MODE_MSK
Definition: ad463x.h:97
struct no_os_gpio_desc * gpio_pgia_a1
Definition: ad463x.h:244
#define READ(no_bytes)
Definition: spi_engine.h:68
struct no_os_gpio_init_param * gpio_resetn
Definition: ad463x.h:203
bool has_pgia
Definition: ad463x.h:278
#define AD463X_SPI_COMPATIBLE_MODE
Definition: ad463x.h:126
int32_t ad463x_set_pwr_mode(struct ad463x_dev *dev, uint8_t mode)
Set power mode.
Definition: ad463x.c:200
int32_t ad463x_exit_reg_cfg_mode(struct ad463x_dev *dev)
Exit register configuration mode.
Definition: ad463x.c:266
#define AD463X_OFFSET_2
Definition: ad463x.h:116
@ ID_AD4632_20
Definition: ad463x.h:171
Structure holding the parameters for SPI initialization.
Definition: no_os_spi.h:131
int32_t ad463x_spi_reg_read(struct ad463x_dev *dev, uint16_t reg_addr, uint8_t *reg_data)
Read device register.
Definition: ad463x.c:87
int32_t no_os_gpio_get_optional(struct no_os_gpio_desc **desc, const struct no_os_gpio_init_param *param)
Get the value of an optional GPIO.
Definition: no_os_gpio.c:81