Go to the documentation of this file.
54 #define AD9250_READ (1 << 15)
55 #define AD9250_WRITE (0 << 15)
56 #define AD9250_CNT(x) ((((x) & 0x3) - 1) << 13)
57 #define AD9250_ADDR(x) ((x) & 0xFF)
59 #define AD9250_R1B (1 << 8)
60 #define AD9250_R2B (2 << 8)
61 #define AD9250_R3B (3 << 8)
62 #define AD9250_TRANSF_LEN(x) (((x) >> 8) & 0xFF)
63 #define SHADOW(x) ((x) << 16)
66 #define AD9250_REG_SPI_CFG (AD9250_R1B | 0x00)
67 #define AD9250_REG_CHIP_ID (AD9250_R1B | 0x01)
68 #define AD9250_REG_CHIP_INFO (AD9250_R1B | 0x02)
71 #define AD9250_REG_CH_INDEX (AD9250_R1B | 0x05)
72 #define AD9250_REG_DEVICE_UPDATE (AD9250_R1B | 0xFF)
75 #define AD9250_REG_PDWN (AD9250_R1B | 0x08)
76 #define AD9250_REG_CLOCK (AD9250_R1B | 0x09 | SHADOW(1))
77 #define AD9250_REG_PLL_STAT (AD9250_R1B | 0x0A)
78 #define AD9250_REG_CLOCK_DIV (AD9250_R1B | 0x0B | SHADOW(2))
79 #define AD9250_REG_TEST (AD9250_R1B | 0x0D | SHADOW(3))
80 #define AD9250_REG_BIST (AD9250_R1B | 0x0E | SHADOW(4))
81 #define AD9250_REG_OFFSET (AD9250_R1B | 0x10 | SHADOW(5))
82 #define AD9250_REG_OUT_MODE (AD9250_R1B | 0x14 | SHADOW(6))
83 #define AD9250_REG_CML (AD9250_R1B | 0x15)
84 #define AD9250_REG_VREF (AD9250_R1B | 0x18 | SHADOW(7))
85 #define AD9250_REG_USER_TEST1 (AD9250_R2B | 0x1A)
86 #define AD9250_REG_USER_TEST2 (AD9250_R2B | 0x1C)
87 #define AD9250_REG_USER_TEST3 (AD9250_R2B | 0x1E)
88 #define AD9250_REG_USER_TEST4 (AD9250_R2B | 0x20)
89 #define AD9250_REG_PLL_ENCODE (AD9250_R1B | 0x21)
90 #define AD9250_REG_BIST_MISR (AD9250_R2B | 0x25)
91 #define AD9250_REG_SYS_CTRL (AD9250_R1B | 0x3A | SHADOW(8))
92 #define AD9250_REG_DCC_CTRL (AD9250_R1B | 0x40 | SHADOW(9))
93 #define AD9250_REG_DCC_VAL (AD9250_R2B | 0x42 | SHADOW(10))
94 #define AD9250_REG_FAST_DETECT (AD9250_R1B | 0x45 | SHADOW(11))
95 #define AD9250_REG_FD_UPPER_THD (AD9250_R2B | 0x48 | SHADOW(12))
96 #define AD9250_REG_FD_LOWER_THD (AD9250_R2B | 0x4A | SHADOW(13))
97 #define AD9250_REG_FD_DWELL_TIME (AD9250_R2B | 0x4C | SHADOW(14))
98 #define AD9250_REG_204B_QUICK_CFG (AD9250_R1B | 0x5E)
99 #define AD9250_REG_204B_CTRL1 (AD9250_R1B | 0x5F)
100 #define AD9250_REG_204B_CTRL2 (AD9250_R1B | 0x60)
101 #define AD9250_REG_204B_CTRL3 (AD9250_R1B | 0x61)
102 #define AD9250_REG_204B_DID_CFG (AD9250_R1B | 0x64)
103 #define AD9250_REG_204B_BID_CFG (AD9250_R1B | 0x65)
104 #define AD9250_REG_204B_LID_CFG0 (AD9250_R1B | 0x66)
105 #define AD9250_REG_204B_LID_CFG1 (AD9250_R1B | 0x67)
106 #define AD9250_REG_204B_PARAM_SCR_L (AD9250_R1B | 0x6E)
107 #define AD9250_REG_204B_PARAM_F (AD9250_R1B | 0x6F)
108 #define AD9250_REG_204B_PARAM_K (AD9250_R1B | 0x70)
109 #define AD9250_REG_204B_PARAM_M (AD9250_R1B | 0x71)
110 #define AD9250_REG_204B_PARAM_CS_N (AD9250_R1B | 0x72)
111 #define AD9250_REG_204B_PARAM_NP (AD9250_R1B | 0x73)
112 #define AD9250_REG_204B_PARAM_S (AD9250_R1B | 0x74)
113 #define AD9250_REG_204B_PARAM_HD_CF (AD9250_R1B | 0x75)
114 #define AD9250_REG_204B_RESV1 (AD9250_R1B | 0x76)
115 #define AD9250_REG_204B_RESV2 (AD9250_R1B | 0x77)
116 #define AD9250_REG_204B_CHKSUM0 (AD9250_R1B | 0x79)
117 #define AD9250_REG_204B_CHKSUM1 (AD9250_R1B | 0x7A)
118 #define AD9250_REG_204B_LANE_ASSGN1 (AD9250_R1B | 0x82)
119 #define AD9250_REG_204B_LANE_ASSGN2 (AD9250_R1B | 0x83)
120 #define AD9250_REG_204B_LMFC_OFFSET (AD9250_R1B | 0x8B)
121 #define AD9250_REG_204B_PRE_EMPHASIS (AD9250_R1B | 0xA8)
124 #define AD9250_SPI_CFG_LSB_FIRST ((1 << 6) | (1 << 1))
125 #define AD9250_SPI_CFG_SOFT_RST ((1 << 5) | (1 << 2))
128 #define AD9250_CH_INDEX_ADC_A (1 << 0)
129 #define AD9250_CH_INDEX_ADC_B (1 << 1)
132 #define AD9250_DEVICE_UPDATE_SW (1 << 0)
135 #define AD9250_PDWN_EXTERN (1 << 5)
136 #define AD9250_PDWN_JTX (1 << 4)
137 #define AD9250_PDWN_JESD204B(x) (((x) & 0x3) << 2)
138 #define AD9250_PDWN_CHIP(x) (((x) & 0x3) << 0)
141 #define AD9250_CLOCK_SELECTION(x) (((x) & 0x3) << 4)
142 #define AD9250_CLOCK_DUTY_CYCLE (1 << 0)
145 #define AD9250_PLL_STAT_LOCKED (1 << 7)
146 #define AD9250_PLL_STAT_204B_LINK_RDY (1 << 0)
149 #define AD9250_CLOCK_DIV_PHASE(x) (((x) & 0x7) << 3)
150 #define AD9250_CLOCK_DIV_RATIO(x) (((x) & 0x7) << 0)
153 #define AD9250_TEST_USER_TEST_MODE(x) (((x) & 0x3) << 6)
154 #define AD9250_TEST_RST_PN_LONG (1 << 5)
155 #define AD9250_TEST_RST_PN_SHOR (1 << 4)
156 #define AD9250_TEST_OUTPUT_TEST(x) (((x) & 0xF) << 0)
159 #define AD9250_TEST_OFF 0x00
160 #define AD9250_TEST_MID_SCALE 0x01
161 #define AD9250_TEST_POS_FSCALE 0x02
162 #define AD9250_TEST_NEG_FSCALE 0x03
163 #define AD9250_TEST_CHECKBOARD 0x04
164 #define AD9250_TEST_PNLONG 0x05
165 #define AD9250_TEST_ONE2ZERO 0x07
166 #define AD9250_TEST_PATTERN 0x08
167 #define AD9250_TEST_RAMP 0x0F
170 #define AD9250_BIST_RESET (1 << 2)
171 #define AD9250_BIST_ENABLE (1 << 0)
174 #define AD9250_REG_OFFSET_ADJUST(x) (((x) & 0x3F) << 0)
177 #define AD9250_OUT_MODE_JTX_BIT_ASSIGN(x) (((x) & 0x7) << 5)
178 #define AD9250_OUT_MODE_DISABLE (1 << 4)
179 #define AD9250_OUT_MODE_INVERT_DATA (1 << 3)
180 #define AD9250_OUT_MODE_DATA_FORMAT(x) (((x) & 0x1) << 0)
183 #define AD9250_OUT_OFFSET_BINARY 0x00
184 #define AD9250_OUT_2S_COMPLEMENT 0x01
187 #define AD9250_CML_DIFF_OUT_LEVEL(x) (((x) & 0x7) << 0)
190 #define AD9250_VREF_FS_ADJUST(x) (((x) & 0x1F) << 0)
193 #define AD9250_PLL_ENCODE(x) (((x) & 0x3) << 3)
196 #define AD9250_SYS_CTRL_REALIGN_ON_SYNCINB (1 << 4)
197 #define AD9250_SYS_CTRL_REALIGN_ON_SYSREF (1 << 3)
198 #define AD9250_SYS_CTRL_SYSREF_MODE (1 << 2)
199 #define AD9250_SYS_CTRL_SYSREF_EN (1 << 1)
200 #define AD9250_SYS_CTRL_SYNCINB_EN (1 << 0)
203 #define AD9250_DCC_CTRL_FREEZE_DCC (1 << 6)
204 #define AD9250_DCC_CTRL_DCC_BW(x) (((x) & 0xF) << 2)
205 #define AD9250_DCC_CTRL_DCC_EN (1 << 1)
208 #define AD9250_FAST_DETECT_PIN_FCT (1 << 4)
209 #define AD9250_FAST_DETECT_FORCE_FDA_FDB_PIN (1 << 3)
210 #define AD9250_FAST_DETECT_FORCE_FDA_FDB_VAL (1 << 2)
211 #define AD9250_FAST_DETECT_OUTPUT_ENABLE (1 << 0)
214 #define AD9250_204B_QUICK_CFG(x) (((x) & 0xFF) << 0)
217 #define AD9250_204B_CTRL1_TAIL_BITS (1 << 6)
218 #define AD9250_204B_CTRL1_TEST_SAMPLE_EN (1 << 5)
219 #define AD9250_204B_CTRL1_ILAS_MODE(x) (((x) & 0x3) << 2)
220 #define AD9250_204B_CTRL1_POWER_DOWN (1 << 0)
223 #define AD9250_204B_CTRL2_INVERT_JESD_BITS (1 << 1)
226 #define AD9250_204B_CTRL3_TEST_DATA_INJ_PT(x) (((x) & 0x3) << 4)
227 #define AD9250_204B_CTRL3_JESD_TEST_MODE(x) (((x) & 0xF) << 0)
230 #define AD9250_204B_PARAM_SCR_L_SCRAMBLING (1 << 7)
231 #define AD9250_204B_PARAM_SCR_L_LANES (1 << 0)
234 #define AD9250_204B_PARAM_CS_N_NR_CTRL_BITS(x) (((x) & 0x3) << 6)
235 #define AD9250_204B_PARAM_CS_N_ADC_RESOLUTION(x) (((x) & 0xF) << 0)
238 #define AD9250_204B_PARAM_NP_JESD_SUBCLASS(x) (((x) & 0x3) << 5)
239 #define AD9250_204B_PARAM_NP_JESD_N_VAL(x) (((x) & 0xF) << 0)
242 #define AD9250_204B_PARAM_S(x) (((x) << 0x1F) << 0)
245 #define AD9250_204B_PARAM_HD_CF_HD_VAL (1 << 7)
246 #define AD9250_204B_PARAM_HD_CF_CF_VAL(x) (((x) & 0x1F) << 0)
249 #define AD9250_204B_LANE_ASSGN1(x) (((x) & 0x3) << 4)
252 #define AD9250_204B_LANE_ASSGN2(x) (((x) &0x3) << 0)
255 #define AD9250_204B_LMFC_OFFSET(x) (((x) & 0x1F) << 0)
546 int32_t register_address);
549 int32_t register_address,
550 int32_t register_value);
585 int32_t user_pattern);
#define AD9250_REG_204B_PARAM_NP
Definition: ad9250.h:111
int32_t ad9250_jesd204b_setup(struct ad9250_dev *dev)
Configures the JESD204B interface.
Definition: ad9250.c:838
#define AD9250_BIST_ENABLE
Definition: ad9250.h:171
@ AD9250_SHD_REG_OFFSET
Definition: ad9250.h:507
@ AD9250_SHD_REG_BIST
Definition: ad9250.h:506
uint32_t timeout
Definition: ad413x.c:55
#define AD9250_REG_USER_TEST1
Definition: ad9250.h:85
int32_t ad9250_output_invert(struct ad9250_dev *dev, int32_t invert)
Activates the inverted (1) or normal (0) output mode. Note: This function modifies a shadowed registe...
Definition: ad9250.c:586
int8_t lane0_assign
Definition: ad9250.h:451
#define AD9250_REG_DCC_CTRL
Definition: ad9250.h:92
int8_t en_fd
Definition: ad9250.h:469
int8_t invert_logic_bits
Definition: ad9250.h:415
int32_t ad9250_jesd204b_select_test_injection_point(struct ad9250_dev *dev, int32_t inj_point)
Selects the point in the processing path of a lane, where the test data will be inserted.
Definition: ad9250.c:1062
#define AD9250_BIST_RESET
Definition: ad9250.h:170
#define AD9250_204B_CTRL2_INVERT_JESD_BITS
Definition: ad9250.h:223
shadow_registers
Definition: ad6673.h:503
#define SHADOW(x)
Definition: ad6673.h:64
int32_t ad9250_set_user_pattern(struct ad9250_dev *dev, int32_t pattern_no, int32_t user_pattern)
Configures a User Test Pattern.
Definition: ad9250.c:716
int32_t ad9250_is_shadow_register(int32_t register_address)
Checks if the register is shadowed.
Definition: ad9250.c:402
int32_t ad9250_soft_reset(struct ad9250_dev *dev)
Resets all registers to their default values.
Definition: ad9250.c:326
#define AD9250_PDWN_EXTERN
Definition: ad9250.h:135
int8_t pin_force_value
Definition: ad9250.h:487
int8_t en_sys_ref
Definition: ad9250.h:421
int32_t no_os_spi_write_and_read(struct no_os_spi_desc *desc, uint8_t *data, uint16_t bytes_number)
Write and read data to/from SPI.
Definition: no_os_spi.c:165
int32_t ad9250_reset_pn23(struct ad9250_dev *dev, int32_t rst)
Sets (1) or clears (0) the reset long PN sequence bit(PN23).
Definition: ad9250.c:685
int32_t ad9250_bist_enable(struct ad9250_dev *dev, int32_t enable)
Enables the Build-In-Self-Test.
Definition: ad9250.c:739
int32_t ad9250_select_channel_for_config(struct ad9250_dev *dev, int32_t channel)
Selects a channel as the current channel for further configurations.
Definition: ad9250.c:451
int32_t ad9250_jesd204b_pwr_mode(struct ad9250_dev *dev, int32_t mode)
Configures the power mode of the JESD204B data transmit block.
Definition: ad9250.c:1028
int32_t ad9250_set_user_pattern(struct ad9250_dev *dev, int32_t pattern_no, int32_t user_pattern)
Configures a User Test Pattern.
Definition: ad9250.c:716
#define AD9250_204B_LANE_ASSGN2(x)
Definition: ad9250.h:252
Header file of SPI Interface.
#define AD9250_CH_INDEX_ADC_B
Definition: ad9250.h:129
int32_t ad9250_dcc_bandwidth(struct ad9250_dev *dev, int32_t bw)
Selects the bandwidth value for the DC correction circuit.
Definition: ad9250.c:1243
#define AD9250_REG_TEST
Definition: ad9250.h:79
@ AD9250_SHD_REG_TEST
Definition: ad9250.h:505
#define AD9250_204B_CTRL1_ILAS_MODE(x)
Definition: ad9250.h:219
int16_t df_dwell_time
Definition: ad9250.h:493
#define AD9250_REG_204B_LID_CFG1
Definition: ad9250.h:105
int8_t lane1_assign
Definition: ad9250.h:456
#define AD9250_OUT_MODE_JTX_BIT_ASSIGN(x)
Definition: ad9250.h:177
Header file of AD9250 Driver.
#define AD9250_REG_CML
Definition: ad9250.h:83
@ AD9250_SHD_REG_FAST_DETECT
Definition: ad9250.h:513
#define AD9250_REG_VREF
Definition: ad9250.h:84
#define AD9250_REG_204B_LID_CFG0
Definition: ad9250.h:104
int32_t ad9250_output_disable(struct ad9250_dev *dev, int32_t en)
Disables (1) or enables (0) the data output. Note: This function modifies a shadowed register,...
Definition: ad9250.c:551
int32_t ad9250_set_bits_to_reg(struct ad9250_dev *dev, uint32_t register_address, uint8_t bits_value, uint8_t mask)
Sets a bit/group of bits inside a register without modifying other bits.
Definition: ad9250.c:361
#define AD9250_204B_PARAM_SCR_L_SCRAMBLING
Definition: ad9250.h:230
#define AD9250_REG_FD_LOWER_THD
Definition: ad9250.h:96
int32_t ad9250_dcc_freeze(struct ad9250_dev *dev, int32_t freeze)
Freezes DC correction value.
Definition: ad9250.c:1275
#define AD9250_REG_204B_QUICK_CFG
Definition: ad9250.h:98
@ AD9250_SHD_REG_SYS_CTRL
Definition: ad9250.h:510
int32_t ad9250_transfer(struct ad9250_dev *dev)
Initiates a transfer and waits for the operation to end. Note: This function may be called after a sh...
Definition: ad9250.c:294
#define AD9250_SYS_CTRL_REALIGN_ON_SYNCINB
Definition: ad9250.h:196
#define AD9250_204B_PARAM_CS_N_NR_CTRL_BITS(x)
Definition: ad9250.h:234
#define AD9250_REG_204B_BID_CFG
Definition: ad9250.h:103
const int32_t shadow_regs[SHADOW_REGISTER_COUNT]
Definition: ad9250.c:51
Definition: ad9361_util.h:75
int32_t ad9250_jesd204b_setup(struct ad9250_dev *dev)
Configures the JESD204B interface.
Definition: ad9250.c:838
int32_t ad9250_reset_pn23(struct ad9250_dev *dev, int32_t rst)
Sets (1) or clears (0) the reset long PN sequence bit(PN23).
Definition: ad9250.c:685
int8_t en_ilas_test
Definition: ad9250.h:409
@ AD9250_SHD_REG_VREF
Definition: ad9250.h:509
#define AD9250_CLOCK_SELECTION(x)
Definition: ad9250.h:141
Fast Detect module configuration.
Definition: ad9250.h:463
int8_t pin_function
Definition: ad9250.h:475
#define AD9250_PLL_ENCODE(x)
Definition: ad9250.h:193
int32_t ad9250_jesd204b_select_test_injection_point(struct ad9250_dev *dev, int32_t inj_point)
Selects the point in the processing path of a lane, where the test data will be inserted.
Definition: ad9250.c:1062
int8_t en_sync_in_b
Definition: ad9250.h:427
#define AD9250_TEST_RST_PN_SHOR
Definition: ad9250.h:155
#define AD9250_REG_SPI_CFG
Definition: ad9250.h:66
int32_t ad9250_setup(struct ad9250_dev **device, struct ad9250_init_param init_param)
Configures the device.
Definition: ad9250.c:92
#define AD9250_SPI_CFG_SOFT_RST
Definition: ad9250.h:125
int8_t quick_cfg_option
Definition: ad9250.h:349
#define AD9250_FAST_DETECT_FORCE_FDA_FDB_VAL
Definition: ad9250.h:210
#define AD9250_DCC_CTRL_DCC_EN
Definition: ad9250.h:205
int32_t shadow_regs[SHADOW_REGISTER_COUNT]
Definition: ad9250.h:525
int32_t ad9250_output_format(struct ad9250_dev *dev, int32_t format)
Specifies the output format. Note: This function modifies a shadowed register, therefore a call of ad...
Definition: ad9250.c:621
int32_t ad9250_bist_enable(struct ad9250_dev *dev, int32_t enable)
Enables the Build-In-Self-Test.
Definition: ad9250.c:739
#define AD9250_DEVICE_UPDATE_SW
Definition: ad9250.h:132
@ AD9250_SHD_REG_DCC_VAL
Definition: ad9250.h:512
#define AD9250_OUT_MODE_DISABLE
Definition: ad9250.h:178
#define AD9250_REG_204B_PARAM_CS_N
Definition: ad9250.h:110
int32_t ad9250_jesd204b_pwr_mode(struct ad9250_dev *dev, int32_t mode)
Configures the power mode of the JESD204B data transmit block.
Definition: ad9250.c:1028
int32_t ad9250_dcc_freeze(struct ad9250_dev *dev, int32_t freeze)
Freezes DC correction value.
Definition: ad9250.c:1275
@ AD9250_SHD_REG_DCC_CTRL
Definition: ad9250.h:511
int8_t tail_bits_mode
Definition: ad9250.h:378
int32_t ad9250_setup(struct ad9250_dev **device, struct ad9250_init_param init_param)
Configures the device.
Definition: ad9250.c:92
#define AD9250_REG_FD_DWELL_TIME
Definition: ad9250.h:97
#define AD9250_REG_BIST
Definition: ad9250.h:80
@ AD9250_SHD_REG_CLOCK_DIV
Definition: ad9250.h:504
#define AD9250_204B_LANE_ASSGN1(x)
Definition: ad9250.h:249
#define AD9250_CLOCK_DIV_PHASE(x)
Definition: ad9250.h:149
@ SHADOW_REGISTER_COUNT
Definition: ad6673.h:520
#define AD9250_REG_204B_PARAM_SCR_L
Definition: ad9250.h:106
int32_t ad9250_jesd204b_invert_logic(struct ad9250_dev *dev, int32_t invert)
Inverts the logic of JESD204B bits.
Definition: ad9250.c:1135
#define AD9250_PDWN_JTX
Definition: ad9250.h:136
#define AD9250_SYS_CTRL_SYSREF_EN
Definition: ad9250.h:199
int32_t ad9250_test_mode(struct ad9250_dev *dev, int32_t mode)
Sets the ADC's test mode.
Definition: ad9250.c:491
struct ad9250_fast_detect_cfg * p_fd
Definition: ad9250.h:499
#define AD9250_REG_204B_CTRL2
Definition: ad9250.h:100
#define AD9250_REG_204B_LANE_ASSGN1
Definition: ad9250.h:118
#define AD9250_FAST_DETECT_FORCE_FDA_FDB_PIN
Definition: ad9250.h:209
#define AD9250_REG_PDWN
Definition: ad9250.h:75
#define AD9250_REG_SYS_CTRL
Definition: ad9250.h:91
int16_t fd_lower_tresh
Definition: ad9250.h:491
int32_t ad9250_reset_PN29(struct ad9250_dev *dev, int32_t rst)
int8_t subclass
Definition: ad9250.h:355
int8_t cml_level
Definition: ad9250.h:341
struct ad9250_state ad9250_st
Definition: ad9250.h:524
int8_t bid
Definition: ad9250.h:382
int32_t ad9250_reset_pn9(struct ad9250_dev *dev, int32_t rst)
Sets (1) or clears (0) the reset short PN sequence bit(PN9).
Definition: ad9250.c:653
int8_t jtx_in_standby
Definition: ad9250.h:332
#define AD9250_204B_CTRL1_POWER_DOWN
Definition: ad9250.h:220
Structure holding SPI descriptor.
Definition: no_os_spi.h:177
@ AD9250_SHD_REG_FD_UPPER_THD
Definition: ad9250.h:514
#define AD9250_204B_CTRL1_TAIL_BITS
Definition: ad9250.h:217
int32_t ad9250_jesd204b_invert_logic(struct ad9250_dev *dev, int32_t invert)
Inverts the logic of JESD204B bits.
Definition: ad9250.c:1135
#define AD9250_REG_OFFSET
Definition: ad9250.h:81
#define AD9250_SYS_CTRL_SYNCINB_EN
Definition: ad9250.h:200
int32_t ad9250_output_format(struct ad9250_dev *dev, int32_t format)
Specifies the output format. Note: This function modifies a shadowed register, therefore a call of ad...
Definition: ad9250.c:621
int8_t sys_ref_mode
Definition: ad9250.h:433
@ AD9250_SHD_REG_CLOCK
Definition: ad9250.h:503
int32_t ad9250_offset_adj(struct ad9250_dev *dev, int32_t adj)
Sets the offset adjustment.
Definition: ad9250.c:521
@ AD9250_SHD_REG_FD_DWELL_TIME
Definition: ad9250.h:516
#define AD9250_FAST_DETECT_PIN_FCT
Definition: ad9250.h:208
#define AD9250_REG_CLOCK
Definition: ad9250.h:76
int32_t ad9250_output_disable(struct ad9250_dev *dev, int32_t en)
Disables (1) or enables (0) the data output. Note: This function modifies a shadowed register,...
Definition: ad9250.c:551
JESD204B interface configuration.
Definition: ad9250.h:326
int8_t align_sys_ref
Definition: ad9250.h:445
#define AD9250_CLOCK_DIV_RATIO(x)
Definition: ad9250.h:150
#define AD9250_CML_DIFF_OUT_LEVEL(x)
Definition: ad9250.h:187
int32_t ad9250_write(struct ad9250_dev *dev, int32_t register_address, int32_t register_value)
Writes a value to the selected register.
Definition: ad9250.c:250
struct ad9250_jesd204b_cfg * p_jesd204b
Definition: ad9250.h:498
void * no_os_malloc(size_t size)
Allocate memory and return a pointer to it.
Definition: chibios_alloc.c:49
#define AD9250_VREF_FS_ADJUST(x)
Definition: ad9250.h:190
int32_t ad9250_read(struct ad9250_dev *dev, int32_t register_address)
Reads the value of the selected register.
Definition: ad9250.c:213
int32_t ad9250_dcc_enable(struct ad9250_dev *dev, int32_t enable)
Enables DC correction for use in the output data signal path.
Definition: ad9250.c:1209
int16_t fd_upper_tresh
Definition: ad9250.h:489
int8_t k
Definition: ad9250.h:391
#define AD9250_REG_OFFSET_ADJUST(x)
Definition: ad9250.h:174
int32_t ad9250_soft_reset(struct ad9250_dev *dev)
Resets all registers to their default values.
Definition: ad9250.c:326
int32_t ad9250_chip_pwr_mode(struct ad9250_dev *dev, int32_t mode)
Configures the power mode of the chip.
Definition: ad9250.c:418
#define AD9250_TRANSF_LEN(x)
Definition: ad9250.h:62
#define AD9250_204B_CTRL3_TEST_DATA_INJ_PT(x)
Definition: ad9250.h:226
void no_os_free(void *ptr)
Deallocate memory previously allocated by a call to no_os_calloc or no_os_malloc.
Definition: chibios_alloc.c:75
int32_t ad9250_select_channel_for_config(struct ad9250_dev *dev, int32_t channel)
Selects a channel as the current channel for further configurations.
Definition: ad9250.c:451
int32_t ad9250_dcc_enable(struct ad9250_dev *dev, int32_t enable)
Enables DC correction for use in the output data signal path.
Definition: ad9250.c:1209
int32_t ad9250_jesd204b_test_mode(struct ad9250_dev *dev, int32_t test_mode)
Selects a JESD204B test mode.
Definition: ad9250.c:1103
#define AD9250_DCC_CTRL_FREEZE_DCC
Definition: ad9250.h:203
int32_t ad9250_dcc_bandwidth(struct ad9250_dev *dev, int32_t bw)
Selects the bandwidth value for the DC correction circuit.
Definition: ad9250.c:1243
#define AD9250_ADDR(x)
Definition: ad9250.h:57
#define AD9250_CLOCK_DUTY_CYCLE
Definition: ad9250.h:142
struct ad9250_platform_data * pdata
Definition: ad9250.h:497
#define AD9250_DCC_CTRL_DCC_BW(x)
Definition: ad9250.h:204
struct no_os_spi_init_param spi_init
Definition: ad9250.h:530
int32_t ad9250_write(struct ad9250_dev *dev, int32_t register_address, int32_t register_value)
Writes a value to the selected register.
Definition: ad9250.c:250
@ AD9250_SHD_REG_FD_LOWER_THD
Definition: ad9250.h:515
int32_t ad9250_jesd204b_test_mode(struct ad9250_dev *dev, int32_t test_mode)
Selects a JESD204B test mode.
Definition: ad9250.c:1103
struct ad7616_init_param init_param
Definition: ad7616_sdz.c:119
#define AD9250_PDWN_JESD204B(x)
Definition: ad9250.h:137
#define AD9250_SYS_CTRL_REALIGN_ON_SYSREF
Definition: ad9250.h:197
int32_t ad9250_bist_reset(struct ad9250_dev *dev, int32_t reset)
Resets the Build-In-Self-Test.
Definition: ad9250.c:769
#define AD9250_204B_QUICK_CFG(x)
Definition: ad9250.h:214
#define AD9250_REG_204B_DID_CFG
Definition: ad9250.h:102
int8_t lid1
Definition: ad9250.h:386
#define AD9250_REG_FAST_DETECT
Definition: ad9250.h:94
@ AD9250_SHD_REG_OUT_MODE
Definition: ad9250.h:508
int32_t ad9250_read(struct ad9250_dev *dev, int32_t register_address)
Reads the value of the selected register.
Definition: ad9250.c:213
int8_t ctrl_bits_assign
Definition: ad9250.h:372
int8_t did
Definition: ad9250.h:380
int32_t ad9250_jesd204b_set_frames(struct ad9250_dev *dev, int32_t k_frames)
Sets number of frames per multiframe (K).
Definition: ad9250.c:801
#define AD9250_REG_204B_LANE_ASSGN2
Definition: ad9250.h:119
#define AD9250_TEST_RST_PN_LONG
Definition: ad9250.h:154
#define AD9250_READ
Definition: ad9250.h:54
#define AD9250_204B_CTRL3_JESD_TEST_MODE(x)
Definition: ad9250.h:227
int32_t ad9250_output_invert(struct ad9250_dev *dev, int32_t invert)
Activates the inverted (1) or normal (0) output mode. Note: This function modifies a shadowed registe...
Definition: ad9250.c:586
int32_t ad9250_bist_reset(struct ad9250_dev *dev, int32_t reset)
Resets the Build-In-Self-Test.
Definition: ad9250.c:769
int32_t no_os_spi_remove(struct no_os_spi_desc *desc)
Free the resources allocated by no_os_spi_init().
Definition: no_os_spi.c:122
struct no_os_spi_desc * spi_desc
Definition: ad9250.h:522
#define AD9250_REG_204B_CTRL1
Definition: ad9250.h:99
#define AD9250_OUT_MODE_INVERT_DATA
Definition: ad9250.h:179
int32_t ad9250_fast_detect_setup(struct ad9250_dev *dev)
Configures the Fast-Detect module.
Definition: ad9250.c:1164
int32_t ad9250_test_mode(struct ad9250_dev *dev, int32_t mode)
Sets the ADC's test mode.
Definition: ad9250.c:491
@ SHADOW_REGISTER_COUNT
Definition: ad9250.h:517
int8_t align_sync_in_b
Definition: ad9250.h:439
int32_t no_os_spi_init(struct no_os_spi_desc **desc, const struct no_os_spi_init_param *param)
Initialize the SPI communication peripheral.
Definition: no_os_spi.c:58
int8_t ctrl_bits_no
Definition: ad9250.h:362
#define AD9250_REG_OUT_MODE
Definition: ad9250.h:82
#define AD9250_REG_CLOCK_DIV
Definition: ad9250.h:78
int32_t ad9250_remove(struct ad9250_dev *dev)
Free the resources allocated by ad9250_setup().
Definition: ad9250.c:194
int32_t ad9250_chip_pwr_mode(struct ad9250_dev *dev, int32_t mode)
Configures the power mode of the chip.
Definition: ad9250.c:418
#define AD9250_REG_204B_PARAM_K
Definition: ad9250.h:108
int8_t ilas_mode
Definition: ad9250.h:403
#define AD9250_REG_DEVICE_UPDATE
Definition: ad9250.h:72
#define AD9250_REG_PLL_ENCODE
Definition: ad9250.h:89
#define AD9250_TEST_OUTPUT_TEST(x)
Definition: ad9250.h:156
struct ad9250_state ad9250_st_init
Definition: ad9250.h:532
#define AD9250_REG_204B_CTRL3
Definition: ad9250.h:101
int32_t ad9250_remove(struct ad9250_dev *dev)
Free the resources allocated by ad9250_setup().
Definition: ad9250.c:194
#define AD9250_PDWN_CHIP(x)
Definition: ad9250.h:138
#define AD9250_CH_INDEX_ADC_A
Definition: ad9250.h:128
#define AD9250_OUT_MODE_DATA_FORMAT(x)
Definition: ad9250.h:180
#define AD9250_WRITE
Definition: ad9250.h:55
#define AD9250_REG_FD_UPPER_THD
Definition: ad9250.h:95
int8_t scrambling
Definition: ad9250.h:397
int32_t ad9250_fast_detect_setup(struct ad9250_dev *dev)
Configures the Fast-Detect module.
Definition: ad9250.c:1164
#define AD9250_204B_CTRL1_TEST_SAMPLE_EN
Definition: ad9250.h:218
int32_t ad9250_offset_adj(struct ad9250_dev *dev, int32_t adj)
Sets the offset adjustment.
Definition: ad9250.c:521
int8_t force_pins
Definition: ad9250.h:481
int32_t ad9250_transfer(struct ad9250_dev *dev)
Initiates a transfer and waits for the operation to end. Note: This function may be called after a sh...
Definition: ad9250.c:294
#define AD9250_204B_PARAM_NP_JESD_SUBCLASS(x)
Definition: ad9250.h:238
#define AD9250_REG_CH_INDEX
Definition: ad9250.h:71
Structure holding the parameters for SPI initialization.
Definition: no_os_spi.h:131
#define AD9250_FAST_DETECT_OUTPUT_ENABLE
Definition: ad9250.h:211
int8_t lid0
Definition: ad9250.h:384
#define AD9250_SYS_CTRL_SYSREF_MODE
Definition: ad9250.h:198