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no-OS
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JESD204B interface configuration. More...
#include <ad9250.h>
Public Attributes | |
| int8_t | jtx_in_standby |
| int8_t | cml_level |
| int8_t | quick_cfg_option |
| int8_t | subclass |
| int8_t | ctrl_bits_no |
| int8_t | ctrl_bits_assign |
| int8_t | tail_bits_mode |
| int8_t | did |
| int8_t | bid |
| int8_t | lid0 |
| int8_t | lid1 |
| int8_t | k |
| int8_t | scrambling |
| int8_t | ilas_mode |
| int8_t | en_ilas_test |
| int8_t | invert_logic_bits |
| int8_t | en_sys_ref |
| int8_t | en_sync_in_b |
| int8_t | sys_ref_mode |
| int8_t | align_sync_in_b |
| int8_t | align_sys_ref |
| int8_t | lane0_assign |
| int8_t | lane1_assign |
JESD204B interface configuration.
| int8_t ad9250_jesd204b_cfg::align_sync_in_b |
Options for interpreting single on SYNCINB+-. 0 = normal mode 1 = realign lanes on every active SYNCINB+-
| int8_t ad9250_jesd204b_cfg::align_sys_ref |
Options for interpreting single on SYSREF+-. 0 = normal mode; 1 = realign lanes on every active SYSREF+-
| int8_t ad9250_jesd204b_cfg::bid |
JESD204B bank identification value : BID[3:0]
| int8_t ad9250_jesd204b_cfg::cml_level |
JESD204B CML differential output drive level adjustment. 0 = 81% of nominal (that is, 238 mV) 1 = 89% of nominal (that is, 262 mV) 2 = 98% of nominal (that is, 286 mV) 3 = nominal [default] (that is, 293 mV) 6 = 126% of nominal (that is, 368 mV)
| int8_t ad9250_jesd204b_cfg::ctrl_bits_assign |
JTX CS bits assignment. 0 = {overrange||underrange, valid} 1 = {overrange||underrange} 2 = {overrange||underrange, blank} 3 = {blank, valid} 4 = {blank, blank} All others = {overrange||underrange, valid}
| int8_t ad9250_jesd204b_cfg::ctrl_bits_no |
Number of control bits (CS). 0 = no control bits(CS = 0) 1 = 1 control bit (CS = 1) 2 = 2 control bits (CS = 2)
| int8_t ad9250_jesd204b_cfg::did |
JESD204B device identification value: DID[7:0]
| int8_t ad9250_jesd204b_cfg::en_ilas_test |
JESD204B test sample. 0 = disabled 1 = enabled
| int8_t ad9250_jesd204b_cfg::en_sync_in_b |
Enable SYNCINB+- buffer. 0 = buffer disabled 1 = buffer enabled
| int8_t ad9250_jesd204b_cfg::en_sys_ref |
SYSREF+- enable. 0 = disabled 1 = enabled
| int8_t ad9250_jesd204b_cfg::ilas_mode |
Initial lane alignment sequence (ILAS) mode. 1 = ILAS normal mode enabled 3 = ILAS always on, test mode
| int8_t ad9250_jesd204b_cfg::invert_logic_bits |
Invert logic of JESD204B bits. 0 = non-invert 1 = invert
| int8_t ad9250_jesd204b_cfg::jtx_in_standby |
JTX in standby. 0 = 204B core is unaffected in standby 1 = 204B core is powered down except for PLL during standby
| int8_t ad9250_jesd204b_cfg::k |
JESD204B number of frames per multiframe (K); set value of K per JESD204B specifications, but also must be a multiple of 4 octets.
| int8_t ad9250_jesd204b_cfg::lane0_assign |
Option to remap converter and lane assignments. 0 = assign Logical Lane 0 to Physical Lane A [default] 1 = assign Logical Lane 0 to Physical Lane B
| int8_t ad9250_jesd204b_cfg::lane1_assign |
| int8_t ad9250_jesd204b_cfg::lid0 |
JESD204B lane0 identification value: LID[4:0]
| int8_t ad9250_jesd204b_cfg::lid1 |
JESD204B lane1 identification value: LID[4:0]
| int8_t ad9250_jesd204b_cfg::quick_cfg_option |
Quick configuration register. 0x11 = M = 1, L = 1; one converter, one lane 0x12 = M = 1, L = 2; one converter, two lanes 0x21 = M = 2, L = 1; two converters, one lane 0x22 = M = 2, L = 2; two converters, two lanes
| int8_t ad9250_jesd204b_cfg::scrambling |
JESD204B scrambling (SCR). 0 = disabled 1 = enabled
| int8_t ad9250_jesd204b_cfg::subclass |
JESD204B subclass. 0 = Subclass 0 1 = Subclass 1
| int8_t ad9250_jesd204b_cfg::sys_ref_mode |
SYSREF+- mode. 0 = continuous reset clock dividers 1 = sync on next SYSREF+- rising edge only
| int8_t ad9250_jesd204b_cfg::tail_bits_mode |
Tail bits: If CS bits are not enabled. 0 = extra bits are 0 1 = extra bits are 9-bit PN
1.8.17