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ade9078.h
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1 /***************************************************************************/
33 #ifndef __ADE9078_H__
34 #define __ADE9078_H__
35 
36 /******************************************************************************/
37 /***************************** Include Files **********************************/
38 /******************************************************************************/
39 #include <stdbool.h>
40 #include <stdint.h>
41 #include <string.h>
42 #include "no_os_util.h"
43 #include "no_os_spi.h"
44 #include "no_os_gpio.h"
45 #include "no_os_print_log.h"
46 
47 /******************************************************************************/
48 /********************** Macros and Constants Definitions **********************/
49 /******************************************************************************/
50 
51 /* SPI commands */
52 #define ADE9078_SPI_READ NO_OS_BIT(3)
53 
54 #define ENABLE 0x0001
55 #define DISABLE 0x0000
56 
57 /* ADE9078 Register Map */
58 #define ADE9078_REG_AIGAIN 0x0000
59 #define ADE9078_REG_AIGAIN0 0x0001
60 #define ADE9078_REG_AIGAIN1 0x0002
61 #define ADE9078_REG_AIGAIN2 0x0003
62 #define ADE9078_REG_AIGAIN3 0x0004
63 #define ADE9078_REG_AIGAIN4 0x0005
64 #define ADE9078_REG_APHCAL0 0x0006
65 #define ADE9078_REG_APHCAL1 0x0007
66 #define ADE9078_REG_APHCAL2 0x0008
67 #define ADE9078_REG_APHCAL3 0x0009
68 #define ADE9078_REG_APHCAL4 0x000A
69 #define ADE9078_REG_AVGAIN 0x000B
70 #define ADE9078_REG_AIRMSOS 0x000C
71 #define ADE9078_REG_AVRMSOS 0x000D
72 #define ADE9078_REG_APGAIN 0x000E
73 #define ADE9078_REG_AWATTOS 0x000F
74 #define ADE9078_REG_AVAROS 0x0010
75 #define ADE9078_REG_AFVAROS 0x0012
76 #define ADE9078_REG_BIGAIN 0x0020
77 #define ADE9078_REG_BIGAIN0 0x0021
78 #define ADE9078_REG_BIGAIN1 0x0022
79 #define ADE9078_REG_BIGAIN2 0x0023
80 #define ADE9078_REG_BIGAIN3 0x0024
81 #define ADE9078_REG_BIGAIN4 0x0025
82 #define ADE9078_REG_BPHCAL0 0x0026
83 #define ADE9078_REG_BPHCAL1 0x0027
84 #define ADE9078_REG_BPHCAL2 0x0028
85 #define ADE9078_REG_BPHCAL3 0x0029
86 #define ADE9078_REG_BPHCAL4 0x002A
87 #define ADE9078_REG_BVGAIN 0x002B
88 #define ADE9078_REG_BIRMSOS 0x002C
89 #define ADE9078_REG_BVRMSOS 0x002D
90 #define ADE9078_REG_BPGAIN 0x002E
91 #define ADE9078_REG_BWATTOS 0x002F
92 #define ADE9078_REG_BVAROS 0x0030
93 #define ADE9078_REG_BFVAROS 0x0032
94 #define ADE9078_REG_CIGAIN 0x0040
95 #define ADE9078_REG_CIGAIN0 0x0041
96 #define ADE9078_REG_CIGAIN1 0x0042
97 #define ADE9078_REG_CIGAIN2 0x0043
98 #define ADE9078_REG_CIGAIN3 0x0044
99 #define ADE9078_REG_CIGAIN4 0x0045
100 #define ADE9078_REG_CPHCAL0 0x0046
101 #define ADE9078_REG_CPHCAL1 0x0047
102 #define ADE9078_REG_CPHCAL2 0x0048
103 #define ADE9078_REG_CPHCAL3 0x0049
104 #define ADE9078_REG_CPHCAL4 0x004A
105 #define ADE9078_REG_CVGAIN 0x004B
106 #define ADE9078_REG_CIRMSOS 0x004C
107 #define ADE9078_REG_CVRMSOS 0x004D
108 #define ADE9078_REG_CPGAIN 0x004E
109 #define ADE9078_REG_CWATTOS 0x004F
110 #define ADE9078_REG_CVAROS 0x0050
111 #define ADE9078_REG_CFVAROS 0x0052
112 #define ADE9078_REG_CONFIG0 0x0060
113 #define ADE9078_REG_MTTHR_L0 0x0061
114 #define ADE9078_REG_MTTHR_L1 0x0062
115 #define ADE9078_REG_MTTHR_L2 0x0063
116 #define ADE9078_REG_MTTHR_L3 0x0064
117 #define ADE9078_REG_MTTHR_L4 0x0065
118 #define ADE9078_REG_MTTHR_H0 0x0066
119 #define ADE9078_REG_MTTHR_H1 0x0067
120 #define ADE9078_REG_MTTHR_H2 0x0068
121 #define ADE9078_REG_MTTHR_H3 0x0069
122 #define ADE9078_REG_MTTHR_H4 0x006A
123 #define ADE9078_REG_NIRMSOS 0x006B
124 #define ADE9078_REG_ISUMRMSOS 0x006C
125 #define ADE9078_REG_NIGAIN 0x006D
126 #define ADE9078_REG_NPHCAL 0x006E
127 #define ADE9078_REG_VNOM 0x0071
128 #define ADE9078_REG_DICOEFF 0x0072
129 #define ADE9078_REG_ISUMLVL 0x0073
130 #define ADE9078_REG_AI_PCF 0x020A
131 #define ADE9078_REG_AV_PCF 0x020B
132 #define ADE9078_REG_AIRMS 0x020C
133 #define ADE9078_REG_AVRMS 0x020D
134 #define ADE9078_REG_AWATT 0x0210
135 #define ADE9078_REG_AVAR 0x0211
136 #define ADE9078_REG_AVA 0x0212
137 #define ADE9078_REG_AFVAR 0x0214
138 #define ADE9078_REG_APF 0x0216
139 #define ADE9078_REG_AMTREGION 0x021D
140 #define ADE9078_REG_BI_PCF 0x022A
141 #define ADE9078_REG_BV_PCF 0x022B
142 #define ADE9078_REG_BIRMS 0x022C
143 #define ADE9078_REG_BVRMS 0x022D
144 #define ADE9078_REG_BWATT 0x0230
145 #define ADE9078_REG_BVAR 0x0231
146 #define ADE9078_REG_BVA 0x0232
147 #define ADE9078_REG_BFVAR 0x0234
148 #define ADE9078_REG_BPF 0x0236
149 #define ADE9078_REG_BMTREGION 0x023D
150 #define ADE9078_REG_CI_PCF 0x024A
151 #define ADE9078_REG_CV_PCF 0x024B
152 #define ADE9078_REG_CIRMS 0x024C
153 #define ADE9078_REG_CVRMS 0x024D
154 #define ADE9078_REG_CWATT 0x0250
155 #define ADE9078_REG_CVAR 0x0251
156 #define ADE9078_REG_CVA 0x0252
157 #define ADE9078_REG_CFVAR 0x0254
158 #define ADE9078_REG_CPF 0x0256
159 #define ADE9078_REG_CMTREGION 0x025D
160 #define ADE9078_REG_NI_PCF 0x0265
161 #define ADE9078_REG_NIRMS 0x0266
162 #define ADE9078_REG_ISUMRMS 0x0269
163 #define ADE9078_REG_VERSION2 0x026A
164 #define ADE9078_REG_AWATT_ACC 0x02E5
165 #define ADE9078_REG_AWATTHR_LO 0x02E6
166 #define ADE9078_REG_AWATTHR_HI 0x02E7
167 #define ADE9078_REG_AVAR_ACC 0x02EF
168 #define ADE9078_REG_AVARHR_LO 0x02F0
169 #define ADE9078_REG_AVARHR_HI 0x02F1
170 #define ADE9078_REG_AVA_ACC 0x02F9
171 #define ADE9078_REG_AVAHR_LO 0x02FA
172 #define ADE9078_REG_AVAHR_HI 0x02FB
173 #define ADE9078_REG_AFVAR_ACC 0x030D
174 #define ADE9078_REG_AFVARHR_LO 0x030E
175 #define ADE9078_REG_AFVARHR_HI 0x030F
176 #define ADE9078_REG_BWATT_ACC 0x0321
177 #define ADE9078_REG_BWATTHR_LO 0x0322
178 #define ADE9078_REG_BWATTHR_HI 0x0323
179 #define ADE9078_REG_BVAR_ACC 0x032B
180 #define ADE9078_REG_BVARHR_LO 0x032C
181 #define ADE9078_REG_BVARHR_HI 0x032D
182 #define ADE9078_REG_BVA_ACC 0x0335
183 #define ADE9078_REG_BVAHR_LO 0x0336
184 #define ADE9078_REG_BVAHR_HI 0x0337
185 #define ADE9078_REG_BFVAR_ACC 0x0349
186 #define ADE9078_REG_BFVARHR_LO 0x034A
187 #define ADE9078_REG_BFVARHR_HI 0x034B
188 #define ADE9078_REG_CWATT_ACC 0x035D
189 #define ADE9078_REG_CWATTHR_LO 0x035E
190 #define ADE9078_REG_CWATTHR_HI 0x035F
191 #define ADE9078_REG_CVAR_ACC 0x0367
192 #define ADE9078_REG_CVARHR_LO 0x0368
193 #define ADE9078_REG_CVARHR_HI 0x0369
194 #define ADE9078_REG_CVA_ACC 0x0371
195 #define ADE9078_REG_CVAHR_LO 0x0372
196 #define ADE9078_REG_CVAHR_HI 0x0373
197 #define ADE9078_REG_CFVAR_ACC 0x0385
198 #define ADE9078_REG_CFVARHR_LO 0x0386
199 #define ADE9078_REG_CFVARHR_HI 0x0387
200 #define ADE9078_REG_PWATT_ACC 0x0397
201 #define ADE9078_REG_NWATT_ACC 0x039B
202 #define ADE9078_REG_PVAR_ACC 0x039F
203 #define ADE9078_REG_NVAR_ACC 0x03A3
204 #define ADE9078_REG_IPEAK 0x0400
205 #define ADE9078_REG_VPEAK 0x0401
206 #define ADE9078_REG_STATUS0 0x0402
207 #define ADE9078_REG_STATUS1 0x0403
208 #define ADE9078_REG_EVENT_STATUS 0x0404
209 #define ADE9078_REG_MASK0 0x0405
210 #define ADE9078_REG_MASK1 0x0406
211 #define ADE9078_REG_EVENT_MASK 0x0407
212 #define ADE9078_REG_USER_PERIOD 0x040E
213 #define ADE9078_REG_VLEVEL 0x040F
214 #define ADE9078_REG_APERIOD 0x0418
215 #define ADE9078_REG_BPERIOD 0x0419
216 #define ADE9078_REG_CPERIOD 0x041A
217 #define ADE9078_REG_COM_PERIOD 0x041B
218 #define ADE9078_REG_ACT_NL_LVL 0x041C
219 #define ADE9078_REG_REACT_NL_LVL 0x041D
220 #define ADE9078_REG_APP_NL_LVL 0x041E
221 #define ADE9078_REG_PHNOLOAD 0x041F
222 #define ADE9078_REG_WTHR 0x0420
223 #define ADE9078_REG_VARTHR 0x0421
224 #define ADE9078_REG_VATHR 0x0422
225 #define ADE9078_REG_LAST_DATA_32 0x0423
226 #define ADE9078_REG_ADC_REDIRECT 0x0424
227 #define ADE9078_REG_CF_LCFG 0x0425
228 #define ADE9078_REG_PART_ID 0x0472
229 #define ADE9078_REG_RUN 0x0480
230 #define ADE9078_REG_CONFIG1 0x0481
231 #define ADE9078_REG_ANGL_VA_VB 0x0482
232 #define ADE9078_REG_ANGL_VB_VC 0x0483
233 #define ADE9078_REG_ANGL_VA_VC 0x0484
234 #define ADE9078_REG_ANGL_VA_IA 0x0485
235 #define ADE9078_REG_ANGL_VB_IB 0x0486
236 #define ADE9078_REG_ANGL_VC_IC 0x0487
237 #define ADE9078_REG_ANGL_IA_IB 0x0488
238 #define ADE9078_REG_ANGL_IB_IC 0x0489
239 #define ADE9078_REG_ANGL_IA_IC 0x048A
240 #define ADE9078_REG_CFMODE 0x0490
241 #define ADE9078_REG_COMPMODE 0x0491
242 #define ADE9078_REG_ACCMODE 0x0492
243 #define ADE9078_REG_CONFIG3 0x0493
244 #define ADE9078_REG_CF1DEN 0x0494
245 #define ADE9078_REG_CF2DEN 0x0495
246 #define ADE9078_REG_CF3DEN 0x0496
247 #define ADE9078_REG_CF4DEN 0x0497
248 #define ADE9078_REG_ZXTOUT 0x0498
249 #define ADE9078_REG_ZXTHRSH 0x0499
250 #define ADE9078_REG_ZX_LP_SEL 0x049A
251 #define ADE9078_REG_SEQ_CYC 0x049C
252 #define ADE9078_REG_PHSIGN 0x049D
253 #define ADE9078_REG_WFB_CFG 0x04A0
254 #define ADE9078_REG_WFB_PG_IRQEN 0x04A1
255 #define ADE9078_REG_WFB_TRG_CFG 0x04A2
256 #define ADE9078_REG_WFB_TRG_STAT 0x04A3
257 #define ADE9078_REG_CONFIG5 0x04A4
258 #define ADE9078_REG_CRC_RSLT 0x04A8
259 #define ADE9078_REG_CRC_SPI 0x04A9
260 #define ADE9078_REG_LAST_DATA_16 0x04AC
261 #define ADE9078_REG_LAST_CMD 0x04AE
262 #define ADE9078_REG_CONFIG2 0x04AF
263 #define ADE9078_REG_EP_CFG 0x04B0
264 #define ADE9078_REG_PWR_TIME 0x04B1
265 #define ADE9078_REG_EGY_TIME 0x04B2
266 #define ADE9078_REG_CRC_FORCE 0x04B4
267 #define ADE9078_REG_CRC_OPTEN 0x04B5
268 #define ADE9078_REG_TEMP_CFG 0x04B6
269 #define ADE9078_REG_PSM2_CFG 0x04B8
270 #define ADE9078_REG_PGA_GAIN 0x04B9
271 #define ADE9078_REG_CHNL_DIS 0x04BA
272 #define ADE9078_REG_WR_LOCK 0x04BF
273 #define ADE9078_REG_VAR_DIS 0x04E0
274 #define ADE9078_REG_RESERVED1 0x04F0
275 #define ADE9078_REG_VERSION 0x04FE
276 #define ADE9078_REG_AI_SINC_DAT 0x0500
277 #define ADE9078_REG_AV_SINC_DAT 0x0501
278 #define ADE9078_REG_BI_SINC_DAT 0x0502
279 #define ADE9078_REG_BV_SINC_DAT 0x0503
280 #define ADE9078_REG_CI_SINC_DAT 0x0504
281 #define ADE9078_REG_CV_SINC_DAT 0x0505
282 #define ADE9078_REG_NI_SINC_DAT 0x0506
283 #define ADE9078_REG_AI_LPF_DAT 0x0510
284 #define ADE9078_REG_AV_LPF_DAT 0x0511
285 #define ADE9078_REG_BI_LPF_DAT 0x0512
286 #define ADE9078_REG_BV_LPF_DAT 0x0513
287 #define ADE9078_REG_CI_LPF_DAT 0x0514
288 #define ADE9078_REG_CV_LPF_DAT 0x0515
289 #define ADE9078_REG_NI_LPF_DAT 0x0516
290 #define ADE9078_REG_AV_PCF_1 0x0600
291 #define ADE9078_REG_BV_PCF_1 0x0601
292 #define ADE9078_REG_CV_PCF_1 0x0602
293 #define ADE9078_REG_NI_PCF_1 0x0603
294 #define ADE9078_REG_AI_PCF_1 0x0604
295 #define ADE9078_REG_BI_PCF_1 0x0605
296 #define ADE9078_REG_CI_PCF_1 0x0606
297 #define ADE9078_REG_AIRMS_1 0x0607
298 #define ADE9078_REG_BIRMS_1 0x0608
299 #define ADE9078_REG_CIRMS_1 0x0609
300 #define ADE9078_REG_AVRMS_1 0x060A
301 #define ADE9078_REG_BVRMS_1 0x060B
302 #define ADE9078_REG_CVRMS_1 0x060C
303 #define ADE9078_REG_NIRMS_1 0x060D
304 #define ADE9078_REG_AWATT_1 0x060E
305 #define ADE9078_REG_BWATT_1 0x060F
306 #define ADE9078_REG_CWATT_1 0x0610
307 #define ADE9078_REG_AVA_1 0x0611
308 #define ADE9078_REG_BVA_1 0x0612
309 #define ADE9078_REG_CVA_1 0x0613
310 #define ADE9078_REG_AVAR_1 0x0614
311 #define ADE9078_REG_BVAR_1 0x0615
312 #define ADE9078_REG_CVAR_1 0x0616
313 #define ADE9078_REG_AFVAR_1 0x0617
314 #define ADE9078_REG_BFVAR_1 0x0618
315 #define ADE9078_REG_CFVAR_1 0x0619
316 #define ADE9078_REG_APF_1 0x061A
317 #define ADE9078_REG_BPF_1 0x061B
318 #define ADE9078_REG_CPF_1 0x061C
319 #define ADE9078_REG_AV_PCF_2 0x0680
320 #define ADE9078_REG_AI_PCF_2 0x0681
321 #define ADE9078_REG_AIRMS_2 0x0682
322 #define ADE9078_REG_AVRMS_2 0x0683
323 #define ADE9078_REG_AWATT_2 0x0684
324 #define ADE9078_REG_AVA_2 0x0685
325 #define ADE9078_REG_AVAR_2 0x0686
326 #define ADE9078_REG_AFVAR_2 0x0687
327 #define ADE9078_REG_APF_2 0x0688
328 #define ADE9078_REG_BV_PCF_2 0x0693
329 #define ADE9078_REG_BI_PCF_2 0x0694
330 #define ADE9078_REG_BIRMS_2 0x0695
331 #define ADE9078_REG_BVRMS_2 0x0696
332 #define ADE9078_REG_BWATT_2 0x0697
333 #define ADE9078_REG_BVA_2 0x0698
334 #define ADE9078_REG_BVAR_2 0x0699
335 #define ADE9078_REG_BFVAR_2 0x069A
336 #define ADE9078_REG_BPF_2 0x069B
337 #define ADE9078_REG_CV_PCF_2 0x06A6
338 #define ADE9078_REG_CI_PCF_2 0x06A7
339 #define ADE9078_REG_CIRMS_2 0x06A8
340 #define ADE9078_REG_CVRMS_2 0x06A9
341 #define ADE9078_REG_CWATT_2 0x06AA
342 #define ADE9078_REG_CVA_2 0x06AB
343 #define ADE9078_REG_CVAR_2 0x06AC
344 #define ADE9078_REG_CFVAR_2 0x06AD
345 #define ADE9078_REG_CPF_2 0x06AE
346 #define ADE9078_REG_NI_PCF_2 0x06B9
347 #define ADE9078_REG_NIRMS_2 0x06BA
348 
349 /* ADE9078_REG_CONFIG0 Bit Definition */
350 #define ADE9078_DISRPLPF NO_OS_BIT(13)
351 #define ADE9078_DISAPLPF NO_OS_BIT(12)
352 #define ADE9078_ININTEN NO_OS_BIT(11)
353 #define ADE9078_VNOMC_EN NO_OS_BIT(10)
354 #define ADE9078_VNOMB_EN NO_OS_BIT(9)
355 #define ADE9078_VNOMA_EN NO_OS_BIT(8)
356 #define ADE9078_ZX_SRC_SEL NO_OS_BIT(6)
357 #define ADE9078_INTEN NO_OS_BIT(5)
358 #define ADE9078_MTEN NO_OS_BIT(4)
359 #define ADE9078_HPFDIS NO_OS_BIT(3)
360 #define ADE9078_ISUM_CFG NO_OS_GENMASK(1, 0)
361 
362 /* ADE9078_REG_AMTREGION Bit Definition */
363 #define ADE9078_AREGION NO_OS_GENMASK(3, 0)
364 
365 /* ADE9078_REG_BMTREGION Bit Definition */
366 #define ADE9078_BREGION NO_OS_GENMASK(3, 0)
367 
368 /* ADE9078_REG_CMTREGION Bit Definition */
369 #define ADE9078_CREGION NO_OS_GENMASK(3, 0)
370 
371 /* ADE9078_REG_IPEAK Bit Definition */
372 #define ADE9078_IPPHASE NO_OS_GENMASK(26, 24)
373 #define ADE9078_IPEAKVAL NO_OS_GENMASK(23, 0)
374 
375 /* ADE9078_REG_VPEAK Bit Definition */
376 #define ADE9078_VPPHASE NO_OS_GENMASK(26, 24)
377 #define ADE9078_VPEAKVAL NO_OS_GENMASK(23, 0)
378 
379 /* ADE9078_REG_STATUS0 Bit Definition */
380 #define ADE9078_STATUS0_MISMTCH NO_OS_BIT(24)
381 #define ADE9078_STATUS0_COH_WFB_FULL NO_OS_BIT(23)
382 #define ADE9078_STATUS0_WFB_TRIG NO_OS_BIT(22)
383 #define ADE9078_STATUS0_PF_RDY NO_OS_BIT(21)
384 #define ADE9078_STATUS0_PWRRDY NO_OS_BIT(18)
385 #define ADE9078_STATUS0_PAGE_FULL NO_OS_BIT(17)
386 #define ADE9078_STATUS0_WFB_TRIG_IRQ NO_OS_BIT(16)
387 #define ADE9078_STATUS0_DREADY NO_OS_BIT(15)
388 #define ADE9078_STATUS0_CF4 NO_OS_BIT(14)
389 #define ADE9078_STATUS0_CF3 NO_OS_BIT(13)
390 #define ADE9078_STATUS0_CF2 NO_OS_BIT(12)
391 #define ADE9078_STATUS0_CF1 NO_OS_BIT(11)
392 #define ADE9078_STATUS0_REVPSUM4 NO_OS_BIT(10)
393 #define ADE9078_STATUS0_REVPSUM3 NO_OS_BIT(9)
394 #define ADE9078_STATUS0_REVPSUM2 NO_OS_BIT(8)
395 #define ADE9078_STATUS0_REVPSUM1 NO_OS_BIT(7)
396 #define ADE9078_STATUS0_REVRPC NO_OS_BIT(6)
397 #define ADE9078_STATUS0_REVRPB NO_OS_BIT(5)
398 #define ADE9078_STATUS0_REVRPA NO_OS_BIT(4)
399 #define ADE9078_STATUS0_REVAPC NO_OS_BIT(3)
400 #define ADE9078_STATUS0_REVAPB NO_OS_BIT(2)
401 #define ADE9078_STATUS0_REVAPA NO_OS_BIT(1)
402 #define ADE9078_STATUS0_EGYRDY NO_OS_BIT(0)
403 
404 /* ADE9078_REG_STATUS1 Bit Definition */
405 #define ADE9078_STATUS1_ERROR3 NO_OS_BIT(31)
406 #define ADE9078_STATUS1_ERROR2 NO_OS_BIT(30)
407 #define ADE9078_STATUS1_ERROR1 NO_OS_BIT(29)
408 #define ADE9078_STATUS1_ERROR0 NO_OS_BIT(28)
409 #define ADE9078_STATUS1_CRC_DONE NO_OS_BIT(27)
410 #define ADE9078_STATUS1_CRC_CHG NO_OS_BIT(26)
411 #define ADE9078_STATUS1_SEQERR NO_OS_BIT(18)
412 #define ADE9078_STATUS1_RSTDONE NO_OS_BIT(16)
413 #define ADE9078_STATUS1_ZXIC NO_OS_BIT(15)
414 #define ADE9078_STATUS1_ZXIB NO_OS_BIT(14)
415 #define ADE9078_STATUS1_ZXIA NO_OS_BIT(13)
416 #define ADE9078_STATUS1_ZXCOMB NO_OS_BIT(12)
417 #define ADE9078_STATUS1_ZXVC NO_OS_BIT(11)
418 #define ADE9078_STATUS1_ZXVB NO_OS_BIT(10)
419 #define ADE9078_STATUS1_ZXVA NO_OS_BIT(9)
420 #define ADE9078_STATUS1_ZXTOVC NO_OS_BIT(8)
421 #define ADE9078_STATUS1_ZXTOVB NO_OS_BIT(7)
422 #define ADE9078_STATUS1_ZXTOVA NO_OS_BIT(6)
423 #define ADE9078_STATUS1_RFNOLOAD NO_OS_BIT(4)
424 #define ADE9078_STATUS1_VANLOAD NO_OS_BIT(2)
425 #define ADE9078_STATUS1_RNLOAD NO_OS_BIT(1)
426 #define ADE9078_STATUS1_ANLOAD NO_OS_BIT(0)
427 
428 /* ADE9078_REG_EVENT_STATUS Bit Definition */
429 #define ADE9078_EVENT_DREADY NO_OS_BIT(16)
430 #define ADE9078_EVENT_RFNOLOAD NO_OS_BIT(14)
431 #define ADE9078_EVENT_VANLOAD NO_OS_BIT(12)
432 #define ADE9078_EVENT_RNLOAD NO_OS_BIT(11)
433 #define ADE9078_EVENT_ANLOAD NO_OS_BIT(10)
434 #define ADE9078_EVENT_REVPSUM4 NO_OS_BIT(9)
435 #define ADE9078_EVENT_REVPSUM3 NO_OS_BIT(8)
436 #define ADE9078_EVENT_REVPSUM2 NO_OS_BIT(7)
437 #define ADE9078_EVENT_REVPSUM1 NO_OS_BIT(6)
438 
439 /* ADE9078_REG_MASK0 Bit Definition */
440 #define ADE9078_MASK0_MISMTCH NO_OS_BIT(24)
441 #define ADE9078_MASK0_COH_WFB_FULL NO_OS_BIT(23)
442 #define ADE9078_MASK0_WFB_TRIG NO_OS_BIT(22)
443 #define ADE9078_MASK0_THD_PF_RDY NO_OS_BIT(21)
444 #define ADE9078_MASK0_PWRRDY NO_OS_BIT(18)
445 #define ADE9078_MASK0_PAGE_FULL NO_OS_BIT(17)
446 #define ADE9078_MASK0_WFB_TRIG_IRQ NO_OS_BIT(16)
447 #define ADE9078_MASK0_DREADY NO_OS_BIT(15)
448 #define ADE9078_MASK0_CF4 NO_OS_BIT(14)
449 #define ADE9078_MASK0_CF3 NO_OS_BIT(13)
450 #define ADE9078_MASK0_CF2 NO_OS_BIT(12)
451 #define ADE9078_MASK0_CF1 NO_OS_BIT(11)
452 #define ADE9078_MASK0_REVPSUM4 NO_OS_BIT(10)
453 #define ADE9078_MASK0_REVPSUM3 NO_OS_BIT(9)
454 #define ADE9078_MASK0_REVPSUM2 NO_OS_BIT(8)
455 #define ADE9078_MASK0_REVPSUM1 NO_OS_BIT(7)
456 #define ADE9078_MASK0_REVRPC NO_OS_BIT(6)
457 #define ADE9078_MASK0_REVRPB NO_OS_BIT(5)
458 #define ADE9078_MASK0_REVRPA NO_OS_BIT(4)
459 #define ADE9078_MASK0_REVAPC NO_OS_BIT(3)
460 #define ADE9078_MASK0_REVAPB NO_OS_BIT(2)
461 #define ADE9078_MASK0_REVAPA NO_OS_BIT(1)
462 #define ADE9078_MASK0_EGYRDY NO_OS_BIT(0)
463 
464 /* ADE9078_REG_MASK1 Bit Definition */
465 #define ADE9078_MASK1_ERROR3 NO_OS_BIT(31)
466 #define ADE9078_MASK1_ERROR2 NO_OS_BIT(30)
467 #define ADE9078_MASK1_ERROR1 NO_OS_BIT(29)
468 #define ADE9078_MASK1_ERROR0 NO_OS_BIT(28)
469 #define ADE9078_MASK1_CRC_DONE NO_OS_BIT(27)
470 #define ADE9078_MASK1_CRC_CHG NO_OS_BIT(26)
471 #define ADE9078_MASK1_SEQERR NO_OS_BIT(18)
472 #define ADE9078_MASK1_ZXIC NO_OS_BIT(15)
473 #define ADE9078_MASK1_ZXIB NO_OS_BIT(14)
474 #define ADE9078_MASK1_ZXIA NO_OS_BIT(13)
475 #define ADE9078_MASK1_ZXCOMB NO_OS_BIT(12)
476 #define ADE9078_MASK1_ZXVC NO_OS_BIT(11)
477 #define ADE9078_MASK1_ZXVB NO_OS_BIT(10)
478 #define ADE9078_MASK1_ZXVA NO_OS_BIT(9)
479 #define ADE9078_MASK1_ZXTOVC NO_OS_BIT(8)
480 #define ADE9078_MASK1_ZXTOVB NO_OS_BIT(7)
481 #define ADE9078_MASK1_ZXTOVA NO_OS_BIT(6)
482 #define ADE9078_MASK1_RFNOLOAD NO_OS_BIT(4)
483 #define ADE9078_MASK1_VANLOAD NO_OS_BIT(2)
484 #define ADE9078_MASK1_RNLOAD NO_OS_BIT(1)
485 #define ADE9078_MASK1_ANLOAD NO_OS_BIT(0)
486 
487 /* ADE9078_REG_EVENT_MASK Bit Definition */
488 #define ADE9078_EVENT_DREADY_MSK NO_OS_BIT(16)
489 #define ADE9078_EVENT_RFNOLOAD_MSK NO_OS_BIT(14)
490 #define ADE9078_EVENT_VANLOAD_MSK NO_OS_BIT(12)
491 #define ADE9078_EVENT_RNLOAD_MSK NO_OS_BIT(11)
492 #define ADE9078_EVENT_ANLOAD_MSK NO_OS_BIT(10)
493 #define ADE9078_EVENT_REVPSUM4_MSK NO_OS_BIT(9)
494 #define ADE9078_EVENT_REVPSUM3_MSK NO_OS_BIT(8)
495 #define ADE9078_EVENT_REVPSUM2_MSK NO_OS_BIT(7)
496 #define ADE9078_EVENT_REVPSUM1_MSK NO_OS_BIT(6)
497 
498 /* ADE9078_REG_VLEVEL Bit Definition */
499 #define ADE9078_VLEVEL_VAL NO_OS_GENMASK(23, 0)
500 
501 /* ADE9078_REG_PHNOLOAD Bit Definition */
502 #define ADE9078_CFVARNL NO_OS_BIT(16)
503 #define ADE9078_CVANL NO_OS_BIT(14)
504 #define ADE9078_CVARNL NO_OS_BIT(13)
505 #define ADE9078_CWATTNL NO_OS_BIT(12)
506 #define ADE9078_BFVARNL NO_OS_BIT(10)
507 #define ADE9078_BVANL NO_OS_BIT(8)
508 #define ADE9078_BVARNL NO_OS_BIT(7)
509 #define ADE9078_BWATTNL NO_OS_BIT(6)
510 #define ADE9078_AFVARNL NO_OS_BIT(4)
511 #define ADE9078_AVANL NO_OS_BIT(2)
512 #define ADE9078_AVARNL NO_OS_BIT(1)
513 #define ADE9078_AWATTNL NO_OS_BIT(0)
514 
515 /* ADE9078_REG_ADC_REDIRECT Bit Definition */
516 #define ADE9078_VC_DIN NO_OS_GENMASK(20, 18)
517 #define ADE9078_VB_DIN NO_OS_GENMASK(17, 15)
518 #define ADE9078_VA_DIN NO_OS_GENMASK(14, 12)
519 #define ADE9078_IN_DIN NO_OS_GENMASK(11, 9)
520 #define ADE9078_IC_DIN NO_OS_GENMASK(8, 6)
521 #define ADE9078_IB_DIN NO_OS_GENMASK(5, 3)
522 #define ADE9078_IA_DIN NO_OS_GENMASK(2, 0)
523 
524 /* ADE9078_REG_CF_LCFG Bit Definition */
525 #define ADE9078_CF4_LT NO_OS_BIT(22)
526 #define ADE9078_CF3_LT NO_OS_BIT(21)
527 #define ADE9078_CF2_LT NO_OS_BIT(20)
528 #define ADE9078_CF1_LT NO_OS_BIT(19)
529 #define ADE9078_CF_LTMR NO_OS_GENMASK(18, 0)
530 
531 /* ADE9078_REG_PART_ID Bit Definition */
532 #define ADE9078_AD73370_ID NO_OS_BIT(21)
533 #define ADE9078_ADE9000_ID NO_OS_BIT(20)
534 #define ADE9078_ADE9004_ID NO_OS_BIT(16)
535 
536 /* ADE9078_REG_CONFIG1 Bit Definition */
537 #define ADE9078_EXT_REF NO_OS_BIT(15)
538 #define ADE9078_IRQ0_ON_IRQ1 NO_OS_BIT(12)
539 #define ADE9078_BURST_EN NO_OS_BIT(11)
540 #define ADE9078_PWR_SETTLE NO_OS_GENMASK(9, 8)
541 #define ADE9078_CF_ACC_CLR NO_OS_BIT(5)
542 #define ADE9078_CF4_CFG NO_OS_GENMASK(3, 2)
543 #define ADE9078_CF3_CFG NO_OS_BIT(1)
544 #define ADE9078_SWRST NO_OS_BIT(0)
545 
546 /* ADE9078_REG_CFMODE Bit Definition */
547 #define ADE9078_CF4DIS NO_OS_BIT(15)
548 #define ADE9078_CF3DIS NO_OS_BIT(14)
549 #define ADE9078_CF2DIS NO_OS_BIT(13)
550 #define ADE9078_CF1DIS NO_OS_BIT(12)
551 #define ADE9078_CF4SEL NO_OS_GENMASK(11, 9)
552 #define ADE9078_CF3SEL NO_OS_GENMASK(8, 6)
553 #define ADE9078_CF2SEL NO_OS_GENMASK(5, 3)
554 #define ADE9078_CF1SEL NO_OS_GENMASK(2, 0)
555 
556 /* ADE9078_REG_COMPMODE Bit Definition */
557 #define ADE9078_TERMSEL4 NO_OS_GENMASK(11, 9)
558 #define ADE9078_TERMSEL3 NO_OS_GENMASK(8, 6)
559 #define ADE9078_TERMSEL2 NO_OS_GENMASK(5, 3)
560 #define ADE9078_TERMSEL1 NO_OS_GENMASK(2, 0)
561 
562 /* ADE9078_REG_ACCMODE Bit Definition */
563 #define ADE9078_SELFREQ NO_OS_BIT(8)
564 #define ADE9078_ICONSEL NO_OS_BIT(7)
565 #define ADE9078_VCONSEL NO_OS_GENMASK(6, 4)
566 #define ADE9078_VARACC NO_OS_GENMASK(3, 2)
567 #define ADE9078_WATTACC NO_OS_GENMASK(1, 0)
568 
569 /* ADE9078_REG_CONFIG3 Bit Definition */
570 #define ADE9078_PEAKSEL NO_OS_GENMASK(4, 2)
571 
572 /* ADE9078_REG_ZX_LP_SEL Bit Definition */
573 #define ADE9078_LP_SEL NO_OS_GENMASK(4, 3)
574 #define ADE9078_ZX_SEL NO_OS_GENMASK(2, 1)
575 
576 /* ADE9078_REG_PHSIGN Bit Definition */
577 #define ADE9078_SUM4SIGN NO_OS_BIT(9)
578 #define ADE9078_SUM3SIGN NO_OS_BIT(8)
579 #define ADE9078_SUM2SIGN NO_OS_BIT(7)
580 #define ADE9078_SUM1SIGN NO_OS_BIT(6)
581 #define ADE9078_CVARSIGN NO_OS_BIT(5)
582 #define ADE9078_CWSIGN NO_OS_BIT(4)
583 #define ADE9078_BVARSIGN NO_OS_BIT(3)
584 #define ADE9078_BWSIGN NO_OS_BIT(2)
585 #define ADE9078_AVARSIGN NO_OS_BIT(1)
586 #define ADE9078_AWSIGN NO_OS_BIT(0)
587 
588 /* ADE9078_REG_WFB_CFG Bit Definition */
589 #define ADE9078_WF_IN_EN NO_OS_BIT(12)
590 #define ADE9078_WF_SRC NO_OS_GENMASK(9, 8)
591 #define ADE9078_WF_MODE NO_OS_BIT(7, 6)
592 #define ADE9078_WF_CAP_SEL NO_OS_BIT(5)
593 #define ADE9078_WF_CAP_EN NO_OS_BIT(4)
594 #define ADE9078_BURST_CHAN NO_OS_GENMASK(3, 0)
595 
596 /* ADE9078_WFB_TRG_CFG Bit Definition */
597 #define ADE9078_TRIG_FORCE NO_OS_BIT(10)
598 #define ADE9078_ZXCOMB NO_OS_BIT(9)
599 #define ADE9078_ZXVC NO_OS_BIT(8)
600 #define ADE9078_ZXVB NO_OS_BIT(7)
601 #define ADE9078_ZXVA NO_OS_BIT(6)
602 #define ADE9078_ZXIC NO_OS_BIT(5)
603 #define ADE9078_ZXIB NO_OS_BIT(4)
604 #define ADE9078_ZXIA NO_OS_BIT(3)
605 
606 /* ADE9078_WFB_TRG_STAT Bit Definition */
607 #define ADE9078_WFB_LAST_PAGE NO_OS_GENMASK(15, 12)
608 #define ADE9078_WFB_TRIG_ADDR NO_OS_GENMASK(10, 0)
609 
610 /* ADE9078_CONFIG2 Bit Definition */
611 #define ADE9078_UPERIOD_SEL NO_OS_BIT(12)
612 #define ADE9078_HPF_CRN NO_OS_GENMASK(11, 9)
613 
614 /* ADE9078_EP_CFG Bit Definition */
615 #define ADE9078_NOLOAD_TMR NO_OS_GENMASK(15, 13)
616 #define ADE9078_PWR_SIGN_SEL_1 NO_OS_BIT(7)
617 #define ADE9078_RD_RST_EN NO_OS_BIT(5)
618 #define ADE9078_EGY_LD_ACCUM NO_OS_BIT(4)
619 #define ADE9078_EGY_TMR_MODE NO_OS_BIT(1)
620 #define ADE9078_EGY_PWR_EN NO_OS_BIT(0)
621 
622 /* ADE9078_CRC_FORCE Bit Definition */
623 #define ADE9078_FORCE_CRC_UPDATE NO_OS_BIT(0)
624 
625 /* ADE9078_CRC_OPTEN Bit Definition */
626 #define ADE9078_CRC_WFB_TRG_CFG_EN NO_OS_BIT(15)
627 #define ADE9078_CRC_WFB_PG_IRQEN NO_OS_BIT(14)
628 #define ADE9078_CRC_WFB_CFG_EN NO_OS_BIT(13)
629 #define ADE9078_CRC_SEQ_CYC_EN NO_OS_BIT(12)
630 #define ADE9078_CRC_ZXLPSEL_EN NO_OS_BIT(11)
631 #define ADE9078_CRC_ZXTOUT_EN NO_OS_BIT(10)
632 #define ADE9078_CRC_APP_NL_LVL_EN NO_OS_BIT(9)
633 #define ADE9078_CRC_REACT_NL_LVL_EN NO_OS_BIT(8)
634 #define ADE9078_CRC_ACT_NL_LVL_EN NO_OS_BIT(7)
635 #define ADE9078_CRC_EVENT_MASK_EN NO_OS_BIT(2)
636 #define ADE9078_CRC_MASK1_EN NO_OS_BIT(1)
637 #define ADE9078_CRC_MASK0_EN NO_OS_BIT(0)
638 
639 /* ADE9078_PSM2_CFG Bit Definition */
640 #define ADE9078_PKDET_LVL NO_OS_BIT(8, 5)
641 #define ADE9078_LPLINE NO_OS_BIT(4, 0)
642 
643 /* ADE9078_PGA_GAIN Bit Definition */
644 #define ADE9078_VC_GAIN NO_OS_GENMASK(13, 12)
645 #define ADE9078_VB_GAIN NO_OS_GENMASK(11, 10)
646 #define ADE9078_VA_GAIN NO_OS_GENMASK(9, 8)
647 #define ADE9078_IN_GAIN NO_OS_GENMASK(7, 6)
648 #define ADE9078_IC_GAIN NO_OS_GENMASK(5, 4)
649 #define ADE9078_IB_GAIN NO_OS_GENMASK(3, 2)
650 #define ADE9078_IA_GAIN NO_OS_GENMASK(1, 0)
651 
652 /* ADE9078_CHNL_DIS Bit Definition */
653 #define ADE9078_VC_DISADC NO_OS_BIT(6)
654 #define ADE9078_VB_DISADC NO_OS_BIT(5)
655 #define ADE9078_VA_DISADC NO_OS_BIT(4)
656 #define ADE9078_IN_DISADC NO_OS_BIT(3)
657 #define ADE9078_IC_DISADC NO_OS_BIT(2)
658 #define ADE9078_IB_DISADC NO_OS_BIT(1)
659 #define ADE9078_IA_DISADC NO_OS_BIT(0)
660 
661 /* ADE9078_VAR_DIS Bit Definition */
662 #define ADE9078_VARDIS NO_OS_BIT(0)
663 
664 /* Miscellaneous Definitions */
665 #define ADE9078_CHIP_ID 0x63
666 #define ADE9078_PART_ID 0
667 #define ADE9078_RESET_RECOVER 100
668 
669 /*Configuration registers*/
670 /*PGA@0x0000. Gain of all channels=1*/
671 #define ADE9078_PGA_GAIN 0x0000
672 /*Integrator disabled*/
673 #define ADE9078_CONFIG0 0x00000000
674 /*CF3/ZX pin outputs Zero crossing */
675 #define ADE9078_CONFIG1 0x0002
676 /*Default High pass corner frequency of 1.2475Hz*/
677 #define ADE9078_CONFIG2 0x0A00
678 /*Peak and overcurrent detection disabled*/
679 #define ADE9078_CONFIG3 0x0000
680 /*50Hz operation, 3P4W Wye configuration, signed accumulation*/
681 #define ADE9078_ACCMODE 0x0000
682 /*Line period and zero crossing obtained from combined signals VA,VB and VC*/
683 #define ADE9078_ZX_LP_SEL 0x001E
684 /*Enable EGYRDY interrupt*/
685 #define ADE9078_MASK0 0x00000001
686 /*MASK1 interrupts disabled*/
687 #define ADE9078_MASK1 0x00000000
688 /*Events disabled */
689 #define ADE9078_EVENT_MASK 0x00000000
690 /*Assuming Vnom=1/2 of full scale.*/
691 /*Refer Technical reference manual for detailed calculations.*/
692 #define ADE9078_VLEVEL 0x00117514
693 /* Set DICOEFF= 0xFFFFE000 when integrator is enabled*/
694 #define ADE9078_DICOEFF 0x00000000
695 /*Constant Definitions***/
696 /*DSP ON*/
697 #define ADE9078_RUN_ON 0x0001
698 /*Energy Accumulation Settings*/
699 /*Enable energy accumulation, accumulate samples at 8ksps*/
700 /*latch energy accumulation after EGYRDY*/
701 /*If accumulation is changed to half line cycle mode, change EGY_TIME*/
702 #define ADE9078_EP_CFG 0x0001
703 /*Accumulate 8000 samples*/
704 #define ADE9078_EGY_TIME 0x1F3F
705 /*Waveform buffer Settings*/
706 /*Neutral current samples enabled, Resampled data enabled*/
707 /*Burst all channels*/
708 #define ADE9078_WFB_CFG 0x1000
709 /*size of buffer to read. 512 Max.Each element IA,VA...IN has max 512 points*/
710 /*[Size of waveform buffer/number of sample sets = 2048/4 = 512]*/
711 /*(Refer ADE9078 technical reference manual for more details)*/
712 #define WFB_ELEMENT_ARRAY_SIZE 512
713 /*Full scale Codes (FS) referred from Datasheet.*/
714 /*Respective digital codes are produced when ADC inputs*/
715 /*are at full scale. Do not Change. */
716 #define ADE9078_RMS_FS_CODES 52866837
717 #define ADE9078_WATT_FS_CODES 20823646
718 
719 /* Assuming a transformer ratio of 1000:1 and 10 ohms burden resistance value */
720 #define ADE9078_BURDEN_RES 10
721 #define ADE9078_CURRENT_TR_RATIO 1000
722 #define ADE9078_CURRENT_TR_FCN (ADE9078_CURRENT_TR_RATIO / ADE9078_BURDEN_RES)
723 /* Assuming a voltage divider with Rlow 1k and Rup 990k */
724 #define ADE9078_UP_RES 990000
725 #define ADE9078_DOWN_RES 1000
726 #define ADE9078_VOLTAGE_TR_FCN ((ADE9078_DOWN_RES + ADE9078_UP_RES) / ADE9078_DOWN_RES)
727 
728 // 0.707V rms full scale * 1000 for mili units
729 #define ADE9078_FS_VOLTAGE 707
730 
731 /******************************************************************************/
732 /*************************** Types Declarations *******************************/
733 /******************************************************************************/
734 
740  /* Approximated neutral current rms calculation */
742  /* Determine positive mismatch between neutral and
743  phase currents */
745  /* determine negative mismatch between neutral and
746  phase currents */
748  /* approximated neutral current rms calculation */
750 };
751 
758  /* 0 */
760  /* 1 */
762  /* 2 */
764  /* 3 */
766  /* 4 */
768  /* function disabled */
770 };
771 
778  /* 0 */
780  /* 1 */
782  /* 2 */
784  /* 3 */
786  /* 4 */
788  /* function disabled */
790 };
791 
798  /* 0 */
800  /* 1 */
802  /* 2 */
804  /* 3 */
806  /* 4 */
808  /* function disabled */
810 };
811 
818  /* Digital to freq converter */
820  /* Digital to freq converter */
822  /* Event */
824  /* Dready */
826 };
827 
833  /* 64 ms */
835  /* 128 ms */
837  /* 256 ms */
839  /* 0 ms */
841 };
842 
850  /* Total active power */
852  /* Total reactive power */
854  /* Total apparent power */
856  /* Fundamental reactive power */
858  /* Total active power */
860  /* Total active power2 */
862 };
863 
869  /* 50 Hz */
871  /* 60 Hz */
873 };
874 
880  /* 4 wire wye */
882  /* 3-wire delta. VB' = VA − VC */
884  /* 4-wire wye, nonBlondel compliant. VB' = −VA − VC */
886  /* 4-wire delta, nonBlondel compliant. VB' = −VA */
888  /* 3-wire delta. VA' = VA − VB; VB' = VA − VC; VC' = VC − VB*/
890 };
891 
898  /* signed acc mode */
900  /* absolute value acc mode */
902  /* positive acc mode */
904  /* negative acc mode */
906 };
907 
915  /* signed acc mode */
917  /* absolute value acc mode */
919  /* positive acc mode */
921  /* negative acc mode */
923 };
924 
932  /* Phase A voltage zero-crossing signal */
934  /* Phase B voltage zero-crossing signal */
936  /* Phase C voltage zero-crossing signal */
938  /* Zero-crossing on combined signal from VA, VB, and VC */
940 };
941 
948  /* Sinc4 output at 32 kSPS */
950  /* Sinc4 + IIR LPF output at 8 kSPS */
952  /* Current and voltage channel waveform samples,
953  processed by the DSP (xI_PCF, xV_PCF) at 4 kSPS */
955 };
956 
963  /* Stop when waveform buffer is full */
965  /* Continuous fill—stop only on enabled trigger
966  events */
968  /* Continuous filling—center capture around
969  enabled trigger events. */
971  /* Continuous fill—save event address of enabled
972  trigger events */
974 };
975 
982  /* All channels */
984  /* IA and VA */
986  /* IB and VB */
988  /* IC and VC */
990  /* IA */
992  /* VA */
994  /* IB */
996  /* VB */
998  /* IC */
1000  /* VC */
1002  /* IN if WF_IN_EN = 1*/
1004  /* Burst Disable read single addr */
1006 };
1007 
1014  /* 39.695 Hz. */
1016  /* 19.6375 Hz. */
1018  /* 9.895 Hz. */
1020  /* 4.9675 Hz. */
1022  /* 2.49 Hz. */
1024  /* 1.2475 Hz. */
1026  /* 0.625 Hz. */
1028  /* 0.3125 Hz. */
1030 };
1031 
1038  /* 64 samples */
1040  /* 128 samples */
1042  /* 256 samples */
1044  /* 512 samples */
1046  /* 1024 samples */
1048  /* 2048 samples */
1050  /* 4096 samples */
1052  /* disable no load threshold */
1054 };
1055 
1063  /* 100:1 */
1065  /* 200:1 */
1067  /* 300:1 */
1069  /* 400:1 */
1071  /* 500:1 */
1073  /* 600:1 */
1075  /* 700:1 */
1077  /* 800:1 */
1079  /* 900:1 */
1081  /* 1000:1 */
1083  /* 1100:1 */
1085  /* 1200:1 */
1087  /* 1300:1 */
1089  /* 1400:1 */
1091  /* 1500:1 */
1093  /* 1600:1 */
1095 };
1096 
1102  /* Gain = 1 */
1104  /* Gain = 2 */
1106  /* Gain = 3 */
1108  /* Gain = 4 */
1110 };
1111 
1120 };
1121 
1130 };
1131 
1137  /* SPI is not available in PSM2 & PSM3*/
1138  /* PSM0 normal mode */
1140  /* PSM1 Tamper measurement mode */
1142  /* PSM2 Current peak detect mode */
1144  /* PSM3 IDLE */
1146 };
1147 
1155  /* psm0 descriptor */
1157  /* psm1 descriptor */
1159  /* reset descriptor */
1161  /* Variable for mode selection */
1162  uint8_t power_mode;
1163 };
1164 
1169 struct ade9078_dev {
1172  /* psm0 descriptor */
1174  /* psm1 descriptor */
1176  /* psm1 descriptor */
1178  /* Variable storing the WATT value */
1179  uint32_t watt_val;
1180  /* Variable storing the IRMS value */
1181  uint32_t irms_val;
1182  /* Variable storing the VRMS value */
1183  uint32_t vrms_val;
1184  /* Variable for mode selection */
1185  uint8_t power_mode;
1186 };
1187 
1188 /******************************************************************************/
1189 /************************ Functions Declarations ******************************/
1190 /******************************************************************************/
1191 
1192 /* Read device register. */
1193 int ade9078_read(struct ade9078_dev *dev, uint16_t reg_addr,
1194  uint32_t *reg_data);
1195 
1196 /* Write device register. */
1197 int ade9078_write(struct ade9078_dev *dev, uint16_t reg_addr,
1198  uint32_t reg_data);
1199 
1200 /* Set power mode */
1201 int ade9078_set_power_mode(struct ade9078_dev *dev);
1202 
1203 /* Update specific register bits. */
1204 int ade9078_update_bits(struct ade9078_dev *dev, uint16_t reg_addr,
1205  uint32_t mask, uint32_t reg_data);
1206 
1207 /* Read Energy/Power for specific phase */
1208 int ade9078_read_data_ph(struct ade9078_dev *dev, enum ade9078_phase phase);
1209 
1210 /* Set User Energy use model */
1211 int ade9078_set_egy_model(struct ade9078_dev *dev, enum ade9078_egy_model model,
1212  uint16_t value);
1213 
1214 /* Initialize the device. */
1215 int ade9078_init(struct ade9078_dev **device,
1217 
1218 /* Setup the device */
1219 int ade9078_setup(struct ade9078_dev *dev);
1220 
1221 /* Remove the device and release resources. */
1222 int ade9078_remove(struct ade9078_dev *dev);
1223 
1224 /* Get interrupt indicator from STATUS0 register. */
1225 int ade9078_get_int_status0(struct ade9078_dev *dev, uint32_t msk,
1226  uint8_t *status);
1227 
1228 #endif // __ADE9078_H__
ADE9078_ACC_NEGATIVE
@ ADE9078_ACC_NEGATIVE
Definition: ade9078.h:905
ADE9078_REG_CONFIG0
#define ADE9078_REG_CONFIG0
Definition: ade9078.h:112
ADE9078_NOLOAD_SAMPLES_64
@ ADE9078_NOLOAD_SAMPLES_64
Definition: ade9078.h:1039
ade9078_read
int ade9078_read(struct ade9078_dev *dev, uint16_t reg_addr, uint32_t *reg_data)
Read device register.
Definition: ade9078.c:55
ADE9078_EGY_TIME
#define ADE9078_EGY_TIME
Definition: ade9078.h:704
ADE9078_BIGAIN_BPHCAL_0
@ ADE9078_BIGAIN_BPHCAL_0
Definition: ade9078.h:779
ade9078_read_data_ph
int ade9078_read_data_ph(struct ade9078_dev *dev, enum ade9078_phase phase)
Read the power/energy for specific phase.
Definition: ade9078.c:242
ade9078_init_param
ADE9078 Device initialization parameters.
Definition: ade9078.h:1152
no_os_put_unaligned_be16
void no_os_put_unaligned_be16(uint16_t val, uint8_t *buf)
ADE9078_HPF_0_3125
@ ADE9078_HPF_0_3125
Definition: ade9078.h:1029
ade9078_no_load_tmr_e
ade9078_no_load_tmr_e
This register configures how many 4 kSPS samples to evaluate the no load condition over.
Definition: ade9078.h:1037
ADE9078_REG_CONFIG2
#define ADE9078_REG_CONFIG2
Definition: ade9078.h:262
no_os_alloc.h
ADE9078_DICOEFF
#define ADE9078_DICOEFF
Definition: ade9078.h:694
ADE9078_ISUM_DET_MISM_NEG
@ ADE9078_ISUM_DET_MISM_NEG
Definition: ade9078.h:747
ade9078_set_egy_model
int ade9078_set_egy_model(struct ade9078_dev *dev, enum ade9078_egy_model model, uint16_t value)
Set User Energy use model.
Definition: ade9078.c:319
ADE9078_REG_STATUS0
#define ADE9078_REG_STATUS0
Definition: ade9078.h:206
ADE9078_4WIRE_WYE_VA_VC
@ ADE9078_4WIRE_WYE_VA_VC
Definition: ade9078.h:885
ADE9078_CURRENT_TR_FCN
#define ADE9078_CURRENT_TR_FCN
Definition: ade9078.h:722
ADE9078_NOLOAD_SAMPLES_512
@ ADE9078_NOLOAD_SAMPLES_512
Definition: ade9078.h:1045
ADE9078_CONFIG0
#define ADE9078_CONFIG0
Definition: ade9078.h:673
ade9078_isum_cfg_e
ade9078_isum_cfg_e
ADE9078 isum calculation configuration.
Definition: ade9078.h:739
ade9078_dev
ADE9078 Device structure.
Definition: ade9078.h:1169
ADE9078_BURST_IC
@ ADE9078_BURST_IC
Definition: ade9078.h:999
ADE9078_CF4_SEL_APPARENT_P
@ ADE9078_CF4_SEL_APPARENT_P
Definition: ade9078.h:855
NO_OS_GENMASK
#define NO_OS_GENMASK(h, l)
Definition: no_os_util.h:82
no_os_spi_write_and_read
int32_t no_os_spi_write_and_read(struct no_os_spi_desc *desc, uint8_t *data, uint16_t bytes_number)
Write and read data to/from SPI.
Definition: no_os_spi.c:159
ADE9078_HPF_0_625
@ ADE9078_HPF_0_625
Definition: ade9078.h:1027
ADE9078_REG_VLEVEL
#define ADE9078_REG_VLEVEL
Definition: ade9078.h:213
ADE9078_BURST_IA_VA
@ ADE9078_BURST_IA_VA
Definition: ade9078.h:985
ADE9078_REG_PGA_GAIN
#define ADE9078_REG_PGA_GAIN
Definition: ade9078.h:270
no_os_spi.h
Header file of SPI Interface.
ADE9078_PKDET_LVL_600
@ ADE9078_PKDET_LVL_600
Definition: ade9078.h:1074
ADE9078_AIGAIN_APHCAL_3
@ ADE9078_AIGAIN_APHCAL_3
Definition: ade9078.h:765
ade9078_dev::psm0_desc
struct no_os_gpio_desc * psm0_desc
Definition: ade9078.h:1173
ADE9078_ACCMODE
#define ADE9078_ACCMODE
Definition: ade9078.h:681
ade9078_get_int_status0
int ade9078_get_int_status0(struct ade9078_dev *dev, uint32_t msk, uint8_t *status)
Get interrupt indicator from STATUS0 register.
Definition: ade9078.c:215
ADE9078_PKDET_LVL_1600
@ ADE9078_PKDET_LVL_1600
Definition: ade9078.h:1094
ADE9078_REG_EVENT_MASK
#define ADE9078_REG_EVENT_MASK
Definition: ade9078.h:211
ADE9078_CF4_EVENT
@ ADE9078_CF4_EVENT
Definition: ade9078.h:823
ADE9078_PKDET_LVL_300
@ ADE9078_PKDET_LVL_300
Definition: ade9078.h:1068
ADE9078_SRC_DSP
@ ADE9078_SRC_DSP
Definition: ade9078.h:954
no_os_units.h
Header file of Units.
ADE9078_REG_CONFIG5
#define ADE9078_REG_CONFIG5
Definition: ade9078.h:257
pr_err
#define pr_err(fmt, args...)
Definition: no_os_print_log.h:88
ADE9078_EGY_TMR_MODE
#define ADE9078_EGY_TMR_MODE
Definition: ade9078.h:619
ADE9078_PWR_SETTLE_3
@ ADE9078_PWR_SETTLE_3
Definition: ade9078.h:840
ADE9078_EGY_WITH_RESET
@ ADE9078_EGY_WITH_RESET
Definition: ade9078.h:1127
ADE9078_CF4_SEL_TOTAL_ACTIVE_P
@ ADE9078_CF4_SEL_TOTAL_ACTIVE_P
Definition: ade9078.h:859
ADE9078_CF4_DREADY
@ ADE9078_CF4_DREADY
Definition: ade9078.h:825
no_os_delay.h
Header file of Delay functions.
ADE9078_REG_RUN
#define ADE9078_REG_RUN
Definition: ade9078.h:229
ADE9078_CIGAIN_CPHCAL_3
@ ADE9078_CIGAIN_CPHCAL_3
Definition: ade9078.h:805
ADE9078_PKDET_LVL_400
@ ADE9078_PKDET_LVL_400
Definition: ade9078.h:1070
ADE9078_CF4_SEL_ACTIV_P
@ ADE9078_CF4_SEL_ACTIV_P
Definition: ade9078.h:851
ADE9078_REG_CVRMS
#define ADE9078_REG_CVRMS
Definition: ade9078.h:153
ADE9078_REG_MASK1
#define ADE9078_REG_MASK1
Definition: ade9078.h:210
ADE9078_CIGAIN_CPHCAL_1
@ ADE9078_CIGAIN_CPHCAL_1
Definition: ade9078.h:801
ade9078_phase
ade9078_phase
ADE9078 available phases.
Definition: ade9078.h:1116
ade9078_update_bits
int ade9078_update_bits(struct ade9078_dev *dev, uint16_t reg_addr, uint32_t mask, uint32_t reg_data)
Update specific register bits.
Definition: ade9078.c:188
ADE9078_PGA_GAIN
#define ADE9078_PGA_GAIN
Definition: ade9078.h:671
ade9078_read
int ade9078_read(struct ade9078_dev *dev, uint16_t reg_addr, uint32_t *reg_data)
Read device register.
Definition: ade9078.c:55
NORMAL_MODE
@ NORMAL_MODE
Definition: ade9078.h:1139
device
Definition: ad9361_util.h:69
ade9078_cf4_pin_out_cfg_e
ade9078_cf4_pin_out_cfg_e
ADE9078 These bits indicate which function to output on CF4 pin.
Definition: ade9078.h:817
ADE9078_EGY_NR_SAMPLES
@ ADE9078_EGY_NR_SAMPLES
Definition: ade9078.h:1129
NO_OS_GPIO_HIGH
@ NO_OS_GPIO_HIGH
Definition: no_os_gpio.h:117
ade9078_read_data_ph
int ade9078_read_data_ph(struct ade9078_dev *dev, enum ade9078_phase phase)
Read the power/energy for specific phase.
Definition: ade9078.c:242
no_os_print_log.h
Print messages helpers.
ADE9078_CF4_D_F_CONV2
@ ADE9078_CF4_D_F_CONV2
Definition: ade9078.h:821
ade9078_dev::reset_desc
struct no_os_gpio_desc * reset_desc
Definition: ade9078.h:1177
ADE9078_EGY_LD_ACCUM
#define ADE9078_EGY_LD_ACCUM
Definition: ade9078.h:618
ADE9078_MODE_CENTER_CAPTURE
@ ADE9078_MODE_CENTER_CAPTURE
Definition: ade9078.h:970
ade9078_init_param::reset_desc
struct no_os_gpio_desc * reset_desc
Definition: ade9078.h:1160
ADE9078_NOLOAD_SAMPLES_DISABLE
@ ADE9078_NOLOAD_SAMPLES_DISABLE
Definition: ade9078.h:1053
ade9078_setup
int ade9078_setup(struct ade9078_dev *dev)
Setup the device.
Definition: ade9078.c:466
ade9078_get_int_status0
int ade9078_get_int_status0(struct ade9078_dev *dev, uint32_t msk, uint8_t *status)
Get interrupt indicator from STATUS0 register.
Definition: ade9078.c:215
no_os_calloc
void * no_os_calloc(size_t nitems, size_t size)
Allocate memory and return a pointer to it, set memory to 0.
Definition: chibios_alloc.c:54
ade9078_init
int ade9078_init(struct ade9078_dev **device, struct ade9078_init_param init_param)
Initialize the device.
Definition: ade9078.c:380
ADE9078_COM_PERIOD
@ ADE9078_COM_PERIOD
Definition: ade9078.h:922
ADE9078_MODE_TRIG_EN_EVENTS
@ ADE9078_MODE_TRIG_EN_EVENTS
Definition: ade9078.h:967
ade9078_vc_gain_e
ade9078_vc_gain_e
ADE9078 PGA gain for Voltage Channel C ADC.
Definition: ade9078.h:1101
ADE9078_REG_EP_CFG
#define ADE9078_REG_EP_CFG
Definition: ade9078.h:263
ADE9078_NOLOAD_SAMPLES_2048
@ ADE9078_NOLOAD_SAMPLES_2048
Definition: ade9078.h:1049
ADE9078_BURST_VA
@ ADE9078_BURST_VA
Definition: ade9078.h:993
ADE9078_EGY_PWR_EN
#define ADE9078_EGY_PWR_EN
Definition: ade9078.h:620
ADE9078_RMS_FS_CODES
#define ADE9078_RMS_FS_CODES
Definition: ade9078.h:716
ADE9078_CIGAIN_CPHCAL_0
@ ADE9078_CIGAIN_CPHCAL_0
Definition: ade9078.h:799
ade9078_setup
int ade9078_setup(struct ade9078_dev *dev)
Setup the device.
Definition: ade9078.c:466
NO_OS_GPIO_LOW
@ NO_OS_GPIO_LOW
Definition: no_os_gpio.h:115
ADE9078_PART_ID
#define ADE9078_PART_ID
Definition: ade9078.h:666
ade9078_pwr_settle_e
ade9078_pwr_settle_e
ADE9078 Power settle time.
Definition: ade9078.h:832
ADE9078_RUN_ON
#define ADE9078_RUN_ON
Definition: ade9078.h:697
ADE9078_HPF_36_695
@ ADE9078_HPF_36_695
Definition: ade9078.h:1015
ADE9078_REG_DICOEFF
#define ADE9078_REG_DICOEFF
Definition: ade9078.h:128
ade9078_init_param::power_mode
uint8_t power_mode
Definition: ade9078.h:1162
ADE9078_VC_GAIN_1
@ ADE9078_VC_GAIN_1
Definition: ade9078.h:1103
ADE9078_BIGAIN_BPHCAL_DISABLE
@ ADE9078_BIGAIN_BPHCAL_DISABLE
Definition: ade9078.h:789
ade9078_burst_ch_e
ade9078_burst_ch_e
Selects which data to read out of the waveform buffer through SPI.
Definition: ade9078.h:981
no_os_mdelay
void no_os_mdelay(uint32_t msecs)
Wait until msecs milliseconds passed.
Definition: aducm3029_delay.c:126
ADE9078_3WIRE_DELTA_2
@ ADE9078_3WIRE_DELTA_2
Definition: ade9078.h:889
no_os_field_prep
uint32_t no_os_field_prep(uint32_t mask, uint32_t val)
ADE9078_BIGAIN_BPHCAL_1
@ ADE9078_BIGAIN_BPHCAL_1
Definition: ade9078.h:781
ADE9078_CPERIOD
@ ADE9078_CPERIOD
Definition: ade9078.h:920
ade9078_dev::psm1_desc
struct no_os_gpio_desc * psm1_desc
Definition: ade9078.h:1175
ADE9078_WATT_FS_CODES
#define ADE9078_WATT_FS_CODES
Definition: ade9078.h:717
ADE9078_REG_CIRMS
#define ADE9078_REG_CIRMS
Definition: ade9078.h:152
ADE9078_REG_BWATT
#define ADE9078_REG_BWATT
Definition: ade9078.h:144
ADE9078_CONFIG2
#define ADE9078_CONFIG2
Definition: ade9078.h:677
ADE9078_BURST_IB
@ ADE9078_BURST_IB
Definition: ade9078.h:995
ADE9078_PKDET_LVL_700
@ ADE9078_PKDET_LVL_700
Definition: ade9078.h:1076
ADE9078_REG_ACCMODE
#define ADE9078_REG_ACCMODE
Definition: ade9078.h:242
ADE9078_REG_PART_ID
#define ADE9078_REG_PART_ID
Definition: ade9078.h:228
ADE9078_EP_CFG
#define ADE9078_EP_CFG
Definition: ade9078.h:702
ade9078_freq_sel_e
ade9078_freq_sel_e
ADE9078 Freq value.
Definition: ade9078.h:868
ade9078_dev::spi_desc
struct no_os_spi_desc * spi_desc
Definition: ade9078.h:1171
ade9078_line_period_sel_e
ade9078_line_period_sel_e
Selects line period measurement used for VRMS½ cycle, 10 cycle rms/12 cycle rms, and resampling.
Definition: ade9078.h:914
ADE9078_MODE_STOP_FULL
@ ADE9078_MODE_STOP_FULL
Definition: ade9078.h:964
ADE9078_AIGAIN_APHCAL_DISABLE
@ ADE9078_AIGAIN_APHCAL_DISABLE
Definition: ade9078.h:769
ADE9078_REG_AVRMS
#define ADE9078_REG_AVRMS
Definition: ade9078.h:133
no_os_put_unaligned_be32
void no_os_put_unaligned_be32(uint32_t val, uint8_t *buf)
ADE9078_VC_GAIN_4
@ ADE9078_VC_GAIN_4
Definition: ade9078.h:1109
ADE9078_PHASE_B
@ ADE9078_PHASE_B
Definition: ade9078.h:1118
ADE9078_REG_AIRMS
#define ADE9078_REG_AIRMS
Definition: ade9078.h:132
ADE9078_ACC_ABSOLUTE
@ ADE9078_ACC_ABSOLUTE
Definition: ade9078.h:901
ADE9078_VOLTAGE_TR_FCN
#define ADE9078_VOLTAGE_TR_FCN
Definition: ade9078.h:726
ADE9078_RD_RST_EN
#define ADE9078_RD_RST_EN
Definition: ade9078.h:617
ADE9078_PKDET_LVL_500
@ ADE9078_PKDET_LVL_500
Definition: ade9078.h:1072
ADE9078_CIGAIN_CPHCAL_2
@ ADE9078_CIGAIN_CPHCAL_2
Definition: ade9078.h:803
ADE9078_AIGAIN_APHCAL_2
@ ADE9078_AIGAIN_APHCAL_2
Definition: ade9078.h:763
ADE9078_ISUM_APROX_N
@ ADE9078_ISUM_APROX_N
Definition: ade9078.h:741
ADE9078_ACC_SIGNED
@ ADE9078_ACC_SIGNED
Definition: ade9078.h:899
ade9078_write
int ade9078_write(struct ade9078_dev *dev, uint16_t reg_addr, uint32_t reg_data)
Write device register.
Definition: ade9078.c:102
ade9078_init
int ade9078_init(struct ade9078_dev **device, struct ade9078_init_param init_param)
Initialize the device.
Definition: ade9078.c:380
ade9078_dev::vrms_val
uint32_t vrms_val
Definition: ade9078.h:1183
ADE9078_4WIRE_WYE_VA
@ ADE9078_4WIRE_WYE_VA
Definition: ade9078.h:887
ADE9078_PHASE_C
@ ADE9078_PHASE_C
Definition: ade9078.h:1119
ADE9078_PKDET_LVL_1300
@ ADE9078_PKDET_LVL_1300
Definition: ade9078.h:1088
ADE9078_REG_WFB_CFG
#define ADE9078_REG_WFB_CFG
Definition: ade9078.h:253
ADE9078_AIGAIN_APHCAL_4
@ ADE9078_AIGAIN_APHCAL_4
Definition: ade9078.h:767
ade9078_write
int ade9078_write(struct ade9078_dev *dev, uint16_t reg_addr, uint32_t reg_data)
Write device register.
Definition: ade9078.c:102
no_os_spi_desc
Structure holding SPI descriptor.
Definition: no_os_spi.h:192
ade9078_hpf_freq_e
ade9078_hpf_freq_e
High-pass filter corner (f3dB) enabled when the HPFDIS bit in the CONFIG0 register is equal to zero.
Definition: ade9078.h:1013
ADE9078_REG_CONFIG1
#define ADE9078_REG_CONFIG1
Definition: ade9078.h:230
ade9078_dev::watt_val
uint32_t watt_val
Definition: ade9078.h:1179
ADE9078_CF4_SEL_FUN_REACTIVE_P
@ ADE9078_CF4_SEL_FUN_REACTIVE_P
Definition: ade9078.h:857
no_os_gpio_desc
Structure holding the GPIO descriptor.
Definition: no_os_gpio.h:96
ADE9078_BURST_ALL_CH
@ ADE9078_BURST_ALL_CH
Definition: ade9078.h:983
ADE9078_NOLOAD_SAMPLES_1024
@ ADE9078_NOLOAD_SAMPLES_1024
Definition: ade9078.h:1047
ADE9078_BURST_IC_VC
@ ADE9078_BURST_IC_VC
Definition: ade9078.h:989
ADE9078_BURST_IB_VB
@ ADE9078_BURST_IB_VB
Definition: ade9078.h:987
ADE9078_ZXVB_SEL
@ ADE9078_ZXVB_SEL
Definition: ade9078.h:935
ADE9078_REG_ZX_LP_SEL
#define ADE9078_REG_ZX_LP_SEL
Definition: ade9078.h:250
ADE9078_CONFIG1
#define ADE9078_CONFIG1
Definition: ade9078.h:675
ADE9078_VLEVEL
#define ADE9078_VLEVEL
Definition: ade9078.h:692
ade9078_init_param::psm0_desc
struct no_os_gpio_desc * psm0_desc
Definition: ade9078.h:1156
IDLE_MODE
@ IDLE_MODE
Definition: ade9078.h:1145
ADE9078_APERIOD
@ ADE9078_APERIOD
Definition: ade9078.h:916
ADE9078_BIGAIN_BPHCAL_4
@ ADE9078_BIGAIN_BPHCAL_4
Definition: ade9078.h:787
ADE9078_REG_CWATT
#define ADE9078_REG_CWATT
Definition: ade9078.h:154
TAMPER_MODE
@ TAMPER_MODE
Definition: ade9078.h:1141
ADE9078_HPF_9_895
@ ADE9078_HPF_9_895
Definition: ade9078.h:1019
ADE9078_ADE9000_ID
#define ADE9078_ADE9000_ID
Definition: ade9078.h:533
ade9078_set_egy_model
int ade9078_set_egy_model(struct ade9078_dev *dev, enum ade9078_egy_model model, uint16_t value)
Set User Energy use model.
Definition: ade9078.c:319
ade9078_cf4_sel_e
ade9078_cf4_sel_e
ADE9078 Type of energy output on the CF4 pin. Configure TERMSEL4 in the COMPMODE register to select w...
Definition: ade9078.h:849
ade9078_wf_mode_e
ade9078_wf_mode_e
Fixed data rate waveforms filling and trigger based modes.
Definition: ade9078.h:962
ADE9078_REG_BIRMS
#define ADE9078_REG_BIRMS
Definition: ade9078.h:142
ADE9078_WFB_CFG
#define ADE9078_WFB_CFG
Definition: ade9078.h:708
ADE9078_HPF_4_9675
@ ADE9078_HPF_4_9675
Definition: ade9078.h:1021
ADE9078_AIGAIN_APHCAL_0
@ ADE9078_AIGAIN_APHCAL_0
Definition: ade9078.h:759
ADE9078_BIGAIN_BPHCAL_3
@ ADE9078_BIGAIN_BPHCAL_3
Definition: ade9078.h:785
ADE9078_HPF_1_2475
@ ADE9078_HPF_1_2475
Definition: ade9078.h:1025
no_os_free
void no_os_free(void *ptr)
Deallocate memory previously allocated by a call to no_os_calloc or no_os_malloc.
Definition: chibios_alloc.c:69
ADE9078_BURST_IN
@ ADE9078_BURST_IN
Definition: ade9078.h:1003
ADE9078_PKDET_LVL_100
@ ADE9078_PKDET_LVL_100
Definition: ade9078.h:1064
ADE9078_ZXCOMB_SEL
@ ADE9078_ZXCOMB_SEL
Definition: ade9078.h:939
ADE9078_EGY_HALF_LINE_CYCLES
@ ADE9078_EGY_HALF_LINE_CYCLES
Definition: ade9078.h:1128
ADE9078_SELFREQ_50
@ ADE9078_SELFREQ_50
Definition: ade9078.h:870
ADE9078_PKDET_LVL_1200
@ ADE9078_PKDET_LVL_1200
Definition: ade9078.h:1086
ADE9078_SRC_SINC4_IIR
@ ADE9078_SRC_SINC4_IIR
Definition: ade9078.h:951
ADE9078_BPERIOD
@ ADE9078_BPERIOD
Definition: ade9078.h:918
ADE9078_CIGAIN_CPHCAL_4
@ ADE9078_CIGAIN_CPHCAL_4
Definition: ade9078.h:807
ADE9078_CONFIG3
#define ADE9078_CONFIG3
Definition: ade9078.h:679
ADE9078_VC_GAIN_3
@ ADE9078_VC_GAIN_3
Definition: ade9078.h:1107
ADE9078_AIGAIN_APHCAL_1
@ ADE9078_AIGAIN_APHCAL_1
Definition: ade9078.h:761
ADE9078_CF4_SEL_REACTIV_P
@ ADE9078_CF4_SEL_REACTIV_P
Definition: ade9078.h:853
ADE9078_SPI_READ
#define ADE9078_SPI_READ
Definition: ade9078.h:52
ade9078.h
Header file of ADE9078 Driver.
ADE9078_REG_EGY_TIME
#define ADE9078_REG_EGY_TIME
Definition: ade9078.h:265
CURRENT_PEAK_DETECT_MODE
@ CURRENT_PEAK_DETECT_MODE
Definition: ade9078.h:1143
ADE9078_BURST_VB
@ ADE9078_BURST_VB
Definition: ade9078.h:997
ADE9078_NOLOAD_SAMPLES_4096
@ ADE9078_NOLOAD_SAMPLES_4096
Definition: ade9078.h:1051
no_os_gpio_set_value
int32_t no_os_gpio_set_value(struct no_os_gpio_desc *desc, uint8_t value)
Set the value of the specified GPIO.
Definition: no_os_gpio.c:197
no_os_get_unaligned_be32
uint32_t no_os_get_unaligned_be32(uint8_t *buf)
ADE9078_REG_CONFIG3
#define ADE9078_REG_CONFIG3
Definition: ade9078.h:243
init_param
struct ad7616_init_param init_param
Definition: ad7616_sdz.c:113
ade9078_remove
int ade9078_remove(struct ade9078_dev *dev)
Remove the device and release resources.
Definition: ade9078.c:526
ade9078_zx_select_e
ade9078_zx_select_e
Selects the zero-crossing signal, which can be routed to the CF3/ZX output pin and used for line cycl...
Definition: ade9078.h:931
ADE9078_MASK1
#define ADE9078_MASK1
Definition: ade9078.h:687
ADE9078_ZXVA_SEL
@ ADE9078_ZXVA_SEL
Definition: ade9078.h:933
ADE9078_CHIP_ID
#define ADE9078_CHIP_ID
Definition: ade9078.h:665
ade9078_var_acc_mode_e
ade9078_var_acc_mode_e
ADE9078 Total and fundamental reactive power accumulation mode for energy registers and CFx pulses.
Definition: ade9078.h:897
ADE9078_ZXVC_SEL
@ ADE9078_ZXVC_SEL
Definition: ade9078.h:937
ADE9078_EVENT_MASK
#define ADE9078_EVENT_MASK
Definition: ade9078.h:689
ADE9078_PKDET_LVL_1000
@ ADE9078_PKDET_LVL_1000
Definition: ade9078.h:1082
ade9078_update_bits
int ade9078_update_bits(struct ade9078_dev *dev, uint16_t reg_addr, uint32_t mask, uint32_t reg_data)
Update specific register bits.
Definition: ade9078.c:188
no_os_spi_remove
int32_t no_os_spi_remove(struct no_os_spi_desc *desc)
Free the resources allocated by no_os_spi_init().
Definition: no_os_spi.c:116
ade9078_wf_src_e
ade9078_wf_src_e
Waveform buffer source and DREADY (data ready update rate) selection.
Definition: ade9078.h:947
ADE9078_SRC_SINC4
@ ADE9078_SRC_SINC4
Definition: ade9078.h:949
no_os_gpio.h
Header file of GPIO Interface.
ADE9078_CF4_D_F_CONV
@ ADE9078_CF4_D_F_CONV
Definition: ade9078.h:819
ADE9078_PWR_SETTLE_1
@ ADE9078_PWR_SETTLE_1
Definition: ade9078.h:836
ADE9078_HPF_19_6375
@ ADE9078_HPF_19_6375
Definition: ade9078.h:1017
ADE9078_BURST_IA
@ ADE9078_BURST_IA
Definition: ade9078.h:991
ADE9078_REG_AWATT
#define ADE9078_REG_AWATT
Definition: ade9078.h:134
ADE9078_BURST_DISABLED
@ ADE9078_BURST_DISABLED
Definition: ade9078.h:1005
ade9078_set_power_mode
int ade9078_set_power_mode(struct ade9078_dev *dev)
Set power mode.
Definition: ade9078.c:129
ade9078_power_mode_e
ade9078_power_mode_e
ADE9078 Power mode selection.
Definition: ade9078.h:1136
ADE9078_ZX_LP_SEL
#define ADE9078_ZX_LP_SEL
Definition: ade9078.h:683
ade9078_egy_model
ade9078_egy_model
ADE9078 available user energy use models.
Definition: ade9078.h:1126
NORMAL_MODE
@ NORMAL_MODE
Definition: ade7880.h:778
ADE9078_ISUM_DET_MISM_POS
@ ADE9078_ISUM_DET_MISM_POS
Definition: ade9078.h:744
ade9078_dev::irms_val
uint32_t irms_val
Definition: ade9078.h:1181
no_os_spi_init
int32_t no_os_spi_init(struct no_os_spi_desc **desc, const struct no_os_spi_init_param *param)
Initialize the SPI communication peripheral.
Definition: no_os_spi.c:52
no_os_get_unaligned_be16
uint16_t no_os_get_unaligned_be16(uint8_t *buf)
ADE9078_PKDET_LVL_1100
@ ADE9078_PKDET_LVL_1100
Definition: ade9078.h:1084
ADE9078_PWR_SETTLE_2
@ ADE9078_PWR_SETTLE_2
Definition: ade9078.h:838
ADE9078_BURST_VC
@ ADE9078_BURST_VC
Definition: ade9078.h:1001
no_os_util.h
Header file of utility functions.
no_os_find_first_set_bit
uint32_t no_os_find_first_set_bit(uint32_t word)
ADE9078_PHASE_A
@ ADE9078_PHASE_A
Definition: ade9078.h:1117
ADE9078_NOLOAD_SAMPLES_128
@ ADE9078_NOLOAD_SAMPLES_128
Definition: ade9078.h:1041
ADE9078_RESET_RECOVER
#define ADE9078_RESET_RECOVER
Definition: ade9078.h:667
ADE9078_MODE_SAVE_EVENT_ADDR
@ ADE9078_MODE_SAVE_EVENT_ADDR
Definition: ade9078.h:973
ADE9078_PKDET_LVL_800
@ ADE9078_PKDET_LVL_800
Definition: ade9078.h:1078
ade9078_bregion_sel_e
ade9078_bregion_sel_e
ADE9078 These bits indicate which BIGAINx and BPHCALx is currently being used.
Definition: ade9078.h:777
ADE9078_REG_BVRMS
#define ADE9078_REG_BVRMS
Definition: ade9078.h:143
ADE9078_HPF_2_49
@ ADE9078_HPF_2_49
Definition: ade9078.h:1023
ade9078_aregion_sel_e
ade9078_aregion_sel_e
ADE9078 These bits indicate which AIGAINx and APHCALx is currently being used.
Definition: ade9078.h:757
ADE9078_SELFREQ_60
@ ADE9078_SELFREQ_60
Definition: ade9078.h:872
ade9078_init_param::psm1_desc
struct no_os_gpio_desc * psm1_desc
Definition: ade9078.h:1158
ADE9078_ISUM_APROX_N_RMS
@ ADE9078_ISUM_APROX_N_RMS
Definition: ade9078.h:749
ADE9078_ACC_POSITIVE
@ ADE9078_ACC_POSITIVE
Definition: ade9078.h:903
ADE9078_NOLOAD_SAMPLES_256
@ ADE9078_NOLOAD_SAMPLES_256
Definition: ade9078.h:1043
ADE9078_PWR_SETTLE_0
@ ADE9078_PWR_SETTLE_0
Definition: ade9078.h:834
ade9078_dev::power_mode
uint8_t power_mode
Definition: ade9078.h:1185
ade9078_init_param::spi_init
struct no_os_spi_init_param * spi_init
Definition: ade9078.h:1154
ADE9078_FS_VOLTAGE
#define ADE9078_FS_VOLTAGE
Definition: ade9078.h:729
ADE9078_PKDET_LVL_900
@ ADE9078_PKDET_LVL_900
Definition: ade9078.h:1080
ADE9078_4WIRE_WYE
@ ADE9078_4WIRE_WYE
Definition: ade9078.h:881
no_os_test_bit
int no_os_test_bit(int pos, const volatile void *addr)
Definition: no_os_util.h:132
ade9078_pkdet_lvl_e
ade9078_pkdet_lvl_e
ADE9078 These bits configure the PSM2 low power comparator peak current detection Level,...
Definition: ade9078.h:1062
ADE9078_PKDET_LVL_1500
@ ADE9078_PKDET_LVL_1500
Definition: ade9078.h:1092
ADE9078_REG_VERSION
#define ADE9078_REG_VERSION
Definition: ade9078.h:275
ade9078_vconsel_e
ade9078_vconsel_e
ADE9078 3-wire and 4-wire hardware configuration selection.
Definition: ade9078.h:879
ADE9078_CIGAIN_CPHCAL_DISABLE
@ ADE9078_CIGAIN_CPHCAL_DISABLE
Definition: ade9078.h:809
errno.h
Error macro definition for ARM Compiler.
ADE9078_CF4_SEL_TOTAL_ACTIVE_P_2
@ ADE9078_CF4_SEL_TOTAL_ACTIVE_P_2
Definition: ade9078.h:861
ADE9078_BIGAIN_BPHCAL_2
@ ADE9078_BIGAIN_BPHCAL_2
Definition: ade9078.h:783
ADE9078_PKDET_LVL_200
@ ADE9078_PKDET_LVL_200
Definition: ade9078.h:1066
ade9078_set_power_mode
int ade9078_set_power_mode(struct ade9078_dev *dev)
Set power mode.
Definition: ade9078.c:129
ADE9078_PKDET_LVL_1400
@ ADE9078_PKDET_LVL_1400
Definition: ade9078.h:1090
ADE9078_3WIRE_DELTA
@ ADE9078_3WIRE_DELTA
Definition: ade9078.h:883
chip_id
chip_id
Definition: ad9172.h:51
no_os_spi_init_param
Structure holding the parameters for SPI initialization.
Definition: no_os_spi.h:140
ade9078_cregion_sel_e
ade9078_cregion_sel_e
ADE9078 These bits indicate which CIGAINx and CPHCALx is currently being used.
Definition: ade9078.h:797
ade9078_remove
int ade9078_remove(struct ade9078_dev *dev)
Remove the device and release resources.
Definition: ade9078.c:526
ADE9078_VC_GAIN_2
@ ADE9078_VC_GAIN_2
Definition: ade9078.h:1105