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#define | ADE9078_SPI_READ NO_OS_BIT(3) |
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#define | ENABLE 0x0001 |
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#define | DISABLE 0x0000 |
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#define | ADE9078_REG_AIGAIN 0x0000 |
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#define | ADE9078_REG_AIGAIN0 0x0001 |
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#define | ADE9078_REG_AIGAIN1 0x0002 |
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#define | ADE9078_REG_AIGAIN2 0x0003 |
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#define | ADE9078_REG_AIGAIN3 0x0004 |
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#define | ADE9078_REG_AIGAIN4 0x0005 |
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#define | ADE9078_REG_APHCAL0 0x0006 |
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#define | ADE9078_REG_APHCAL1 0x0007 |
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#define | ADE9078_REG_APHCAL2 0x0008 |
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#define | ADE9078_REG_APHCAL3 0x0009 |
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#define | ADE9078_REG_APHCAL4 0x000A |
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#define | ADE9078_REG_AVGAIN 0x000B |
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#define | ADE9078_REG_AIRMSOS 0x000C |
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#define | ADE9078_REG_AVRMSOS 0x000D |
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#define | ADE9078_REG_APGAIN 0x000E |
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#define | ADE9078_REG_AWATTOS 0x000F |
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#define | ADE9078_REG_AVAROS 0x0010 |
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#define | ADE9078_REG_AFVAROS 0x0012 |
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#define | ADE9078_REG_BIGAIN 0x0020 |
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#define | ADE9078_REG_BIGAIN0 0x0021 |
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#define | ADE9078_REG_BIGAIN1 0x0022 |
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#define | ADE9078_REG_BIGAIN2 0x0023 |
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#define | ADE9078_REG_BIGAIN3 0x0024 |
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#define | ADE9078_REG_BIGAIN4 0x0025 |
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#define | ADE9078_REG_BPHCAL0 0x0026 |
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#define | ADE9078_REG_BPHCAL1 0x0027 |
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#define | ADE9078_REG_BPHCAL2 0x0028 |
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#define | ADE9078_REG_BPHCAL3 0x0029 |
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#define | ADE9078_REG_BPHCAL4 0x002A |
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#define | ADE9078_REG_BVGAIN 0x002B |
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#define | ADE9078_REG_BIRMSOS 0x002C |
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#define | ADE9078_REG_BVRMSOS 0x002D |
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#define | ADE9078_REG_BPGAIN 0x002E |
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#define | ADE9078_REG_BWATTOS 0x002F |
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#define | ADE9078_REG_BVAROS 0x0030 |
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#define | ADE9078_REG_BFVAROS 0x0032 |
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#define | ADE9078_REG_CIGAIN 0x0040 |
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#define | ADE9078_REG_CIGAIN0 0x0041 |
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#define | ADE9078_REG_CIGAIN1 0x0042 |
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#define | ADE9078_REG_CIGAIN2 0x0043 |
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#define | ADE9078_REG_CIGAIN3 0x0044 |
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#define | ADE9078_REG_CIGAIN4 0x0045 |
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#define | ADE9078_REG_CPHCAL0 0x0046 |
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#define | ADE9078_REG_CPHCAL1 0x0047 |
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#define | ADE9078_REG_CPHCAL2 0x0048 |
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#define | ADE9078_REG_CPHCAL3 0x0049 |
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#define | ADE9078_REG_CPHCAL4 0x004A |
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#define | ADE9078_REG_CVGAIN 0x004B |
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#define | ADE9078_REG_CIRMSOS 0x004C |
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#define | ADE9078_REG_CVRMSOS 0x004D |
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#define | ADE9078_REG_CPGAIN 0x004E |
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#define | ADE9078_REG_CWATTOS 0x004F |
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#define | ADE9078_REG_CVAROS 0x0050 |
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#define | ADE9078_REG_CFVAROS 0x0052 |
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#define | ADE9078_REG_CONFIG0 0x0060 |
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#define | ADE9078_REG_MTTHR_L0 0x0061 |
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#define | ADE9078_REG_MTTHR_L1 0x0062 |
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#define | ADE9078_REG_MTTHR_L2 0x0063 |
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#define | ADE9078_REG_MTTHR_L3 0x0064 |
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#define | ADE9078_REG_MTTHR_L4 0x0065 |
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#define | ADE9078_REG_MTTHR_H0 0x0066 |
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#define | ADE9078_REG_MTTHR_H1 0x0067 |
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#define | ADE9078_REG_MTTHR_H2 0x0068 |
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#define | ADE9078_REG_MTTHR_H3 0x0069 |
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#define | ADE9078_REG_MTTHR_H4 0x006A |
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#define | ADE9078_REG_NIRMSOS 0x006B |
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#define | ADE9078_REG_ISUMRMSOS 0x006C |
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#define | ADE9078_REG_NIGAIN 0x006D |
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#define | ADE9078_REG_NPHCAL 0x006E |
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#define | ADE9078_REG_VNOM 0x0071 |
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#define | ADE9078_REG_DICOEFF 0x0072 |
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#define | ADE9078_REG_ISUMLVL 0x0073 |
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#define | ADE9078_REG_AI_PCF 0x020A |
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#define | ADE9078_REG_AV_PCF 0x020B |
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#define | ADE9078_REG_AIRMS 0x020C |
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#define | ADE9078_REG_AVRMS 0x020D |
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#define | ADE9078_REG_AWATT 0x0210 |
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#define | ADE9078_REG_AVAR 0x0211 |
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#define | ADE9078_REG_AVA 0x0212 |
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#define | ADE9078_REG_AFVAR 0x0214 |
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#define | ADE9078_REG_APF 0x0216 |
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#define | ADE9078_REG_AMTREGION 0x021D |
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#define | ADE9078_REG_BI_PCF 0x022A |
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#define | ADE9078_REG_BV_PCF 0x022B |
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#define | ADE9078_REG_BIRMS 0x022C |
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#define | ADE9078_REG_BVRMS 0x022D |
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#define | ADE9078_REG_BWATT 0x0230 |
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#define | ADE9078_REG_BVAR 0x0231 |
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#define | ADE9078_REG_BVA 0x0232 |
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#define | ADE9078_REG_BFVAR 0x0234 |
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#define | ADE9078_REG_BPF 0x0236 |
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#define | ADE9078_REG_BMTREGION 0x023D |
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#define | ADE9078_REG_CI_PCF 0x024A |
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#define | ADE9078_REG_CV_PCF 0x024B |
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#define | ADE9078_REG_CIRMS 0x024C |
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#define | ADE9078_REG_CVRMS 0x024D |
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#define | ADE9078_REG_CWATT 0x0250 |
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#define | ADE9078_REG_CVAR 0x0251 |
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#define | ADE9078_REG_CVA 0x0252 |
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#define | ADE9078_REG_CFVAR 0x0254 |
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#define | ADE9078_REG_CPF 0x0256 |
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#define | ADE9078_REG_CMTREGION 0x025D |
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#define | ADE9078_REG_NI_PCF 0x0265 |
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#define | ADE9078_REG_NIRMS 0x0266 |
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#define | ADE9078_REG_ISUMRMS 0x0269 |
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#define | ADE9078_REG_VERSION2 0x026A |
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#define | ADE9078_REG_AWATT_ACC 0x02E5 |
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#define | ADE9078_REG_AWATTHR_LO 0x02E6 |
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#define | ADE9078_REG_AWATTHR_HI 0x02E7 |
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#define | ADE9078_REG_AVAR_ACC 0x02EF |
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#define | ADE9078_REG_AVARHR_LO 0x02F0 |
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#define | ADE9078_REG_AVARHR_HI 0x02F1 |
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#define | ADE9078_REG_AVA_ACC 0x02F9 |
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#define | ADE9078_REG_AVAHR_LO 0x02FA |
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#define | ADE9078_REG_AVAHR_HI 0x02FB |
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#define | ADE9078_REG_AFVAR_ACC 0x030D |
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#define | ADE9078_REG_AFVARHR_LO 0x030E |
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#define | ADE9078_REG_AFVARHR_HI 0x030F |
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#define | ADE9078_REG_BWATT_ACC 0x0321 |
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#define | ADE9078_REG_BWATTHR_LO 0x0322 |
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#define | ADE9078_REG_BWATTHR_HI 0x0323 |
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#define | ADE9078_REG_BVAR_ACC 0x032B |
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#define | ADE9078_REG_BVARHR_LO 0x032C |
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#define | ADE9078_REG_BVARHR_HI 0x032D |
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#define | ADE9078_REG_BVA_ACC 0x0335 |
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#define | ADE9078_REG_BVAHR_LO 0x0336 |
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#define | ADE9078_REG_BVAHR_HI 0x0337 |
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#define | ADE9078_REG_BFVAR_ACC 0x0349 |
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#define | ADE9078_REG_BFVARHR_LO 0x034A |
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#define | ADE9078_REG_BFVARHR_HI 0x034B |
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#define | ADE9078_REG_CWATT_ACC 0x035D |
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#define | ADE9078_REG_CWATTHR_LO 0x035E |
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#define | ADE9078_REG_CWATTHR_HI 0x035F |
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#define | ADE9078_REG_CVAR_ACC 0x0367 |
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#define | ADE9078_REG_CVARHR_LO 0x0368 |
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#define | ADE9078_REG_CVARHR_HI 0x0369 |
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#define | ADE9078_REG_CVA_ACC 0x0371 |
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#define | ADE9078_REG_CVAHR_LO 0x0372 |
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#define | ADE9078_REG_CVAHR_HI 0x0373 |
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#define | ADE9078_REG_CFVAR_ACC 0x0385 |
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#define | ADE9078_REG_CFVARHR_LO 0x0386 |
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#define | ADE9078_REG_CFVARHR_HI 0x0387 |
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#define | ADE9078_REG_PWATT_ACC 0x0397 |
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#define | ADE9078_REG_NWATT_ACC 0x039B |
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#define | ADE9078_REG_PVAR_ACC 0x039F |
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#define | ADE9078_REG_NVAR_ACC 0x03A3 |
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#define | ADE9078_REG_IPEAK 0x0400 |
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#define | ADE9078_REG_VPEAK 0x0401 |
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#define | ADE9078_REG_STATUS0 0x0402 |
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#define | ADE9078_REG_STATUS1 0x0403 |
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#define | ADE9078_REG_EVENT_STATUS 0x0404 |
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#define | ADE9078_REG_MASK0 0x0405 |
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#define | ADE9078_REG_MASK1 0x0406 |
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#define | ADE9078_REG_EVENT_MASK 0x0407 |
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#define | ADE9078_REG_USER_PERIOD 0x040E |
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#define | ADE9078_REG_VLEVEL 0x040F |
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#define | ADE9078_REG_APERIOD 0x0418 |
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#define | ADE9078_REG_BPERIOD 0x0419 |
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#define | ADE9078_REG_CPERIOD 0x041A |
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#define | ADE9078_REG_COM_PERIOD 0x041B |
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#define | ADE9078_REG_ACT_NL_LVL 0x041C |
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#define | ADE9078_REG_REACT_NL_LVL 0x041D |
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#define | ADE9078_REG_APP_NL_LVL 0x041E |
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#define | ADE9078_REG_PHNOLOAD 0x041F |
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#define | ADE9078_REG_WTHR 0x0420 |
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#define | ADE9078_REG_VARTHR 0x0421 |
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#define | ADE9078_REG_VATHR 0x0422 |
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#define | ADE9078_REG_LAST_DATA_32 0x0423 |
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#define | ADE9078_REG_ADC_REDIRECT 0x0424 |
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#define | ADE9078_REG_CF_LCFG 0x0425 |
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#define | ADE9078_REG_PART_ID 0x0472 |
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#define | ADE9078_REG_RUN 0x0480 |
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#define | ADE9078_REG_CONFIG1 0x0481 |
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#define | ADE9078_REG_ANGL_VA_VB 0x0482 |
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#define | ADE9078_REG_ANGL_VB_VC 0x0483 |
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#define | ADE9078_REG_ANGL_VA_VC 0x0484 |
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#define | ADE9078_REG_ANGL_VA_IA 0x0485 |
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#define | ADE9078_REG_ANGL_VB_IB 0x0486 |
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#define | ADE9078_REG_ANGL_VC_IC 0x0487 |
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#define | ADE9078_REG_ANGL_IA_IB 0x0488 |
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#define | ADE9078_REG_ANGL_IB_IC 0x0489 |
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#define | ADE9078_REG_ANGL_IA_IC 0x048A |
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#define | ADE9078_REG_CFMODE 0x0490 |
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#define | ADE9078_REG_COMPMODE 0x0491 |
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#define | ADE9078_REG_ACCMODE 0x0492 |
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#define | ADE9078_REG_CONFIG3 0x0493 |
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#define | ADE9078_REG_CF1DEN 0x0494 |
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#define | ADE9078_REG_CF2DEN 0x0495 |
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#define | ADE9078_REG_CF3DEN 0x0496 |
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#define | ADE9078_REG_CF4DEN 0x0497 |
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#define | ADE9078_REG_ZXTOUT 0x0498 |
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#define | ADE9078_REG_ZXTHRSH 0x0499 |
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#define | ADE9078_REG_ZX_LP_SEL 0x049A |
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#define | ADE9078_REG_SEQ_CYC 0x049C |
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#define | ADE9078_REG_PHSIGN 0x049D |
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#define | ADE9078_REG_WFB_CFG 0x04A0 |
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#define | ADE9078_REG_WFB_PG_IRQEN 0x04A1 |
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#define | ADE9078_REG_WFB_TRG_CFG 0x04A2 |
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#define | ADE9078_REG_WFB_TRG_STAT 0x04A3 |
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#define | ADE9078_REG_CONFIG5 0x04A4 |
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#define | ADE9078_REG_CRC_RSLT 0x04A8 |
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#define | ADE9078_REG_CRC_SPI 0x04A9 |
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#define | ADE9078_REG_LAST_DATA_16 0x04AC |
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#define | ADE9078_REG_LAST_CMD 0x04AE |
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#define | ADE9078_REG_CONFIG2 0x04AF |
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#define | ADE9078_REG_EP_CFG 0x04B0 |
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#define | ADE9078_REG_PWR_TIME 0x04B1 |
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#define | ADE9078_REG_EGY_TIME 0x04B2 |
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#define | ADE9078_REG_CRC_FORCE 0x04B4 |
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#define | ADE9078_REG_CRC_OPTEN 0x04B5 |
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#define | ADE9078_REG_TEMP_CFG 0x04B6 |
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#define | ADE9078_REG_PSM2_CFG 0x04B8 |
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#define | ADE9078_REG_PGA_GAIN 0x04B9 |
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#define | ADE9078_REG_CHNL_DIS 0x04BA |
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#define | ADE9078_REG_WR_LOCK 0x04BF |
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#define | ADE9078_REG_VAR_DIS 0x04E0 |
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#define | ADE9078_REG_RESERVED1 0x04F0 |
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#define | ADE9078_REG_VERSION 0x04FE |
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#define | ADE9078_REG_AI_SINC_DAT 0x0500 |
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#define | ADE9078_REG_AV_SINC_DAT 0x0501 |
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#define | ADE9078_REG_BI_SINC_DAT 0x0502 |
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#define | ADE9078_REG_BV_SINC_DAT 0x0503 |
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#define | ADE9078_REG_CI_SINC_DAT 0x0504 |
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#define | ADE9078_REG_CV_SINC_DAT 0x0505 |
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#define | ADE9078_REG_NI_SINC_DAT 0x0506 |
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#define | ADE9078_REG_AI_LPF_DAT 0x0510 |
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#define | ADE9078_REG_AV_LPF_DAT 0x0511 |
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#define | ADE9078_REG_BI_LPF_DAT 0x0512 |
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#define | ADE9078_REG_BV_LPF_DAT 0x0513 |
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#define | ADE9078_REG_CI_LPF_DAT 0x0514 |
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#define | ADE9078_REG_CV_LPF_DAT 0x0515 |
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#define | ADE9078_REG_NI_LPF_DAT 0x0516 |
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#define | ADE9078_REG_AV_PCF_1 0x0600 |
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#define | ADE9078_REG_BV_PCF_1 0x0601 |
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#define | ADE9078_REG_CV_PCF_1 0x0602 |
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#define | ADE9078_REG_NI_PCF_1 0x0603 |
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#define | ADE9078_REG_AI_PCF_1 0x0604 |
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#define | ADE9078_REG_BI_PCF_1 0x0605 |
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#define | ADE9078_REG_CI_PCF_1 0x0606 |
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#define | ADE9078_REG_AIRMS_1 0x0607 |
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#define | ADE9078_REG_BIRMS_1 0x0608 |
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#define | ADE9078_REG_CIRMS_1 0x0609 |
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#define | ADE9078_REG_AVRMS_1 0x060A |
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#define | ADE9078_REG_BVRMS_1 0x060B |
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#define | ADE9078_REG_CVRMS_1 0x060C |
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#define | ADE9078_REG_NIRMS_1 0x060D |
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#define | ADE9078_REG_AWATT_1 0x060E |
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#define | ADE9078_REG_BWATT_1 0x060F |
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#define | ADE9078_REG_CWATT_1 0x0610 |
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#define | ADE9078_REG_AVA_1 0x0611 |
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#define | ADE9078_REG_BVA_1 0x0612 |
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#define | ADE9078_REG_CVA_1 0x0613 |
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#define | ADE9078_REG_AVAR_1 0x0614 |
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#define | ADE9078_REG_BVAR_1 0x0615 |
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#define | ADE9078_REG_CVAR_1 0x0616 |
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#define | ADE9078_REG_AFVAR_1 0x0617 |
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#define | ADE9078_REG_BFVAR_1 0x0618 |
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#define | ADE9078_REG_CFVAR_1 0x0619 |
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#define | ADE9078_REG_APF_1 0x061A |
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#define | ADE9078_REG_BPF_1 0x061B |
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#define | ADE9078_REG_CPF_1 0x061C |
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#define | ADE9078_REG_AV_PCF_2 0x0680 |
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#define | ADE9078_REG_AI_PCF_2 0x0681 |
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#define | ADE9078_REG_AIRMS_2 0x0682 |
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#define | ADE9078_REG_AVRMS_2 0x0683 |
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#define | ADE9078_REG_AWATT_2 0x0684 |
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#define | ADE9078_REG_AVA_2 0x0685 |
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#define | ADE9078_REG_AVAR_2 0x0686 |
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#define | ADE9078_REG_AFVAR_2 0x0687 |
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#define | ADE9078_REG_APF_2 0x0688 |
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#define | ADE9078_REG_BV_PCF_2 0x0693 |
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#define | ADE9078_REG_BI_PCF_2 0x0694 |
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#define | ADE9078_REG_BIRMS_2 0x0695 |
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#define | ADE9078_REG_BVRMS_2 0x0696 |
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#define | ADE9078_REG_BWATT_2 0x0697 |
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#define | ADE9078_REG_BVA_2 0x0698 |
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#define | ADE9078_REG_BVAR_2 0x0699 |
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#define | ADE9078_REG_BFVAR_2 0x069A |
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#define | ADE9078_REG_BPF_2 0x069B |
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#define | ADE9078_REG_CV_PCF_2 0x06A6 |
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#define | ADE9078_REG_CI_PCF_2 0x06A7 |
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#define | ADE9078_REG_CIRMS_2 0x06A8 |
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#define | ADE9078_REG_CVRMS_2 0x06A9 |
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#define | ADE9078_REG_CWATT_2 0x06AA |
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#define | ADE9078_REG_CVA_2 0x06AB |
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#define | ADE9078_REG_CVAR_2 0x06AC |
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#define | ADE9078_REG_CFVAR_2 0x06AD |
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#define | ADE9078_REG_CPF_2 0x06AE |
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#define | ADE9078_REG_NI_PCF_2 0x06B9 |
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#define | ADE9078_REG_NIRMS_2 0x06BA |
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#define | ADE9078_DISRPLPF NO_OS_BIT(13) |
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#define | ADE9078_DISAPLPF NO_OS_BIT(12) |
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#define | ADE9078_ININTEN NO_OS_BIT(11) |
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#define | ADE9078_VNOMC_EN NO_OS_BIT(10) |
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#define | ADE9078_VNOMB_EN NO_OS_BIT(9) |
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#define | ADE9078_VNOMA_EN NO_OS_BIT(8) |
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#define | ADE9078_ZX_SRC_SEL NO_OS_BIT(6) |
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#define | ADE9078_INTEN NO_OS_BIT(5) |
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#define | ADE9078_MTEN NO_OS_BIT(4) |
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#define | ADE9078_HPFDIS NO_OS_BIT(3) |
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#define | ADE9078_ISUM_CFG NO_OS_GENMASK(1, 0) |
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#define | ADE9078_AREGION NO_OS_GENMASK(3, 0) |
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#define | ADE9078_BREGION NO_OS_GENMASK(3, 0) |
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#define | ADE9078_CREGION NO_OS_GENMASK(3, 0) |
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#define | ADE9078_IPPHASE NO_OS_GENMASK(26, 24) |
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#define | ADE9078_IPEAKVAL NO_OS_GENMASK(23, 0) |
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#define | ADE9078_VPPHASE NO_OS_GENMASK(26, 24) |
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#define | ADE9078_VPEAKVAL NO_OS_GENMASK(23, 0) |
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#define | ADE9078_STATUS0_MISMTCH NO_OS_BIT(24) |
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#define | ADE9078_STATUS0_COH_WFB_FULL NO_OS_BIT(23) |
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#define | ADE9078_STATUS0_WFB_TRIG NO_OS_BIT(22) |
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#define | ADE9078_STATUS0_PF_RDY NO_OS_BIT(21) |
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#define | ADE9078_STATUS0_PWRRDY NO_OS_BIT(18) |
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#define | ADE9078_STATUS0_PAGE_FULL NO_OS_BIT(17) |
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#define | ADE9078_STATUS0_WFB_TRIG_IRQ NO_OS_BIT(16) |
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#define | ADE9078_STATUS0_DREADY NO_OS_BIT(15) |
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#define | ADE9078_STATUS0_CF4 NO_OS_BIT(14) |
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#define | ADE9078_STATUS0_CF3 NO_OS_BIT(13) |
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#define | ADE9078_STATUS0_CF2 NO_OS_BIT(12) |
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#define | ADE9078_STATUS0_CF1 NO_OS_BIT(11) |
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#define | ADE9078_STATUS0_REVPSUM4 NO_OS_BIT(10) |
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#define | ADE9078_STATUS0_REVPSUM3 NO_OS_BIT(9) |
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#define | ADE9078_STATUS0_REVPSUM2 NO_OS_BIT(8) |
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#define | ADE9078_STATUS0_REVPSUM1 NO_OS_BIT(7) |
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#define | ADE9078_STATUS0_REVRPC NO_OS_BIT(6) |
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#define | ADE9078_STATUS0_REVRPB NO_OS_BIT(5) |
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#define | ADE9078_STATUS0_REVRPA NO_OS_BIT(4) |
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#define | ADE9078_STATUS0_REVAPC NO_OS_BIT(3) |
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#define | ADE9078_STATUS0_REVAPB NO_OS_BIT(2) |
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#define | ADE9078_STATUS0_REVAPA NO_OS_BIT(1) |
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#define | ADE9078_STATUS0_EGYRDY NO_OS_BIT(0) |
|
#define | ADE9078_STATUS1_ERROR3 NO_OS_BIT(31) |
|
#define | ADE9078_STATUS1_ERROR2 NO_OS_BIT(30) |
|
#define | ADE9078_STATUS1_ERROR1 NO_OS_BIT(29) |
|
#define | ADE9078_STATUS1_ERROR0 NO_OS_BIT(28) |
|
#define | ADE9078_STATUS1_CRC_DONE NO_OS_BIT(27) |
|
#define | ADE9078_STATUS1_CRC_CHG NO_OS_BIT(26) |
|
#define | ADE9078_STATUS1_SEQERR NO_OS_BIT(18) |
|
#define | ADE9078_STATUS1_RSTDONE NO_OS_BIT(16) |
|
#define | ADE9078_STATUS1_ZXIC NO_OS_BIT(15) |
|
#define | ADE9078_STATUS1_ZXIB NO_OS_BIT(14) |
|
#define | ADE9078_STATUS1_ZXIA NO_OS_BIT(13) |
|
#define | ADE9078_STATUS1_ZXCOMB NO_OS_BIT(12) |
|
#define | ADE9078_STATUS1_ZXVC NO_OS_BIT(11) |
|
#define | ADE9078_STATUS1_ZXVB NO_OS_BIT(10) |
|
#define | ADE9078_STATUS1_ZXVA NO_OS_BIT(9) |
|
#define | ADE9078_STATUS1_ZXTOVC NO_OS_BIT(8) |
|
#define | ADE9078_STATUS1_ZXTOVB NO_OS_BIT(7) |
|
#define | ADE9078_STATUS1_ZXTOVA NO_OS_BIT(6) |
|
#define | ADE9078_STATUS1_RFNOLOAD NO_OS_BIT(4) |
|
#define | ADE9078_STATUS1_VANLOAD NO_OS_BIT(2) |
|
#define | ADE9078_STATUS1_RNLOAD NO_OS_BIT(1) |
|
#define | ADE9078_STATUS1_ANLOAD NO_OS_BIT(0) |
|
#define | ADE9078_EVENT_DREADY NO_OS_BIT(16) |
|
#define | ADE9078_EVENT_RFNOLOAD NO_OS_BIT(14) |
|
#define | ADE9078_EVENT_VANLOAD NO_OS_BIT(12) |
|
#define | ADE9078_EVENT_RNLOAD NO_OS_BIT(11) |
|
#define | ADE9078_EVENT_ANLOAD NO_OS_BIT(10) |
|
#define | ADE9078_EVENT_REVPSUM4 NO_OS_BIT(9) |
|
#define | ADE9078_EVENT_REVPSUM3 NO_OS_BIT(8) |
|
#define | ADE9078_EVENT_REVPSUM2 NO_OS_BIT(7) |
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#define | ADE9078_EVENT_REVPSUM1 NO_OS_BIT(6) |
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#define | ADE9078_MASK0_MISMTCH NO_OS_BIT(24) |
|
#define | ADE9078_MASK0_COH_WFB_FULL NO_OS_BIT(23) |
|
#define | ADE9078_MASK0_WFB_TRIG NO_OS_BIT(22) |
|
#define | ADE9078_MASK0_THD_PF_RDY NO_OS_BIT(21) |
|
#define | ADE9078_MASK0_PWRRDY NO_OS_BIT(18) |
|
#define | ADE9078_MASK0_PAGE_FULL NO_OS_BIT(17) |
|
#define | ADE9078_MASK0_WFB_TRIG_IRQ NO_OS_BIT(16) |
|
#define | ADE9078_MASK0_DREADY NO_OS_BIT(15) |
|
#define | ADE9078_MASK0_CF4 NO_OS_BIT(14) |
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#define | ADE9078_MASK0_CF3 NO_OS_BIT(13) |
|
#define | ADE9078_MASK0_CF2 NO_OS_BIT(12) |
|
#define | ADE9078_MASK0_CF1 NO_OS_BIT(11) |
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#define | ADE9078_MASK0_REVPSUM4 NO_OS_BIT(10) |
|
#define | ADE9078_MASK0_REVPSUM3 NO_OS_BIT(9) |
|
#define | ADE9078_MASK0_REVPSUM2 NO_OS_BIT(8) |
|
#define | ADE9078_MASK0_REVPSUM1 NO_OS_BIT(7) |
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#define | ADE9078_MASK0_REVRPC NO_OS_BIT(6) |
|
#define | ADE9078_MASK0_REVRPB NO_OS_BIT(5) |
|
#define | ADE9078_MASK0_REVRPA NO_OS_BIT(4) |
|
#define | ADE9078_MASK0_REVAPC NO_OS_BIT(3) |
|
#define | ADE9078_MASK0_REVAPB NO_OS_BIT(2) |
|
#define | ADE9078_MASK0_REVAPA NO_OS_BIT(1) |
|
#define | ADE9078_MASK0_EGYRDY NO_OS_BIT(0) |
|
#define | ADE9078_MASK1_ERROR3 NO_OS_BIT(31) |
|
#define | ADE9078_MASK1_ERROR2 NO_OS_BIT(30) |
|
#define | ADE9078_MASK1_ERROR1 NO_OS_BIT(29) |
|
#define | ADE9078_MASK1_ERROR0 NO_OS_BIT(28) |
|
#define | ADE9078_MASK1_CRC_DONE NO_OS_BIT(27) |
|
#define | ADE9078_MASK1_CRC_CHG NO_OS_BIT(26) |
|
#define | ADE9078_MASK1_SEQERR NO_OS_BIT(18) |
|
#define | ADE9078_MASK1_ZXIC NO_OS_BIT(15) |
|
#define | ADE9078_MASK1_ZXIB NO_OS_BIT(14) |
|
#define | ADE9078_MASK1_ZXIA NO_OS_BIT(13) |
|
#define | ADE9078_MASK1_ZXCOMB NO_OS_BIT(12) |
|
#define | ADE9078_MASK1_ZXVC NO_OS_BIT(11) |
|
#define | ADE9078_MASK1_ZXVB NO_OS_BIT(10) |
|
#define | ADE9078_MASK1_ZXVA NO_OS_BIT(9) |
|
#define | ADE9078_MASK1_ZXTOVC NO_OS_BIT(8) |
|
#define | ADE9078_MASK1_ZXTOVB NO_OS_BIT(7) |
|
#define | ADE9078_MASK1_ZXTOVA NO_OS_BIT(6) |
|
#define | ADE9078_MASK1_RFNOLOAD NO_OS_BIT(4) |
|
#define | ADE9078_MASK1_VANLOAD NO_OS_BIT(2) |
|
#define | ADE9078_MASK1_RNLOAD NO_OS_BIT(1) |
|
#define | ADE9078_MASK1_ANLOAD NO_OS_BIT(0) |
|
#define | ADE9078_EVENT_DREADY_MSK NO_OS_BIT(16) |
|
#define | ADE9078_EVENT_RFNOLOAD_MSK NO_OS_BIT(14) |
|
#define | ADE9078_EVENT_VANLOAD_MSK NO_OS_BIT(12) |
|
#define | ADE9078_EVENT_RNLOAD_MSK NO_OS_BIT(11) |
|
#define | ADE9078_EVENT_ANLOAD_MSK NO_OS_BIT(10) |
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#define | ADE9078_EVENT_REVPSUM4_MSK NO_OS_BIT(9) |
|
#define | ADE9078_EVENT_REVPSUM3_MSK NO_OS_BIT(8) |
|
#define | ADE9078_EVENT_REVPSUM2_MSK NO_OS_BIT(7) |
|
#define | ADE9078_EVENT_REVPSUM1_MSK NO_OS_BIT(6) |
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#define | ADE9078_VLEVEL_VAL NO_OS_GENMASK(23, 0) |
|
#define | ADE9078_CFVARNL NO_OS_BIT(16) |
|
#define | ADE9078_CVANL NO_OS_BIT(14) |
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#define | ADE9078_CVARNL NO_OS_BIT(13) |
|
#define | ADE9078_CWATTNL NO_OS_BIT(12) |
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#define | ADE9078_BFVARNL NO_OS_BIT(10) |
|
#define | ADE9078_BVANL NO_OS_BIT(8) |
|
#define | ADE9078_BVARNL NO_OS_BIT(7) |
|
#define | ADE9078_BWATTNL NO_OS_BIT(6) |
|
#define | ADE9078_AFVARNL NO_OS_BIT(4) |
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#define | ADE9078_AVANL NO_OS_BIT(2) |
|
#define | ADE9078_AVARNL NO_OS_BIT(1) |
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#define | ADE9078_AWATTNL NO_OS_BIT(0) |
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#define | ADE9078_VC_DIN NO_OS_GENMASK(20, 18) |
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#define | ADE9078_VB_DIN NO_OS_GENMASK(17, 15) |
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#define | ADE9078_VA_DIN NO_OS_GENMASK(14, 12) |
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#define | ADE9078_IN_DIN NO_OS_GENMASK(11, 9) |
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#define | ADE9078_IC_DIN NO_OS_GENMASK(8, 6) |
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#define | ADE9078_IB_DIN NO_OS_GENMASK(5, 3) |
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#define | ADE9078_IA_DIN NO_OS_GENMASK(2, 0) |
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#define | ADE9078_CF4_LT NO_OS_BIT(22) |
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#define | ADE9078_CF3_LT NO_OS_BIT(21) |
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#define | ADE9078_CF2_LT NO_OS_BIT(20) |
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#define | ADE9078_CF1_LT NO_OS_BIT(19) |
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#define | ADE9078_CF_LTMR NO_OS_GENMASK(18, 0) |
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#define | ADE9078_AD73370_ID NO_OS_BIT(21) |
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#define | ADE9078_ADE9000_ID NO_OS_BIT(20) |
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#define | ADE9078_ADE9004_ID NO_OS_BIT(16) |
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#define | ADE9078_EXT_REF NO_OS_BIT(15) |
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#define | ADE9078_IRQ0_ON_IRQ1 NO_OS_BIT(12) |
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#define | ADE9078_BURST_EN NO_OS_BIT(11) |
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#define | ADE9078_PWR_SETTLE NO_OS_GENMASK(9, 8) |
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#define | ADE9078_CF_ACC_CLR NO_OS_BIT(5) |
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#define | ADE9078_CF4_CFG NO_OS_GENMASK(3, 2) |
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#define | ADE9078_CF3_CFG NO_OS_BIT(1) |
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#define | ADE9078_SWRST NO_OS_BIT(0) |
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#define | ADE9078_CF4DIS NO_OS_BIT(15) |
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#define | ADE9078_CF3DIS NO_OS_BIT(14) |
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#define | ADE9078_CF2DIS NO_OS_BIT(13) |
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#define | ADE9078_CF1DIS NO_OS_BIT(12) |
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#define | ADE9078_CF4SEL NO_OS_GENMASK(11, 9) |
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#define | ADE9078_CF3SEL NO_OS_GENMASK(8, 6) |
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#define | ADE9078_CF2SEL NO_OS_GENMASK(5, 3) |
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#define | ADE9078_CF1SEL NO_OS_GENMASK(2, 0) |
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#define | ADE9078_TERMSEL4 NO_OS_GENMASK(11, 9) |
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#define | ADE9078_TERMSEL3 NO_OS_GENMASK(8, 6) |
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#define | ADE9078_TERMSEL2 NO_OS_GENMASK(5, 3) |
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#define | ADE9078_TERMSEL1 NO_OS_GENMASK(2, 0) |
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#define | ADE9078_SELFREQ NO_OS_BIT(8) |
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#define | ADE9078_ICONSEL NO_OS_BIT(7) |
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#define | ADE9078_VCONSEL NO_OS_GENMASK(6, 4) |
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#define | ADE9078_VARACC NO_OS_GENMASK(3, 2) |
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#define | ADE9078_WATTACC NO_OS_GENMASK(1, 0) |
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#define | ADE9078_PEAKSEL NO_OS_GENMASK(4, 2) |
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#define | ADE9078_LP_SEL NO_OS_GENMASK(4, 3) |
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#define | ADE9078_ZX_SEL NO_OS_GENMASK(2, 1) |
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#define | ADE9078_SUM4SIGN NO_OS_BIT(9) |
|
#define | ADE9078_SUM3SIGN NO_OS_BIT(8) |
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#define | ADE9078_SUM2SIGN NO_OS_BIT(7) |
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#define | ADE9078_SUM1SIGN NO_OS_BIT(6) |
|
#define | ADE9078_CVARSIGN NO_OS_BIT(5) |
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#define | ADE9078_CWSIGN NO_OS_BIT(4) |
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#define | ADE9078_BVARSIGN NO_OS_BIT(3) |
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#define | ADE9078_BWSIGN NO_OS_BIT(2) |
|
#define | ADE9078_AVARSIGN NO_OS_BIT(1) |
|
#define | ADE9078_AWSIGN NO_OS_BIT(0) |
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#define | ADE9078_WF_IN_EN NO_OS_BIT(12) |
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#define | ADE9078_WF_SRC NO_OS_GENMASK(9, 8) |
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#define | ADE9078_WF_MODE NO_OS_BIT(7, 6) |
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#define | ADE9078_WF_CAP_SEL NO_OS_BIT(5) |
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#define | ADE9078_WF_CAP_EN NO_OS_BIT(4) |
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#define | ADE9078_BURST_CHAN NO_OS_GENMASK(3, 0) |
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#define | ADE9078_TRIG_FORCE NO_OS_BIT(10) |
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#define | ADE9078_ZXCOMB NO_OS_BIT(9) |
|
#define | ADE9078_ZXVC NO_OS_BIT(8) |
|
#define | ADE9078_ZXVB NO_OS_BIT(7) |
|
#define | ADE9078_ZXVA NO_OS_BIT(6) |
|
#define | ADE9078_ZXIC NO_OS_BIT(5) |
|
#define | ADE9078_ZXIB NO_OS_BIT(4) |
|
#define | ADE9078_ZXIA NO_OS_BIT(3) |
|
#define | ADE9078_WFB_LAST_PAGE NO_OS_GENMASK(15, 12) |
|
#define | ADE9078_WFB_TRIG_ADDR NO_OS_GENMASK(10, 0) |
|
#define | ADE9078_UPERIOD_SEL NO_OS_BIT(12) |
|
#define | ADE9078_HPF_CRN NO_OS_GENMASK(11, 9) |
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#define | ADE9078_NOLOAD_TMR NO_OS_GENMASK(15, 13) |
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#define | ADE9078_PWR_SIGN_SEL_1 NO_OS_BIT(7) |
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#define | ADE9078_RD_RST_EN NO_OS_BIT(5) |
|
#define | ADE9078_EGY_LD_ACCUM NO_OS_BIT(4) |
|
#define | ADE9078_EGY_TMR_MODE NO_OS_BIT(1) |
|
#define | ADE9078_EGY_PWR_EN NO_OS_BIT(0) |
|
#define | ADE9078_FORCE_CRC_UPDATE NO_OS_BIT(0) |
|
#define | ADE9078_CRC_WFB_TRG_CFG_EN NO_OS_BIT(15) |
|
#define | ADE9078_CRC_WFB_PG_IRQEN NO_OS_BIT(14) |
|
#define | ADE9078_CRC_WFB_CFG_EN NO_OS_BIT(13) |
|
#define | ADE9078_CRC_SEQ_CYC_EN NO_OS_BIT(12) |
|
#define | ADE9078_CRC_ZXLPSEL_EN NO_OS_BIT(11) |
|
#define | ADE9078_CRC_ZXTOUT_EN NO_OS_BIT(10) |
|
#define | ADE9078_CRC_APP_NL_LVL_EN NO_OS_BIT(9) |
|
#define | ADE9078_CRC_REACT_NL_LVL_EN NO_OS_BIT(8) |
|
#define | ADE9078_CRC_ACT_NL_LVL_EN NO_OS_BIT(7) |
|
#define | ADE9078_CRC_EVENT_MASK_EN NO_OS_BIT(2) |
|
#define | ADE9078_CRC_MASK1_EN NO_OS_BIT(1) |
|
#define | ADE9078_CRC_MASK0_EN NO_OS_BIT(0) |
|
#define | ADE9078_PKDET_LVL NO_OS_BIT(8, 5) |
|
#define | ADE9078_LPLINE NO_OS_BIT(4, 0) |
|
#define | ADE9078_VC_GAIN NO_OS_GENMASK(13, 12) |
|
#define | ADE9078_VB_GAIN NO_OS_GENMASK(11, 10) |
|
#define | ADE9078_VA_GAIN NO_OS_GENMASK(9, 8) |
|
#define | ADE9078_IN_GAIN NO_OS_GENMASK(7, 6) |
|
#define | ADE9078_IC_GAIN NO_OS_GENMASK(5, 4) |
|
#define | ADE9078_IB_GAIN NO_OS_GENMASK(3, 2) |
|
#define | ADE9078_IA_GAIN NO_OS_GENMASK(1, 0) |
|
#define | ADE9078_VC_DISADC NO_OS_BIT(6) |
|
#define | ADE9078_VB_DISADC NO_OS_BIT(5) |
|
#define | ADE9078_VA_DISADC NO_OS_BIT(4) |
|
#define | ADE9078_IN_DISADC NO_OS_BIT(3) |
|
#define | ADE9078_IC_DISADC NO_OS_BIT(2) |
|
#define | ADE9078_IB_DISADC NO_OS_BIT(1) |
|
#define | ADE9078_IA_DISADC NO_OS_BIT(0) |
|
#define | ADE9078_VARDIS NO_OS_BIT(0) |
|
#define | ADE9078_CHIP_ID 0x63 |
|
#define | ADE9078_PART_ID 0 |
|
#define | ADE9078_RESET_RECOVER 100 |
|
#define | ADE9078_PGA_GAIN 0x0000 |
|
#define | ADE9078_CONFIG0 0x00000000 |
|
#define | ADE9078_CONFIG1 0x0002 |
|
#define | ADE9078_CONFIG2 0x0A00 |
|
#define | ADE9078_CONFIG3 0x0000 |
|
#define | ADE9078_ACCMODE 0x0000 |
|
#define | ADE9078_ZX_LP_SEL 0x001E |
|
#define | ADE9078_MASK0 0x00000001 |
|
#define | ADE9078_MASK1 0x00000000 |
|
#define | ADE9078_EVENT_MASK 0x00000000 |
|
#define | ADE9078_VLEVEL 0x00117514 |
|
#define | ADE9078_DICOEFF 0x00000000 |
|
#define | ADE9078_RUN_ON 0x0001 |
|
#define | ADE9078_EP_CFG 0x0001 |
|
#define | ADE9078_EGY_TIME 0x1F3F |
|
#define | ADE9078_WFB_CFG 0x1000 |
|
#define | WFB_ELEMENT_ARRAY_SIZE 512 |
|
#define | ADE9078_RMS_FS_CODES 52866837 |
|
#define | ADE9078_WATT_FS_CODES 20823646 |
|
#define | ADE9078_BURDEN_RES 10 |
|
#define | ADE9078_CURRENT_TR_RATIO 1000 |
|
#define | ADE9078_CURRENT_TR_FCN (ADE9078_CURRENT_TR_RATIO / ADE9078_BURDEN_RES) |
|
#define | ADE9078_UP_RES 990000 |
|
#define | ADE9078_DOWN_RES 1000 |
|
#define | ADE9078_VOLTAGE_TR_FCN ((ADE9078_DOWN_RES + ADE9078_UP_RES) / ADE9078_DOWN_RES) |
|
#define | ADE9078_FS_VOLTAGE 707 |
|
|
enum | ade9078_isum_cfg_e {
ADE9078_ISUM_APROX_N,
ADE9078_ISUM_DET_MISM_POS,
ADE9078_ISUM_DET_MISM_NEG,
ADE9078_ISUM_APROX_N_RMS
} |
| ADE9078 isum calculation configuration. More...
|
|
enum | ade9078_aregion_sel_e {
ADE9078_AIGAIN_APHCAL_0,
ADE9078_AIGAIN_APHCAL_1,
ADE9078_AIGAIN_APHCAL_2,
ADE9078_AIGAIN_APHCAL_3,
ADE9078_AIGAIN_APHCAL_4,
ADE9078_AIGAIN_APHCAL_DISABLE = 15
} |
| ADE9078 These bits indicate which AIGAINx and APHCALx is currently being used. More...
|
|
enum | ade9078_bregion_sel_e {
ADE9078_BIGAIN_BPHCAL_0,
ADE9078_BIGAIN_BPHCAL_1,
ADE9078_BIGAIN_BPHCAL_2,
ADE9078_BIGAIN_BPHCAL_3,
ADE9078_BIGAIN_BPHCAL_4,
ADE9078_BIGAIN_BPHCAL_DISABLE = 15
} |
| ADE9078 These bits indicate which BIGAINx and BPHCALx is currently being used. More...
|
|
enum | ade9078_cregion_sel_e {
ADE9078_CIGAIN_CPHCAL_0,
ADE9078_CIGAIN_CPHCAL_1,
ADE9078_CIGAIN_CPHCAL_2,
ADE9078_CIGAIN_CPHCAL_3,
ADE9078_CIGAIN_CPHCAL_4,
ADE9078_CIGAIN_CPHCAL_DISABLE = 15
} |
| ADE9078 These bits indicate which CIGAINx and CPHCALx is currently being used. More...
|
|
enum | ade9078_cf4_pin_out_cfg_e {
ADE9078_CF4_D_F_CONV,
ADE9078_CF4_D_F_CONV2,
ADE9078_CF4_EVENT,
ADE9078_CF4_DREADY
} |
| ADE9078 These bits indicate which function to output on CF4 pin. More...
|
|
enum | ade9078_pwr_settle_e {
ADE9078_PWR_SETTLE_0,
ADE9078_PWR_SETTLE_1,
ADE9078_PWR_SETTLE_2,
ADE9078_PWR_SETTLE_3
} |
| ADE9078 Power settle time. More...
|
|
enum | ade9078_cf4_sel_e {
ADE9078_CF4_SEL_ACTIV_P,
ADE9078_CF4_SEL_REACTIV_P,
ADE9078_CF4_SEL_APPARENT_P,
ADE9078_CF4_SEL_FUN_REACTIVE_P = 4,
ADE9078_CF4_SEL_TOTAL_ACTIVE_P = 6,
ADE9078_CF4_SEL_TOTAL_ACTIVE_P_2
} |
| ADE9078 Type of energy output on the CF4 pin. Configure TERMSEL4 in the COMPMODE register to select which phases are included. More...
|
|
enum | ade9078_freq_sel_e {
ADE9078_SELFREQ_50,
ADE9078_SELFREQ_60
} |
| ADE9078 Freq value. More...
|
|
enum | ade9078_vconsel_e {
ADE9078_4WIRE_WYE,
ADE9078_3WIRE_DELTA,
ADE9078_4WIRE_WYE_VA_VC,
ADE9078_4WIRE_WYE_VA,
ADE9078_3WIRE_DELTA_2
} |
| ADE9078 3-wire and 4-wire hardware configuration selection. More...
|
|
enum | ade9078_var_acc_mode_e {
ADE9078_ACC_SIGNED,
ADE9078_ACC_ABSOLUTE,
ADE9078_ACC_POSITIVE,
ADE9078_ACC_NEGATIVE
} |
| ADE9078 Total and fundamental reactive power accumulation mode for energy registers and CFx pulses. More...
|
|
enum | ade9078_line_period_sel_e {
ADE9078_APERIOD,
ADE9078_BPERIOD,
ADE9078_CPERIOD,
ADE9078_COM_PERIOD
} |
| Selects line period measurement used for VRMS½ cycle, 10 cycle rms/12 cycle rms, and resampling. More...
|
|
enum | ade9078_zx_select_e {
ADE9078_ZXVA_SEL,
ADE9078_ZXVB_SEL,
ADE9078_ZXVC_SEL,
ADE9078_ZXCOMB_SEL
} |
| Selects the zero-crossing signal, which can be routed to the CF3/ZX output pin and used for line cycle energy accumulation. More...
|
|
enum | ade9078_wf_src_e {
ADE9078_SRC_SINC4,
ADE9078_SRC_SINC4_IIR = 2,
ADE9078_SRC_DSP
} |
| Waveform buffer source and DREADY (data ready update rate) selection. More...
|
|
enum | ade9078_wf_mode_e {
ADE9078_MODE_STOP_FULL,
ADE9078_MODE_TRIG_EN_EVENTS,
ADE9078_MODE_CENTER_CAPTURE,
ADE9078_MODE_SAVE_EVENT_ADDR
} |
| Fixed data rate waveforms filling and trigger based modes. More...
|
|
enum | ade9078_burst_ch_e {
ADE9078_BURST_ALL_CH,
ADE9078_BURST_IA_VA,
ADE9078_BURST_IB_VB,
ADE9078_BURST_IC_VC,
ADE9078_BURST_IA = 8,
ADE9078_BURST_VA,
ADE9078_BURST_IB,
ADE9078_BURST_VB,
ADE9078_BURST_IC,
ADE9078_BURST_VC,
ADE9078_BURST_IN,
ADE9078_BURST_DISABLED
} |
| Selects which data to read out of the waveform buffer through SPI. More...
|
|
enum | ade9078_hpf_freq_e {
ADE9078_HPF_36_695,
ADE9078_HPF_19_6375,
ADE9078_HPF_9_895,
ADE9078_HPF_4_9675,
ADE9078_HPF_2_49,
ADE9078_HPF_1_2475,
ADE9078_HPF_0_625,
ADE9078_HPF_0_3125
} |
| High-pass filter corner (f3dB) enabled when the HPFDIS bit in the CONFIG0 register is equal to zero. More...
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|
enum | ade9078_no_load_tmr_e {
ADE9078_NOLOAD_SAMPLES_64,
ADE9078_NOLOAD_SAMPLES_128,
ADE9078_NOLOAD_SAMPLES_256,
ADE9078_NOLOAD_SAMPLES_512,
ADE9078_NOLOAD_SAMPLES_1024,
ADE9078_NOLOAD_SAMPLES_2048,
ADE9078_NOLOAD_SAMPLES_4096,
ADE9078_NOLOAD_SAMPLES_DISABLE
} |
| This register configures how many 4 kSPS samples to evaluate the no load condition over. More...
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|
enum | ade9078_pkdet_lvl_e {
ADE9078_PKDET_LVL_100,
ADE9078_PKDET_LVL_200,
ADE9078_PKDET_LVL_300,
ADE9078_PKDET_LVL_400,
ADE9078_PKDET_LVL_500,
ADE9078_PKDET_LVL_600,
ADE9078_PKDET_LVL_700,
ADE9078_PKDET_LVL_800,
ADE9078_PKDET_LVL_900,
ADE9078_PKDET_LVL_1000,
ADE9078_PKDET_LVL_1100,
ADE9078_PKDET_LVL_1200,
ADE9078_PKDET_LVL_1300,
ADE9078_PKDET_LVL_1400,
ADE9078_PKDET_LVL_1500,
ADE9078_PKDET_LVL_1600
} |
| ADE9078 These bits configure the PSM2 low power comparator peak current detection Level, listed as the input signal level with respect to full scale. More...
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|
enum | ade9078_vc_gain_e {
ADE9078_VC_GAIN_1,
ADE9078_VC_GAIN_2,
ADE9078_VC_GAIN_3,
ADE9078_VC_GAIN_4
} |
| ADE9078 PGA gain for Voltage Channel C ADC. More...
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|
enum | ade9078_phase {
ADE9078_PHASE_A,
ADE9078_PHASE_B,
ADE9078_PHASE_C
} |
| ADE9078 available phases. More...
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|
enum | ade9078_egy_model {
ADE9078_EGY_WITH_RESET,
ADE9078_EGY_HALF_LINE_CYCLES,
ADE9078_EGY_NR_SAMPLES
} |
| ADE9078 available user energy use models. More...
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|
enum | ade9078_power_mode_e {
NORMAL_MODE,
TAMPER_MODE,
CURRENT_PEAK_DETECT_MODE,
IDLE_MODE
} |
| ADE9078 Power mode selection. More...
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|
Header file of ADE9078 Driver.
- Author
- REtz (radu..nosp@m.etz@.nosp@m.analo.nosp@m.g.co.nosp@m.m)
Copyright 2024(c) Analog Devices, Inc.
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