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#define | ADF4368_SOFT_RESET_R_MSK NO_OS_BIT(7) |
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#define | ADF4368_LSB_FIRST_R_MSK NO_OS_BIT(6) |
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#define | ADF4368_ADDRESS_ASC_R_MSK NO_OS_BIT(5) |
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#define | ADF4368_SDO_ACTIVE_R_MSK NO_OS_BIT(4) |
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#define | ADF4368_SDO_ACTIVE_MSK NO_OS_BIT(3) |
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#define | ADF4368_ADDRESS_ASC_MSK NO_OS_BIT(2) |
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#define | ADF4368_LSB_FIRST_MSK NO_OS_BIT(1) |
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#define | ADF4368_SOFT_RESET_MSK NO_OS_BIT(0) |
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#define | ADF4368_RESET_CMD 0x81 |
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#define | ADF4368_SDO_ACTIVE_SPI_3W 0x0 |
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#define | ADF4368_SDO_ACTIVE_SPI_4W 0x1 |
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#define | ADF4368_ADDR_ASC_AUTO_DECR 0x0 |
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#define | ADF4368_ADDR_ASC_AUTO_INCR 0x1 |
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#define | ADF4368_LSB_FIRST_MSB 0x0 |
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#define | ADF4368_LSB_FIRST_LSB 0x1 |
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#define | ADF4368_SOFT_RESET_N_OP 0x0 |
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#define | ADF4368_SOFT_RESET_EN 0x1 |
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#define | ADF4368_SINGLE_INSTR_MSK NO_OS_BIT(7) |
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#define | ADF4368_MASTER_RB_CTRL_MSK NO_OS_BIT(5) |
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#define | ADF4368_SPI_STREAM_EN 0x0 |
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#define | ADF4368_SPI_STREAM_DIS 0x1 |
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#define | ADF4368_CHIP_TYPE 0x06 |
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#define | ADF4368_PRODUCT_ID_LSB 0x0005 |
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#define | ADF4368_PRODUCT_ID_MSB 0x0005 |
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#define | ADF4368_SCRATCHPAD_MSK NO_OS_GENMASK(7, 0) |
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#define | ADF4368_N_INT_LSB_MSK NO_OS_GENMASK(7, 0) |
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#define | ADF4368_CLKOUT_DIV_MSK NO_OS_GENMASK(7, 6) |
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#define | ADF4368_INT_MODE_MSK NO_OS_BIT(5) |
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#define | ADF4368_INV_CLK_OUT_MSK NO_OS_BIT(4) |
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#define | ADF4368_N_INT_MSB_MSK NO_OS_GENMASK(3, 0) |
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#define | ADF4368_FRAC1WORD_LSB_MSK NO_OS_GENMASK(7, 0) |
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#define | ADF4368_FRAC1WORD_MID_MSK NO_OS_GENMASK(7, 0) |
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#define | ADF4368_FRAC1WORD_MSB_MSK NO_OS_GENMASK(7, 0) |
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#define | ADF4368_M_VCO_CORE_MSK NO_OS_GENMASK(7, 6) |
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#define | ADF4368_M_VCO_BIAS_MSK NO_OS_GENMASK(5, 2) |
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#define | ADF4368_CMOS_OV_MSK NO_OS_BIT(1) |
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#define | ADF4368_FRAC1WORD_MSB NO_OS_BIT(0) |
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#define | ADF4368_M_VCO_BAND_MSK NO_OS_GENMASK(7, 0) |
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#define | ADF4368_FRAC2WORD_LSB_MSK NO_OS_GENMASK(7, 0) |
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#define | ADF4368_FRAC2WORD_MID_MSK NO_OS_GENMASK(7, 0) |
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#define | ADF4368_FRAC2WORD_MSB_MSK NO_OS_GENMASK(7, 0) |
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#define | ADF4368_MOD2WORD_LSB_MSK NO_OS_GENMASK(7, 0) |
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#define | ADF4368_MOD2WORD_MID_MSK NO_OS_GENMASK(7, 0) |
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#define | ADF4368_MOD2WORD_MSB_MSK NO_OS_GENMASK(7, 0) |
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#define | ADF4368_FINE_BLEED_LSB_MSK NO_OS_GENMASK(7, 0) |
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#define | ADF4368_EN_PHASE_RESYNC_MSK NO_OS_BIT(7) |
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#define | ADF4368_EN_REF_RST_MSK NO_OS_BIT(6) |
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#define | ADF4368_TIMED_SYNC_MSK NO_OS_BIT(5) |
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#define | ADF4368_COARSE_BLEED_MSK NO_OS_GENMASK(4, 1) |
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#define | ADF4368_FINE_BLEED_MSB_MSK NO_OS_BIT(0) |
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#define | ADF4368_SW_SYNC_MSK NO_OS_BIT(7) |
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#define | ADF4368_PHASE_ADJ_MSK NO_OS_BIT(6) |
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#define | ADF4368_BLEED_POL_MSK NO_OS_BIT(5) |
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#define | ADF4368_EN_BLEED_MSK NO_OS_BIT(4) |
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#define | ADF4368_CP_I_MSK NO_OS_GENMASK(3, 0) |
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#define | ADF4368_EN_AUTOCAL_MSK NO_OS_BIT(7) |
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#define | ADF4368_EN_RDBLR_MSK NO_OS_BIT(6) |
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#define | ADF4368_R_DIV_MSK NO_OS_GENMASK(5, 0) |
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#define | ADF4368_PHASE_WORD_LSB_MSK NO_OS_GENMASK(7, 0) |
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#define | ADF4368_PHASE_WORD_MID_MSK NO_OS_GENMASK(7, 0) |
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#define | ADF4368_PHASE_WORD_MSB_MSK NO_OS_GENMASK(7, 0) |
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#define | ADF4368_PHASE_ADJUSTMENT_MSK NO_OS_GENMASK(7, 0) |
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#define | ADF4368_RESYNC_WAIT_LSB_MSK NO_OS_GENMASK(7, 0) |
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#define | ADF4368_RESYNC_WAIT_MID_MSK NO_OS_GENMASK(7, 0) |
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#define | ADF4368_RESYNC_WAIT_MSB_MSK NO_OS_GENMASK(7, 0) |
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#define | ADF4368_REG28_RSV1 NO_OS_BIT(7) |
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#define | ADF4368_LSB_P1 NO_OS_BIT(6) |
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#define | ADF4368_VAR_MOD_EN_MSK NO_OS_BIT(5) |
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#define | ADF4368_REG28_RSV2 NO_OS_GENMASK(4, 2) |
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#define | ADF4368_REG28_RSV3 NO_OS_BIT(1) |
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#define | ADF4368_REG28_RSV4 NO_OS_BIT(0) |
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#define | ADF4368_CLK2_OPWR_MSK NO_OS_GENMASK(7, 4) |
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#define | ADF4368_CLK1_OPWR_MSK NO_OS_GENMASK(3, 0) |
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#define | ADF4368_REG2A_RSV5 NO_OS_BIT(7) |
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#define | ADF4368_ADJ_POL_MSK NO_OS_BIT(6) |
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#define | ADF4368_REG2A_RSV4 NO_OS_BIT(5) |
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#define | ADF4368_PD_SYNC NO_OS_BIT(4) |
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#define | ADF4368_REG2A_RSV3 NO_OS_BIT(3) |
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#define | ADF4368_PD_RDET NO_OS_BIT(2) |
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#define | ADF4368_REG2A_RSV2 NO_OS_BIT(1) |
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#define | ADF4368_REG2A_RSV1 NO_OS_BIT(0) |
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#define | ADF4368_PD_ALL NO_OS_BIT(7) |
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#define | ADF4368_REG2B_RSV4 NO_OS_BIT(6) |
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#define | ADF4368_REG2B_RSV3 NO_OS_BIT(5) |
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#define | ADF4368_REG2B_RSV2 NO_OS_BIT(4) |
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#define | ADF4368_PD_LD NO_OS_BIT(3) |
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#define | ADF4368_REG2B_RSV1 NO_OS_BIT(2) |
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#define | ADF4368_PD_CLKOUT1_MSK NO_OS_BIT(1) |
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#define | ADF4368_PD_CLKOUT2_MSK NO_OS_BIT(0) |
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#define | ADF4368_LDWIN_PW_MSK NO_OS_GENMASK(7, 5) |
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#define | ADF4368_LD_COUNT_MSK NO_OS_GENMASK(4, 0) |
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#define | ADF4368_EN_DNCLK_MSK NO_OS_BIT(7) |
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#define | ADF4368_EN_DRCLK_MSK NO_OS_BIT(6) |
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#define | ADF4368_EN_LOL_MSK NO_OS_BIT(5) |
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#define | ADF4368_EN_LDWIN_MSK NO_OS_BIT(4) |
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#define | ADF4368_REG2D_RSV2 NO_OS_BIT(3) |
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#define | ADF4368_RST_LD_MSK NO_OS_BIT(2) |
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#define | ADF4368_REG2D_RSV1 NO_OS_GENMASK(1, 0) |
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#define | ADF4368_MUXOUT_MSK NO_OS_GENMASK(7, 4) |
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#define | ADF4368_REG2E_RSV1 NO_OS_BIT(3) |
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#define | ADF4368_EN_CPTEST_MSK NO_OS_BIT(2) |
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#define | ADF4368_CP_DOWN_MSK NO_OS_BIT(1) |
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#define | ADF4368_CP_UP_MSK NO_OS_BIT(0) |
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#define | ADF4368_BST_REF_MSK NO_OS_BIT(7) |
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#define | ADF4368_FILT_REF_MSK NO_OS_BIT(6) |
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#define | ADF4368_REF_SEL_MSK NO_OS_BIT(5) |
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#define | ADF4368_REG2F_RSV2 NO_OS_BIT(5) |
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#define | ADF4368_REG2F_RSV1 NO_OS_GENMASK(3, 0) |
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#define | ADF4368_MUTE_NCLK_MSK NO_OS_BIT(7) |
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#define | ADF4368_REG30_RSV3 NO_OS_BIT(6) |
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#define | ADF4368_DRCLK_DEL_MSK NO_OS_GENMASK(5, 3) |
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#define | ADF4368_DNCLK_DEL_MSK NO_OS_GENMASK(2, 0) |
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#define | ADF4368_SYNC_DEL_MSK NO_OS_GENMASK(7, 5) |
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#define | ADF4368_RST_SYS_MSK NO_OS_BIT(4) |
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#define | ADF4368_EN_ADC_CLK_MSK NO_OS_BIT(3) |
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#define | ADF4368_REG31_RSV3 NO_OS_BIT(2) |
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#define | ADF4368_REG31_RSV2 NO_OS_BIT(1) |
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#define | ADF4368_REG31_RSV1 NO_OS_BIT(0) |
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#define | ADF4368_REG35_RSV4 NO_OS_BIT(7) |
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#define | ADF4368_REG35_RSV3 NO_OS_GENMASK(6, 3) |
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#define | ADF4368_DCLK_MODE_MSK NO_OS_BIT(2) |
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#define | ADF4368_REG35_RSV2 NO_OS_BIT(1) |
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#define | ADF4368_REG35_RSV1 NO_OS_BIT(0) |
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#define | ADF4368_CLKODIV_DB_MSK NO_OS_BIT(7) |
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#define | ADF4368_DCLK_DIV_DB_MSK NO_OS_BIT(6) |
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#define | ADF4368_REG36_RSV3 NO_OS_BIT(5) |
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#define | ADF4368_REG36_RSV2 NO_OS_BIT(4) |
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#define | ADF4368_REG36_RSV1 NO_OS_GENMASK(3, 0) |
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#define | ADF4368_VCO_BAND_DIV NO_OS_GENMASK(7, 0) |
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#define | ADF4368_SYNTH_LOCK_TIMEOUT_LSB_MSK NO_OS_GENMASK(7, 0) |
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#define | ADF4368_O_VCO_DB_MSK NO_OS_BIT(7) |
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#define | ADF4368_SYNTH_LOCK_TIMEOUT_MSB_MSK NO_OS_GENMASK(6, 0) |
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#define | ADF4368_VCO_ALC_TIMEOUT_LSB_MSK NO_OS_GENMASK(7, 0) |
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#define | ADF4368_DEL_CTRL_DB_MSK NO_OS_BIT(7) |
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#define | ADF4368_VCO_ALC_TIMEOUT_MSB_MSK NO_OS_GENMASK(6, 0) |
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#define | ADF4368_ADC_CLK_DIV_MSK NO_OS_GENMASK(7, 0) |
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#define | ADF4368_EN_ADC_CNV_MSK NO_OS_BIT(7) |
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#define | ADF4368_REG3F_RSV5 NO_OS_BIT(6) |
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#define | ADF4368_REG3F_RSV4 NO_OS_BIT(5) |
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#define | ADF4368_REG3F_RSV3 NO_OS_BIT(4) |
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#define | ADF4368_REG3F_RSV2 NO_OS_BIT(3) |
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#define | ADF4368_REG3F_RSV1 NO_OS_BIT(2) |
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#define | ADF4368_EN_ADC_MSK NO_OS_BIT(1) |
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#define | ADF4368_ADC_A_CONV_MSK NO_OS_BIT(0) |
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#define | ADF4368_REG40_RSV1 NO_OS_GENMASK(5, 3) |
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#define | ADF4368_MUTE_CLKOUT2_MSK NO_OS_GENMASK(5, 3) |
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#define | ADF4368_MUTE_CLKOUT1_MSK NO_OS_GENMASK(2, 0) |
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#define | ADF4368_REG43_RSV5 NO_OS_BIT(7) |
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#define | ADF4368_ADC_CLK_SEL_MSK NO_OS_BIT(6) |
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#define | ADF4368_REG43_RSV4 NO_OS_BIT(5) |
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#define | ADF4368_REG43_RSV3 NO_OS_BIT(4) |
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#define | ADF4368_REG43_RSV2 NO_OS_BIT(3) |
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#define | ADF4368_REG43_RSV1 NO_OS_GENMASK(2, 0) |
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#define | ADF4368_REG4E_RSV2 NO_OS_GENMASK(7, 6) |
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#define | ADF4368_DCLK_DIV1_MSK NO_OS_GENMASK(5, 4) |
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#define | ADF4368_O_VCO_BAND_MSK NO_OS_BIT(3) |
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#define | ADF4368_O_VCO_CORE_MSK NO_OS_BIT(2) |
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#define | ADF4368_O_VCO_BIAS_MSK NO_OS_BIT(1) |
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#define | ADF4368_REG4E_RSV1 NO_OS_BIT(0) |
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#define | ADF4368_REG53_RSV2 NO_OS_BIT(7) |
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#define | ADF4368_PD_SYNC_MON_MSK NO_OS_BIT(6) |
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#define | ADF4368_SYNC_SEL_MSK NO_OS_BIT(5) |
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#define | ADF4368_RST_SYNC_MON_MSK NO_OS_BIT(4) |
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#define | ADF4368_REG53_RSV1 NO_OS_GENMASK(3, 0) |
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#define | ADF4368_REG54_RSV1 NO_OS_GENMASK(7, 1) |
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#define | ADF4368_ADC_ST_CNV_MSK NO_OS_BIT(1) |
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#define | ADF4368_EN_CLK2_MSK NO_OS_BIT(7) |
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#define | ADF4368_EN_CLK1_MSK NO_OS_BIT(6) |
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#define | ADF4368_SYNC_OK_MSK NO_OS_BIT(5) |
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#define | ADF4368_REG58_RSV1 NO_OS_BIT(4) |
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#define | ADF4368_REF_OK_MSK NO_OS_BIT(3) |
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#define | ADF4368_ADC_BUSY_MSK NO_OS_BIT(2) |
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#define | ADF4368_FSM_BUSY_MSK NO_OS_BIT(1) |
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#define | ADF4368_LOCKED_MSK NO_OS_BIT(0) |
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#define | ADF4368_REG5A_RSV1 NO_OS_GENMASK(7, 2) |
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#define | ADF4368_VCO_CORE_MSK NO_OS_GENMASK(1, 0) |
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#define | ADF4368_CHIP_TEMP_LSB_MSK NO_OS_GENMASK(7, 0) |
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#define | ADF4368_REG5C_RSV1 NO_OS_GENMASK(7, 1) |
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#define | ADF4368_CHIP_TEMP_MSB_MSK NO_OS_BIT(0) |
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#define | ADF4368_VCO_BAND_MSK NO_OS_GENMASK(7, 0) |
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#define | ADF4368_REG60_RSV1 NO_OS_GENMASK(7, 4) |
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#define | ADF4368_VCO_BIAS_MSK NO_OS_GENMASK(3, 0) |
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#define | ADF4368_VERSION_MSK NO_OS_GENMASK(7, 0) |
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#define | ADF4368_SPI_4W_CFG(x) |
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#define | ADF4368_SPI_LSB_CFG(x) |
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#define | ADF4368_BLEED_MSB_MSK |
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#define | ADF4368_SPI_SCRATCHPAD_TEST 0x5A |
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#define | ADF4368_SPI_WRITE_CMD 0x0 |
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#define | ADF4368_SPI_READ_CMD 0x8000 |
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#define | ADF4368_SPI_DUMMY_DATA 0x00 |
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#define | ADF4368_BUFF_SIZE_BYTES 3 |
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#define | ADF4368_VCO_FREQ_MIN 6400000000U |
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#define | ADF4368_VCO_FREQ_MAX 12800000000U |
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#define | ADF4368_MOD1WORD 0x2000000U |
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#define | ADF4368_MOD2WORD_MAX 0xFFFFFFU |
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#define | ADF4368_PHASE_RESYNC_MOD2WORD_MAX 0x1FFFFU |
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#define | ADF4368_CHANNEL_SPACING_MAX 78125U |
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#define | ADF4368_PFD_FREQ_MAX 625000000U |
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#define | ADF4368_PFD_FREQ_FRAC_MAX 250000000U |
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#define | ADF4368_DCLK_DIV1_0_MAX 160000000U |
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#define | ADF4368_DCLK_DIV1_1_MAX 320000000U |
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#define | ADF4368_CLKOUT_DIV_REG_VAL_MAX 3 |
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#define | ADF4368_RFOUT_MAX 12800000000U |
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#define | ADF4368_RFOUT_MIN 800000000U |
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#define | ADF4368_REF_CLK_MAX 4000000000U |
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#define | ADF4368_REF_CLK_MIN 10000000 |
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#define | ADF4368_REF_DIV_MAX 63 |
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#define | ADF4368_OUT_PWR_MAX 15 |
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#define | ADF4368_CPI_VAL_MAX 15 |
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#define | ADF4368_BLEED_WORD_MAX 8191 |
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#define | ADF4368_FRAC_N_INT_MIN 19 |
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#define | ADF4368_INT_N_INT_MIN 4 |
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#define | ADF4368_PHASE_BLEED_CNST 2044000 |
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#define | ADF4368_BLEED_N_INT_TH 35 |
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#define | ADF4368_COARSE_BLEED_CNST 202 |
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#define | ADF4368_FINE_BLEED_CNST1 250 |
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#define | ADF4368_FINE_BLEED_CNST2 512 |
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#define | ADF4368_FINE_BLEED_CNST3 567 |
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#define | ADF4368_SIGMA_DELTA_MOD_CNST 4096 |
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#define | ADF4368_POR_DELAY_US 200 |
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#define | ADF4368_LKD_DELAY_MS 9 |
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#define | ADF4368_MHZ MEGA |
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#define | ADF4368_S_TO_NS NANO |
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#define | ADF4368_NS_TO_PS KHZ_PER_MHZ |
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#define | ADF4368_PS_TO_NS KHZ_PER_MHZ |
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#define | ADF4368_PS_TO_US MICRO |
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#define | ADF4368_US_TO_MS MILLI |
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#define | ADF4368_MS_TO_S MILLI |
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#define | ADF4368_PS_TO_S PICO |
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#define | ADF4368_US_TO_FS NANO |
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#define | ADF4368_NS_TO_S NANO |
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int | adf4368_spi_write (struct adf4368_dev *dev, uint16_t reg_addr, uint8_t data) |
| Writes data to ADF4368 over SPI. More...
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int | adf4368_spi_read (struct adf4368_dev *dev, uint16_t reg_addr, uint8_t *data) |
| Reads data from ADF4368 over SPI. More...
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int | adf4368_spi_update_bits (struct adf4368_dev *dev, uint16_t reg_addr, uint8_t mask, uint8_t data) |
| Updates the values of the ADF4368 register. More...
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int | adf4368_reg_dump (struct adf4368_dev *dev) |
| Will output on the terminal the values of all the ADF4368 registers. More...
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int | adf4368_set_out_power (struct adf4368_dev *dev, uint8_t ch, int32_t pwr) |
| Set the output power register value of a channel and reset everything over to maximum supported value of 15 to the max. value. More...
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int | adf4368_get_out_power (struct adf4368_dev *dev, uint8_t ch, int32_t *pwr) |
| Gets the output power register value. More...
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int | adf4368_set_en_chan (struct adf4368_dev *dev, uint8_t ch, bool en) |
| Set the output channel to enable or disable based on the passed parameter. If the parameter is different then 0 it will set the doubler to enable. More...
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int | adf4368_get_en_chan (struct adf4368_dev *dev, uint8_t ch, bool *en) |
| Gets the value the output channel if it is enabled or disable. More...
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int | adf4368_set_ref_clk (struct adf4368_dev *dev, uint64_t val) |
| Set the desired reference frequency and reset everything over to maximum supported value of 4GHz to the max. value and everything under the minimum supported value of 10MHz to the min. value. More...
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int | adf4368_get_ref_clk (struct adf4368_dev *dev, uint64_t *val) |
| Gets the user proposed reference frequency. More...
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int | adf4368_set_en_ref_doubler (struct adf4368_dev *dev, bool en) |
| Set the reference doubler to enable or disable based on the passed parameter. If the parameter is different then 0 it will set the doubler to enable. More...
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int | adf4368_get_en_ref_doubler (struct adf4368_dev *dev, bool *en) |
| Gets the value the doubler if it is enabled or disable and stores it it the dev structure. More...
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int | adf4368_set_ref_div (struct adf4368_dev *dev, int32_t div) |
| Set the reference divider value and reset everything over to maximum supported value of 63 to the max. value. More...
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int | adf4368_get_ref_div (struct adf4368_dev *dev, int32_t *div) |
| Gets the value the reference divider. More...
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int | adf4368_set_cp_i (struct adf4368_dev *dev, int32_t reg_val) |
| Set the charge pump value which will be written to the register. The value will be between 0 and 15 on 8 bits. For more information please consult the Datasheet. More...
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int | adf4368_get_cp_i (struct adf4368_dev *dev, int32_t *reg_val) |
| Gets the charge pump value from the register. The value will be between 0 and 15 on 8 bits. For more information please consult the Datasheet. More...
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int | adf4368_set_bleed_word (struct adf4368_dev *dev, int32_t word) |
| Set the bleed word, which represents the value of the bleed current written to the register space. More...
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int | adf4368_get_bleed_word (struct adf4368_dev *dev, int32_t *word) |
| Gets the value of the bleed word. More...
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int | adf4368_set_rfout (struct adf4368_dev *dev, uint64_t val) |
| Set the desired output frequency and reset everything over to maximum supported value of 12.8GHz to the max. value and everything under the minimum supported value of 800MHz to the min. value. More...
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int | adf4368_get_rfout (struct adf4368_dev *dev, uint64_t *val) |
| Gets the user proposed output frequency. More...
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int | adf4368_set_sync_setup (struct adf4368_dev *dev, bool en) |
| Set EZSYNC and Timed SYNC features' initial state. Waits for SW_SYNC toggle or SYNC pin. More...
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int | adf4368_get_sync_setup (struct adf4368_dev *dev, bool *en) |
| Gets the value of the SYNC features' powerdown bit. More...
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int | adf4368_set_sw_sync (struct adf4368_dev *dev, uint8_t sw_sync) |
| Set Software SYNC Request. Setting SW_SYNC resets the RF block. Clearing SW_SYNC makes ready for a new reference clock. More...
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int | adf4368_get_sw_sync (struct adf4368_dev *dev, uint8_t *sw_sync) |
| Gets the value of the SW_SYNC bit. More...
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int | adf4368_set_temperature (struct adf4368_dev *dev, bool en) |
| Set Temperature Readback feature's initial state. This feature should be disabled after reading temperature. More...
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int | adf4368_get_temperature (struct adf4368_dev *dev, int32_t *temp) |
| Gets the value of the approximate die temperature. More...
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int | adf4368_set_phase_sdm (struct adf4368_dev *dev, uint32_t phase_fs) |
| Set the phase adjustment in femto-seconds with Sigma Delta Modulation. This approach only support MAX %22 in degree phase. Recommend to use in fractional mode. More...
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int | adf4368_get_phase_sdm (struct adf4368_dev *dev, uint32_t *phase_fs) |
| Get the phase adjustment in femto-seconds with Sigma Delta Modulation. More...
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int | adf4368_set_phase_bleedi (struct adf4368_dev *dev, uint32_t phase_fs, bool phase_pol) |
| Set the phase adjustment in femto-seconds. The phase adjust will enable the Bleed current. Recommend to use in integer mode. More...
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int | adf4368_set_phase (struct adf4368_dev *dev, uint32_t phase_fs, bool phase_pol) |
| Set the phase adjustment in femto-seconds. Function choose the phase adjustment method according to Integer mode. More...
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int | adf4368_get_phase (struct adf4368_dev *dev, uint32_t *phase_fs, bool *phase_pol) |
| Get the phase adjustment in femto-seconds. Function choose the phase adjustment method according to Integer mode. More...
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int | adf4368_set_default_regs (struct adf4368_dev *dev, bool spi_4wire) |
| Applys a softreset, sets the SPI 4 wire mode and writes the default registers. More...
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int | adf4368_get_default_regs (struct adf4368_dev *dev, bool *spi_4wire) |
| Reads and Checks the registers values equal to default values. More...
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int | adf4368_set_freq (struct adf4368_dev *dev) |
| Set the output frequency. More...
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int | adf4368_init (struct adf4368_dev **device, struct adf4368_init_param *init_param) |
| Initializes the adf4368. More...
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int | adf4368_remove (struct adf4368_dev *dev) |
| Free resources allocated for ADF4368. More...
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Implementation of ADF4368 Driver.
- Author
- Sirac Kucukarabacioglu (sirac.nosp@m..kuc.nosp@m.ukara.nosp@m.baci.nosp@m.oglu@.nosp@m.anal.nosp@m.og.co.nosp@m.m)
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