Go to the documentation of this file.
42 #define ADIN1110_BUFF_LEN 1530
43 #define ADIN1110_ETH_ALEN 6
44 #define ADIN1110_ETHERTYPE_LEN 2
45 #define ADIN1110_ETH_HDR_LEN 14
46 #define ADIN1110_ADDR_FILT_LEN 16
48 #define ADIN1110_FCS_LEN 4
49 #define ADIN1110_MAC_LEN 6
51 #define ADIN1110_ADDR_MASK NO_OS_GENMASK(12, 0)
52 #define ADIN1110_RD_FRAME_SIZE 7
53 #define ADIN1110_WR_FRAME_SIZE 6
54 #define ADIN1110_RD_HDR_SIZE 3
55 #define ADIN1110_WR_HDR_SIZE 2
56 #define ADIN1110_PHY_ID_REG 1
58 #define ADIN1110_PHY_ID 0x0283BC91
59 #define ADIN2111_PHY_ID 0x0283BCA1
61 #define ADIN1110_PORTS 1
62 #define ADIN2111_PORTS 2
64 #define ADIN1110_CD_MASK NO_OS_BIT(15)
65 #define ADIN1110_RW_MASK NO_OS_BIT(13)
67 #define ADIN1110_SOFT_RST_REG 0x3C
68 #define ADIN1110_RESET_REG 0x03
69 #define ADIN1110_SWRESET NO_OS_BIT(0)
70 #define ADIN1110_SWRESET_KEY1 0x4F1C
71 #define ADIN1110_SWRESET_KEY2 0xC1F4
72 #define ADIN1110_SWRELEASE_KEY1 0x6F1A
73 #define ADIN1110_SWRELEASE_KEY2 0xA1F6
75 #define ADIN1110_SPI_CD NO_OS_BIT(7)
76 #define ADIN1110_SPI_RW NO_OS_BIT(5)
78 #define ADIN1110_CONFIG1_REG 0x04
79 #define ADIN1110_CONFIG1_SYNC NO_OS_BIT(15)
81 #define ADIN1110_CONFIG2_REG 0x06
82 #define ADIN2111_P2_FWD_UNK2HOST_MASK NO_OS_BIT(12)
83 #define ADIN2111_PORT_CUT_THRU_EN NO_OS_BIT(11)
84 #define ADIN1110_CRC_APPEND NO_OS_BIT(5)
85 #define ADIN1110_FWD_UNK2HOST_MASK NO_OS_BIT(2)
87 #define ADIN1110_STATUS0_REG 0x08
88 #define ADIN1110_STATUS0_TXPE_MASK NO_OS_BIT(0)
89 #define ADIN1110_RESETC_MASK NO_OS_BIT(6)
91 #define ADIN1110_STATUS1_REG 0x09
92 #define ADIN1110_LINK_STATE_MASK NO_OS_BIT(0)
93 #define ADIN2111_P2_RX_RDY NO_OS_BIT(17)
94 #define ADIN1110_SPI_ERR NO_OS_BIT(10)
95 #define ADIN1110_RX_RDY NO_OS_BIT(4)
97 #define ADIN1110_IMASK1_REG 0x0D
98 #define ADIN2111_RX_RDY_IRQ NO_OS_BIT(17)
99 #define ADIN1110_SPI_ERR_IRQ NO_OS_BIT(10)
100 #define ADIN1110_RX_RDY_IRQ NO_OS_BIT(4)
101 #define ADIN1110_TX_RDY_IRQ NO_OS_BIT(3)
103 #define ADIN1110_MDIOACC(x) (0x20 + (x))
104 #define ADIN1110_MDIO_TRDONE NO_OS_BIT(31)
105 #define ADIN1110_MDIO_TAERR NO_OS_BIT(30)
106 #define ADIN1110_MDIO_ST NO_OS_GENMASK(29, 28)
107 #define ADIN1110_MDIO_OP NO_OS_GENMASK(27, 26)
108 #define ADIN1110_MDIO_PRTAD NO_OS_GENMASK(25, 21)
109 #define ADIN1110_MDIO_DEVAD NO_OS_GENMASK(20, 16)
110 #define ADIN1110_MDIO_DATA NO_OS_GENMASK(15, 0)
112 #define ADIN1110_MMD_ACR_DEVAD_MASK NO_OS_GENMASK(4, 0)
113 #define ADIN1110_MMD_ACR_FUNCTION_MASK NO_OS_GENMASK(15, 14)
114 #define ADIN1110_MMD_ACCESS_MASK NO_OS_GENMASK(15, 0)
115 #define ADIN1110_MMD_ACCESS_CTRL_REG 0x0D
116 #define ADIN1110_MMD_ACCESS_REG 0x0E
118 #define ADIN1110_MI_SFT_PD_MASK NO_OS_BIT(11)
119 #define ADIN1110_MDIO_PHY_ID(x) ((x) + 1)
120 #define ADIN1110_MI_CONTROL_REG 0x0
122 #define ADIN1110_CRSM_SFT_PD_CNTRL_REG 0x8812
123 #define ADIN1110_CRSM_SFT_PD_MASK NO_OS_BIT(0)
125 #define ADIN1110_TX_FSIZE_REG 0x30
126 #define ADIN1110_TX_REG 0x31
127 #define ADIN1110_TX_SPACE_REG 0x32
129 #define ADIN1110_FIFO_CLR_REG 0x36
130 #define ADIN1110_FIFO_CLR_RX_MASK NO_OS_BIT(0)
131 #define ADIN1110_FIFO_CLR_TX_MASK NO_OS_BIT(1)
133 #define ADIN1110_MAC_RST_STATUS_REG 0x3B
135 #define ADIN2111_MAC_ADDR_APPLY2PORT2 NO_OS_BIT(31)
136 #define ADIN1110_MAC_ADDR_APPLY2PORT NO_OS_BIT(30)
137 #define ADIN2111_MAC_ADDR_TO_OTHER_PORT NO_OS_BIT(17)
138 #define ADIN1110_MAC_ADDR_TO_HOST NO_OS_BIT(16)
140 #define ADIN1110_MAC_ADDR_FILT_UPR_REG(x) (0x50 + 2 * (x))
141 #define ADIN1110_MAC_ADDR_FILT_LWR_REG(x) (0x51 + 2 * (x))
143 #define ADIN1110_MAC_ADDR_UPR_MASK NO_OS_GENMASK(15, 0)
144 #define ADIN1110_MAC_ADDR_LWR_MASK NO_OS_GENMASK(31, 0)
146 #define ADIN1110_MAC_ADDR_MASK_UPR_REG 0x70
147 #define ADIN1110_MAC_ADDR_MASK_LWR_REG 0x71
149 #define ADIN1110_RX_FRM_CNT_REG 0xA0
150 #define ADIN1110_RX_CRC_ERR_CNT_REG 0xA4
151 #define ADIN1110_RX_ALGN_ERR_CNT_REG 0xA5
152 #define ADIN1110_RX_LS_ERR_CNT_REG 0xA6
153 #define ADIN1110_RX_PHY_ERR_CNT_REG 0xA7
154 #define ADIN1110_TX_FRM_CNT_REG 0xA8
155 #define ADIN1110_TX_BCAST_CNT_REG 0xA9
156 #define ADIN1110_TX_MCAST_CNT_REG 0xAA
157 #define ADIN1110_TX_UCAST_CNT_REG 0xAB
158 #define ADIN1110_RX_BCAST_CNT_REG 0xA1
159 #define ADIN1110_RX_MCAST_CNT_REG 0xA2
160 #define ADIN1110_RX_UCAST_CNT_REG 0xA3
162 #define ADIN1110_RX_DROP_FULL_CNT_REG 0xAC
163 #define ADIN1110_RX_DROP_FILT_CNT_REG 0xAD
165 #define ADIN1110_RX_FSIZE_REG 0x90
166 #define ADIN1110_RX_REG 0x91
168 #define ADIN2111_RX_P2_FSIZE_REG 0xC0
169 #define ADIN2111_RX_P2_REG 0xC1
171 #define ADIN1110_CLEAR_STATUS0 0xFFF
174 #define ADIN1110_MDIO_OP_ADDR 0x0
175 #define ADIN1110_MDIO_OP_WR 0x1
176 #define ADIN1110_MDIO_OP_RD 0x3
178 #define ADIN1110_WR_HEADER_LEN 2
179 #define ADIN1110_FRAME_HEADER_LEN 2
180 #define ADIN1110_RD_HEADER_LEN 3
181 #define ADIN1110_REG_LEN 4
182 #define ADIN1110_CRC_LEN 1
183 #define ADIN1110_FEC_LEN 4
185 #define ADIN_MAC_MULTICAST_ADDR_SLOT 0
186 #define ADIN_MAC_BROADCAST_ADDR_SLOT 1
187 #define ADIN_MAC_P1_ADDR_SLOT 2
188 #define ADIN_MAC_P2_ADDR_SLOT 3
189 #define ADIN_MAC_FDB_ADDR_SLOT 4
#define ADIN1110_SPI_RW
Definition: adin1110.h:76
#define ADIN1110_RX_REG
Definition: adin1110.h:166
#define ADIN1110_MDIO_PRTAD
Definition: adin1110.h:108
#define ADIN1110_FRAME_HEADER_LEN
Definition: adin1110.h:179
void no_os_put_unaligned_be16(uint16_t val, uint8_t *buf)
struct no_os_spi_desc * comm_desc
Definition: adin1110.h:204
#define ADIN1110_MAC_ADDR_FILT_UPR_REG(x)
Definition: adin1110.h:140
#define ADIN1110_ETH_HDR_LEN
Definition: adin1110.h:45
Structure holding the parameters for GPIO initialization.
Definition: no_os_gpio.h:79
@ ADIN2111
Definition: adin1110.h:196
#define ADIN1110_TX_REG
Definition: adin1110.h:126
#define ADIN1110_CONFIG1_SYNC
Definition: adin1110.h:79
int adin1110_broadcast_filter(struct adin1110_desc *, bool)
Set/clear a broadcast filter. By enabling this, broadcast frames will be forwarded to the host.
Definition: adin1110.c:470
#define ADIN1110_WR_HEADER_LEN
Definition: adin1110.h:178
#define ADIN1110_REG_LEN
Definition: adin1110.h:181
#define ADIN1110_CRSM_SFT_PD_MASK
Definition: adin1110.h:123
uint8_t mac_dest[ADIN1110_ETH_ALEN]
Definition: adin1110.h:227
#define ADIN1110_TX_SPACE_REG
Definition: adin1110.h:127
#define ADIN1110_MAC_ADDR_TO_HOST
Definition: adin1110.h:138
#define ADIN1110_SWRESET_KEY1
Definition: adin1110.h:70
#define ADIN1110_CRC_LEN
Definition: adin1110.h:182
int adin1110_clear_mac_addr(struct adin1110_desc *desc, uint8_t mac_address[ADIN1110_ETH_ALEN])
Drop a MAC address filter.
Definition: adin1110.c:424
Header file of SPI Interface.
#define ADIN1110_MDIO_PHY_ID(x)
Definition: adin1110.h:119
uint8_t * payload
Definition: adin1110.h:230
adin1110_chip_id
The chips supported by this driver.
Definition: adin1110.h:194
#define ADIN1110_RD_HEADER_LEN
Definition: adin1110.h:180
int adin1110_reg_read(struct adin1110_desc *desc, uint16_t addr, uint32_t *data)
Read a register's value.
Definition: adin1110.c:108
int adin1110_set_mac_addr(struct adin1110_desc *desc, uint8_t mac_address[ADIN1110_ETH_ALEN])
Set a MAC address destination filter, frames who's DA doesn't match are dropped.
Definition: adin1110.c:376
int adin1110_read_fifo(struct adin1110_desc *, uint32_t, struct adin1110_eth_buff *)
Read a frame from the RX FIFO.
Definition: adin1110.c:561
Definition: no_os_spi.h:100
Header file of Delay functions.
#define ADIN1110_CONFIG2_REG
Definition: adin1110.h:81
#define ADIN1110_SWRELEASE_KEY2
Definition: adin1110.h:73
int adin1110_reg_update(struct adin1110_desc *, uint16_t, uint32_t, uint32_t)
Update a register's value based on a mask.
Definition: adin1110.c:158
uint32_t phy_id
Definition: adin1110.c:50
Initialization parameter for the device descriptor.
Definition: adin1110.h:214
#define ADIN1110_MAC_LEN
Definition: adin1110.h:49
int adin1110_mac_reset(struct adin1110_desc *)
Reset the MAC device.
Definition: adin1110.c:634
#define ADIN1110_FCS_LEN
Definition: adin1110.h:48
@ NO_OS_GPIO_HIGH
Definition: no_os_gpio.h:117
#define ADIN1110_PHY_ID
Definition: adin1110.h:58
uint8_t mac_address[ADIN1110_ETH_ALEN]
Definition: adin1110.h:218
int adin1110_init(struct adin1110_desc **desc, struct adin1110_init_param *param)
Initialize the device.
Definition: adin1110.c:848
#define ADIN1110_ADDR_MASK
Definition: adin1110.h:51
enum adin1110_chip_id chip_type
Definition: adin1110.h:203
int adin1110_phy_reset(struct adin1110_desc *desc)
Reset the PHY device.
Definition: adin1110.c:692
int adin1110_read_fifo(struct adin1110_desc *desc, uint32_t port, struct adin1110_eth_buff *eth_buff)
Read a frame from the RX FIFO.
Definition: adin1110.c:561
uint8_t ethertype[2]
Definition: adin1110.h:229
uint32_t num_ports
Definition: adin1110.c:51
#define ADIN1110_MDIO_OP_ADDR
Definition: adin1110.h:174
NO_OS_DECLARE_CRC8_TABLE(_crc_table)
#define ADIN1110_MAC_ADDR_UPR_MASK
Definition: adin1110.h:143
#define ADIN2111_RX_RDY_IRQ
Definition: adin1110.h:98
int adin1110_reg_update(struct adin1110_desc *desc, uint16_t addr, uint32_t mask, uint32_t data)
Update a register's value based on a mask.
Definition: adin1110.c:158
#define ADIN1110_STATUS1_REG
Definition: adin1110.h:91
@ NO_OS_GPIO_LOW
Definition: no_os_gpio.h:115
uint8_t * tx_buff
Definition: no_os_spi.h:102
#define ADIN1110_ADDR_FILT_LEN
Definition: adin1110.h:46
#define ADIN1110_PHY_ID_REG
Definition: adin1110.h:56
int adin1110_write_fifo(struct adin1110_desc *, uint32_t, struct adin1110_eth_buff *)
Write a frame to the TX FIFO.
Definition: adin1110.c:489
void no_os_mdelay(uint32_t msecs)
Wait until msecs milliseconds passed.
Definition: aducm3029_delay.c:126
int adin1110_set_mac_addr(struct adin1110_desc *desc, uint8_t mac_address[ADIN1110_ETH_ALEN])
Set a MAC address destination filter, frames who's DA doesn't match are dropped.
Definition: adin1110.c:376
uint32_t no_os_field_prep(uint32_t mask, uint32_t val)
@ ADIN1110
Definition: adin1110.h:195
#define ADIN1110_IMASK1_REG
Definition: adin1110.h:97
#define ADIN2111_PHY_ID
Definition: adin1110.h:59
int adin1110_mdio_read_c45(struct adin1110_desc *, uint32_t, uint32_t, uint16_t, uint16_t *)
Read a PHY register using clause 45.
Definition: adin1110.c:320
int adin1110_mdio_write_c45(struct adin1110_desc *, uint32_t, uint32_t, uint32_t, uint16_t)
Write a PHY register using clause 45.
Definition: adin1110.c:262
#define ADIN1110_MDIO_OP_RD
Definition: adin1110.h:176
#define ADIN2111_RX_P2_FSIZE_REG
Definition: adin1110.h:168
#define ADIN1110_FEC_LEN
Definition: adin1110.h:183
#define ADIN1110_SPI_ERR_IRQ
Definition: adin1110.h:99
void no_os_crc8_populate_msb(uint8_t *table, const uint8_t polynomial)
void no_os_put_unaligned_be32(uint32_t val, uint8_t *buf)
#define ADIN2111_RX_P2_REG
Definition: adin1110.h:169
int adin1110_remove(struct adin1110_desc *desc)
Free a device descriptor.
Definition: adin1110.c:936
uint8_t data[ADIN1110_BUFF_LEN]
Definition: adin1110.h:206
#define ADIN1110_MDIO_OP
Definition: adin1110.h:107
#define ADIN1110_RW_MASK
Definition: adin1110.h:65
int adin1110_phy_reset(struct adin1110_desc *)
Reset the PHY device.
Definition: adin1110.c:692
#define ADIN1110_MDIO_OP_WR
Definition: adin1110.h:175
#define ADIN1110_MDIO_DATA
Definition: adin1110.h:110
int adin1110_sw_reset(struct adin1110_desc *desc)
Reset both the MAC and PHY.
Definition: adin1110.c:728
#define ADIN1110_MAC_ADDR_APPLY2PORT
Definition: adin1110.h:136
uint32_t len
Definition: adin1110.h:226
#define ADIN1110_SOFT_RST_REG
Definition: adin1110.h:67
#define ADIN1110_RX_RDY_IRQ
Definition: adin1110.h:100
int adin1110_link_state(struct adin1110_desc *desc, uint32_t *state)
Reset both the MAC and PHY.
Definition: adin1110.c:739
int32_t no_os_gpio_remove(struct no_os_gpio_desc *desc)
Free the resources allocated by no_os_gpio_get().
Definition: no_os_gpio.c:104
Structure holding SPI descriptor.
Definition: no_os_spi.h:192
#define ADIN1110_STATUS0_REG
Definition: adin1110.h:87
Structure holding the GPIO descriptor.
Definition: no_os_gpio.h:96
#define ADIN1110_RX_FSIZE_REG
Definition: adin1110.h:165
#define ADIN1110_CRC_POLYNOMIAL
Definition: adin1110.c:45
int adin1110_reg_write(struct adin1110_desc *, uint16_t, uint32_t)
Write a register's value.
Definition: adin1110.c:72
struct no_os_gpio_desc * reset_gpio
Definition: adin1110.h:207
#define ADIN1110_SPI_CD
Definition: adin1110.h:75
int32_t no_os_spi_transfer(struct no_os_spi_desc *desc, struct no_os_spi_msg *msgs, uint32_t len)
Iterate over head list and send all spi messages.
Definition: no_os_spi.c:185
uint32_t bytes_number
Definition: no_os_spi.h:106
int adin1110_mdio_write_c45(struct adin1110_desc *desc, uint32_t phy_id, uint32_t dev_id, uint32_t reg, uint16_t data)
Write a PHY register using clause 45.
Definition: adin1110.c:262
int adin1110_write_fifo(struct adin1110_desc *desc, uint32_t port, struct adin1110_eth_buff *eth_buff)
Write a frame to the TX FIFO.
Definition: adin1110.c:489
int adin1110_broadcast_filter(struct adin1110_desc *desc, bool enabled)
Set/clear a broadcast filter. By enabling this, broadcast frames will be forwarded to the host.
Definition: adin1110.c:470
int adin1110_reg_read(struct adin1110_desc *, uint16_t, uint32_t *)
Read a register's value.
Definition: adin1110.c:108
int adin1110_mac_reset(struct adin1110_desc *desc)
Reset the MAC device.
Definition: adin1110.c:634
#define ADIN1110_MAC_ADDR_FILT_LWR_REG(x)
Definition: adin1110.h:141
uint32_t no_os_field_get(uint32_t mask, uint32_t word)
#define ADIN1110_WR_FRAME_SIZE
Definition: adin1110.h:53
#define ADIN2111_P2_FWD_UNK2HOST_MASK
Definition: adin1110.h:82
Buffer structure used for frame RX and TX transactions.
Definition: adin1110.h:225
#define ADIN2111_MAC_ADDR_APPLY2PORT2
Definition: adin1110.h:135
uint8_t no_os_crc8(const uint8_t *table, const uint8_t *pdata, size_t nbytes, uint8_t crc)
Definition: adin1110.c:49
struct no_os_spi_init_param comm_param
Definition: adin1110.h:216
int adin1110_reg_write(struct adin1110_desc *desc, uint16_t addr, uint32_t data)
Write a register's value.
Definition: adin1110.c:72
#define ADIN1110_MDIO_ST
Definition: adin1110.h:106
int adin1110_remove(struct adin1110_desc *)
Free a device descriptor.
Definition: adin1110.c:936
#define ADIN1110_MAC_RST_STATUS_REG
Definition: adin1110.h:133
int adin1110_init(struct adin1110_desc **, struct adin1110_init_param *)
Initialize the device.
Definition: adin1110.c:848
enum adin1110_chip_id chip_type
Definition: adin1110.h:215
#define ADIN1110_TX_RDY_IRQ
Definition: adin1110.h:101
int adin1110_mdio_read_c45(struct adin1110_desc *desc, uint32_t phy_id, uint32_t dev_id, uint16_t reg, uint16_t *data)
Read a PHY register using clause 45.
Definition: adin1110.c:320
int adin1110_set_promisc(struct adin1110_desc *, uint32_t, bool)
Set a port in promiscuous mode. All MAC filters are dropped.
Definition: adin1110.c:759
int adin1110_mdio_write(struct adin1110_desc *desc, uint32_t phy_id, uint32_t reg, uint16_t data)
Write a PHY register using clause 22.
Definition: adin1110.c:222
int32_t no_os_gpio_set_value(struct no_os_gpio_desc *desc, uint8_t value)
Set the value of the specified GPIO.
Definition: no_os_gpio.c:197
uint32_t no_os_get_unaligned_be32(uint8_t *buf)
#define ADIN1110_BUFF_LEN
Definition: adin1110.h:42
int adin1110_link_state(struct adin1110_desc *, uint32_t *)
Reset both the MAC and PHY.
Definition: adin1110.c:739
#define ADIN1110_CONFIG1_REG
Definition: adin1110.h:78
ADIN1110 device descriptor.
Definition: adin1110.h:202
#define no_os_align(x, align)
Definition: no_os_util.h:121
#define ADIN1110_TX_FSIZE_REG
Definition: adin1110.h:125
#define ADIN1110_MDIO_DEVAD
Definition: adin1110.h:109
#define ADIN1110_SWRESET_KEY2
Definition: adin1110.h:71
#define ADIN1110_MDIO_TRDONE
Definition: adin1110.h:104
uint8_t mac_address[ADIN1110_ETH_ALEN]
Definition: adin1110.h:205
#define ADIN1110_SWRELEASE_KEY1
Definition: adin1110.h:72
#define ADIN1110_CRSM_SFT_PD_CNTRL_REG
Definition: adin1110.h:122
int32_t no_os_spi_remove(struct no_os_spi_desc *desc)
Free the resources allocated by no_os_spi_init().
Definition: no_os_spi.c:116
int adin1110_mdio_read(struct adin1110_desc *, uint32_t, uint32_t, uint16_t *)
Read a PHY register using clause 22.
Definition: adin1110.c:182
Header file of GPIO Interface.
#define ADIN1110_LINK_STATE_MASK
Definition: adin1110.h:92
int adin1110_set_promisc(struct adin1110_desc *desc, uint32_t port, bool promisc)
Set a port in promiscuous mode. All MAC filters are dropped.
Definition: adin1110.c:759
int adin1110_sw_reset(struct adin1110_desc *)
Reset both the MAC and PHY.
Definition: adin1110.c:728
#define ADIN1110_CRC_APPEND
Definition: adin1110.h:84
int32_t no_os_spi_init(struct no_os_spi_desc **desc, const struct no_os_spi_init_param *param)
Initialize the SPI communication peripheral.
Definition: no_os_spi.c:52
uint8_t mac_source[ADIN1110_ETH_ALEN]
Definition: adin1110.h:228
uint16_t no_os_get_unaligned_be16(uint8_t *buf)
#define ADIN1110_CD_MASK
Definition: adin1110.h:64
int adin1110_mdio_write(struct adin1110_desc *, uint32_t, uint32_t, uint16_t)
Write a PHY register using clause 22.
Definition: adin1110.c:222
struct no_os_gpio_init_param reset_param
Definition: adin1110.h:217
Header file of utility functions.
#define ADIN1110_WR_HDR_SIZE
Definition: adin1110.h:55
#define ADIN1110_FWD_UNK2HOST_MASK
Definition: adin1110.h:85
#define ADIN1110_RESET_REG
Definition: adin1110.h:68
bool append_crc
Definition: adin1110.h:219
#define ADIN1110_RESETC_MASK
Definition: adin1110.h:89
#define ADIN1110_ETH_ALEN
Definition: adin1110.h:43
#define ADIN1110_MDIOACC(x)
Definition: adin1110.h:103
int32_t no_os_gpio_direction_output(struct no_os_gpio_desc *desc, uint8_t value)
Enable the output direction of the specified GPIO.
Definition: no_os_gpio.c:147
dev_id
Definition: ad9361.h:3328
Header file of CRC-8 computation.
bool append_crc
Definition: adin1110.h:208
Error macro definition for ARM Compiler.
int adin1110_mdio_read(struct adin1110_desc *desc, uint32_t phy_id, uint32_t reg, uint16_t *data)
Read a PHY register using clause 22.
Definition: adin1110.c:182
Structure holding the parameters for SPI initialization.
Definition: no_os_spi.h:140
int32_t no_os_gpio_get_optional(struct no_os_gpio_desc **desc, const struct no_os_gpio_init_param *param)
Get the value of an optional GPIO.
Definition: no_os_gpio.c:75