adin1110.h File Reference

#include <stdbool.h>
#include "no_os_spi.h"
#include "no_os_gpio.h"
#include "no_os_util.h"
#include "oa_tc6.h"

Include dependency graph for adin1110.h:

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Go to the source code of this file.

Classes
struct	adin1110_desc
	ADIN1110 device descriptor. More...
struct	adin1110_init_param
	Initialization parameter for the device descriptor. More...
struct	adin1110_eth_buff
	Buffer structure used for frame RX and TX transactions. More...

Macros
#define	ADIN1110_BUFF_LEN   1530
#define	ADIN1110_ETH_ALEN   6
#define	ADIN1110_ETHERTYPE_LEN   2
#define	ADIN1110_ETH_HDR_LEN   14
#define	ADIN1110_ADDR_FILT_LEN   16
#define	ADIN1110_FCS_LEN   4
#define	ADIN1110_MAC_LEN   6
#define	ADIN1110_ADDR_MASK   NO_OS_GENMASK(12, 0)
#define	ADIN1110_RD_FRAME_SIZE   7
#define	ADIN1110_WR_FRAME_SIZE   6
#define	ADIN1110_RD_HDR_SIZE   3
#define	ADIN1110_WR_HDR_SIZE   2
#define	ADIN1110_PHY_ID_REG   1
#define	ADIN1110_PHY_ID   0x0283BC91
#define	ADIN2111_PHY_ID   0x0283BCA1
#define	ADIN1110_PORTS   1
#define	ADIN2111_PORTS   2
#define	ADIN1110_CD_MASK   NO_OS_BIT(15)
#define	ADIN1110_RW_MASK   NO_OS_BIT(13)
#define	ADIN1110_SOFT_RST_REG   0x3C
#define	ADIN1110_RESET_REG   0x03
#define	ADIN1110_SWRESET   NO_OS_BIT(0)
#define	ADIN1110_SWRESET_KEY1   0x4F1C
#define	ADIN1110_SWRESET_KEY2   0xC1F4
#define	ADIN1110_SWRELEASE_KEY1   0x6F1A
#define	ADIN1110_SWRELEASE_KEY2   0xA1F6
#define	ADIN1110_SPI_CD   NO_OS_BIT(7)
#define	ADIN1110_SPI_RW   NO_OS_BIT(5)
#define	ADIN1110_CONFIG1_REG   0x04
#define	ADIN1110_CONFIG1_SYNC   NO_OS_BIT(15)
#define	ADIN1110_CONFIG2_REG   0x06
#define	ADIN2111_P2_FWD_UNK2HOST_MASK   NO_OS_BIT(12)
#define	ADIN2111_PORT_CUT_THRU_EN   NO_OS_BIT(11)
#define	ADIN1110_CRC_APPEND   NO_OS_BIT(5)
#define	ADIN1110_FWD_UNK2HOST_MASK   NO_OS_BIT(2)
#define	ADIN1110_STATUS0_REG   0x08
#define	ADIN1110_STATUS0_TXPE_MASK   NO_OS_BIT(0)
#define	ADIN1110_RESETC_MASK   NO_OS_BIT(6)
#define	ADIN1110_STATUS1_REG   0x09
#define	ADIN1110_LINK_STATE_MASK   NO_OS_BIT(0)
#define	ADIN2111_P2_RX_RDY   NO_OS_BIT(17)
#define	ADIN1110_SPI_ERR   NO_OS_BIT(10)
#define	ADIN1110_RX_RDY   NO_OS_BIT(4)
#define	ADIN1110_IMASK1_REG   0x0D
#define	ADIN2111_RX_RDY_IRQ   NO_OS_BIT(17)
#define	ADIN1110_SPI_ERR_IRQ   NO_OS_BIT(10)
#define	ADIN1110_RX_RDY_IRQ   NO_OS_BIT(4)
#define	ADIN1110_TX_RDY_IRQ   NO_OS_BIT(3)
#define	ADIN1110_MDIOACC(x)
#define	ADIN1110_MDIO_TRDONE   NO_OS_BIT(31)
#define	ADIN1110_MDIO_TAERR   NO_OS_BIT(30)
#define	ADIN1110_MDIO_ST   NO_OS_GENMASK(29, 28)
#define	ADIN1110_MDIO_OP   NO_OS_GENMASK(27, 26)
#define	ADIN1110_MDIO_PRTAD   NO_OS_GENMASK(25, 21)
#define	ADIN1110_MDIO_DEVAD   NO_OS_GENMASK(20, 16)
#define	ADIN1110_MDIO_DATA   NO_OS_GENMASK(15, 0)
#define	ADIN1110_MMD_ACR_DEVAD_MASK   NO_OS_GENMASK(4, 0)
#define	ADIN1110_MMD_ACR_FUNCTION_MASK   NO_OS_GENMASK(15, 14)
#define	ADIN1110_MMD_ACCESS_MASK   NO_OS_GENMASK(15, 0)
#define	ADIN1110_MMD_ACCESS_CTRL_REG   0x0D
#define	ADIN1110_MMD_ACCESS_REG   0x0E
#define	ADIN1110_MI_SFT_PD_MASK   NO_OS_BIT(11)
#define	ADIN1110_MDIO_PHY_ID(x)
#define	ADIN1110_MI_CONTROL_REG   0x0
#define	ADIN1110_CRSM_SFT_PD_CNTRL_REG   0x8812
#define	ADIN1110_CRSM_SFT_PD_MASK   NO_OS_BIT(0)
#define	ADIN1110_TX_FSIZE_REG   0x30
#define	ADIN1110_TX_REG   0x31
#define	ADIN1110_TX_SPACE_REG   0x32
#define	ADIN1110_FIFO_CLR_REG   0x36
#define	ADIN1110_FIFO_CLR_RX_MASK   NO_OS_BIT(0)
#define	ADIN1110_FIFO_CLR_TX_MASK   NO_OS_BIT(1)
#define	ADIN1110_MAC_RST_STATUS_REG   0x3B
#define	ADIN2111_MAC_ADDR_APPLY2PORT2   NO_OS_BIT(31)
#define	ADIN1110_MAC_ADDR_APPLY2PORT   NO_OS_BIT(30)
#define	ADIN2111_MAC_ADDR_TO_OTHER_PORT   NO_OS_BIT(17)
#define	ADIN1110_MAC_ADDR_TO_HOST   NO_OS_BIT(16)
#define	ADIN1110_MAC_ADDR_FILT_UPR_REG(x)
#define	ADIN1110_MAC_ADDR_FILT_LWR_REG(x)
#define	ADIN1110_MAC_ADDR_UPR_MASK   NO_OS_GENMASK(15, 0)
#define	ADIN1110_MAC_ADDR_LWR_MASK   NO_OS_GENMASK(31, 0)
#define	ADIN1110_MAC_ADDR_MASK_UPR_REG   0x70
#define	ADIN1110_MAC_ADDR_MASK_LWR_REG   0x71
#define	ADIN1110_RX_FRM_CNT_REG   0xA0
#define	ADIN1110_RX_CRC_ERR_CNT_REG   0xA4
#define	ADIN1110_RX_ALGN_ERR_CNT_REG   0xA5
#define	ADIN1110_RX_LS_ERR_CNT_REG   0xA6
#define	ADIN1110_RX_PHY_ERR_CNT_REG   0xA7
#define	ADIN1110_TX_FRM_CNT_REG   0xA8
#define	ADIN1110_TX_BCAST_CNT_REG   0xA9
#define	ADIN1110_TX_MCAST_CNT_REG   0xAA
#define	ADIN1110_TX_UCAST_CNT_REG   0xAB
#define	ADIN1110_RX_BCAST_CNT_REG   0xA1
#define	ADIN1110_RX_MCAST_CNT_REG   0xA2
#define	ADIN1110_RX_UCAST_CNT_REG   0xA3
#define	ADIN1110_RX_DROP_FULL_CNT_REG   0xAC
#define	ADIN1110_RX_DROP_FILT_CNT_REG   0xAD
#define	ADIN1110_RX_FSIZE_REG   0x90
#define	ADIN1110_RX_REG   0x91
#define	ADIN2111_RX_P2_FSIZE_REG   0xC0
#define	ADIN2111_RX_P2_REG   0xC1
#define	ADIN1110_CLEAR_STATUS0   0xFFF
#define	ADIN1110_MDIO_OP_ADDR   0x0
#define	ADIN1110_MDIO_OP_WR   0x1
#define	ADIN1110_MDIO_OP_RD   0x3
#define	ADIN1110_WR_HEADER_LEN   2
#define	ADIN1110_FRAME_HEADER_LEN   2
#define	ADIN1110_RD_HEADER_LEN   3
#define	ADIN1110_REG_LEN   4
#define	ADIN1110_CRC_LEN   1
#define	ADIN1110_FEC_LEN   4
#define	ADIN_MAC_MULTICAST_ADDR_SLOT   0
#define	ADIN_MAC_BROADCAST_ADDR_SLOT   1
#define	ADIN_MAC_P1_ADDR_SLOT   2
#define	ADIN_MAC_P2_ADDR_SLOT   3
#define	ADIN_MAC_FDB_ADDR_SLOT   4

Enumerations
enum	adin1110_chip_id {   ADIN1110 ,   ADIN2111 }
	The chips supported by this driver. More...

Functions
int	adin1110_sw_reset (struct adin1110_desc *)
	Reset both the MAC and PHY.
int	adin1110_reg_update (struct adin1110_desc *, uint16_t, uint32_t, uint32_t)
	Update a register's value based on a mask.
int	adin1110_reg_write (struct adin1110_desc *, uint16_t, uint32_t)
	Write a register's value.
int	adin1110_reg_read (struct adin1110_desc *, uint16_t, uint32_t *)
	Read a register's value.
int	adin1110_write_fifo (struct adin1110_desc *, uint32_t, struct adin1110_eth_buff *)
	Write a frame to the TX FIFO.
int	adin1110_read_fifo (struct adin1110_desc *, uint32_t, struct adin1110_eth_buff *)
	Read a frame from the RX FIFO.
int	adin1110_mdio_write (struct adin1110_desc *, uint32_t, uint32_t, uint16_t)
	Write a PHY register using clause 22.
int	adin1110_mdio_read (struct adin1110_desc *, uint32_t, uint32_t, uint16_t *)
	Read a PHY register using clause 22.
int	adin1110_mdio_write_c45 (struct adin1110_desc *, uint32_t, uint32_t, uint32_t, uint16_t)
	Write a PHY register using clause 45.
int	adin1110_mdio_read_c45 (struct adin1110_desc *, uint32_t, uint32_t, uint16_t, uint16_t *)
	Read a PHY register using clause 45.
int	adin1110_link_state (struct adin1110_desc *, uint32_t *)
	Reset both the MAC and PHY.
int	adin1110_set_promisc (struct adin1110_desc *, uint32_t, bool)
	Set a port in promiscuous mode. All MAC filters are dropped.
int	adin1110_set_mac_addr (struct adin1110_desc *desc, uint8_t mac_address[ADIN1110_ETH_ALEN])
	Set a MAC address destination filter, frames who's DA doesn't match are dropped.
int	adin1110_broadcast_filter (struct adin1110_desc *, bool)
	Set/clear a broadcast filter. By enabling this, broadcast frames will be forwarded to the host.
int	adin1110_mac_reset (struct adin1110_desc *)
	Reset the MAC device.
int	adin1110_phy_reset (struct adin1110_desc *)
	Reset the PHY device.
int	adin1110_init (struct adin1110_desc **, struct adin1110_init_param *)
	Initialize the device.
int	adin1110_remove (struct adin1110_desc *)
	Free a device descriptor.

Macro Definition Documentation

ADIN1110_ADDR_FILT_LEN

#define ADIN1110_ADDR_FILT_LEN   16

ADIN1110_ADDR_MASK

#define ADIN1110_ADDR_MASK   NO_OS_GENMASK(12, 0)

ADIN1110_BUFF_LEN

#define ADIN1110_BUFF_LEN   1530

ADIN1110_CD_MASK

#define ADIN1110_CD_MASK   NO_OS_BIT(15)

ADIN1110_CLEAR_STATUS0

#define ADIN1110_CLEAR_STATUS0   0xFFF

ADIN1110_CONFIG1_REG

#define ADIN1110_CONFIG1_REG   0x04

ADIN1110_CONFIG1_SYNC

#define ADIN1110_CONFIG1_SYNC   NO_OS_BIT(15)

ADIN1110_CONFIG2_REG

#define ADIN1110_CONFIG2_REG   0x06

ADIN1110_CRC_APPEND

#define ADIN1110_CRC_APPEND   NO_OS_BIT(5)

ADIN1110_CRC_LEN

#define ADIN1110_CRC_LEN   1

ADIN1110_CRSM_SFT_PD_CNTRL_REG

#define ADIN1110_CRSM_SFT_PD_CNTRL_REG   0x8812

ADIN1110_CRSM_SFT_PD_MASK

#define ADIN1110_CRSM_SFT_PD_MASK   NO_OS_BIT(0)

ADIN1110_ETH_ALEN

#define ADIN1110_ETH_ALEN   6

ADIN1110_ETH_HDR_LEN

#define ADIN1110_ETH_HDR_LEN   14

ADIN1110_ETHERTYPE_LEN

#define ADIN1110_ETHERTYPE_LEN   2

ADIN1110_FCS_LEN

#define ADIN1110_FCS_LEN   4

ADIN1110_FEC_LEN

#define ADIN1110_FEC_LEN   4

ADIN1110_FIFO_CLR_REG

#define ADIN1110_FIFO_CLR_REG   0x36

ADIN1110_FIFO_CLR_RX_MASK

#define ADIN1110_FIFO_CLR_RX_MASK   NO_OS_BIT(0)

ADIN1110_FIFO_CLR_TX_MASK

#define ADIN1110_FIFO_CLR_TX_MASK   NO_OS_BIT(1)

ADIN1110_FRAME_HEADER_LEN

#define ADIN1110_FRAME_HEADER_LEN   2

ADIN1110_FWD_UNK2HOST_MASK

#define ADIN1110_FWD_UNK2HOST_MASK   NO_OS_BIT(2)

ADIN1110_IMASK1_REG

#define ADIN1110_IMASK1_REG   0x0D

ADIN1110_LINK_STATE_MASK

#define ADIN1110_LINK_STATE_MASK   NO_OS_BIT(0)

ADIN1110_MAC_ADDR_APPLY2PORT

#define ADIN1110_MAC_ADDR_APPLY2PORT   NO_OS_BIT(30)

ADIN1110_MAC_ADDR_FILT_LWR_REG

#define ADIN1110_MAC_ADDR_FILT_LWR_REG

(

x

)

Value:

(0x51 + 2 * (x))

ADIN1110_MAC_ADDR_FILT_UPR_REG

#define ADIN1110_MAC_ADDR_FILT_UPR_REG

(

x

)

Value:

(0x50 + 2 * (x))

ADIN1110_MAC_ADDR_LWR_MASK

#define ADIN1110_MAC_ADDR_LWR_MASK   NO_OS_GENMASK(31, 0)

ADIN1110_MAC_ADDR_MASK_LWR_REG

#define ADIN1110_MAC_ADDR_MASK_LWR_REG   0x71

ADIN1110_MAC_ADDR_MASK_UPR_REG

#define ADIN1110_MAC_ADDR_MASK_UPR_REG   0x70

ADIN1110_MAC_ADDR_TO_HOST

#define ADIN1110_MAC_ADDR_TO_HOST   NO_OS_BIT(16)

ADIN1110_MAC_ADDR_UPR_MASK

#define ADIN1110_MAC_ADDR_UPR_MASK   NO_OS_GENMASK(15, 0)

ADIN1110_MAC_LEN

#define ADIN1110_MAC_LEN   6

ADIN1110_MAC_RST_STATUS_REG

#define ADIN1110_MAC_RST_STATUS_REG   0x3B

ADIN1110_MDIO_DATA

#define ADIN1110_MDIO_DATA   NO_OS_GENMASK(15, 0)

ADIN1110_MDIO_DEVAD

#define ADIN1110_MDIO_DEVAD   NO_OS_GENMASK(20, 16)

ADIN1110_MDIO_OP

#define ADIN1110_MDIO_OP   NO_OS_GENMASK(27, 26)

ADIN1110_MDIO_OP_ADDR

#define ADIN1110_MDIO_OP_ADDR   0x0

ADIN1110_MDIO_OP_RD

#define ADIN1110_MDIO_OP_RD   0x3

ADIN1110_MDIO_OP_WR

#define ADIN1110_MDIO_OP_WR   0x1

ADIN1110_MDIO_PHY_ID

#define ADIN1110_MDIO_PHY_ID

(

x

)

Value:

((x) + 1)

ADIN1110_MDIO_PRTAD

#define ADIN1110_MDIO_PRTAD   NO_OS_GENMASK(25, 21)

ADIN1110_MDIO_ST

#define ADIN1110_MDIO_ST   NO_OS_GENMASK(29, 28)

ADIN1110_MDIO_TAERR

#define ADIN1110_MDIO_TAERR   NO_OS_BIT(30)

ADIN1110_MDIO_TRDONE

#define ADIN1110_MDIO_TRDONE   NO_OS_BIT(31)

ADIN1110_MDIOACC

#define ADIN1110_MDIOACC

(

x

)

Value:

(0x20 + (x))

ADIN1110_MI_CONTROL_REG

#define ADIN1110_MI_CONTROL_REG   0x0

ADIN1110_MI_SFT_PD_MASK

#define ADIN1110_MI_SFT_PD_MASK   NO_OS_BIT(11)

ADIN1110_MMD_ACCESS_CTRL_REG

#define ADIN1110_MMD_ACCESS_CTRL_REG   0x0D

ADIN1110_MMD_ACCESS_MASK

#define ADIN1110_MMD_ACCESS_MASK   NO_OS_GENMASK(15, 0)

ADIN1110_MMD_ACCESS_REG

#define ADIN1110_MMD_ACCESS_REG   0x0E

ADIN1110_MMD_ACR_DEVAD_MASK

#define ADIN1110_MMD_ACR_DEVAD_MASK   NO_OS_GENMASK(4, 0)

ADIN1110_MMD_ACR_FUNCTION_MASK

#define ADIN1110_MMD_ACR_FUNCTION_MASK   NO_OS_GENMASK(15, 14)

ADIN1110_PHY_ID

#define ADIN1110_PHY_ID   0x0283BC91

ADIN1110_PHY_ID_REG

#define ADIN1110_PHY_ID_REG   1

ADIN1110_PORTS

#define ADIN1110_PORTS   1

ADIN1110_RD_FRAME_SIZE

#define ADIN1110_RD_FRAME_SIZE   7

ADIN1110_RD_HDR_SIZE

#define ADIN1110_RD_HDR_SIZE   3

ADIN1110_RD_HEADER_LEN

#define ADIN1110_RD_HEADER_LEN   3

ADIN1110_REG_LEN

#define ADIN1110_REG_LEN   4

ADIN1110_RESET_REG

#define ADIN1110_RESET_REG   0x03

ADIN1110_RESETC_MASK

#define ADIN1110_RESETC_MASK   NO_OS_BIT(6)

ADIN1110_RW_MASK

#define ADIN1110_RW_MASK   NO_OS_BIT(13)

ADIN1110_RX_ALGN_ERR_CNT_REG

#define ADIN1110_RX_ALGN_ERR_CNT_REG   0xA5

ADIN1110_RX_BCAST_CNT_REG

#define ADIN1110_RX_BCAST_CNT_REG   0xA1

ADIN1110_RX_CRC_ERR_CNT_REG

#define ADIN1110_RX_CRC_ERR_CNT_REG   0xA4

ADIN1110_RX_DROP_FILT_CNT_REG

#define ADIN1110_RX_DROP_FILT_CNT_REG   0xAD

ADIN1110_RX_DROP_FULL_CNT_REG

#define ADIN1110_RX_DROP_FULL_CNT_REG   0xAC

ADIN1110_RX_FRM_CNT_REG

#define ADIN1110_RX_FRM_CNT_REG   0xA0

ADIN1110_RX_FSIZE_REG

#define ADIN1110_RX_FSIZE_REG   0x90

ADIN1110_RX_LS_ERR_CNT_REG

#define ADIN1110_RX_LS_ERR_CNT_REG   0xA6

ADIN1110_RX_MCAST_CNT_REG

#define ADIN1110_RX_MCAST_CNT_REG   0xA2

ADIN1110_RX_PHY_ERR_CNT_REG

#define ADIN1110_RX_PHY_ERR_CNT_REG   0xA7

ADIN1110_RX_RDY

#define ADIN1110_RX_RDY   NO_OS_BIT(4)

ADIN1110_RX_RDY_IRQ

#define ADIN1110_RX_RDY_IRQ   NO_OS_BIT(4)

ADIN1110_RX_REG

#define ADIN1110_RX_REG   0x91

ADIN1110_RX_UCAST_CNT_REG

#define ADIN1110_RX_UCAST_CNT_REG   0xA3

ADIN1110_SOFT_RST_REG

#define ADIN1110_SOFT_RST_REG   0x3C

ADIN1110_SPI_CD

#define ADIN1110_SPI_CD   NO_OS_BIT(7)

ADIN1110_SPI_ERR

#define ADIN1110_SPI_ERR   NO_OS_BIT(10)

ADIN1110_SPI_ERR_IRQ

#define ADIN1110_SPI_ERR_IRQ   NO_OS_BIT(10)

ADIN1110_SPI_RW

#define ADIN1110_SPI_RW   NO_OS_BIT(5)

ADIN1110_STATUS0_REG

#define ADIN1110_STATUS0_REG   0x08

ADIN1110_STATUS0_TXPE_MASK

#define ADIN1110_STATUS0_TXPE_MASK   NO_OS_BIT(0)

ADIN1110_STATUS1_REG

#define ADIN1110_STATUS1_REG   0x09

ADIN1110_SWRELEASE_KEY1

#define ADIN1110_SWRELEASE_KEY1   0x6F1A

ADIN1110_SWRELEASE_KEY2

#define ADIN1110_SWRELEASE_KEY2   0xA1F6

ADIN1110_SWRESET

#define ADIN1110_SWRESET   NO_OS_BIT(0)

ADIN1110_SWRESET_KEY1

#define ADIN1110_SWRESET_KEY1   0x4F1C

ADIN1110_SWRESET_KEY2

#define ADIN1110_SWRESET_KEY2   0xC1F4

ADIN1110_TX_BCAST_CNT_REG

#define ADIN1110_TX_BCAST_CNT_REG   0xA9

ADIN1110_TX_FRM_CNT_REG

#define ADIN1110_TX_FRM_CNT_REG   0xA8

ADIN1110_TX_FSIZE_REG

#define ADIN1110_TX_FSIZE_REG   0x30

ADIN1110_TX_MCAST_CNT_REG

#define ADIN1110_TX_MCAST_CNT_REG   0xAA

ADIN1110_TX_RDY_IRQ

#define ADIN1110_TX_RDY_IRQ   NO_OS_BIT(3)

ADIN1110_TX_REG

#define ADIN1110_TX_REG   0x31

ADIN1110_TX_SPACE_REG

#define ADIN1110_TX_SPACE_REG   0x32

ADIN1110_TX_UCAST_CNT_REG

#define ADIN1110_TX_UCAST_CNT_REG   0xAB

ADIN1110_WR_FRAME_SIZE

#define ADIN1110_WR_FRAME_SIZE   6

ADIN1110_WR_HDR_SIZE

#define ADIN1110_WR_HDR_SIZE   2

ADIN1110_WR_HEADER_LEN

#define ADIN1110_WR_HEADER_LEN   2

ADIN2111_MAC_ADDR_APPLY2PORT2

#define ADIN2111_MAC_ADDR_APPLY2PORT2   NO_OS_BIT(31)

ADIN2111_MAC_ADDR_TO_OTHER_PORT

#define ADIN2111_MAC_ADDR_TO_OTHER_PORT   NO_OS_BIT(17)

ADIN2111_P2_FWD_UNK2HOST_MASK

#define ADIN2111_P2_FWD_UNK2HOST_MASK   NO_OS_BIT(12)

ADIN2111_P2_RX_RDY

#define ADIN2111_P2_RX_RDY   NO_OS_BIT(17)

ADIN2111_PHY_ID

#define ADIN2111_PHY_ID   0x0283BCA1

ADIN2111_PORT_CUT_THRU_EN

#define ADIN2111_PORT_CUT_THRU_EN   NO_OS_BIT(11)

ADIN2111_PORTS

#define ADIN2111_PORTS   2

ADIN2111_RX_P2_FSIZE_REG

#define ADIN2111_RX_P2_FSIZE_REG   0xC0

ADIN2111_RX_P2_REG

#define ADIN2111_RX_P2_REG   0xC1

ADIN2111_RX_RDY_IRQ

#define ADIN2111_RX_RDY_IRQ   NO_OS_BIT(17)

ADIN_MAC_BROADCAST_ADDR_SLOT

#define ADIN_MAC_BROADCAST_ADDR_SLOT   1

ADIN_MAC_FDB_ADDR_SLOT

#define ADIN_MAC_FDB_ADDR_SLOT   4

ADIN_MAC_MULTICAST_ADDR_SLOT

#define ADIN_MAC_MULTICAST_ADDR_SLOT   0

ADIN_MAC_P1_ADDR_SLOT

#define ADIN_MAC_P1_ADDR_SLOT   2

ADIN_MAC_P2_ADDR_SLOT

#define ADIN_MAC_P2_ADDR_SLOT   3

Enumeration Type Documentation

adin1110_chip_id

enum adin1110_chip_id

The chips supported by this driver.

Enumerator
ADIN1110
ADIN2111

Function Documentation

adin1110_broadcast_filter()

int adin1110_broadcast_filter	(	struct adin1110_desc *	desc,
		bool	enabled )

Set/clear a broadcast filter. By enabling this, broadcast frames will be forwarded to the host.

Parameters

desc	- the device descriptor
enabled	- the set/clear option

Returns

0 in case of success, negative error code otherwise

adin1110_init()

int adin1110_init	(	struct adin1110_desc **	desc,
		struct adin1110_init_param *	param )

Initialize the device.

Parameters

desc	- the device descriptor to be initialized
param	- the device's parameter

Returns

0 in case of success, negative error code otherwise

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adin1110_link_state()

int adin1110_link_state	(	struct adin1110_desc *	desc,
		uint32_t *	state )

Reset both the MAC and PHY.

Parameters

desc	- the device descriptor
state	- status (up/down) of the link

Returns

0 in case of success, negative error code otherwise

adin1110_mac_reset()

int adin1110_mac_reset

(

struct adin1110_desc *

desc

)

Reset the MAC device.

Parameters

desc	- the device descriptor

Returns

0 in case of success, negative error code otherwise

adin1110_mdio_read()

int adin1110_mdio_read	(	struct adin1110_desc *	desc,
		uint32_t	phy_id,
		uint32_t	reg,
		uint16_t *	data )

Read a PHY register using clause 22.

Parameters

desc	- the device descriptor
phy_id	- the phy device's id
reg	- register's address
data	- register's value

Returns

0 in case of success, negative error code otherwise

adin1110_mdio_read_c45()

int adin1110_mdio_read_c45	(	struct adin1110_desc *	desc,
		uint32_t	phy_id,
		uint32_t	dev_id,
		uint16_t	reg,
		uint16_t *	data )

Read a PHY register using clause 45.

Parameters

desc	- the device descriptor
phy_id	- the phy device's MDIO id
dev_id	- the device id of the register
reg	- register's address
data	- register's value

Returns

0 in case of success, negative error code otherwise

adin1110_mdio_write()

int adin1110_mdio_write	(	struct adin1110_desc *	desc,
		uint32_t	phy_id,
		uint32_t	reg,
		uint16_t	data )

Write a PHY register using clause 22.

Parameters

desc	- the device descriptor
phy_id	- the phy device's id
reg	- register's address
data	- register's value

Returns

0 in case of success, negative error code otherwise

adin1110_mdio_write_c45()

int adin1110_mdio_write_c45	(	struct adin1110_desc *	desc,
		uint32_t	phy_id,
		uint32_t	dev_id,
		uint32_t	reg,
		uint16_t	data )

Write a PHY register using clause 45.

Parameters

desc	- the device descriptor
phy_id	- the phy device's MDIO id
dev_id	- the device id of the register
reg	- register's address
data	- register's value

Returns

0 in case of success, negative error code otherwise

adin1110_phy_reset()

int adin1110_phy_reset

(

struct adin1110_desc *

desc

)

Reset the PHY device.

Parameters

desc	- the device descriptor

Returns

0 in case of success, negative error code otherwise

adin1110_read_fifo()

int adin1110_read_fifo	(	struct adin1110_desc *	desc,
		uint32_t	port,
		struct adin1110_eth_buff *	eth_buff )

Read a frame from the RX FIFO.

Parameters

desc	- the device descriptor
port	- the port from which the frame shall be received.
eth_buff	- the frame to be received.

Returns

0 in case of success, negative error code otherwise

Burst read the whole frame

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adin1110_reg_read()

int adin1110_reg_read	(	struct adin1110_desc *	desc,
		uint16_t	addr,
		uint32_t *	data )

Read a register's value.

Parameters

desc	- the device descriptor
addr	- register's address
data	- register's value

Returns

0 in case of success, negative error code otherwise

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adin1110_reg_update()

int adin1110_reg_update	(	struct adin1110_desc *	desc,
		uint16_t	addr,
		uint32_t	mask,
		uint32_t	data )

Update a register's value based on a mask.

Parameters

desc	- the device descriptor
addr	- register's address
mask	- the bits that may be modified
data	- register's value

Returns

0 in case of success, negative error code otherwise

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adin1110_reg_write()

int adin1110_reg_write	(	struct adin1110_desc *	desc,
		uint16_t	addr,
		uint32_t	data )

Write a register's value.

Parameters

desc	- the device descriptor
addr	- register's address
data	- register's value

Returns

0 in case of success, negative error code otherwise

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adin1110_remove()

int adin1110_remove

(

struct adin1110_desc *

desc

)

Free a device descriptor.

Parameters

desc	- the device descriptor to be removed.

Returns

0 in case of success, negative error code otherwise

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adin1110_set_mac_addr()

int adin1110_set_mac_addr	(	struct adin1110_desc *	desc,
		uint8_t	mac_address[ADIN1110_ETH_ALEN] )

Set a MAC address destination filter, frames who's DA doesn't match are dropped.

Parameters

desc	- the device descriptor
mac_address	- the MAC filter to be set

Returns

0 in case of success, negative error code otherwise

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adin1110_set_promisc()

int adin1110_set_promisc	(	struct adin1110_desc *	desc,
		uint32_t	port,
		bool	promisc )

Set a port in promiscuous mode. All MAC filters are dropped.

Parameters

desc	- the device descriptor
port	- the port for which the mode will be applied
promisc	- either enable or disable the promiscuous mode.

Returns

0 in case of success, negative error code otherwise

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adin1110_sw_reset()

int adin1110_sw_reset

(

struct adin1110_desc *

desc

)

Reset both the MAC and PHY.

Parameters

desc	- the device descriptor

Returns

0 in case of success, negative error code otherwise

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adin1110_write_fifo()

int adin1110_write_fifo	(	struct adin1110_desc *	desc,
		uint32_t	port,
		struct adin1110_eth_buff *	eth_buff )

Write a frame to the TX FIFO.

Parameters

desc	- the device descriptor
port	- the port for the frame to be transmitted on.
eth_buff	- the frame to be transmitted.

Returns

0 in case of success, negative error code otherwise

Align the frame length to 4 bytes

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