Basic example main executiont.
Basic example main execution.
- Returns
- ret - Result of the example execution. If working correctly, will execute continuously the while(1) loop and will not return.
Basic example main executiont.
- 50 ADC readings with delay.
- Threshold event (non-blocking).
- Returns
- ret - Result of the example execution. If working correctly, will execute continuously the while(1) loop and will not return.
Basic example main executiont.
- Returns
- ret - Result of the example execution. If working correctly, will execute print the sample data.
Basic example main executiont.
- Returns
- ret - Result of the example execution. If working correctly, will execute continuously the while(1) loop and will not return.
Basic example main executiont.
- Returns
- ret - 0 on success.
Basic example main executiont.
- Returns
- ret - Result of the example execution. If working correctly, will execute continuously function iio_app_run and will not return.
Basic example main executiont.
- Returns
- ret - Result of the example execution. If working correctly, will measure active and reactive energy and RMS for channel A and for voltage stopping whenever an interrupt occurs and resulting in a stoppage of the measurement.
Basic example main executiont.
- Returns
- ret - Result of the example execution.
Basic example main executiont.
This example demonstrates basic ADMT4000 functionality by continuously reading sensor values and displaying them on the console.
- Returns
- 0 in case of success, negative error code otherwise.
Basic example main executiont.
Brings up the full JESD204 link between the FPGA and the ADRV903X:
- AD9528 clock synthesizer setup (DEVCLK + SYSREF)
- SYSREF_REQ GPIO configuration
- ADXCVR initialization (TX and RX)
- AXI JESD204 TX and RX controller initialization
- ADRV903X initialization (firmware load up to PreMcsInit_NonBroadcast)
- AXI clkgen setup (lane_rate / 66 for JESD204C)
- JESD204 topology initialization and FSM start FSM drives: MCS (LINK_SETUP/OPT_SETUP_STAGE1/2) + link enable
- JESD204 link status readback
- Returns
- 0 on success, negative error code on failure.
Basic example main executiont.
Brings up the full JESD204 link and demonstrates DMA data transfer:
- AD9528 clock synthesizer setup (DEVCLK + SYSREF)
- SYSREF_REQ GPIO configuration
- ADXCVR initialization (TX and RX)
- AXI JESD204 TX and RX controller initialization
- ADRV903X initialization (firmware load up to PreMcsInit_NonBroadcast)
- AXI clkgen setup (lane_rate / 66 for JESD204C)
- AXI DAC core init — load sine wave LUT into TX DMA buffer
- AXI ADC core init — reset TPL ADC core + IQ correction
- TX and RX DMAC initialization
- JESD204 topology initialization and FSM start FSM drives: MCS (LINK_SETUP/OPT_SETUP_STAGE1/2) + link enable
- Start TX DMA (continuous sine wave to DAC)
- Wait 1 s then capture RX DMA samples
- Print buffer addresses for inspection
- Returns
- 0 on success, negative error code on failure.
Basic example main executiont.
Brings up the full JESD204 link and starts the IIO application loop:
- AD9528 clock synthesizer setup (DEVCLK + SYSREF)
- SYSREF_REQ GPIO configuration
- ADXCVR initialization (TX and RX)
- AXI JESD204 TX and RX controller initialization
- ADRV903X initialization (firmware load up to PreMcsInit_NonBroadcast)
- AXI clkgen setup (lane_rate / 66 for JESD204C)
- AXI DAC core init — DDS mode (IIO Oscilloscope controls tones)
- AXI ADC core init — reset TPL + IQ correction
- RX data offload — normal mode + per-capture XFER_LENGTH + RESETN
- TX and RX DMAC initialization
- JESD204 topology initialization and FSM start
- IIO application init and run (blocking)
- Returns
- 0 on success, negative error code on failure.
Basic example main executiont.
- Returns
- ret - Result of the example execution. If working correctly, will execute continuously function iio_app_run_with_trigs and will not return.
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