Basic example main executiont.
Basic example main execution.
- Returns
- ret - Result of the example execution. If working correctly, will execute continuously the while(1) loop and will not return.
Basic example main executiont.
- 50 ADC readings with delay.
- Threshold event (non-blocking).
- Returns
- ret - Result of the example execution. If working correctly, will execute continuously the while(1) loop and will not return.
Basic example main executiont.
- Returns
- ret - Result of the example execution. If working correctly, will execute continuously the while(1) loop and will not return.
Basic example main executiont.
- Returns
- ret - Result of the example execution. If working correctly, will execute continuously function iio_app_run and will not return.
Basic example main executiont.
- Returns
- ret - Result of the example execution.
Basic example main executiont.
Brings up the full JESD204 link between the FPGA and the ADRV903X:
- AD9528 clock synthesizer setup (DEVCLK + SYSREF)
- SYSREF_REQ GPIO configuration
- ADXCVR initialization (TX and RX)
- AXI JESD204 TX and RX controller initialization
- ADRV903X initialization (firmware load up to PreMcsInit_NonBroadcast)
- AXI clkgen setup (lane_rate / 66 for JESD204C)
- JESD204 topology initialization and FSM start FSM drives: MCS (LINK_SETUP/OPT_SETUP_STAGE1/2) + link enable
- JESD204 link status readback
- Returns
- 0 on success, negative error code on failure.
Basic example main executiont.
Brings up the full JESD204 link and demonstrates DMA data transfer:
- AD9528 clock synthesizer setup (DEVCLK + SYSREF)
- SYSREF_REQ GPIO configuration
- ADXCVR initialization (TX and RX)
- AXI JESD204 TX and RX controller initialization
- ADRV903X initialization (firmware load up to PreMcsInit_NonBroadcast)
- AXI clkgen setup (lane_rate / 66 for JESD204C)
- AXI DAC core init — load sine wave LUT into TX DMA buffer
- AXI ADC core init — reset TPL ADC core + IQ correction
- TX and RX DMAC initialization
- JESD204 topology initialization and FSM start FSM drives: MCS (LINK_SETUP/OPT_SETUP_STAGE1/2) + link enable
- Start TX DMA (continuous sine wave to DAC)
- Wait 1 s then capture RX DMA samples
- Print buffer addresses for inspection
- Returns
- 0 on success, negative error code on failure.
Basic example main executiont.
Brings up the full JESD204 link and starts the IIO application loop:
- AD9528 clock synthesizer setup (DEVCLK + SYSREF)
- SYSREF_REQ GPIO configuration
- ADXCVR initialization (TX and RX)
- AXI JESD204 TX and RX controller initialization
- ADRV903X initialization (firmware load up to PreMcsInit_NonBroadcast)
- AXI clkgen setup (lane_rate / 66 for JESD204C)
- AXI DAC core init — DDS mode (IIO Oscilloscope controls tones)
- AXI ADC core init — reset TPL + IQ correction
- RX data offload — normal mode + per-capture XFER_LENGTH + RESETN
- TX and RX DMAC initialization
- JESD204 topology initialization and FSM start
- IIO application init and run (blocking)
- Returns
- 0 on success, negative error code on failure.
Basic example main executiont.
- Returns
- ret - Result of the example execution. If working correctly, will execute continuously function iio_app_run_with_trigs and will not return.
Basic example main executiont.
- Returns
- 0 in case of success, negative error code otherwise.
IIO descriptor and initialization parameter.
IIO app.
Declaring iio_devices structure
Initializing IIO app init param.
Initializing IIO app.
Running the IIO app (use iio_info or osc in terminal).
Set the threshold voltage to 5V
The comparator output will be available on the GPO_A pin
Set the DAC output on channel C to 5V
Measure input current on channel D
Initialize the ADC_RDY GPIO and associated IRQ event
- Returns
- 0 if success, negative error code otherwise
Negative temperature
Positive temperature
Negative temperature
Positive temperature
