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Macros
#define	CFGL_SPI_ARQ2_MASK (0xFFU)

#define	CFGL_GPIO_ARQ2_MASK (0xFFU)

#define	CFGL_IIC_X_ARQ2_MASK (0xFFU)

#define	CFGL_IIC_Y_ARQ2_MASK (0xFFU)

#define	PHY1_HS_ERR_MIPI_RX_MIPI_RX12_LANE0_1B_ERR_MASK (0x01U)

#define	PHY1_HS_ERR_MIPI_RX_MIPI_RX12_LANE0_1B_ERR_POS (0U)

#define	PHY1_HS_ERR_MIPI_RX_MIPI_RX12_LANE1_1B_ERR_MASK (0x02U)

#define	PHY1_HS_ERR_MIPI_RX_MIPI_RX12_LANE1_1B_ERR_POS (1U)

#define	PHY1_HS_ERR_MIPI_RX_MIPI_RX12_LANE0_2B_ERR_MASK (0x04U)

#define	PHY1_HS_ERR_MIPI_RX_MIPI_RX12_LANE0_2B_ERR_POS (2U)

#define	PHY1_HS_ERR_MIPI_RX_MIPI_RX12_LANE1_2B_ERR_MASK (0x08U)

#define	PHY1_HS_ERR_MIPI_RX_MIPI_RX12_LANE1_2B_ERR_POS (3U)

#define	PHY1_HS_ERR_MIPI_RX_MIPI_RX12_SKEW_CALIB_LANE1_ERR_MASK (0x10U)

#define	PHY1_HS_ERR_MIPI_RX_MIPI_RX12_SKEW_CALIB_LANE1_ERR_POS (4U)

#define	PHY1_HS_ERR_MIPI_RX_MIPI_RX12_SKEW_CALIB_LANE0_ERR_MASK (0x20U)

#define	PHY1_HS_ERR_MIPI_RX_MIPI_RX12_SKEW_CALIB_LANE0_ERR_POS (5U)

#define	PHY2_HS_ERR_MIPI_RX_MIPI_RX14_LANE0_2B_ERR_MASK (0x01U)

#define	PHY2_HS_ERR_MIPI_RX_MIPI_RX14_LANE0_2B_ERR_POS (0U)

#define	PHY2_HS_ERR_MIPI_RX_MIPI_RX14_LANE1_2B_ERR_MASK (0x02U)

#define	PHY2_HS_ERR_MIPI_RX_MIPI_RX14_LANE1_2B_ERR_POS (1U)

#define	PHY2_HS_ERR_MIPI_RX_MIPI_RX14_LANE0_1B_ERR_MASK (0x04U)

#define	PHY2_HS_ERR_MIPI_RX_MIPI_RX14_LANE0_1B_ERR_POS (2U)

#define	PHY2_HS_ERR_MIPI_RX_MIPI_RX14_LANE1_1B_ERR_MASK (0x08U)

#define	PHY2_HS_ERR_MIPI_RX_MIPI_RX14_LANE1_1B_ERR_POS (3U)

#define	PHY2_HS_ERR_MIPI_RX_MIPI_RX14_SKEW_CALIB_LANE1_ERR_MASK (0x10U)

#define	PHY2_HS_ERR_MIPI_RX_MIPI_RX14_SKEW_CALIB_LANE1_ERR_POS (4U)

#define	PHY2_HS_ERR_MIPI_RX_MIPI_RX14_SKEW_CALIB_LANE0_ERR_MASK (0x20U)

#define	PHY2_HS_ERR_MIPI_RX_MIPI_RX14_SKEW_CALIB_LANE0_ERR_POS (5U)

#define	CTRL1_CSI_ERR_L_MIPI_RX_MIPI_RX19_1B_ECC_ERR_MASK (0x01U)

#define	CTRL1_CSI_ERR_L_MIPI_RX_MIPI_RX19_1B_ECC_ERR_POS (0U)

#define	CTRL1_CSI_ERR_L_MIPI_RX_MIPI_RX19_2B_ECC_ERR_MASK (0x02U)

#define	CTRL1_CSI_ERR_L_MIPI_RX_MIPI_RX19_2B_ECC_ERR_POS (1U)

#define	CTRL1_CSI_ERR_L_MIPI_RX_MIPI_RX19_CRC_ERR_MASK (0x80U)

#define	CTRL1_CSI_ERR_L_MIPI_RX_MIPI_RX19_CRC_ERR_POS (7U)

#define	CTRL1_CSI_ERR_H_MIPI_RX_MIPI_RX20_ALL_MASK (0xFFU)

#define	CTRL1_CSI_ERR_H_MIPI_RX_MIPI_RX20_PKT_TERM_EARLY_ERR_MASK (0x01U)

#define	CTRL1_CSI_ERR_H_MIPI_RX_MIPI_RX20_PKT_TERM_EARLY_ERR_POS (0U)

#define	CTRL1_CSI_ERR_H_MIPI_RX_MIPI_RX20_FRAME_CNT_ERR_MASK (0x02U)

#define	CTRL1_CSI_ERR_H_MIPI_RX_MIPI_RX20_FRAME_CNT_ERR_POS (1U)

#define	PHY1_LP_ERR_MIPI_RX_MIPI_RX11_UNRECOGNIZED_ESC_CMD_RCVD_ON_D0_MASK (0x01U)

#define	PHY1_LP_ERR_MIPI_RX_MIPI_RX11_UNRECOGNIZED_ESC_CMD_RCVD_ON_D0_POS (0U)

#define	PHY1_LP_ERR_MIPI_RX_MIPI_RX11_UNRECOGNIZED_ESC_CMD_RCVD_ON_CLK_MASK (0x02U)

#define	PHY1_LP_ERR_MIPI_RX_MIPI_RX11_UNRECOGNIZED_ESC_CMD_RCVD_ON_CLK_POS (1U)

#define	PHY1_LP_ERR_MIPI_RX_MIPI_RX11_INVALID_LINE_SEQ_ON_D0_MASK (0x04U)

#define	PHY1_LP_ERR_MIPI_RX_MIPI_RX11_INVALID_LINE_SEQ_ON_D0_POS (2U)

#define	PHY1_LP_ERR_MIPI_RX_MIPI_RX11_INVALID_LINE_SEQ_ON_D1_MASK (0x08U)

#define	PHY1_LP_ERR_MIPI_RX_MIPI_RX11_INVALID_LINE_SEQ_ON_D1_POS (3U)

#define	PHY1_LP_ERR_MIPI_RX_MIPI_RX11_INVALID_LINE_SEQ_ON_CLK_MASK (0x10U)

#define	PHY1_LP_ERR_MIPI_RX_MIPI_RX11_INVALID_LINE_SEQ_ON_CLK_POS (4U)

#define	PHY2_LP_ERR_MIPI_RX_MIPI_RX13_UNRECOGNIZED_ESC_CMD_RCVD_ON_D0_MASK (0x01U)

#define	PHY2_LP_ERR_MIPI_RX_MIPI_RX13_UNRECOGNIZED_ESC_CMD_RCVD_ON_D0_POS (0U)

#define	PHY2_LP_ERR_MIPI_RX_MIPI_RX13_UNRECOGNIZED_ESC_CMD_RCVD_ON_CLK_MASK (0x02U)

#define	PHY2_LP_ERR_MIPI_RX_MIPI_RX13_UNRECOGNIZED_ESC_CMD_RCVD_ON_CLK_POS (1U)

#define	PHY2_LP_ERR_MIPI_RX_MIPI_RX13_INVALID_LINE_SEQ_ON_D0_MASK (0x04U)

#define	PHY2_LP_ERR_MIPI_RX_MIPI_RX13_INVALID_LINE_SEQ_ON_D0_POS (2U)

#define	PHY2_LP_ERR_MIPI_RX_MIPI_RX13_INVALID_LINE_SEQ_ON_D1_MASK (0x08U)

#define	PHY2_LP_ERR_MIPI_RX_MIPI_RX13_INVALID_LINE_SEQ_ON_D1_POS (3U)

#define	PHY2_LP_ERR_MIPI_RX_MIPI_RX13_INVALID_LINE_SEQ_ON_CLK_MASK (0x10U)

#define	PHY2_LP_ERR_MIPI_RX_MIPI_RX13_INVALID_LINE_SEQ_ON_CLK_POS (4U)

#define	RX_FEC_EN_GMSL_TX0_ADDR (0x28U)

#define	RX_FEC_EN_GMSL_TX0_MASK (0x01U)

#define	RX_FEC_EN_GMSL_TX0_POS (0U)

#define	PHY_CONFIG_MIPI_RX_MIPI_RX0_ADDR (0x330U)

#define	PHY_CONFIG_MIPI_RX_MIPI_RX0_MASK (0x07U)

#define	PHY_CONFIG_MIPI_RX_MIPI_RX0_POS (0U)

#define	PHY2_LANE_MAP_SER_LANE_0_MIPI_RX_MIPI_RX3_MASK (0x03U)

#define	PHY2_LANE_MAP_SER_LANE_0_MIPI_RX_MIPI_RX3_POS (0U)

#define	PHY2_LANE_MAP_SER_LANE_1_MIPI_RX_MIPI_RX3_MASK (0x0CU)

#define	PHY2_LANE_MAP_SER_LANE_1_MIPI_RX_MIPI_RX3_POS (2U)

#define	PHY1_LANE_MAP_SER_LANE_2_MIPI_RX_MIPI_RX2_MASK (0x30U)

#define	PHY1_LANE_MAP_SER_LANE_2_MIPI_RX_MIPI_RX2_POS (4U)

#define	PHY1_LANE_MAP_SER_LANE_3_MIPI_RX_MIPI_RX2_MASK (0xC0U)

#define	PHY1_LANE_MAP_SER_LANE_3_MIPI_RX_MIPI_RX2_POS (6U)

#define	PHY2_POL_MAP_CLK_LANE_MIPI_RX_MIPI_RX5_MASK (0x04U)

#define	PHY2_POL_MAP_CLK_LANE_MIPI_RX_MIPI_RX5_POS (2U)

#define	PHY2_POL_MAP_DATA_LANE_0_MIPI_RX_MIPI_RX5_MASK (0x01U)

#define	PHY2_POL_MAP_DATA_LANE_0_MIPI_RX_MIPI_RX5_POS (0U)

#define	PHY2_POL_MAP_DATA_LANE_1_MIPI_RX_MIPI_RX5_MASK (0x02U)

#define	PHY2_POL_MAP_DATA_LANE_1_MIPI_RX_MIPI_RX5_POS (1U)

#define	PHY1_POL_MAP_DATA_LANE_2_MIPI_RX_MIPI_RX5_MASK (0x01U)

#define	PHY1_POL_MAP_DATA_LANE_2_MIPI_RX_MIPI_RX5_POS (0U)

#define	PHY1_POL_MAP_DATA_LANE_3_MIPI_RX_MIPI_RX5_MASK (0x02U)

#define	PHY1_POL_MAP_DATA_LANE_3_MIPI_RX_MIPI_RX5_POS (1U)

#define	PHY1_LANE_MAP_MIPI_RX_MIPI_RX2_ALL_MASK (0xFFU)

#define	PHY1_POL_MAP_MIPI_RX_MIPI_RX4_ALL_MASK (0xFFU)

#define	FRONTTOP_EXT12_ADDR (0x3CAU)

#define	FRONTTOP_EXT12_MASK (0xFFU)

#define	FRONTTOP_EXT13_ADDR (0x3CBU)

#define	FRONTTOP_EXT13_MASK (0xFFU)

#define	DATA_TYPE_MASK (0x3FU)

#define	DATA_TYPE_ENABLE_MASK (0x40U)

#define	DATA_TYPE_ENABLE_POS (6U)

#define	INDEPENDENT_VS_FRONTTOP_13_ADDR (0x315U)

#define	INDEPENDENT_VS_FRONTTOP_13_MASK (0x80U)

#define	CLK_SELZ_FRONTTOP_FRONTTOP_0_MASK (0x04U)

#define	CLK_SELZ_FRONTTOP_FRONTTOP_0_POS (2U)

#define	FRONTTOP_FRONTTOP_0_ALL_MASK (0xFFU)

#define	DEV_REG0_ADDR 0x00U

#define	DEV_REG0_DEFAULT 0x80U

#define	CFG_BLOCK_DEV_REG0_ADDR 0x00U

#define	CFG_BLOCK_DEV_REG0_MASK 0x01U

#define	CFG_BLOCK_DEV_REG0_POS 0U

#define	DEV_ADDR_DEV_REG0_ADDR 0x00U

#define	DEV_ADDR_DEV_REG0_MASK 0xFEU

#define	DEV_ADDR_DEV_REG0_POS 1U

#define	DEV_REG1_ADDR 0x01U

#define	DEV_REG1_DEFAULT 0x08U

#define	RX_RATE_DEV_REG1_ADDR 0x01U

#define	RX_RATE_DEV_REG1_MASK 0x03U

#define	RX_RATE_DEV_REG1_POS 0U

#define	TX_RATE_DEV_REG1_ADDR 0x01U

#define	TX_RATE_DEV_REG1_MASK 0x0CU

#define	TX_RATE_DEV_REG1_POS 2U

#define	DIS_REM_CC_DEV_REG1_ADDR 0x01U

#define	DIS_REM_CC_DEV_REG1_MASK 0x10U

#define	DIS_REM_CC_DEV_REG1_POS 4U

#define	DIS_LOCAL_CC_DEV_REG1_ADDR 0x01U

#define	DIS_LOCAL_CC_DEV_REG1_MASK 0x20U

#define	DIS_LOCAL_CC_DEV_REG1_POS 5U

#define	IIC_1_EN_DEV_REG1_ADDR 0x01U

#define	IIC_1_EN_DEV_REG1_MASK 0x40U

#define	IIC_1_EN_DEV_REG1_POS 6U

#define	IIC_2_EN_DEV_REG1_ADDR 0x01U

#define	IIC_2_EN_DEV_REG1_MASK 0x80U

#define	IIC_2_EN_DEV_REG1_POS 7U

#define	DEV_REG2_ADDR 0x02U

#define	DEV_REG2_DEFAULT 0x43U

#define	VID_TX_EN_Z_DEV_REG2_ADDR 0x02U

#define	VID_TX_EN_Z_DEV_REG2_MASK 0x40U

#define	VID_TX_EN_Z_DEV_REG2_POS 6U

#define	DEV_REG3_ADDR 0x03U

#define	DEV_REG3_DEFAULT 0x00U

#define	RCLKSEL_DEV_REG3_ADDR 0x03U

#define	RCLKSEL_DEV_REG3_MASK 0x03U

#define	RCLKSEL_DEV_REG3_POS 0U

#define	RCLK_ALT_DEV_REG3_ADDR 0x03U

#define	RCLK_ALT_DEV_REG3_MASK 0x04U

#define	RCLK_ALT_DEV_REG3_POS 2U

#define	UART_1_EN_DEV_REG3_ADDR 0x03U

#define	UART_1_EN_DEV_REG3_MASK 0x10U

#define	UART_1_EN_DEV_REG3_POS 4U

#define	UART_2_EN_DEV_REG3_ADDR 0x03U

#define	UART_2_EN_DEV_REG3_MASK 0x20U

#define	UART_2_EN_DEV_REG3_POS 5U

#define	DEV_REG4_ADDR 0x04U

#define	DEV_REG4_DEFAULT 0x18U

#define	XTAL_PU_DEV_REG4_ADDR 0x04U

#define	XTAL_PU_DEV_REG4_MASK 0x01U

#define	XTAL_PU_DEV_REG4_POS 0U

#define	CC_CRC_MSGCNTR_OVR_DEV_REG4_ADDR 0x04U

#define	CC_CRC_MSGCNTR_OVR_DEV_REG4_MASK 0x04U

#define	CC_CRC_MSGCNTR_OVR_DEV_REG4_POS 2U

#define	CC_CRC_EN_DEV_REG4_ADDR 0x04U

#define	CC_CRC_EN_DEV_REG4_MASK 0x08U

#define	CC_CRC_EN_DEV_REG4_POS 3U

#define	CC_MSGCNTR_EN_DEV_REG4_ADDR 0x04U

#define	CC_MSGCNTR_EN_DEV_REG4_MASK 0x10U

#define	CC_MSGCNTR_EN_DEV_REG4_POS 4U

#define	DEV_REG5_ADDR 0x05U

#define	DEV_REG5_DEFAULT 0x00U

#define	PU_LF0_DEV_REG5_ADDR 0x05U

#define	PU_LF0_DEV_REG5_MASK 0x01U

#define	PU_LF0_DEV_REG5_POS 0U

#define	PU_LF1_DEV_REG5_ADDR 0x05U

#define	PU_LF1_DEV_REG5_MASK 0x02U

#define	PU_LF1_DEV_REG5_POS 1U

#define	ALT_ERRB_EN_DEV_REG5_ADDR 0x05U

#define	ALT_ERRB_EN_DEV_REG5_MASK 0x10U

#define	ALT_ERRB_EN_DEV_REG5_POS 4U

#define	ALT_LOCK_EN_DEV_REG5_ADDR 0x05U

#define	ALT_LOCK_EN_DEV_REG5_MASK 0x20U

#define	ALT_LOCK_EN_DEV_REG5_POS 5U

#define	ERRB_EN_DEV_REG5_ADDR 0x05U

#define	ERRB_EN_DEV_REG5_MASK 0x40U

#define	ERRB_EN_DEV_REG5_POS 6U

#define	LOCK_EN_DEV_REG5_ADDR 0x05U

#define	LOCK_EN_DEV_REG5_MASK 0x80U

#define	LOCK_EN_DEV_REG5_POS 7U

#define	DEV_REG6_ADDR 0x06U

#define	DEV_REG6_DEFAULT 0x80U

#define	I2CSEL_DEV_REG6_ADDR 0x06U

#define	I2CSEL_DEV_REG6_MASK 0x10U

#define	I2CSEL_DEV_REG6_POS 4U

#define	RCLKEN_DEV_REG6_ADDR 0x06U

#define	RCLKEN_DEV_REG6_MASK 0x20U

#define	RCLKEN_DEV_REG6_POS 5U

#define	DEV_REG13_ADDR 0x0DU

#define	DEV_REG13_DEFAULT 0xB7U

#define	DEV_ID_DEV_REG13_ADDR 0x0DU

#define	DEV_ID_DEV_REG13_MASK 0xFFU

#define	DEV_ID_DEV_REG13_POS 0U

#define	DEV_REG14_ADDR 0x0EU

#define	DEV_REG14_DEFAULT 0x06U

#define	DEV_REV_DEV_REG14_ADDR 0x0EU

#define	DEV_REV_DEV_REG14_MASK 0x0FU

#define	DEV_REV_DEV_REG14_POS 0U

#define	DEV_REG26_ADDR 0x26U

#define	DEV_REG26_DEFAULT 0x22U

#define	LF_0_DEV_REG26_ADDR 0x26U

#define	LF_0_DEV_REG26_MASK 0x07U

#define	LF_0_DEV_REG26_POS 0U

#define	LF_1_DEV_REG26_ADDR 0x26U

#define	LF_1_DEV_REG26_MASK 0x70U

#define	LF_1_DEV_REG26_POS 4U

#define	TCTRL_PWR0_ADDR 0x08U

#define	TCTRL_PWR0_DEFAULT 0x00U

#define	CMP_STATUS_TCTRL_PWR0_ADDR 0x08U

#define	CMP_STATUS_TCTRL_PWR0_MASK 0x1FU

#define	CMP_STATUS_TCTRL_PWR0_POS 0U

#define	VDDBAD_STATUS_TCTRL_PWR0_ADDR 0x08U

#define	VDDBAD_STATUS_TCTRL_PWR0_MASK 0xE0U

#define	VDDBAD_STATUS_TCTRL_PWR0_POS 5U

#define	TCTRL_PWR4_ADDR 0x0CU

#define	TCTRL_PWR4_DEFAULT 0x15U

#define	WAKE_EN_A_TCTRL_PWR4_ADDR 0x0CU

#define	WAKE_EN_A_TCTRL_PWR4_MASK 0x10U

#define	WAKE_EN_A_TCTRL_PWR4_POS 4U

#define	DIS_LOCAL_WAKE_TCTRL_PWR4_ADDR 0x0CU

#define	DIS_LOCAL_WAKE_TCTRL_PWR4_MASK 0x40U

#define	DIS_LOCAL_WAKE_TCTRL_PWR4_POS 6U

#define	TCTRL_CTRL0_ADDR 0x10U

#define	TCTRL_CTRL0_DEFAULT 0x01U

#define	SLEEP_TCTRL_CTRL0_ADDR 0x10U

#define	SLEEP_TCTRL_CTRL0_MASK 0x08U

#define	SLEEP_TCTRL_CTRL0_POS 3U

#define	RESET_ONESHOT_TCTRL_CTRL0_ADDR 0x10U

#define	RESET_ONESHOT_TCTRL_CTRL0_MASK 0x20U

#define	RESET_ONESHOT_TCTRL_CTRL0_POS 5U

#define	RESET_LINK_TCTRL_CTRL0_ADDR 0x10U

#define	RESET_LINK_TCTRL_CTRL0_MASK 0x40U

#define	RESET_LINK_TCTRL_CTRL0_POS 6U

#define	RESET_ALL_TCTRL_CTRL0_ADDR 0x10U

#define	RESET_ALL_TCTRL_CTRL0_MASK 0x80U

#define	RESET_ALL_TCTRL_CTRL0_POS 7U

#define	TCTRL_CTRL1_ADDR 0x11U

#define	TCTRL_CTRL1_DEFAULT 0x02U

#define	CXTP_A_TCTRL_CTRL1_ADDR 0x11U

#define	CXTP_A_TCTRL_CTRL1_MASK 0x01U

#define	CXTP_A_TCTRL_CTRL1_POS 0U

#define	VREF_CAP_EN_TCTRL_CTRL1_ADDR 0x11U

#define	VREF_CAP_EN_TCTRL_CTRL1_MASK 0x40U

#define	VREF_CAP_EN_TCTRL_CTRL1_POS 6U

#define	TCTRL_CTRL2_ADDR 0x12U

#define	TCTRL_CTRL2_DEFAULT 0x04U

#define	LDO_BYPASS_TCTRL_CTRL2_ADDR 0x12U

#define	LDO_BYPASS_TCTRL_CTRL2_MASK 0x10U

#define	LDO_BYPASS_TCTRL_CTRL2_POS 4U

#define	TCTRL_CTRL3_ADDR 0x13U

#define	TCTRL_CTRL3_DEFAULT 0x10U

#define	CMU_LOCKED_TCTRL_CTRL3_ADDR 0x13U

#define	CMU_LOCKED_TCTRL_CTRL3_MASK 0x02U

#define	CMU_LOCKED_TCTRL_CTRL3_POS 1U

#define	ERROR_TCTRL_CTRL3_ADDR 0x13U

#define	ERROR_TCTRL_CTRL3_MASK 0x04U

#define	ERROR_TCTRL_CTRL3_POS 2U

#define	LOCKED_TCTRL_CTRL3_ADDR 0x13U

#define	LOCKED_TCTRL_CTRL3_MASK 0x08U

#define	LOCKED_TCTRL_CTRL3_POS 3U

#define	TCTRL_INTR0_ADDR 0x18U

#define	TCTRL_INTR0_DEFAULT 0xA0U

#define	DEC_ERR_THR_TCTRL_INTR0_ADDR 0x18U

#define	DEC_ERR_THR_TCTRL_INTR0_MASK 0x07U

#define	DEC_ERR_THR_TCTRL_INTR0_POS 0U

#define	AUTO_ERR_RST_EN_TCTRL_INTR0_ADDR 0x18U

#define	AUTO_ERR_RST_EN_TCTRL_INTR0_MASK 0x08U

#define	AUTO_ERR_RST_EN_TCTRL_INTR0_POS 3U

#define	TCTRL_INTR1_ADDR 0x19U

#define	TCTRL_INTR1_DEFAULT 0x00U

#define	AUTO_CNT_RST_EN_TCTRL_INTR1_ADDR 0x19U

#define	AUTO_CNT_RST_EN_TCTRL_INTR1_MASK 0x08U

#define	AUTO_CNT_RST_EN_TCTRL_INTR1_POS 3U

#define	PKT_CNT_EXP_TCTRL_INTR1_ADDR 0x19U

#define	PKT_CNT_EXP_TCTRL_INTR1_MASK 0xF0U

#define	PKT_CNT_EXP_TCTRL_INTR1_POS 4U

#define	TCTRL_INTR2_ADDR 0x1AU

#define	TCTRL_INTR2_DEFAULT 0x09U

#define	DEC_ERR_OEN_A_TCTRL_INTR2_ADDR 0x1AU

#define	DEC_ERR_OEN_A_TCTRL_INTR2_MASK 0x01U

#define	DEC_ERR_OEN_A_TCTRL_INTR2_POS 0U

#define	IDLE_ERR_OEN_TCTRL_INTR2_ADDR 0x1AU

#define	IDLE_ERR_OEN_TCTRL_INTR2_MASK 0x04U

#define	IDLE_ERR_OEN_TCTRL_INTR2_POS 2U

#define	LFLT_INT_OEN_TCTRL_INTR2_ADDR 0x1AU

#define	LFLT_INT_OEN_TCTRL_INTR2_MASK 0x08U

#define	LFLT_INT_OEN_TCTRL_INTR2_POS 3U

#define	REM_ERR_OEN_TCTRL_INTR2_ADDR 0x1AU

#define	REM_ERR_OEN_TCTRL_INTR2_MASK 0x20U

#define	REM_ERR_OEN_TCTRL_INTR2_POS 5U

#define	REFGEN_UNLOCKED_OEN_TCTRL_INTR2_ADDR 0x1AU

#define	REFGEN_UNLOCKED_OEN_TCTRL_INTR2_MASK 0x80U

#define	REFGEN_UNLOCKED_OEN_TCTRL_INTR2_POS 7U

#define	TCTRL_INTR3_ADDR 0x1BU

#define	TCTRL_INTR3_DEFAULT 0x00U

#define	DEC_ERR_FLAG_A_TCTRL_INTR3_ADDR 0x1BU

#define	DEC_ERR_FLAG_A_TCTRL_INTR3_MASK 0x01U

#define	DEC_ERR_FLAG_A_TCTRL_INTR3_POS 0U

#define	IDLE_ERR_FLAG_TCTRL_INTR3_ADDR 0x1BU

#define	IDLE_ERR_FLAG_TCTRL_INTR3_MASK 0x04U

#define	IDLE_ERR_FLAG_TCTRL_INTR3_POS 2U

#define	LFLT_INT_TCTRL_INTR3_ADDR 0x1BU

#define	LFLT_INT_TCTRL_INTR3_MASK 0x08U

#define	LFLT_INT_TCTRL_INTR3_POS 3U

#define	REM_ERR_FLAG_TCTRL_INTR3_ADDR 0x1BU

#define	REM_ERR_FLAG_TCTRL_INTR3_MASK 0x20U

#define	REM_ERR_FLAG_TCTRL_INTR3_POS 5U

#define	REFGEN_UNLOCKED_TCTRL_INTR3_ADDR 0x1BU

#define	REFGEN_UNLOCKED_TCTRL_INTR3_MASK 0x80U

#define	REFGEN_UNLOCKED_TCTRL_INTR3_POS 7U

#define	TCTRL_INTR4_ADDR 0x1CU

#define	TCTRL_INTR4_DEFAULT 0x08U

#define	PKT_CNT_OEN_TCTRL_INTR4_ADDR 0x1CU

#define	PKT_CNT_OEN_TCTRL_INTR4_MASK 0x02U

#define	PKT_CNT_OEN_TCTRL_INTR4_POS 1U

#define	RT_CNT_OEN_TCTRL_INTR4_ADDR 0x1CU

#define	RT_CNT_OEN_TCTRL_INTR4_MASK 0x04U

#define	RT_CNT_OEN_TCTRL_INTR4_POS 2U

#define	MAX_RT_OEN_TCTRL_INTR4_ADDR 0x1CU

#define	MAX_RT_OEN_TCTRL_INTR4_MASK 0x08U

#define	MAX_RT_OEN_TCTRL_INTR4_POS 3U

#define	VDD18_OV_OEN_TCTRL_INTR4_ADDR 0x1CU

#define	VDD18_OV_OEN_TCTRL_INTR4_MASK 0x10U

#define	VDD18_OV_OEN_TCTRL_INTR4_POS 4U

#define	VDD_OV_OEN_TCTRL_INTR4_ADDR 0x1CU

#define	VDD_OV_OEN_TCTRL_INTR4_MASK 0x20U

#define	VDD_OV_OEN_TCTRL_INTR4_POS 5U

#define	EOM_ERR_OEN_A_TCTRL_INTR4_ADDR 0x1CU

#define	EOM_ERR_OEN_A_TCTRL_INTR4_MASK 0x40U

#define	EOM_ERR_OEN_A_TCTRL_INTR4_POS 6U

#define	VREG_OV_OEN_TCTRL_INTR4_ADDR 0x1CU

#define	VREG_OV_OEN_TCTRL_INTR4_MASK 0x80U

#define	VREG_OV_OEN_TCTRL_INTR4_POS 7U

#define	TCTRL_INTR5_ADDR 0x1DU

#define	TCTRL_INTR5_DEFAULT 0x00U

#define	PKT_CNT_FLAG_TCTRL_INTR5_ADDR 0x1DU

#define	PKT_CNT_FLAG_TCTRL_INTR5_MASK 0x02U

#define	PKT_CNT_FLAG_TCTRL_INTR5_POS 1U

#define	RT_CNT_FLAG_TCTRL_INTR5_ADDR 0x1DU

#define	RT_CNT_FLAG_TCTRL_INTR5_MASK 0x04U

#define	RT_CNT_FLAG_TCTRL_INTR5_POS 2U

#define	MAX_RT_FLAG_TCTRL_INTR5_ADDR 0x1DU

#define	MAX_RT_FLAG_TCTRL_INTR5_MASK 0x08U

#define	MAX_RT_FLAG_TCTRL_INTR5_POS 3U

#define	VDD18_OV_FLAG_TCTRL_INTR5_ADDR 0x1DU

#define	VDD18_OV_FLAG_TCTRL_INTR5_MASK 0x10U

#define	VDD18_OV_FLAG_TCTRL_INTR5_POS 4U

#define	VDD_OV_FLAG_TCTRL_INTR5_ADDR 0x1DU

#define	VDD_OV_FLAG_TCTRL_INTR5_MASK 0x20U

#define	VDD_OV_FLAG_TCTRL_INTR5_POS 5U

#define	EOM_ERR_FLAG_A_TCTRL_INTR5_ADDR 0x1DU

#define	EOM_ERR_FLAG_A_TCTRL_INTR5_MASK 0x40U

#define	EOM_ERR_FLAG_A_TCTRL_INTR5_POS 6U

#define	VREG_OV_FLAG_TCTRL_INTR5_ADDR 0x1DU

#define	VREG_OV_FLAG_TCTRL_INTR5_MASK 0x80U

#define	VREG_OV_FLAG_TCTRL_INTR5_POS 7U

#define	TCTRL_INTR6_ADDR 0x1EU

#define	TCTRL_INTR6_DEFAULT 0xFBU

#define	MIPI_ERR_OEN_TCTRL_INTR6_ADDR 0x1EU

#define	MIPI_ERR_OEN_TCTRL_INTR6_MASK 0x01U

#define	MIPI_ERR_OEN_TCTRL_INTR6_POS 0U

#define	ADC_INT_OEN_TCTRL_INTR6_ADDR 0x1EU

#define	ADC_INT_OEN_TCTRL_INTR6_MASK 0x04U

#define	ADC_INT_OEN_TCTRL_INTR6_POS 2U

#define	RTTN_CRC_ERR_OEN_TCTRL_INTR6_ADDR 0x1EU

#define	RTTN_CRC_ERR_OEN_TCTRL_INTR6_MASK 0x08U

#define	RTTN_CRC_ERR_OEN_TCTRL_INTR6_POS 3U

#define	EFUSE_CRC_ERR_OEN_TCTRL_INTR6_ADDR 0x1EU

#define	EFUSE_CRC_ERR_OEN_TCTRL_INTR6_MASK 0x10U

#define	EFUSE_CRC_ERR_OEN_TCTRL_INTR6_POS 4U

#define	VDDBAD_INT_OEN_TCTRL_INTR6_ADDR 0x1EU

#define	VDDBAD_INT_OEN_TCTRL_INTR6_MASK 0x20U

#define	VDDBAD_INT_OEN_TCTRL_INTR6_POS 5U

#define	PORZ_INT_OEN_TCTRL_INTR6_ADDR 0x1EU

#define	PORZ_INT_OEN_TCTRL_INTR6_MASK 0x40U

#define	PORZ_INT_OEN_TCTRL_INTR6_POS 6U

#define	VDDCMP_INT_OEN_TCTRL_INTR6_ADDR 0x1EU

#define	VDDCMP_INT_OEN_TCTRL_INTR6_MASK 0x80U

#define	VDDCMP_INT_OEN_TCTRL_INTR6_POS 7U

#define	TCTRL_INTR7_ADDR 0x1FU

#define	TCTRL_INTR7_DEFAULT 0x00U

#define	MIPI_ERR_FLAG_TCTRL_INTR7_ADDR 0x1FU

#define	MIPI_ERR_FLAG_TCTRL_INTR7_MASK 0x01U

#define	MIPI_ERR_FLAG_TCTRL_INTR7_POS 0U

#define	ADC_INT_FLAG_TCTRL_INTR7_ADDR 0x1FU

#define	ADC_INT_FLAG_TCTRL_INTR7_MASK 0x04U

#define	ADC_INT_FLAG_TCTRL_INTR7_POS 2U

#define	RTTN_CRC_INT_TCTRL_INTR7_ADDR 0x1FU

#define	RTTN_CRC_INT_TCTRL_INTR7_MASK 0x08U

#define	RTTN_CRC_INT_TCTRL_INTR7_POS 3U

#define	EFUSE_CRC_ERR_TCTRL_INTR7_ADDR 0x1FU

#define	EFUSE_CRC_ERR_TCTRL_INTR7_MASK 0x10U

#define	EFUSE_CRC_ERR_TCTRL_INTR7_POS 4U

#define	VDDBAD_INT_FLAG_TCTRL_INTR7_ADDR 0x1FU

#define	VDDBAD_INT_FLAG_TCTRL_INTR7_MASK 0x20U

#define	VDDBAD_INT_FLAG_TCTRL_INTR7_POS 5U

#define	PORZ_INT_FLAG_TCTRL_INTR7_ADDR 0x1FU

#define	PORZ_INT_FLAG_TCTRL_INTR7_MASK 0x40U

#define	PORZ_INT_FLAG_TCTRL_INTR7_POS 6U

#define	VDDCMP_INT_FLAG_TCTRL_INTR7_ADDR 0x1FU

#define	VDDCMP_INT_FLAG_TCTRL_INTR7_MASK 0x80U

#define	VDDCMP_INT_FLAG_TCTRL_INTR7_POS 7U

#define	TCTRL_INTR8_ADDR 0x20U

#define	TCTRL_INTR8_DEFAULT 0x9FU

#define	ERR_TX_ID_TCTRL_INTR8_ADDR 0x20U

#define	ERR_TX_ID_TCTRL_INTR8_MASK 0x1FU

#define	ERR_TX_ID_TCTRL_INTR8_POS 0U

#define	ERR_TX_EN_TCTRL_INTR8_ADDR 0x20U

#define	ERR_TX_EN_TCTRL_INTR8_MASK 0x80U

#define	ERR_TX_EN_TCTRL_INTR8_POS 7U

#define	TCTRL_INTR9_ADDR 0x21U

#define	TCTRL_INTR9_DEFAULT 0xDFU

#define	ERR_RX_ID_TCTRL_INTR9_ADDR 0x21U

#define	ERR_RX_ID_TCTRL_INTR9_MASK 0x1FU

#define	ERR_RX_ID_TCTRL_INTR9_POS 0U

#define	ERR_RX_EN_TCTRL_INTR9_ADDR 0x21U

#define	ERR_RX_EN_TCTRL_INTR9_MASK 0x80U

#define	ERR_RX_EN_TCTRL_INTR9_POS 7U

#define	TCTRL_CNT0_ADDR 0x22U

#define	TCTRL_CNT0_DEFAULT 0x00U

#define	DEC_ERR_A_TCTRL_CNT0_ADDR 0x22U

#define	DEC_ERR_A_TCTRL_CNT0_MASK 0xFFU

#define	DEC_ERR_A_TCTRL_CNT0_POS 0U

#define	TCTRL_CNT2_ADDR 0x24U

#define	TCTRL_CNT2_DEFAULT 0x00U

#define	IDLE_ERR_TCTRL_CNT2_ADDR 0x24U

#define	IDLE_ERR_TCTRL_CNT2_MASK 0xFFU

#define	IDLE_ERR_TCTRL_CNT2_POS 0U

#define	TCTRL_CNT3_ADDR 0x25U

#define	TCTRL_CNT3_DEFAULT 0x00U

#define	PKT_CNT_TCTRL_CNT3_ADDR 0x25U

#define	PKT_CNT_TCTRL_CNT3_MASK 0xFFU

#define	PKT_CNT_TCTRL_CNT3_POS 0U

#define	GMSL_TX0_ADDR 0x28U

#define	GMSL_TX0_DEFAULT 0x60U

#define	TX_FEC_EN_GMSL_TX0_ADDR 0x28U

#define	TX_FEC_EN_GMSL_TX0_MASK 0x02U

#define	TX_FEC_EN_GMSL_TX0_POS 1U

#define	GMSL_TX1_ADDR 0x29U

#define	GMSL_TX1_DEFAULT 0x08U

#define	DIS_ENC_GMSL_TX1_ADDR 0x29U

#define	DIS_ENC_GMSL_TX1_MASK 0x01U

#define	DIS_ENC_GMSL_TX1_POS 0U

#define	DIS_SCR_GMSL_TX1_ADDR 0x29U

#define	DIS_SCR_GMSL_TX1_MASK 0x02U

#define	DIS_SCR_GMSL_TX1_POS 1U

#define	TX_FEC_CRC_EN_GMSL_TX1_ADDR 0x29U

#define	TX_FEC_CRC_EN_GMSL_TX1_MASK 0x08U

#define	TX_FEC_CRC_EN_GMSL_TX1_POS 3U

#define	ERRG_EN_A_GMSL_TX1_ADDR 0x29U

#define	ERRG_EN_A_GMSL_TX1_MASK 0x10U

#define	ERRG_EN_A_GMSL_TX1_POS 4U

#define	LINK_PRBS_GEN_GMSL_TX1_ADDR 0x29U

#define	LINK_PRBS_GEN_GMSL_TX1_MASK 0x80U

#define	LINK_PRBS_GEN_GMSL_TX1_POS 7U

#define	GMSL_TX2_ADDR 0x2AU

#define	GMSL_TX2_DEFAULT 0x20U

#define	ERRG_PER_GMSL_TX2_ADDR 0x2AU

#define	ERRG_PER_GMSL_TX2_MASK 0x01U

#define	ERRG_PER_GMSL_TX2_POS 0U

#define	ERRG_BURST_GMSL_TX2_ADDR 0x2AU

#define	ERRG_BURST_GMSL_TX2_MASK 0x0EU

#define	ERRG_BURST_GMSL_TX2_POS 1U

#define	ERRG_RATE_GMSL_TX2_ADDR 0x2AU

#define	ERRG_RATE_GMSL_TX2_MASK 0x30U

#define	ERRG_RATE_GMSL_TX2_POS 4U

#define	ERRG_CNT_GMSL_TX2_ADDR 0x2AU

#define	ERRG_CNT_GMSL_TX2_MASK 0xC0U

#define	ERRG_CNT_GMSL_TX2_POS 6U

#define	GMSL_TX3_ADDR 0x2BU

#define	GMSL_TX3_DEFAULT 0x44U

#define	TX_FEC_ACTIVE_GMSL_TX3_ADDR 0x2BU

#define	TX_FEC_ACTIVE_GMSL_TX3_MASK 0x20U

#define	TX_FEC_ACTIVE_GMSL_TX3_POS 5U

#define	GMSL_RX0_ADDR 0x2CU

#define	GMSL_RX0_DEFAULT 0x00U

#define	PKT_CNT_SEL_GMSL_RX0_ADDR 0x2CU

#define	PKT_CNT_SEL_GMSL_RX0_MASK 0x0FU

#define	PKT_CNT_SEL_GMSL_RX0_POS 0U

#define	PKT_CNT_LBW_GMSL_RX0_ADDR 0x2CU

#define	PKT_CNT_LBW_GMSL_RX0_MASK 0xC0U

#define	PKT_CNT_LBW_GMSL_RX0_POS 6U

#define	GMSL_RX1_ADDR 0x2DU

#define	GMSL_RX1_DEFAULT 0x28U

#define	LINK_PRBS_CHK_GMSL_RX1_ADDR 0x2DU

#define	LINK_PRBS_CHK_GMSL_RX1_MASK 0x80U

#define	LINK_PRBS_CHK_GMSL_RX1_POS 7U

#define	GMSL_GPIOA_ADDR 0x30U

#define	GMSL_GPIOA_DEFAULT 0x41U

#define	GPIO_FWD_CDLY_GMSL_GPIOA_ADDR 0x30U

#define	GPIO_FWD_CDLY_GMSL_GPIOA_MASK 0x3FU

#define	GPIO_FWD_CDLY_GMSL_GPIOA_POS 0U

#define	GMSL_GPIOB_ADDR 0x31U

#define	GMSL_GPIOB_DEFAULT 0x88U

#define	GPIO_REV_CDLY_GMSL_GPIOB_ADDR 0x31U

#define	GPIO_REV_CDLY_GMSL_GPIOB_MASK 0x3FU

#define	GPIO_REV_CDLY_GMSL_GPIOB_POS 0U

#define	CC_I2C_0_ADDR 0x40U

#define	CC_I2C_0_DEFAULT 0x26U

#define	SLV_TO_CC_I2C_0_ADDR 0x40U

#define	SLV_TO_CC_I2C_0_MASK 0x07U

#define	SLV_TO_CC_I2C_0_POS 0U

#define	SLV_SH_CC_I2C_0_ADDR 0x40U

#define	SLV_SH_CC_I2C_0_MASK 0x30U

#define	SLV_SH_CC_I2C_0_POS 4U

#define	CC_I2C_1_ADDR 0x41U

#define	CC_I2C_1_DEFAULT 0x56U

#define	MST_TO_CC_I2C_1_ADDR 0x41U

#define	MST_TO_CC_I2C_1_MASK 0x07U

#define	MST_TO_CC_I2C_1_POS 0U

#define	MST_BT_CC_I2C_1_ADDR 0x41U

#define	MST_BT_CC_I2C_1_MASK 0x70U

#define	MST_BT_CC_I2C_1_POS 4U

#define	CC_I2C_2_ADDR 0x42U

#define	CC_I2C_2_DEFAULT 0x00U

#define	SRC_A_CC_I2C_2_ADDR 0x42U

#define	SRC_A_CC_I2C_2_MASK 0xFEU

#define	SRC_A_CC_I2C_2_POS 1U

#define	CC_I2C_3_ADDR 0x43U

#define	CC_I2C_3_DEFAULT 0x00U

#define	DST_A_CC_I2C_3_ADDR 0x43U

#define	DST_A_CC_I2C_3_MASK 0xFEU

#define	DST_A_CC_I2C_3_POS 1U

#define	CC_I2C_4_ADDR 0x44U

#define	CC_I2C_4_DEFAULT 0x00U

#define	SRC_B_CC_I2C_4_ADDR 0x44U

#define	SRC_B_CC_I2C_4_MASK 0xFEU

#define	SRC_B_CC_I2C_4_POS 1U

#define	CC_I2C_5_ADDR 0x45U

#define	CC_I2C_5_DEFAULT 0x00U

#define	DST_B_CC_I2C_5_ADDR 0x45U

#define	DST_B_CC_I2C_5_MASK 0xFEU

#define	DST_B_CC_I2C_5_POS 1U

#define	CC_UART_0_ADDR 0x48U

#define	CC_UART_0_DEFAULT 0x42U

#define	BYPASS_EN_CC_UART_0_ADDR 0x48U

#define	BYPASS_EN_CC_UART_0_MASK 0x01U

#define	BYPASS_EN_CC_UART_0_POS 0U

#define	BYPASS_TO_CC_UART_0_ADDR 0x48U

#define	BYPASS_TO_CC_UART_0_MASK 0x06U

#define	BYPASS_TO_CC_UART_0_POS 1U

#define	BYPASS_DIS_PAR_CC_UART_0_ADDR 0x48U

#define	BYPASS_DIS_PAR_CC_UART_0_MASK 0x08U

#define	BYPASS_DIS_PAR_CC_UART_0_POS 3U

#define	LOC_MS_EN_CC_UART_0_ADDR 0x48U

#define	LOC_MS_EN_CC_UART_0_MASK 0x10U

#define	LOC_MS_EN_CC_UART_0_POS 4U

#define	REM_MS_EN_CC_UART_0_ADDR 0x48U

#define	REM_MS_EN_CC_UART_0_MASK 0x20U

#define	REM_MS_EN_CC_UART_0_POS 5U

#define	CC_I2C_PT_0_ADDR 0x4CU

#define	CC_I2C_PT_0_DEFAULT 0x26U

#define	SLV_TO_PT_CC_I2C_PT_0_ADDR 0x4CU

#define	SLV_TO_PT_CC_I2C_PT_0_MASK 0x07U

#define	SLV_TO_PT_CC_I2C_PT_0_POS 0U

#define	SLV_SH_PT_CC_I2C_PT_0_ADDR 0x4CU

#define	SLV_SH_PT_CC_I2C_PT_0_MASK 0x30U

#define	SLV_SH_PT_CC_I2C_PT_0_POS 4U

#define	CC_I2C_PT_1_ADDR 0x4DU

#define	CC_I2C_PT_1_DEFAULT 0x56U

#define	MST_TO_PT_CC_I2C_PT_1_ADDR 0x4DU

#define	MST_TO_PT_CC_I2C_PT_1_MASK 0x07U

#define	MST_TO_PT_CC_I2C_PT_1_POS 0U

#define	MST_BT_PT_CC_I2C_PT_1_ADDR 0x4DU

#define	MST_BT_PT_CC_I2C_PT_1_MASK 0x70U

#define	MST_BT_PT_CC_I2C_PT_1_POS 4U

#define	CC_UART_PT_0_ADDR 0x4FU

#define	CC_UART_PT_0_DEFAULT 0x00U

#define	DIS_PAR_1_CC_UART_PT_0_ADDR 0x4FU

#define	DIS_PAR_1_CC_UART_PT_0_MASK 0x04U

#define	DIS_PAR_1_CC_UART_PT_0_POS 2U

#define	BITLEN_MAN_CFG_1_CC_UART_PT_0_ADDR 0x4FU

#define	BITLEN_MAN_CFG_1_CC_UART_PT_0_MASK 0x08U

#define	BITLEN_MAN_CFG_1_CC_UART_PT_0_POS 3U

#define	DIS_PAR_2_CC_UART_PT_0_ADDR 0x4FU

#define	DIS_PAR_2_CC_UART_PT_0_MASK 0x40U

#define	DIS_PAR_2_CC_UART_PT_0_POS 6U

#define	BITLEN_MAN_CFG_2_CC_UART_PT_0_ADDR 0x4FU

#define	BITLEN_MAN_CFG_2_CC_UART_PT_0_MASK 0x80U

#define	BITLEN_MAN_CFG_2_CC_UART_PT_0_POS 7U

#define	CFGV_VIDEO_Z_TX0_ADDR 0x58U

#define	CFGV_VIDEO_Z_TX0_DEFAULT 0x30U

#define	TX_CRC_EN_CFGV_VIDEO_Z_TX0_ADDR 0x58U

#define	TX_CRC_EN_CFGV_VIDEO_Z_TX0_MASK 0x80U

#define	TX_CRC_EN_CFGV_VIDEO_Z_TX0_POS 7U

#define	CFGV_VIDEO_Z_TX3_ADDR 0x5BU

#define	CFGV_VIDEO_Z_TX3_DEFAULT 0x02U

#define	TX_STR_SEL_CFGV_VIDEO_Z_TX3_ADDR 0x5BU

#define	TX_STR_SEL_CFGV_VIDEO_Z_TX3_MASK 0x03U

#define	TX_STR_SEL_CFGV_VIDEO_Z_TX3_POS 0U

#define	CFGI_INFOFR_TR0_ADDR 0x78U

#define	CFGI_INFOFR_TR0_DEFAULT 0xF0U

#define	RX_CRC_EN_CFGI_INFOFR_TR0_ADDR 0x78U

#define	RX_CRC_EN_CFGI_INFOFR_TR0_MASK 0x40U

#define	RX_CRC_EN_CFGI_INFOFR_TR0_POS 6U

#define	TX_CRC_EN_CFGI_INFOFR_TR0_ADDR 0x78U

#define	TX_CRC_EN_CFGI_INFOFR_TR0_MASK 0x80U

#define	TX_CRC_EN_CFGI_INFOFR_TR0_POS 7U

#define	CFGI_INFOFR_TR3_ADDR 0x7BU

#define	CFGI_INFOFR_TR3_DEFAULT 0x00U

#define	TX_SRC_ID_CFGI_INFOFR_TR3_ADDR 0x7BU

#define	TX_SRC_ID_CFGI_INFOFR_TR3_MASK 0x07U

#define	TX_SRC_ID_CFGI_INFOFR_TR3_POS 0U

#define	CFGI_INFOFR_TR4_ADDR 0x7CU

#define	CFGI_INFOFR_TR4_DEFAULT 0xFFU

#define	RX_SRC_SEL_CFGI_INFOFR_TR4_ADDR 0x7CU

#define	RX_SRC_SEL_CFGI_INFOFR_TR4_MASK 0xFFU

#define	RX_SRC_SEL_CFGI_INFOFR_TR4_POS 0U

#define	CFGL_SPI_TR0_ADDR 0x80U

#define	CFGL_SPI_TR0_DEFAULT 0xF0U

#define	RX_CRC_EN_CFGL_SPI_TR0_ADDR 0x80U

#define	RX_CRC_EN_CFGL_SPI_TR0_MASK 0x40U

#define	RX_CRC_EN_CFGL_SPI_TR0_POS 6U

#define	TX_CRC_EN_CFGL_SPI_TR0_ADDR 0x80U

#define	TX_CRC_EN_CFGL_SPI_TR0_MASK 0x80U

#define	TX_CRC_EN_CFGL_SPI_TR0_POS 7U

#define	CFGL_SPI_TR3_ADDR 0x83U

#define	CFGL_SPI_TR3_DEFAULT 0x00U

#define	TX_SRC_ID_CFGL_SPI_TR3_ADDR 0x83U

#define	TX_SRC_ID_CFGL_SPI_TR3_MASK 0x07U

#define	TX_SRC_ID_CFGL_SPI_TR3_POS 0U

#define	CFGL_SPI_TR4_ADDR 0x84U

#define	CFGL_SPI_TR4_DEFAULT 0xFFU

#define	RX_SRC_SEL_CFGL_SPI_TR4_ADDR 0x84U

#define	RX_SRC_SEL_CFGL_SPI_TR4_MASK 0xFFU

#define	RX_SRC_SEL_CFGL_SPI_TR4_POS 0U

#define	CFGL_SPI_ARQ0_ADDR 0x85U

#define	CFGL_SPI_ARQ0_DEFAULT 0x98U

#define	DIS_DBL_ACK_RETX_CFGL_SPI_ARQ0_ADDR 0x85U

#define	DIS_DBL_ACK_RETX_CFGL_SPI_ARQ0_MASK 0x04U

#define	DIS_DBL_ACK_RETX_CFGL_SPI_ARQ0_POS 2U

#define	ARQ0_EN_CFGL_SPI_ARQ0_ADDR 0x85U

#define	ARQ0_EN_CFGL_SPI_ARQ0_MASK 0x08U

#define	ARQ0_EN_CFGL_SPI_ARQ0_POS 3U

#define	CFGL_SPI_ARQ1_ADDR 0x86U

#define	CFGL_SPI_ARQ1_DEFAULT 0x72U

#define	RT_CNT_OEN_CFGL_SPI_ARQ1_ADDR 0x86U

#define	RT_CNT_OEN_CFGL_SPI_ARQ1_MASK 0x01U

#define	RT_CNT_OEN_CFGL_SPI_ARQ1_POS 0U

#define	MAX_RT_ERR_OEN_CFGL_SPI_ARQ1_ADDR 0x86U

#define	MAX_RT_ERR_OEN_CFGL_SPI_ARQ1_MASK 0x02U

#define	MAX_RT_ERR_OEN_CFGL_SPI_ARQ1_POS 1U

#define	CFGL_SPI_ARQ2_ADDR 0x87U

#define	CFGL_SPI_ARQ2_DEFAULT 0x00U

#define	RT_CNT_CFGL_SPI_ARQ2_ADDR 0x87U

#define	RT_CNT_CFGL_SPI_ARQ2_MASK 0x7FU

#define	RT_CNT_CFGL_SPI_ARQ2_POS 0U

#define	MAX_RT_ERR_CFGL_SPI_ARQ2_ADDR 0x87U

#define	MAX_RT_ERR_CFGL_SPI_ARQ2_MASK 0x80U

#define	MAX_RT_ERR_CFGL_SPI_ARQ2_POS 7U

#define	CFGL_GPIO_TR0_ADDR 0x90U

#define	CFGL_GPIO_TR0_DEFAULT 0xF0U

#define	RX_CRC_EN_CFGL_GPIO_TR0_ADDR 0x90U

#define	RX_CRC_EN_CFGL_GPIO_TR0_MASK 0x40U

#define	RX_CRC_EN_CFGL_GPIO_TR0_POS 6U

#define	TX_CRC_EN_CFGL_GPIO_TR0_ADDR 0x90U

#define	TX_CRC_EN_CFGL_GPIO_TR0_MASK 0x80U

#define	TX_CRC_EN_CFGL_GPIO_TR0_POS 7U

#define	CFGL_GPIO_TR3_ADDR 0x93U

#define	CFGL_GPIO_TR3_DEFAULT 0x00U

#define	TX_SRC_ID_CFGL_GPIO_TR3_ADDR 0x93U

#define	TX_SRC_ID_CFGL_GPIO_TR3_MASK 0x07U

#define	TX_SRC_ID_CFGL_GPIO_TR3_POS 0U

#define	CFGL_GPIO_TR4_ADDR 0x94U

#define	CFGL_GPIO_TR4_DEFAULT 0xFFU

#define	RX_SRC_SEL_CFGL_GPIO_TR4_ADDR 0x94U

#define	RX_SRC_SEL_CFGL_GPIO_TR4_MASK 0xFFU

#define	RX_SRC_SEL_CFGL_GPIO_TR4_POS 0U

#define	CFGL_GPIO_ARQ0_ADDR 0x95U

#define	CFGL_GPIO_ARQ0_DEFAULT 0x98U

#define	DIS_DBL_ACK_RETX_CFGL_GPIO_ARQ0_ADDR 0x95U

#define	DIS_DBL_ACK_RETX_CFGL_GPIO_ARQ0_MASK 0x04U

#define	DIS_DBL_ACK_RETX_CFGL_GPIO_ARQ0_POS 2U

#define	ARQ0_EN_CFGL_GPIO_ARQ0_ADDR 0x95U

#define	ARQ0_EN_CFGL_GPIO_ARQ0_MASK 0x08U

#define	ARQ0_EN_CFGL_GPIO_ARQ0_POS 3U

#define	CFGL_GPIO_ARQ1_ADDR 0x96U

#define	CFGL_GPIO_ARQ1_DEFAULT 0x72U

#define	RT_CNT_OEN_CFGL_GPIO_ARQ1_ADDR 0x96U

#define	RT_CNT_OEN_CFGL_GPIO_ARQ1_MASK 0x01U

#define	RT_CNT_OEN_CFGL_GPIO_ARQ1_POS 0U

#define	MAX_RT_ERR_OEN_CFGL_GPIO_ARQ1_ADDR 0x96U

#define	MAX_RT_ERR_OEN_CFGL_GPIO_ARQ1_MASK 0x02U

#define	MAX_RT_ERR_OEN_CFGL_GPIO_ARQ1_POS 1U

#define	CFGL_GPIO_ARQ2_ADDR 0x97U

#define	CFGL_GPIO_ARQ2_DEFAULT 0x00U

#define	RT_CNT_CFGL_GPIO_ARQ2_ADDR 0x97U

#define	RT_CNT_CFGL_GPIO_ARQ2_MASK 0x7FU

#define	RT_CNT_CFGL_GPIO_ARQ2_POS 0U

#define	MAX_RT_ERR_CFGL_GPIO_ARQ2_ADDR 0x97U

#define	MAX_RT_ERR_CFGL_GPIO_ARQ2_MASK 0x80U

#define	MAX_RT_ERR_CFGL_GPIO_ARQ2_POS 7U

#define	CFGL_IIC_X_TR0_ADDR 0xA0U

#define	CFGL_IIC_X_TR0_DEFAULT 0xF0U

#define	RX_CRC_EN_CFGL_IIC_X_TR0_ADDR 0xA0U

#define	RX_CRC_EN_CFGL_IIC_X_TR0_MASK 0x40U

#define	RX_CRC_EN_CFGL_IIC_X_TR0_POS 6U

#define	TX_CRC_EN_CFGL_IIC_X_TR0_ADDR 0xA0U

#define	TX_CRC_EN_CFGL_IIC_X_TR0_MASK 0x80U

#define	TX_CRC_EN_CFGL_IIC_X_TR0_POS 7U

#define	CFGL_IIC_X_TR3_ADDR 0xA3U

#define	CFGL_IIC_X_TR3_DEFAULT 0x00U

#define	TX_SRC_ID_CFGL_IIC_X_TR3_ADDR 0xA3U

#define	TX_SRC_ID_CFGL_IIC_X_TR3_MASK 0x07U

#define	TX_SRC_ID_CFGL_IIC_X_TR3_POS 0U

#define	CFGL_IIC_X_TR4_ADDR 0xA4U

#define	CFGL_IIC_X_TR4_DEFAULT 0xFFU

#define	RX_SRC_SEL_CFGL_IIC_X_TR4_ADDR 0xA4U

#define	RX_SRC_SEL_CFGL_IIC_X_TR4_MASK 0xFFU

#define	RX_SRC_SEL_CFGL_IIC_X_TR4_POS 0U

#define	CFGL_IIC_X_ARQ0_ADDR 0xA5U

#define	CFGL_IIC_X_ARQ0_DEFAULT 0x98U

#define	DIS_DBL_ACK_RETX_CFGL_IIC_X_ARQ0_ADDR 0xA5U

#define	DIS_DBL_ACK_RETX_CFGL_IIC_X_ARQ0_MASK 0x04U

#define	DIS_DBL_ACK_RETX_CFGL_IIC_X_ARQ0_POS 2U

#define	ARQ0_EN_CFGL_IIC_X_ARQ0_ADDR 0xA5U

#define	ARQ0_EN_CFGL_IIC_X_ARQ0_MASK 0x08U

#define	ARQ0_EN_CFGL_IIC_X_ARQ0_POS 3U

#define	CFGL_IIC_X_ARQ1_ADDR 0xA6U

#define	CFGL_IIC_X_ARQ1_DEFAULT 0x72U

#define	RT_CNT_OEN_CFGL_IIC_X_ARQ1_ADDR 0xA6U

#define	RT_CNT_OEN_CFGL_IIC_X_ARQ1_MASK 0x01U

#define	RT_CNT_OEN_CFGL_IIC_X_ARQ1_POS 0U

#define	MAX_RT_ERR_OEN_CFGL_IIC_X_ARQ1_ADDR 0xA6U

#define	MAX_RT_ERR_OEN_CFGL_IIC_X_ARQ1_MASK 0x02U

#define	MAX_RT_ERR_OEN_CFGL_IIC_X_ARQ1_POS 1U

#define	CFGL_IIC_X_ARQ2_ADDR 0xA7U

#define	CFGL_IIC_X_ARQ2_DEFAULT 0x00U

#define	RT_CNT_CFGL_IIC_X_ARQ2_ADDR 0xA7U

#define	RT_CNT_CFGL_IIC_X_ARQ2_MASK 0x7FU

#define	RT_CNT_CFGL_IIC_X_ARQ2_POS 0U

#define	MAX_RT_ERR_CFGL_IIC_X_ARQ2_ADDR 0xA7U

#define	MAX_RT_ERR_CFGL_IIC_X_ARQ2_MASK 0x80U

#define	MAX_RT_ERR_CFGL_IIC_X_ARQ2_POS 7U

#define	CFGL_IIC_Y_TR0_ADDR 0xA8U

#define	CFGL_IIC_Y_TR0_DEFAULT 0xF0U

#define	RX_CRC_EN_CFGL_IIC_Y_TR0_ADDR 0xA8U

#define	RX_CRC_EN_CFGL_IIC_Y_TR0_MASK 0x40U

#define	RX_CRC_EN_CFGL_IIC_Y_TR0_POS 6U

#define	TX_CRC_EN_CFGL_IIC_Y_TR0_ADDR 0xA8U

#define	TX_CRC_EN_CFGL_IIC_Y_TR0_MASK 0x80U

#define	TX_CRC_EN_CFGL_IIC_Y_TR0_POS 7U

#define	CFGL_IIC_Y_TR3_ADDR 0xABU

#define	CFGL_IIC_Y_TR3_DEFAULT 0x00U

#define	TX_SRC_ID_CFGL_IIC_Y_TR3_ADDR 0xABU

#define	TX_SRC_ID_CFGL_IIC_Y_TR3_MASK 0x07U

#define	TX_SRC_ID_CFGL_IIC_Y_TR3_POS 0U

#define	CFGL_IIC_Y_TR4_ADDR 0xACU

#define	CFGL_IIC_Y_TR4_DEFAULT 0xFFU

#define	RX_SRC_SEL_CFGL_IIC_Y_TR4_ADDR 0xACU

#define	RX_SRC_SEL_CFGL_IIC_Y_TR4_MASK 0xFFU

#define	RX_SRC_SEL_CFGL_IIC_Y_TR4_POS 0U

#define	CFGL_IIC_Y_ARQ0_ADDR 0xADU

#define	CFGL_IIC_Y_ARQ0_DEFAULT 0x98U

#define	DIS_DBL_ACK_RETX_CFGL_IIC_Y_ARQ0_ADDR 0xADU

#define	DIS_DBL_ACK_RETX_CFGL_IIC_Y_ARQ0_MASK 0x04U

#define	DIS_DBL_ACK_RETX_CFGL_IIC_Y_ARQ0_POS 2U

#define	ARQ0_EN_CFGL_IIC_Y_ARQ0_ADDR 0xADU

#define	ARQ0_EN_CFGL_IIC_Y_ARQ0_MASK 0x08U

#define	ARQ0_EN_CFGL_IIC_Y_ARQ0_POS 3U

#define	CFGL_IIC_Y_ARQ1_ADDR 0xAEU

#define	CFGL_IIC_Y_ARQ1_DEFAULT 0x72U

#define	RT_CNT_OEN_CFGL_IIC_Y_ARQ1_ADDR 0xAEU

#define	RT_CNT_OEN_CFGL_IIC_Y_ARQ1_MASK 0x01U

#define	RT_CNT_OEN_CFGL_IIC_Y_ARQ1_POS 0U

#define	MAX_RT_ERR_OEN_CFGL_IIC_Y_ARQ1_ADDR 0xAEU

#define	MAX_RT_ERR_OEN_CFGL_IIC_Y_ARQ1_MASK 0x02U

#define	MAX_RT_ERR_OEN_CFGL_IIC_Y_ARQ1_POS 1U

#define	CFGL_IIC_Y_ARQ2_ADDR 0xAFU

#define	CFGL_IIC_Y_ARQ2_DEFAULT 0x00U

#define	RT_CNT_CFGL_IIC_Y_ARQ2_ADDR 0xAFU

#define	RT_CNT_CFGL_IIC_Y_ARQ2_MASK 0x7FU

#define	RT_CNT_CFGL_IIC_Y_ARQ2_POS 0U

#define	MAX_RT_ERR_CFGL_IIC_Y_ARQ2_ADDR 0xAFU

#define	MAX_RT_ERR_CFGL_IIC_Y_ARQ2_MASK 0x80U

#define	MAX_RT_ERR_CFGL_IIC_Y_ARQ2_POS 7U

#define	VID_TX_Z_VIDEO_TX0_ADDR 0x110U

#define	VID_TX_Z_VIDEO_TX0_DEFAULT 0x68U

#define	CLKDET_BYP_VID_TX_Z_VIDEO_TX0_ADDR 0x110U

#define	CLKDET_BYP_VID_TX_Z_VIDEO_TX0_MASK 0x04U

#define	CLKDET_BYP_VID_TX_Z_VIDEO_TX0_POS 2U

#define	AUTO_BPP_VID_TX_Z_VIDEO_TX0_ADDR 0x110U

#define	AUTO_BPP_VID_TX_Z_VIDEO_TX0_MASK 0x08U

#define	AUTO_BPP_VID_TX_Z_VIDEO_TX0_POS 3U

#define	ENC_MODE_VID_TX_Z_VIDEO_TX0_ADDR 0x110U

#define	ENC_MODE_VID_TX_Z_VIDEO_TX0_MASK 0x30U

#define	ENC_MODE_VID_TX_Z_VIDEO_TX0_POS 4U

#define	LINE_CRC_EN_VID_TX_Z_VIDEO_TX0_ADDR 0x110U

#define	LINE_CRC_EN_VID_TX_Z_VIDEO_TX0_MASK 0x40U

#define	LINE_CRC_EN_VID_TX_Z_VIDEO_TX0_POS 6U

#define	LINE_CRC_SEL_VID_TX_Z_VIDEO_TX0_ADDR 0x110U

#define	LINE_CRC_SEL_VID_TX_Z_VIDEO_TX0_MASK 0x80U

#define	LINE_CRC_SEL_VID_TX_Z_VIDEO_TX0_POS 7U

#define	VID_TX_Z_VIDEO_TX1_ADDR 0x111U

#define	VID_TX_Z_VIDEO_TX1_DEFAULT 0x58U

#define	BPP_VID_TX_Z_VIDEO_TX1_ADDR 0x111U

#define	BPP_VID_TX_Z_VIDEO_TX1_MASK 0x3FU

#define	BPP_VID_TX_Z_VIDEO_TX1_POS 0U

#define	VID_TX_Z_VIDEO_TX2_ADDR 0x112U

#define	VID_TX_Z_VIDEO_TX2_DEFAULT 0x0AU

#define	LIM_HEART_VID_TX_Z_VIDEO_TX2_ADDR 0x112U

#define	LIM_HEART_VID_TX_Z_VIDEO_TX2_MASK 0x04U

#define	LIM_HEART_VID_TX_Z_VIDEO_TX2_POS 2U

#define	FIFO_WARN_VID_TX_Z_VIDEO_TX2_ADDR 0x112U

#define	FIFO_WARN_VID_TX_Z_VIDEO_TX2_MASK 0x10U

#define	FIFO_WARN_VID_TX_Z_VIDEO_TX2_POS 4U

#define	OVERFLOW_VID_TX_Z_VIDEO_TX2_ADDR 0x112U

#define	OVERFLOW_VID_TX_Z_VIDEO_TX2_MASK 0x20U

#define	OVERFLOW_VID_TX_Z_VIDEO_TX2_POS 5U

#define	DRIFT_ERR_VID_TX_Z_VIDEO_TX2_ADDR 0x112U

#define	DRIFT_ERR_VID_TX_Z_VIDEO_TX2_MASK 0x40U

#define	DRIFT_ERR_VID_TX_Z_VIDEO_TX2_POS 6U

#define	PCLKDET_VID_TX_Z_VIDEO_TX2_ADDR 0x112U

#define	PCLKDET_VID_TX_Z_VIDEO_TX2_MASK 0x80U

#define	PCLKDET_VID_TX_Z_VIDEO_TX2_POS 7U

#define	SPI_SPI_0_ADDR 0x170U

#define	SPI_SPI_0_DEFAULT 0x08U

#define	SPI_EN_SPI_SPI_0_ADDR 0x170U

#define	SPI_EN_SPI_SPI_0_MASK 0x01U

#define	SPI_EN_SPI_SPI_0_POS 0U

#define	MST_SLVN_SPI_SPI_0_ADDR 0x170U

#define	MST_SLVN_SPI_SPI_0_MASK 0x02U

#define	MST_SLVN_SPI_SPI_0_POS 1U

#define	SPI_CC_EN_SPI_SPI_0_ADDR 0x170U

#define	SPI_CC_EN_SPI_SPI_0_MASK 0x04U

#define	SPI_CC_EN_SPI_SPI_0_POS 2U

#define	SPI_IGNR_ID_SPI_SPI_0_ADDR 0x170U

#define	SPI_IGNR_ID_SPI_SPI_0_MASK 0x08U

#define	SPI_IGNR_ID_SPI_SPI_0_POS 3U

#define	SPI_CC_TRG_ID_SPI_SPI_0_ADDR 0x170U

#define	SPI_CC_TRG_ID_SPI_SPI_0_MASK 0x30U

#define	SPI_CC_TRG_ID_SPI_SPI_0_POS 4U

#define	SPI_LOC_ID_SPI_SPI_0_ADDR 0x170U

#define	SPI_LOC_ID_SPI_SPI_0_MASK 0xC0U

#define	SPI_LOC_ID_SPI_SPI_0_POS 6U

#define	SPI_SPI_1_ADDR 0x171U

#define	SPI_SPI_1_DEFAULT 0x1DU

#define	SPI_BASE_PRIO_SPI_SPI_1_ADDR 0x171U

#define	SPI_BASE_PRIO_SPI_SPI_1_MASK 0x03U

#define	SPI_BASE_PRIO_SPI_SPI_1_POS 0U

#define	SPI_LOC_N_SPI_SPI_1_ADDR 0x171U

#define	SPI_LOC_N_SPI_SPI_1_MASK 0xFCU

#define	SPI_LOC_N_SPI_SPI_1_POS 2U

#define	SPI_SPI_2_ADDR 0x172U

#define	SPI_SPI_2_DEFAULT 0x03U

#define	SPIM_SS1_ACT_H_SPI_SPI_2_ADDR 0x172U

#define	SPIM_SS1_ACT_H_SPI_SPI_2_MASK 0x01U

#define	SPIM_SS1_ACT_H_SPI_SPI_2_POS 0U

#define	SPIM_SS2_ACT_H_SPI_SPI_2_ADDR 0x172U

#define	SPIM_SS2_ACT_H_SPI_SPI_2_MASK 0x02U

#define	SPIM_SS2_ACT_H_SPI_SPI_2_POS 1U

#define	SPI_MOD3_SPI_SPI_2_ADDR 0x172U

#define	SPI_MOD3_SPI_SPI_2_MASK 0x04U

#define	SPI_MOD3_SPI_SPI_2_POS 2U

#define	SPI_MOD3_F_SPI_SPI_2_ADDR 0x172U

#define	SPI_MOD3_F_SPI_SPI_2_MASK 0x08U

#define	SPI_MOD3_F_SPI_SPI_2_POS 3U

#define	FULL_SCK_SETUP_SPI_SPI_2_ADDR 0x172U

#define	FULL_SCK_SETUP_SPI_SPI_2_MASK 0x10U

#define	FULL_SCK_SETUP_SPI_SPI_2_POS 4U

#define	REQ_HOLD_OFF_SPI_SPI_2_ADDR 0x172U

#define	REQ_HOLD_OFF_SPI_SPI_2_MASK 0xE0U

#define	REQ_HOLD_OFF_SPI_SPI_2_POS 5U

#define	SPI_SPI_3_ADDR 0x173U

#define	SPI_SPI_3_DEFAULT 0x00U

#define	SPIM_SS_DLY_CLKS_SPI_SPI_3_ADDR 0x173U

#define	SPIM_SS_DLY_CLKS_SPI_SPI_3_MASK 0xFFU

#define	SPIM_SS_DLY_CLKS_SPI_SPI_3_POS 0U

#define	SPI_SPI_4_ADDR 0x174U

#define	SPI_SPI_4_DEFAULT 0x00U

#define	SPIM_SCK_LO_CLKS_SPI_SPI_4_ADDR 0x174U

#define	SPIM_SCK_LO_CLKS_SPI_SPI_4_MASK 0xFFU

#define	SPIM_SCK_LO_CLKS_SPI_SPI_4_POS 0U

#define	SPI_SPI_5_ADDR 0x175U

#define	SPI_SPI_5_DEFAULT 0x00U

#define	SPIM_SCK_HI_CLKS_SPI_SPI_5_ADDR 0x175U

#define	SPIM_SCK_HI_CLKS_SPI_SPI_5_MASK 0xFFU

#define	SPIM_SCK_HI_CLKS_SPI_SPI_5_POS 0U

#define	SPI_SPI_6_ADDR 0x176U

#define	SPI_SPI_6_DEFAULT 0x00U

#define	RWN_IO_EN_SPI_SPI_6_ADDR 0x176U

#define	RWN_IO_EN_SPI_SPI_6_MASK 0x01U

#define	RWN_IO_EN_SPI_SPI_6_POS 0U

#define	BNE_IO_EN_SPI_SPI_6_ADDR 0x176U

#define	BNE_IO_EN_SPI_SPI_6_MASK 0x02U

#define	BNE_IO_EN_SPI_SPI_6_POS 1U

#define	SS_IO_EN_1_SPI_SPI_6_ADDR 0x176U

#define	SS_IO_EN_1_SPI_SPI_6_MASK 0x04U

#define	SS_IO_EN_1_SPI_SPI_6_POS 2U

#define	SS_IO_EN_2_SPI_SPI_6_ADDR 0x176U

#define	SS_IO_EN_2_SPI_SPI_6_MASK 0x08U

#define	SS_IO_EN_2_SPI_SPI_6_POS 3U

#define	SPIS_RWN_SPI_SPI_6_ADDR 0x176U

#define	SPIS_RWN_SPI_SPI_6_MASK 0x10U

#define	SPIS_RWN_SPI_SPI_6_POS 4U

#define	BNE_SPI_SPI_6_ADDR 0x176U

#define	BNE_SPI_SPI_6_MASK 0x20U

#define	BNE_SPI_SPI_6_POS 5U

#define	SPI_SPI_7_ADDR 0x177U

#define	SPI_SPI_7_DEFAULT 0x00U

#define	SPIS_BYTE_CNT_SPI_SPI_7_ADDR 0x177U

#define	SPIS_BYTE_CNT_SPI_SPI_7_MASK 0x1FU

#define	SPIS_BYTE_CNT_SPI_SPI_7_POS 0U

#define	SPI_TX_OVRFLW_SPI_SPI_7_ADDR 0x177U

#define	SPI_TX_OVRFLW_SPI_SPI_7_MASK 0x40U

#define	SPI_TX_OVRFLW_SPI_SPI_7_POS 6U

#define	SPI_RX_OVRFLW_SPI_SPI_7_ADDR 0x177U

#define	SPI_RX_OVRFLW_SPI_SPI_7_MASK 0x80U

#define	SPI_RX_OVRFLW_SPI_SPI_7_POS 7U

#define	SPI_SPI_8_ADDR 0x178U

#define	SPI_SPI_8_DEFAULT 0x00U

#define	REQ_HOLD_OFF_TO_SPI_SPI_8_ADDR 0x178U

#define	REQ_HOLD_OFF_TO_SPI_SPI_8_MASK 0xFFU

#define	REQ_HOLD_OFF_TO_SPI_SPI_8_POS 0U

#define	VTX_Z_CROSS_0_ADDR 0x236U

#define	VTX_Z_CROSS_0_DEFAULT 0x00U

#define	CROSS0_VTX_Z_CROSS_0_ADDR 0x236U

#define	CROSS0_VTX_Z_CROSS_0_MASK 0x1FU

#define	CROSS0_VTX_Z_CROSS_0_POS 0U

#define	CROSS0_F_VTX_Z_CROSS_0_ADDR 0x236U

#define	CROSS0_F_VTX_Z_CROSS_0_MASK 0x20U

#define	CROSS0_F_VTX_Z_CROSS_0_POS 5U

#define	CROSS0_I_VTX_Z_CROSS_0_ADDR 0x236U

#define	CROSS0_I_VTX_Z_CROSS_0_MASK 0x40U

#define	CROSS0_I_VTX_Z_CROSS_0_POS 6U

#define	VTX_Z_CROSS_1_ADDR 0x237U

#define	VTX_Z_CROSS_1_DEFAULT 0x01U

#define	CROSS1_VTX_Z_CROSS_1_ADDR 0x237U

#define	CROSS1_VTX_Z_CROSS_1_MASK 0x1FU

#define	CROSS1_VTX_Z_CROSS_1_POS 0U

#define	CROSS1_F_VTX_Z_CROSS_1_ADDR 0x237U

#define	CROSS1_F_VTX_Z_CROSS_1_MASK 0x20U

#define	CROSS1_F_VTX_Z_CROSS_1_POS 5U

#define	CROSS1_I_VTX_Z_CROSS_1_ADDR 0x237U

#define	CROSS1_I_VTX_Z_CROSS_1_MASK 0x40U

#define	CROSS1_I_VTX_Z_CROSS_1_POS 6U

#define	VTX_Z_CROSS_2_ADDR 0x238U

#define	VTX_Z_CROSS_2_DEFAULT 0x02U

#define	CROSS2_VTX_Z_CROSS_2_ADDR 0x238U

#define	CROSS2_VTX_Z_CROSS_2_MASK 0x1FU

#define	CROSS2_VTX_Z_CROSS_2_POS 0U

#define	CROSS2_F_VTX_Z_CROSS_2_ADDR 0x238U

#define	CROSS2_F_VTX_Z_CROSS_2_MASK 0x20U

#define	CROSS2_F_VTX_Z_CROSS_2_POS 5U

#define	CROSS2_I_VTX_Z_CROSS_2_ADDR 0x238U

#define	CROSS2_I_VTX_Z_CROSS_2_MASK 0x40U

#define	CROSS2_I_VTX_Z_CROSS_2_POS 6U

#define	VTX_Z_CROSS_3_ADDR 0x239U

#define	VTX_Z_CROSS_3_DEFAULT 0x03U

#define	CROSS3_VTX_Z_CROSS_3_ADDR 0x239U

#define	CROSS3_VTX_Z_CROSS_3_MASK 0x1FU

#define	CROSS3_VTX_Z_CROSS_3_POS 0U

#define	CROSS3_F_VTX_Z_CROSS_3_ADDR 0x239U

#define	CROSS3_F_VTX_Z_CROSS_3_MASK 0x20U

#define	CROSS3_F_VTX_Z_CROSS_3_POS 5U

#define	CROSS3_I_VTX_Z_CROSS_3_ADDR 0x239U

#define	CROSS3_I_VTX_Z_CROSS_3_MASK 0x40U

#define	CROSS3_I_VTX_Z_CROSS_3_POS 6U

#define	VTX_Z_CROSS_4_ADDR 0x23AU

#define	VTX_Z_CROSS_4_DEFAULT 0x04U

#define	CROSS4_VTX_Z_CROSS_4_ADDR 0x23AU

#define	CROSS4_VTX_Z_CROSS_4_MASK 0x1FU

#define	CROSS4_VTX_Z_CROSS_4_POS 0U

#define	CROSS4_F_VTX_Z_CROSS_4_ADDR 0x23AU

#define	CROSS4_F_VTX_Z_CROSS_4_MASK 0x20U

#define	CROSS4_F_VTX_Z_CROSS_4_POS 5U

#define	CROSS4_I_VTX_Z_CROSS_4_ADDR 0x23AU

#define	CROSS4_I_VTX_Z_CROSS_4_MASK 0x40U

#define	CROSS4_I_VTX_Z_CROSS_4_POS 6U

#define	VTX_Z_CROSS_5_ADDR 0x23BU

#define	VTX_Z_CROSS_5_DEFAULT 0x05U

#define	CROSS5_VTX_Z_CROSS_5_ADDR 0x23BU

#define	CROSS5_VTX_Z_CROSS_5_MASK 0x1FU

#define	CROSS5_VTX_Z_CROSS_5_POS 0U

#define	CROSS5_F_VTX_Z_CROSS_5_ADDR 0x23BU

#define	CROSS5_F_VTX_Z_CROSS_5_MASK 0x20U

#define	CROSS5_F_VTX_Z_CROSS_5_POS 5U

#define	CROSS5_I_VTX_Z_CROSS_5_ADDR 0x23BU

#define	CROSS5_I_VTX_Z_CROSS_5_MASK 0x40U

#define	CROSS5_I_VTX_Z_CROSS_5_POS 6U

#define	VTX_Z_CROSS_6_ADDR 0x23CU

#define	VTX_Z_CROSS_6_DEFAULT 0x06U

#define	CROSS6_VTX_Z_CROSS_6_ADDR 0x23CU

#define	CROSS6_VTX_Z_CROSS_6_MASK 0x1FU

#define	CROSS6_VTX_Z_CROSS_6_POS 0U

#define	CROSS6_F_VTX_Z_CROSS_6_ADDR 0x23CU

#define	CROSS6_F_VTX_Z_CROSS_6_MASK 0x20U

#define	CROSS6_F_VTX_Z_CROSS_6_POS 5U

#define	CROSS6_I_VTX_Z_CROSS_6_ADDR 0x23CU

#define	CROSS6_I_VTX_Z_CROSS_6_MASK 0x40U

#define	CROSS6_I_VTX_Z_CROSS_6_POS 6U

#define	VTX_Z_CROSS_7_ADDR 0x23DU

#define	VTX_Z_CROSS_7_DEFAULT 0x07U

#define	CROSS7_VTX_Z_CROSS_7_ADDR 0x23DU

#define	CROSS7_VTX_Z_CROSS_7_MASK 0x1FU

#define	CROSS7_VTX_Z_CROSS_7_POS 0U

#define	CROSS7_F_VTX_Z_CROSS_7_ADDR 0x23DU

#define	CROSS7_F_VTX_Z_CROSS_7_MASK 0x20U

#define	CROSS7_F_VTX_Z_CROSS_7_POS 5U

#define	CROSS7_I_VTX_Z_CROSS_7_ADDR 0x23DU

#define	CROSS7_I_VTX_Z_CROSS_7_MASK 0x40U

#define	CROSS7_I_VTX_Z_CROSS_7_POS 6U

#define	VTX_Z_CROSS_8_ADDR 0x23EU

#define	VTX_Z_CROSS_8_DEFAULT 0x08U

#define	CROSS8_VTX_Z_CROSS_8_ADDR 0x23EU

#define	CROSS8_VTX_Z_CROSS_8_MASK 0x1FU

#define	CROSS8_VTX_Z_CROSS_8_POS 0U

#define	CROSS8_F_VTX_Z_CROSS_8_ADDR 0x23EU

#define	CROSS8_F_VTX_Z_CROSS_8_MASK 0x20U

#define	CROSS8_F_VTX_Z_CROSS_8_POS 5U

#define	CROSS8_I_VTX_Z_CROSS_8_ADDR 0x23EU

#define	CROSS8_I_VTX_Z_CROSS_8_MASK 0x40U

#define	CROSS8_I_VTX_Z_CROSS_8_POS 6U

#define	VTX_Z_CROSS_9_ADDR 0x23FU

#define	VTX_Z_CROSS_9_DEFAULT 0x09U

#define	CROSS9_VTX_Z_CROSS_9_ADDR 0x23FU

#define	CROSS9_VTX_Z_CROSS_9_MASK 0x1FU

#define	CROSS9_VTX_Z_CROSS_9_POS 0U

#define	CROSS9_F_VTX_Z_CROSS_9_ADDR 0x23FU

#define	CROSS9_F_VTX_Z_CROSS_9_MASK 0x20U

#define	CROSS9_F_VTX_Z_CROSS_9_POS 5U

#define	CROSS9_I_VTX_Z_CROSS_9_ADDR 0x23FU

#define	CROSS9_I_VTX_Z_CROSS_9_MASK 0x40U

#define	CROSS9_I_VTX_Z_CROSS_9_POS 6U

#define	VTX_Z_CROSS_10_ADDR 0x240U

#define	VTX_Z_CROSS_10_DEFAULT 0x0AU

#define	CROSS10_VTX_Z_CROSS_10_ADDR 0x240U

#define	CROSS10_VTX_Z_CROSS_10_MASK 0x1FU

#define	CROSS10_VTX_Z_CROSS_10_POS 0U

#define	CROSS10_F_VTX_Z_CROSS_10_ADDR 0x240U

#define	CROSS10_F_VTX_Z_CROSS_10_MASK 0x20U

#define	CROSS10_F_VTX_Z_CROSS_10_POS 5U

#define	CROSS10_I_VTX_Z_CROSS_10_ADDR 0x240U

#define	CROSS10_I_VTX_Z_CROSS_10_MASK 0x40U

#define	CROSS10_I_VTX_Z_CROSS_10_POS 6U

#define	VTX_Z_CROSS_11_ADDR 0x241U

#define	VTX_Z_CROSS_11_DEFAULT 0x0BU

#define	CROSS11_VTX_Z_CROSS_11_ADDR 0x241U

#define	CROSS11_VTX_Z_CROSS_11_MASK 0x1FU

#define	CROSS11_VTX_Z_CROSS_11_POS 0U

#define	CROSS11_F_VTX_Z_CROSS_11_ADDR 0x241U

#define	CROSS11_F_VTX_Z_CROSS_11_MASK 0x20U

#define	CROSS11_F_VTX_Z_CROSS_11_POS 5U

#define	CROSS11_I_VTX_Z_CROSS_11_ADDR 0x241U

#define	CROSS11_I_VTX_Z_CROSS_11_MASK 0x40U

#define	CROSS11_I_VTX_Z_CROSS_11_POS 6U

#define	VTX_Z_CROSS_12_ADDR 0x242U

#define	VTX_Z_CROSS_12_DEFAULT 0x0CU

#define	CROSS12_VTX_Z_CROSS_12_ADDR 0x242U

#define	CROSS12_VTX_Z_CROSS_12_MASK 0x1FU

#define	CROSS12_VTX_Z_CROSS_12_POS 0U

#define	CROSS12_F_VTX_Z_CROSS_12_ADDR 0x242U

#define	CROSS12_F_VTX_Z_CROSS_12_MASK 0x20U

#define	CROSS12_F_VTX_Z_CROSS_12_POS 5U

#define	CROSS12_I_VTX_Z_CROSS_12_ADDR 0x242U

#define	CROSS12_I_VTX_Z_CROSS_12_MASK 0x40U

#define	CROSS12_I_VTX_Z_CROSS_12_POS 6U

#define	VTX_Z_CROSS_13_ADDR 0x243U

#define	VTX_Z_CROSS_13_DEFAULT 0x0DU

#define	CROSS13_VTX_Z_CROSS_13_ADDR 0x243U

#define	CROSS13_VTX_Z_CROSS_13_MASK 0x1FU

#define	CROSS13_VTX_Z_CROSS_13_POS 0U

#define	CROSS13_F_VTX_Z_CROSS_13_ADDR 0x243U

#define	CROSS13_F_VTX_Z_CROSS_13_MASK 0x20U

#define	CROSS13_F_VTX_Z_CROSS_13_POS 5U

#define	CROSS13_I_VTX_Z_CROSS_13_ADDR 0x243U

#define	CROSS13_I_VTX_Z_CROSS_13_MASK 0x40U

#define	CROSS13_I_VTX_Z_CROSS_13_POS 6U

#define	VTX_Z_CROSS_14_ADDR 0x244U

#define	VTX_Z_CROSS_14_DEFAULT 0x0EU

#define	CROSS14_VTX_Z_CROSS_14_ADDR 0x244U

#define	CROSS14_VTX_Z_CROSS_14_MASK 0x1FU

#define	CROSS14_VTX_Z_CROSS_14_POS 0U

#define	CROSS14_F_VTX_Z_CROSS_14_ADDR 0x244U

#define	CROSS14_F_VTX_Z_CROSS_14_MASK 0x20U

#define	CROSS14_F_VTX_Z_CROSS_14_POS 5U

#define	CROSS14_I_VTX_Z_CROSS_14_ADDR 0x244U

#define	CROSS14_I_VTX_Z_CROSS_14_MASK 0x40U

#define	CROSS14_I_VTX_Z_CROSS_14_POS 6U

#define	VTX_Z_CROSS_15_ADDR 0x245U

#define	VTX_Z_CROSS_15_DEFAULT 0x0FU

#define	CROSS15_VTX_Z_CROSS_15_ADDR 0x245U

#define	CROSS15_VTX_Z_CROSS_15_MASK 0x1FU

#define	CROSS15_VTX_Z_CROSS_15_POS 0U

#define	CROSS15_F_VTX_Z_CROSS_15_ADDR 0x245U

#define	CROSS15_F_VTX_Z_CROSS_15_MASK 0x20U

#define	CROSS15_F_VTX_Z_CROSS_15_POS 5U

#define	CROSS15_I_VTX_Z_CROSS_15_ADDR 0x245U

#define	CROSS15_I_VTX_Z_CROSS_15_MASK 0x40U

#define	CROSS15_I_VTX_Z_CROSS_15_POS 6U

#define	VTX_Z_CROSS_16_ADDR 0x246U

#define	VTX_Z_CROSS_16_DEFAULT 0x10U

#define	CROSS16_VTX_Z_CROSS_16_ADDR 0x246U

#define	CROSS16_VTX_Z_CROSS_16_MASK 0x1FU

#define	CROSS16_VTX_Z_CROSS_16_POS 0U

#define	CROSS16_F_VTX_Z_CROSS_16_ADDR 0x246U

#define	CROSS16_F_VTX_Z_CROSS_16_MASK 0x20U

#define	CROSS16_F_VTX_Z_CROSS_16_POS 5U

#define	CROSS16_I_VTX_Z_CROSS_16_ADDR 0x246U

#define	CROSS16_I_VTX_Z_CROSS_16_MASK 0x40U

#define	CROSS16_I_VTX_Z_CROSS_16_POS 6U

#define	VTX_Z_CROSS_17_ADDR 0x247U

#define	VTX_Z_CROSS_17_DEFAULT 0x11U

#define	CROSS17_VTX_Z_CROSS_17_ADDR 0x247U

#define	CROSS17_VTX_Z_CROSS_17_MASK 0x1FU

#define	CROSS17_VTX_Z_CROSS_17_POS 0U

#define	CROSS17_F_VTX_Z_CROSS_17_ADDR 0x247U

#define	CROSS17_F_VTX_Z_CROSS_17_MASK 0x20U

#define	CROSS17_F_VTX_Z_CROSS_17_POS 5U

#define	CROSS17_I_VTX_Z_CROSS_17_ADDR 0x247U

#define	CROSS17_I_VTX_Z_CROSS_17_MASK 0x40U

#define	CROSS17_I_VTX_Z_CROSS_17_POS 6U

#define	VTX_Z_CROSS_18_ADDR 0x248U

#define	VTX_Z_CROSS_18_DEFAULT 0x12U

#define	CROSS18_VTX_Z_CROSS_18_ADDR 0x248U

#define	CROSS18_VTX_Z_CROSS_18_MASK 0x1FU

#define	CROSS18_VTX_Z_CROSS_18_POS 0U

#define	CROSS18_F_VTX_Z_CROSS_18_ADDR 0x248U

#define	CROSS18_F_VTX_Z_CROSS_18_MASK 0x20U

#define	CROSS18_F_VTX_Z_CROSS_18_POS 5U

#define	CROSS18_I_VTX_Z_CROSS_18_ADDR 0x248U

#define	CROSS18_I_VTX_Z_CROSS_18_MASK 0x40U

#define	CROSS18_I_VTX_Z_CROSS_18_POS 6U

#define	VTX_Z_CROSS_19_ADDR 0x249U

#define	VTX_Z_CROSS_19_DEFAULT 0x13U

#define	CROSS19_VTX_Z_CROSS_19_ADDR 0x249U

#define	CROSS19_VTX_Z_CROSS_19_MASK 0x1FU

#define	CROSS19_VTX_Z_CROSS_19_POS 0U

#define	CROSS19_F_VTX_Z_CROSS_19_ADDR 0x249U

#define	CROSS19_F_VTX_Z_CROSS_19_MASK 0x20U

#define	CROSS19_F_VTX_Z_CROSS_19_POS 5U

#define	CROSS19_I_VTX_Z_CROSS_19_ADDR 0x249U

#define	CROSS19_I_VTX_Z_CROSS_19_MASK 0x40U

#define	CROSS19_I_VTX_Z_CROSS_19_POS 6U

#define	VTX_Z_CROSS_20_ADDR 0x24AU

#define	VTX_Z_CROSS_20_DEFAULT 0x14U

#define	CROSS20_VTX_Z_CROSS_20_ADDR 0x24AU

#define	CROSS20_VTX_Z_CROSS_20_MASK 0x1FU

#define	CROSS20_VTX_Z_CROSS_20_POS 0U

#define	CROSS20_F_VTX_Z_CROSS_20_ADDR 0x24AU

#define	CROSS20_F_VTX_Z_CROSS_20_MASK 0x20U

#define	CROSS20_F_VTX_Z_CROSS_20_POS 5U

#define	CROSS20_I_VTX_Z_CROSS_20_ADDR 0x24AU

#define	CROSS20_I_VTX_Z_CROSS_20_MASK 0x40U

#define	CROSS20_I_VTX_Z_CROSS_20_POS 6U

#define	VTX_Z_CROSS_21_ADDR 0x24BU

#define	VTX_Z_CROSS_21_DEFAULT 0x15U

#define	CROSS21_VTX_Z_CROSS_21_ADDR 0x24BU

#define	CROSS21_VTX_Z_CROSS_21_MASK 0x1FU

#define	CROSS21_VTX_Z_CROSS_21_POS 0U

#define	CROSS21_F_VTX_Z_CROSS_21_ADDR 0x24BU

#define	CROSS21_F_VTX_Z_CROSS_21_MASK 0x20U

#define	CROSS21_F_VTX_Z_CROSS_21_POS 5U

#define	CROSS21_I_VTX_Z_CROSS_21_ADDR 0x24BU

#define	CROSS21_I_VTX_Z_CROSS_21_MASK 0x40U

#define	CROSS21_I_VTX_Z_CROSS_21_POS 6U

#define	VTX_Z_CROSS_22_ADDR 0x24CU

#define	VTX_Z_CROSS_22_DEFAULT 0x16U

#define	CROSS22_VTX_Z_CROSS_22_ADDR 0x24CU

#define	CROSS22_VTX_Z_CROSS_22_MASK 0x1FU

#define	CROSS22_VTX_Z_CROSS_22_POS 0U

#define	CROSS22_F_VTX_Z_CROSS_22_ADDR 0x24CU

#define	CROSS22_F_VTX_Z_CROSS_22_MASK 0x20U

#define	CROSS22_F_VTX_Z_CROSS_22_POS 5U

#define	CROSS22_I_VTX_Z_CROSS_22_ADDR 0x24CU

#define	CROSS22_I_VTX_Z_CROSS_22_MASK 0x40U

#define	CROSS22_I_VTX_Z_CROSS_22_POS 6U

#define	VTX_Z_CROSS_23_ADDR 0x24DU

#define	VTX_Z_CROSS_23_DEFAULT 0x17U

#define	CROSS23_VTX_Z_CROSS_23_ADDR 0x24DU

#define	CROSS23_VTX_Z_CROSS_23_MASK 0x1FU

#define	CROSS23_VTX_Z_CROSS_23_POS 0U

#define	CROSS23_F_VTX_Z_CROSS_23_ADDR 0x24DU

#define	CROSS23_F_VTX_Z_CROSS_23_MASK 0x20U

#define	CROSS23_F_VTX_Z_CROSS_23_POS 5U

#define	CROSS23_I_VTX_Z_CROSS_23_ADDR 0x24DU

#define	CROSS23_I_VTX_Z_CROSS_23_MASK 0x40U

#define	CROSS23_I_VTX_Z_CROSS_23_POS 6U

#define	VTX_Z_VTX0_ADDR 0x24EU

#define	VTX_Z_VTX0_DEFAULT 0x03U

#define	VTG_MODE_VTX_Z_VTX0_ADDR 0x24EU

#define	VTG_MODE_VTX_Z_VTX0_MASK 0x03U

#define	VTG_MODE_VTX_Z_VTX0_POS 0U

#define	DE_INV_VTX_Z_VTX0_ADDR 0x24EU

#define	DE_INV_VTX_Z_VTX0_MASK 0x04U

#define	DE_INV_VTX_Z_VTX0_POS 2U

#define	HS_INV_VTX_Z_VTX0_ADDR 0x24EU

#define	HS_INV_VTX_Z_VTX0_MASK 0x08U

#define	HS_INV_VTX_Z_VTX0_POS 3U

#define	VS_INV_VTX_Z_VTX0_ADDR 0x24EU

#define	VS_INV_VTX_Z_VTX0_MASK 0x10U

#define	VS_INV_VTX_Z_VTX0_POS 4U

#define	GEN_DE_VTX_Z_VTX0_ADDR 0x24EU

#define	GEN_DE_VTX_Z_VTX0_MASK 0x20U

#define	GEN_DE_VTX_Z_VTX0_POS 5U

#define	GEN_HS_VTX_Z_VTX0_ADDR 0x24EU

#define	GEN_HS_VTX_Z_VTX0_MASK 0x40U

#define	GEN_HS_VTX_Z_VTX0_POS 6U

#define	GEN_VS_VTX_Z_VTX0_ADDR 0x24EU

#define	GEN_VS_VTX_Z_VTX0_MASK 0x80U

#define	GEN_VS_VTX_Z_VTX0_POS 7U

#define	VTX_Z_VTX1_ADDR 0x24FU

#define	VTX_Z_VTX1_DEFAULT 0x01U

#define	VS_TRIG_VTX_Z_VTX1_ADDR 0x24FU

#define	VS_TRIG_VTX_Z_VTX1_MASK 0x01U

#define	VS_TRIG_VTX_Z_VTX1_POS 0U

#define	PATGEN_CLK_SRC_VTX_Z_VTX1_ADDR 0x24FU

#define	PATGEN_CLK_SRC_VTX_Z_VTX1_MASK 0x0EU

#define	PATGEN_CLK_SRC_VTX_Z_VTX1_POS 1U

#define	PCLKDET_VTX_VTX_Z_VTX1_ADDR 0x24FU

#define	PCLKDET_VTX_VTX_Z_VTX1_MASK 0x20U

#define	PCLKDET_VTX_VTX_Z_VTX1_POS 5U

#define	VTX_Z_VTX2_ADDR 0x250U

#define	VTX_Z_VTX2_DEFAULT 0x00U

#define	VS_DLY_2_VTX_Z_VTX2_ADDR 0x250U

#define	VS_DLY_2_VTX_Z_VTX2_MASK 0xFFU

#define	VS_DLY_2_VTX_Z_VTX2_POS 0U

#define	VTX_Z_VTX3_ADDR 0x251U

#define	VTX_Z_VTX3_DEFAULT 0x00U

#define	VS_DLY_1_VTX_Z_VTX3_ADDR 0x251U

#define	VS_DLY_1_VTX_Z_VTX3_MASK 0xFFU

#define	VS_DLY_1_VTX_Z_VTX3_POS 0U

#define	VTX_Z_VTX4_ADDR 0x252U

#define	VTX_Z_VTX4_DEFAULT 0x00U

#define	VS_DLY_0_VTX_Z_VTX4_ADDR 0x252U

#define	VS_DLY_0_VTX_Z_VTX4_MASK 0xFFU

#define	VS_DLY_0_VTX_Z_VTX4_POS 0U

#define	VTX_Z_VTX5_ADDR 0x253U

#define	VTX_Z_VTX5_DEFAULT 0x00U

#define	VS_HIGH_2_VTX_Z_VTX5_ADDR 0x253U

#define	VS_HIGH_2_VTX_Z_VTX5_MASK 0xFFU

#define	VS_HIGH_2_VTX_Z_VTX5_POS 0U

#define	VTX_Z_VTX6_ADDR 0x254U

#define	VTX_Z_VTX6_DEFAULT 0x00U

#define	VS_HIGH_1_VTX_Z_VTX6_ADDR 0x254U

#define	VS_HIGH_1_VTX_Z_VTX6_MASK 0xFFU

#define	VS_HIGH_1_VTX_Z_VTX6_POS 0U

#define	VTX_Z_VTX7_ADDR 0x255U

#define	VTX_Z_VTX7_DEFAULT 0x00U

#define	VS_HIGH_0_VTX_Z_VTX7_ADDR 0x255U

#define	VS_HIGH_0_VTX_Z_VTX7_MASK 0xFFU

#define	VS_HIGH_0_VTX_Z_VTX7_POS 0U

#define	VTX_Z_VTX8_ADDR 0x256U

#define	VTX_Z_VTX8_DEFAULT 0x00U

#define	VS_LOW_2_VTX_Z_VTX8_ADDR 0x256U

#define	VS_LOW_2_VTX_Z_VTX8_MASK 0xFFU

#define	VS_LOW_2_VTX_Z_VTX8_POS 0U

#define	VTX_Z_VTX9_ADDR 0x257U

#define	VTX_Z_VTX9_DEFAULT 0x00U

#define	VS_LOW_1_VTX_Z_VTX9_ADDR 0x257U

#define	VS_LOW_1_VTX_Z_VTX9_MASK 0xFFU

#define	VS_LOW_1_VTX_Z_VTX9_POS 0U

#define	VTX_Z_VTX10_ADDR 0x258U

#define	VTX_Z_VTX10_DEFAULT 0x00U

#define	VS_LOW_0_VTX_Z_VTX10_ADDR 0x258U

#define	VS_LOW_0_VTX_Z_VTX10_MASK 0xFFU

#define	VS_LOW_0_VTX_Z_VTX10_POS 0U

#define	VTX_Z_VTX11_ADDR 0x259U

#define	VTX_Z_VTX11_DEFAULT 0x00U

#define	V2H_2_VTX_Z_VTX11_ADDR 0x259U

#define	V2H_2_VTX_Z_VTX11_MASK 0xFFU

#define	V2H_2_VTX_Z_VTX11_POS 0U

#define	VTX_Z_VTX12_ADDR 0x25AU

#define	VTX_Z_VTX12_DEFAULT 0x00U

#define	V2H_1_VTX_Z_VTX12_ADDR 0x25AU

#define	V2H_1_VTX_Z_VTX12_MASK 0xFFU

#define	V2H_1_VTX_Z_VTX12_POS 0U

#define	VTX_Z_VTX13_ADDR 0x25BU

#define	VTX_Z_VTX13_DEFAULT 0x00U

#define	V2H_0_VTX_Z_VTX13_ADDR 0x25BU

#define	V2H_0_VTX_Z_VTX13_MASK 0xFFU

#define	V2H_0_VTX_Z_VTX13_POS 0U

#define	VTX_Z_VTX14_ADDR 0x25CU

#define	VTX_Z_VTX14_DEFAULT 0x00U

#define	HS_HIGH_1_VTX_Z_VTX14_ADDR 0x25CU

#define	HS_HIGH_1_VTX_Z_VTX14_MASK 0xFFU

#define	HS_HIGH_1_VTX_Z_VTX14_POS 0U

#define	VTX_Z_VTX15_ADDR 0x25DU

#define	VTX_Z_VTX15_DEFAULT 0x00U

#define	HS_HIGH_0_VTX_Z_VTX15_ADDR 0x25DU

#define	HS_HIGH_0_VTX_Z_VTX15_MASK 0xFFU

#define	HS_HIGH_0_VTX_Z_VTX15_POS 0U

#define	VTX_Z_VTX16_ADDR 0x25EU

#define	VTX_Z_VTX16_DEFAULT 0x00U

#define	HS_LOW_1_VTX_Z_VTX16_ADDR 0x25EU

#define	HS_LOW_1_VTX_Z_VTX16_MASK 0xFFU

#define	HS_LOW_1_VTX_Z_VTX16_POS 0U

#define	VTX_Z_VTX17_ADDR 0x25FU

#define	VTX_Z_VTX17_DEFAULT 0x00U

#define	HS_LOW_0_VTX_Z_VTX17_ADDR 0x25FU

#define	HS_LOW_0_VTX_Z_VTX17_MASK 0xFFU

#define	HS_LOW_0_VTX_Z_VTX17_POS 0U

#define	VTX_Z_VTX18_ADDR 0x260U

#define	VTX_Z_VTX18_DEFAULT 0x00U

#define	HS_CNT_1_VTX_Z_VTX18_ADDR 0x260U

#define	HS_CNT_1_VTX_Z_VTX18_MASK 0xFFU

#define	HS_CNT_1_VTX_Z_VTX18_POS 0U

#define	VTX_Z_VTX19_ADDR 0x261U

#define	VTX_Z_VTX19_DEFAULT 0x00U

#define	HS_CNT_0_VTX_Z_VTX19_ADDR 0x261U

#define	HS_CNT_0_VTX_Z_VTX19_MASK 0xFFU

#define	HS_CNT_0_VTX_Z_VTX19_POS 0U

#define	VTX_Z_VTX20_ADDR 0x262U

#define	VTX_Z_VTX20_DEFAULT 0x00U

#define	V2D_2_VTX_Z_VTX20_ADDR 0x262U

#define	V2D_2_VTX_Z_VTX20_MASK 0xFFU

#define	V2D_2_VTX_Z_VTX20_POS 0U

#define	VTX_Z_VTX21_ADDR 0x263U

#define	VTX_Z_VTX21_DEFAULT 0x00U

#define	V2D_1_VTX_Z_VTX21_ADDR 0x263U

#define	V2D_1_VTX_Z_VTX21_MASK 0xFFU

#define	V2D_1_VTX_Z_VTX21_POS 0U

#define	VTX_Z_VTX22_ADDR 0x264U

#define	VTX_Z_VTX22_DEFAULT 0x00U

#define	V2D_0_VTX_Z_VTX22_ADDR 0x264U

#define	V2D_0_VTX_Z_VTX22_MASK 0xFFU

#define	V2D_0_VTX_Z_VTX22_POS 0U

#define	VTX_Z_VTX23_ADDR 0x265U

#define	VTX_Z_VTX23_DEFAULT 0x00U

#define	DE_HIGH_1_VTX_Z_VTX23_ADDR 0x265U

#define	DE_HIGH_1_VTX_Z_VTX23_MASK 0xFFU

#define	DE_HIGH_1_VTX_Z_VTX23_POS 0U

#define	VTX_Z_VTX24_ADDR 0x266U

#define	VTX_Z_VTX24_DEFAULT 0x00U

#define	DE_HIGH_0_VTX_Z_VTX24_ADDR 0x266U

#define	DE_HIGH_0_VTX_Z_VTX24_MASK 0xFFU

#define	DE_HIGH_0_VTX_Z_VTX24_POS 0U

#define	VTX_Z_VTX25_ADDR 0x267U

#define	VTX_Z_VTX25_DEFAULT 0x00U

#define	DE_LOW_1_VTX_Z_VTX25_ADDR 0x267U

#define	DE_LOW_1_VTX_Z_VTX25_MASK 0xFFU

#define	DE_LOW_1_VTX_Z_VTX25_POS 0U

#define	VTX_Z_VTX26_ADDR 0x268U

#define	VTX_Z_VTX26_DEFAULT 0x00U

#define	DE_LOW_0_VTX_Z_VTX26_ADDR 0x268U

#define	DE_LOW_0_VTX_Z_VTX26_MASK 0xFFU

#define	DE_LOW_0_VTX_Z_VTX26_POS 0U

#define	VTX_Z_VTX27_ADDR 0x269U

#define	VTX_Z_VTX27_DEFAULT 0x00U

#define	DE_CNT_1_VTX_Z_VTX27_ADDR 0x269U

#define	DE_CNT_1_VTX_Z_VTX27_MASK 0xFFU

#define	DE_CNT_1_VTX_Z_VTX27_POS 0U

#define	VTX_Z_VTX28_ADDR 0x26AU

#define	VTX_Z_VTX28_DEFAULT 0x00U

#define	DE_CNT_0_VTX_Z_VTX28_ADDR 0x26AU

#define	DE_CNT_0_VTX_Z_VTX28_MASK 0xFFU

#define	DE_CNT_0_VTX_Z_VTX28_POS 0U

#define	VTX_Z_VTX29_ADDR 0x26BU

#define	VTX_Z_VTX29_DEFAULT 0x00U

#define	PATGEN_MODE_VTX_Z_VTX29_ADDR 0x26BU

#define	PATGEN_MODE_VTX_Z_VTX29_MASK 0x03U

#define	PATGEN_MODE_VTX_Z_VTX29_POS 0U

#define	GRAD_MODE_VTX_Z_VTX29_ADDR 0x26BU

#define	GRAD_MODE_VTX_Z_VTX29_MASK 0x04U

#define	GRAD_MODE_VTX_Z_VTX29_POS 2U

#define	VPRBS_FAIL_VTX_Z_VTX29_ADDR 0x26BU

#define	VPRBS_FAIL_VTX_Z_VTX29_MASK 0x20U

#define	VPRBS_FAIL_VTX_Z_VTX29_POS 5U

#define	VID_PRBS_EN_VTX_Z_VTX29_ADDR 0x26BU

#define	VID_PRBS_EN_VTX_Z_VTX29_MASK 0x80U

#define	VID_PRBS_EN_VTX_Z_VTX29_POS 7U

#define	VTX_Z_VTX30_ADDR 0x26CU

#define	VTX_Z_VTX30_DEFAULT 0x04U

#define	GRAD_INC_VTX_Z_VTX30_ADDR 0x26CU

#define	GRAD_INC_VTX_Z_VTX30_MASK 0xFFU

#define	GRAD_INC_VTX_Z_VTX30_POS 0U

#define	VTX_Z_VTX31_ADDR 0x26DU

#define	VTX_Z_VTX31_DEFAULT 0x00U

#define	CHKR_A_L_VTX_Z_VTX31_ADDR 0x26DU

#define	CHKR_A_L_VTX_Z_VTX31_MASK 0xFFU

#define	CHKR_A_L_VTX_Z_VTX31_POS 0U

#define	VTX_Z_VTX32_ADDR 0x26EU

#define	VTX_Z_VTX32_DEFAULT 0x00U

#define	CHKR_A_M_VTX_Z_VTX32_ADDR 0x26EU

#define	CHKR_A_M_VTX_Z_VTX32_MASK 0xFFU

#define	CHKR_A_M_VTX_Z_VTX32_POS 0U

#define	VTX_Z_VTX33_ADDR 0x26FU

#define	VTX_Z_VTX33_DEFAULT 0x00U

#define	CHKR_A_H_VTX_Z_VTX33_ADDR 0x26FU

#define	CHKR_A_H_VTX_Z_VTX33_MASK 0xFFU

#define	CHKR_A_H_VTX_Z_VTX33_POS 0U

#define	VTX_Z_VTX34_ADDR 0x270U

#define	VTX_Z_VTX34_DEFAULT 0x00U

#define	CHKR_B_L_VTX_Z_VTX34_ADDR 0x270U

#define	CHKR_B_L_VTX_Z_VTX34_MASK 0xFFU

#define	CHKR_B_L_VTX_Z_VTX34_POS 0U

#define	VTX_Z_VTX35_ADDR 0x271U

#define	VTX_Z_VTX35_DEFAULT 0x00U

#define	CHKR_B_M_VTX_Z_VTX35_ADDR 0x271U

#define	CHKR_B_M_VTX_Z_VTX35_MASK 0xFFU

#define	CHKR_B_M_VTX_Z_VTX35_POS 0U

#define	VTX_Z_VTX36_ADDR 0x272U

#define	VTX_Z_VTX36_DEFAULT 0x00U

#define	CHKR_B_H_VTX_Z_VTX36_ADDR 0x272U

#define	CHKR_B_H_VTX_Z_VTX36_MASK 0xFFU

#define	CHKR_B_H_VTX_Z_VTX36_POS 0U

#define	VTX_Z_VTX37_ADDR 0x273U

#define	VTX_Z_VTX37_DEFAULT 0x00U

#define	CHKR_RPT_A_VTX_Z_VTX37_ADDR 0x273U

#define	CHKR_RPT_A_VTX_Z_VTX37_MASK 0xFFU

#define	CHKR_RPT_A_VTX_Z_VTX37_POS 0U

#define	VTX_Z_VTX38_ADDR 0x274U

#define	VTX_Z_VTX38_DEFAULT 0x00U

#define	CHKR_RPT_B_VTX_Z_VTX38_ADDR 0x274U

#define	CHKR_RPT_B_VTX_Z_VTX38_MASK 0xFFU

#define	CHKR_RPT_B_VTX_Z_VTX38_POS 0U

#define	VTX_Z_VTX39_ADDR 0x275U

#define	VTX_Z_VTX39_DEFAULT 0x00U

#define	CHKR_ALT_VTX_Z_VTX39_ADDR 0x275U

#define	CHKR_ALT_VTX_Z_VTX39_MASK 0xFFU

#define	CHKR_ALT_VTX_Z_VTX39_POS 0U

#define	VTX_Z_VTX40_ADDR 0x276U

#define	VTX_Z_VTX40_DEFAULT 0x18U

#define	CROSSHS_VTX_Z_VTX40_ADDR 0x276U

#define	CROSSHS_VTX_Z_VTX40_MASK 0x1FU

#define	CROSSHS_VTX_Z_VTX40_POS 0U

#define	CROSSHS_F_VTX_Z_VTX40_ADDR 0x276U

#define	CROSSHS_F_VTX_Z_VTX40_MASK 0x20U

#define	CROSSHS_F_VTX_Z_VTX40_POS 5U

#define	CROSSHS_I_VTX_Z_VTX40_ADDR 0x276U

#define	CROSSHS_I_VTX_Z_VTX40_MASK 0x40U

#define	CROSSHS_I_VTX_Z_VTX40_POS 6U

#define	VTX_Z_VTX41_ADDR 0x277U

#define	VTX_Z_VTX41_DEFAULT 0x19U

#define	CROSSVS_VTX_Z_VTX41_ADDR 0x277U

#define	CROSSVS_VTX_Z_VTX41_MASK 0x1FU

#define	CROSSVS_VTX_Z_VTX41_POS 0U

#define	CROSSVS_F_VTX_Z_VTX41_ADDR 0x277U

#define	CROSSVS_F_VTX_Z_VTX41_MASK 0x20U

#define	CROSSVS_F_VTX_Z_VTX41_POS 5U

#define	CROSSVS_I_VTX_Z_VTX41_ADDR 0x277U

#define	CROSSVS_I_VTX_Z_VTX41_MASK 0x40U

#define	CROSSVS_I_VTX_Z_VTX41_POS 6U

#define	VTX_Z_VTX42_ADDR 0x278U

#define	VTX_Z_VTX42_DEFAULT 0x1AU

#define	CROSSDE_VTX_Z_VTX42_ADDR 0x278U

#define	CROSSDE_VTX_Z_VTX42_MASK 0x1FU

#define	CROSSDE_VTX_Z_VTX42_POS 0U

#define	CROSSDE_F_VTX_Z_VTX42_ADDR 0x278U

#define	CROSSDE_F_VTX_Z_VTX42_MASK 0x20U

#define	CROSSDE_F_VTX_Z_VTX42_POS 5U

#define	CROSSDE_I_VTX_Z_VTX42_ADDR 0x278U

#define	CROSSDE_I_VTX_Z_VTX42_MASK 0x40U

#define	CROSSDE_I_VTX_Z_VTX42_POS 6U

#define	GPIO0_0_GPIO_A_ADDR 0x2BEU

#define	GPIO0_0_GPIO_A_DEFAULT 0x99U

#define	GPIO_OUT_DIS_GPIO0_0_GPIO_A_ADDR 0x2BEU

#define	GPIO_OUT_DIS_GPIO0_0_GPIO_A_MASK 0x01U

#define	GPIO_OUT_DIS_GPIO0_0_GPIO_A_POS 0U

#define	GPIO_TX_EN_GPIO0_0_GPIO_A_ADDR 0x2BEU

#define	GPIO_TX_EN_GPIO0_0_GPIO_A_MASK 0x02U

#define	GPIO_TX_EN_GPIO0_0_GPIO_A_POS 1U

#define	GPIO_RX_EN_GPIO0_0_GPIO_A_ADDR 0x2BEU

#define	GPIO_RX_EN_GPIO0_0_GPIO_A_MASK 0x04U

#define	GPIO_RX_EN_GPIO0_0_GPIO_A_POS 2U

#define	GPIO_IN_GPIO0_0_GPIO_A_ADDR 0x2BEU

#define	GPIO_IN_GPIO0_0_GPIO_A_MASK 0x08U

#define	GPIO_IN_GPIO0_0_GPIO_A_POS 3U

#define	GPIO_OUT_GPIO0_0_GPIO_A_ADDR 0x2BEU

#define	GPIO_OUT_GPIO0_0_GPIO_A_MASK 0x10U

#define	GPIO_OUT_GPIO0_0_GPIO_A_POS 4U

#define	TX_COMP_EN_GPIO0_0_GPIO_A_ADDR 0x2BEU

#define	TX_COMP_EN_GPIO0_0_GPIO_A_MASK 0x20U

#define	TX_COMP_EN_GPIO0_0_GPIO_A_POS 5U

#define	RES_CFG_GPIO0_0_GPIO_A_ADDR 0x2BEU

#define	RES_CFG_GPIO0_0_GPIO_A_MASK 0x80U

#define	RES_CFG_GPIO0_0_GPIO_A_POS 7U

#define	GPIO0_0_GPIO_B_ADDR 0x2BFU

#define	GPIO0_0_GPIO_B_DEFAULT 0xA0U

#define	GPIO_TX_ID_GPIO0_0_GPIO_B_ADDR 0x2BFU

#define	GPIO_TX_ID_GPIO0_0_GPIO_B_MASK 0x1FU

#define	GPIO_TX_ID_GPIO0_0_GPIO_B_POS 0U

#define	OUT_TYPE_GPIO0_0_GPIO_B_ADDR 0x2BFU

#define	OUT_TYPE_GPIO0_0_GPIO_B_MASK 0x20U

#define	OUT_TYPE_GPIO0_0_GPIO_B_POS 5U

#define	PULL_UPDN_SEL_GPIO0_0_GPIO_B_ADDR 0x2BFU

#define	PULL_UPDN_SEL_GPIO0_0_GPIO_B_MASK 0xC0U

#define	PULL_UPDN_SEL_GPIO0_0_GPIO_B_POS 6U

#define	GPIO0_0_GPIO_C_ADDR 0x2C0U

#define	GPIO0_0_GPIO_C_DEFAULT 0x40U

#define	GPIO_RX_ID_GPIO0_0_GPIO_C_ADDR 0x2C0U

#define	GPIO_RX_ID_GPIO0_0_GPIO_C_MASK 0x1FU

#define	GPIO_RX_ID_GPIO0_0_GPIO_C_POS 0U

#define	OVR_RES_CFG_GPIO0_0_GPIO_C_ADDR 0x2C0U

#define	OVR_RES_CFG_GPIO0_0_GPIO_C_MASK 0x80U

#define	OVR_RES_CFG_GPIO0_0_GPIO_C_POS 7U

#define	GPIO1_1_GPIO_A_ADDR 0x2C1U

#define	GPIO1_1_GPIO_A_DEFAULT 0x81U

#define	GPIO_OUT_DIS_GPIO1_1_GPIO_A_ADDR 0x2C1U

#define	GPIO_OUT_DIS_GPIO1_1_GPIO_A_MASK 0x01U

#define	GPIO_OUT_DIS_GPIO1_1_GPIO_A_POS 0U

#define	GPIO_TX_EN_GPIO1_1_GPIO_A_ADDR 0x2C1U

#define	GPIO_TX_EN_GPIO1_1_GPIO_A_MASK 0x02U

#define	GPIO_TX_EN_GPIO1_1_GPIO_A_POS 1U

#define	GPIO_RX_EN_GPIO1_1_GPIO_A_ADDR 0x2C1U

#define	GPIO_RX_EN_GPIO1_1_GPIO_A_MASK 0x04U

#define	GPIO_RX_EN_GPIO1_1_GPIO_A_POS 2U

#define	GPIO_IN_GPIO1_1_GPIO_A_ADDR 0x2C1U

#define	GPIO_IN_GPIO1_1_GPIO_A_MASK 0x08U

#define	GPIO_IN_GPIO1_1_GPIO_A_POS 3U

#define	GPIO_OUT_GPIO1_1_GPIO_A_ADDR 0x2C1U

#define	GPIO_OUT_GPIO1_1_GPIO_A_MASK 0x10U

#define	GPIO_OUT_GPIO1_1_GPIO_A_POS 4U

#define	TX_COMP_EN_GPIO1_1_GPIO_A_ADDR 0x2C1U

#define	TX_COMP_EN_GPIO1_1_GPIO_A_MASK 0x20U

#define	TX_COMP_EN_GPIO1_1_GPIO_A_POS 5U

#define	RES_CFG_GPIO1_1_GPIO_A_ADDR 0x2C1U

#define	RES_CFG_GPIO1_1_GPIO_A_MASK 0x80U

#define	RES_CFG_GPIO1_1_GPIO_A_POS 7U

#define	GPIO1_1_GPIO_B_ADDR 0x2C2U

#define	GPIO1_1_GPIO_B_DEFAULT 0x21U

#define	GPIO_TX_ID_GPIO1_1_GPIO_B_ADDR 0x2C2U

#define	GPIO_TX_ID_GPIO1_1_GPIO_B_MASK 0x1FU

#define	GPIO_TX_ID_GPIO1_1_GPIO_B_POS 0U

#define	OUT_TYPE_GPIO1_1_GPIO_B_ADDR 0x2C2U

#define	OUT_TYPE_GPIO1_1_GPIO_B_MASK 0x20U

#define	OUT_TYPE_GPIO1_1_GPIO_B_POS 5U

#define	PULL_UPDN_SEL_GPIO1_1_GPIO_B_ADDR 0x2C2U

#define	PULL_UPDN_SEL_GPIO1_1_GPIO_B_MASK 0xC0U

#define	PULL_UPDN_SEL_GPIO1_1_GPIO_B_POS 6U

#define	GPIO1_1_GPIO_C_ADDR 0x2C3U

#define	GPIO1_1_GPIO_C_DEFAULT 0x41U

#define	GPIO_RX_ID_GPIO1_1_GPIO_C_ADDR 0x2C3U

#define	GPIO_RX_ID_GPIO1_1_GPIO_C_MASK 0x1FU

#define	GPIO_RX_ID_GPIO1_1_GPIO_C_POS 0U

#define	OVR_RES_CFG_GPIO1_1_GPIO_C_ADDR 0x2C3U

#define	OVR_RES_CFG_GPIO1_1_GPIO_C_MASK 0x80U

#define	OVR_RES_CFG_GPIO1_1_GPIO_C_POS 7U

#define	GPIO2_2_GPIO_A_ADDR 0x2C4U

#define	GPIO2_2_GPIO_A_DEFAULT 0x99U

#define	GPIO_OUT_DIS_GPIO2_2_GPIO_A_ADDR 0x2C4U

#define	GPIO_OUT_DIS_GPIO2_2_GPIO_A_MASK 0x01U

#define	GPIO_OUT_DIS_GPIO2_2_GPIO_A_POS 0U

#define	GPIO_TX_EN_GPIO2_2_GPIO_A_ADDR 0x2C4U

#define	GPIO_TX_EN_GPIO2_2_GPIO_A_MASK 0x02U

#define	GPIO_TX_EN_GPIO2_2_GPIO_A_POS 1U

#define	GPIO_RX_EN_GPIO2_2_GPIO_A_ADDR 0x2C4U

#define	GPIO_RX_EN_GPIO2_2_GPIO_A_MASK 0x04U

#define	GPIO_RX_EN_GPIO2_2_GPIO_A_POS 2U

#define	GPIO_IN_GPIO2_2_GPIO_A_ADDR 0x2C4U

#define	GPIO_IN_GPIO2_2_GPIO_A_MASK 0x08U

#define	GPIO_IN_GPIO2_2_GPIO_A_POS 3U

#define	GPIO_OUT_GPIO2_2_GPIO_A_ADDR 0x2C4U

#define	GPIO_OUT_GPIO2_2_GPIO_A_MASK 0x10U

#define	GPIO_OUT_GPIO2_2_GPIO_A_POS 4U

#define	TX_COMP_EN_GPIO2_2_GPIO_A_ADDR 0x2C4U

#define	TX_COMP_EN_GPIO2_2_GPIO_A_MASK 0x20U

#define	TX_COMP_EN_GPIO2_2_GPIO_A_POS 5U

#define	RES_CFG_GPIO2_2_GPIO_A_ADDR 0x2C4U

#define	RES_CFG_GPIO2_2_GPIO_A_MASK 0x80U

#define	RES_CFG_GPIO2_2_GPIO_A_POS 7U

#define	GPIO2_2_GPIO_B_ADDR 0x2C5U

#define	GPIO2_2_GPIO_B_DEFAULT 0x22U

#define	GPIO_TX_ID_GPIO2_2_GPIO_B_ADDR 0x2C5U

#define	GPIO_TX_ID_GPIO2_2_GPIO_B_MASK 0x1FU

#define	GPIO_TX_ID_GPIO2_2_GPIO_B_POS 0U

#define	OUT_TYPE_GPIO2_2_GPIO_B_ADDR 0x2C5U

#define	OUT_TYPE_GPIO2_2_GPIO_B_MASK 0x20U

#define	OUT_TYPE_GPIO2_2_GPIO_B_POS 5U

#define	PULL_UPDN_SEL_GPIO2_2_GPIO_B_ADDR 0x2C5U

#define	PULL_UPDN_SEL_GPIO2_2_GPIO_B_MASK 0xC0U

#define	PULL_UPDN_SEL_GPIO2_2_GPIO_B_POS 6U

#define	GPIO2_2_GPIO_C_ADDR 0x2C6U

#define	GPIO2_2_GPIO_C_DEFAULT 0x42U

#define	GPIO_RX_ID_GPIO2_2_GPIO_C_ADDR 0x2C6U

#define	GPIO_RX_ID_GPIO2_2_GPIO_C_MASK 0x1FU

#define	GPIO_RX_ID_GPIO2_2_GPIO_C_POS 0U

#define	OVR_RES_CFG_GPIO2_2_GPIO_C_ADDR 0x2C6U

#define	OVR_RES_CFG_GPIO2_2_GPIO_C_MASK 0x80U

#define	OVR_RES_CFG_GPIO2_2_GPIO_C_POS 7U

#define	GPIO3_3_GPIO_A_ADDR 0x2C7U

#define	GPIO3_3_GPIO_A_DEFAULT 0x81U

#define	GPIO_OUT_DIS_GPIO3_3_GPIO_A_ADDR 0x2C7U

#define	GPIO_OUT_DIS_GPIO3_3_GPIO_A_MASK 0x01U

#define	GPIO_OUT_DIS_GPIO3_3_GPIO_A_POS 0U

#define	GPIO_TX_EN_GPIO3_3_GPIO_A_ADDR 0x2C7U

#define	GPIO_TX_EN_GPIO3_3_GPIO_A_MASK 0x02U

#define	GPIO_TX_EN_GPIO3_3_GPIO_A_POS 1U

#define	GPIO_RX_EN_GPIO3_3_GPIO_A_ADDR 0x2C7U

#define	GPIO_RX_EN_GPIO3_3_GPIO_A_MASK 0x04U

#define	GPIO_RX_EN_GPIO3_3_GPIO_A_POS 2U

#define	GPIO_IN_GPIO3_3_GPIO_A_ADDR 0x2C7U

#define	GPIO_IN_GPIO3_3_GPIO_A_MASK 0x08U

#define	GPIO_IN_GPIO3_3_GPIO_A_POS 3U

#define	GPIO_OUT_GPIO3_3_GPIO_A_ADDR 0x2C7U

#define	GPIO_OUT_GPIO3_3_GPIO_A_MASK 0x10U

#define	GPIO_OUT_GPIO3_3_GPIO_A_POS 4U

#define	TX_COMP_EN_GPIO3_3_GPIO_A_ADDR 0x2C7U

#define	TX_COMP_EN_GPIO3_3_GPIO_A_MASK 0x20U

#define	TX_COMP_EN_GPIO3_3_GPIO_A_POS 5U

#define	RES_CFG_GPIO3_3_GPIO_A_ADDR 0x2C7U

#define	RES_CFG_GPIO3_3_GPIO_A_MASK 0x80U

#define	RES_CFG_GPIO3_3_GPIO_A_POS 7U

#define	GPIO3_3_GPIO_B_ADDR 0x2C8U

#define	GPIO3_3_GPIO_B_DEFAULT 0xA3U

#define	GPIO_TX_ID_GPIO3_3_GPIO_B_ADDR 0x2C8U

#define	GPIO_TX_ID_GPIO3_3_GPIO_B_MASK 0x1FU

#define	GPIO_TX_ID_GPIO3_3_GPIO_B_POS 0U

#define	OUT_TYPE_GPIO3_3_GPIO_B_ADDR 0x2C8U

#define	OUT_TYPE_GPIO3_3_GPIO_B_MASK 0x20U

#define	OUT_TYPE_GPIO3_3_GPIO_B_POS 5U

#define	PULL_UPDN_SEL_GPIO3_3_GPIO_B_ADDR 0x2C8U

#define	PULL_UPDN_SEL_GPIO3_3_GPIO_B_MASK 0xC0U

#define	PULL_UPDN_SEL_GPIO3_3_GPIO_B_POS 6U

#define	GPIO3_3_GPIO_C_ADDR 0x2C9U

#define	GPIO3_3_GPIO_C_DEFAULT 0x43U

#define	GPIO_RX_ID_GPIO3_3_GPIO_C_ADDR 0x2C9U

#define	GPIO_RX_ID_GPIO3_3_GPIO_C_MASK 0x1FU

#define	GPIO_RX_ID_GPIO3_3_GPIO_C_POS 0U

#define	OVR_RES_CFG_GPIO3_3_GPIO_C_ADDR 0x2C9U

#define	OVR_RES_CFG_GPIO3_3_GPIO_C_MASK 0x80U

#define	OVR_RES_CFG_GPIO3_3_GPIO_C_POS 7U

#define	GPIO4_4_GPIO_A_ADDR 0x2CAU

#define	GPIO4_4_GPIO_A_DEFAULT 0x99U

#define	GPIO_OUT_DIS_GPIO4_4_GPIO_A_ADDR 0x2CAU

#define	GPIO_OUT_DIS_GPIO4_4_GPIO_A_MASK 0x01U

#define	GPIO_OUT_DIS_GPIO4_4_GPIO_A_POS 0U

#define	GPIO_TX_EN_GPIO4_4_GPIO_A_ADDR 0x2CAU

#define	GPIO_TX_EN_GPIO4_4_GPIO_A_MASK 0x02U

#define	GPIO_TX_EN_GPIO4_4_GPIO_A_POS 1U

#define	GPIO_RX_EN_GPIO4_4_GPIO_A_ADDR 0x2CAU

#define	GPIO_RX_EN_GPIO4_4_GPIO_A_MASK 0x04U

#define	GPIO_RX_EN_GPIO4_4_GPIO_A_POS 2U

#define	GPIO_IN_GPIO4_4_GPIO_A_ADDR 0x2CAU

#define	GPIO_IN_GPIO4_4_GPIO_A_MASK 0x08U

#define	GPIO_IN_GPIO4_4_GPIO_A_POS 3U

#define	GPIO_OUT_GPIO4_4_GPIO_A_ADDR 0x2CAU

#define	GPIO_OUT_GPIO4_4_GPIO_A_MASK 0x10U

#define	GPIO_OUT_GPIO4_4_GPIO_A_POS 4U

#define	TX_COMP_EN_GPIO4_4_GPIO_A_ADDR 0x2CAU

#define	TX_COMP_EN_GPIO4_4_GPIO_A_MASK 0x20U

#define	TX_COMP_EN_GPIO4_4_GPIO_A_POS 5U

#define	RES_CFG_GPIO4_4_GPIO_A_ADDR 0x2CAU

#define	RES_CFG_GPIO4_4_GPIO_A_MASK 0x80U

#define	RES_CFG_GPIO4_4_GPIO_A_POS 7U

#define	GPIO4_4_GPIO_B_ADDR 0x2CBU

#define	GPIO4_4_GPIO_B_DEFAULT 0xA4U

#define	GPIO_TX_ID_GPIO4_4_GPIO_B_ADDR 0x2CBU

#define	GPIO_TX_ID_GPIO4_4_GPIO_B_MASK 0x1FU

#define	GPIO_TX_ID_GPIO4_4_GPIO_B_POS 0U

#define	OUT_TYPE_GPIO4_4_GPIO_B_ADDR 0x2CBU

#define	OUT_TYPE_GPIO4_4_GPIO_B_MASK 0x20U

#define	OUT_TYPE_GPIO4_4_GPIO_B_POS 5U

#define	PULL_UPDN_SEL_GPIO4_4_GPIO_B_ADDR 0x2CBU

#define	PULL_UPDN_SEL_GPIO4_4_GPIO_B_MASK 0xC0U

#define	PULL_UPDN_SEL_GPIO4_4_GPIO_B_POS 6U

#define	GPIO4_4_GPIO_C_ADDR 0x2CCU

#define	GPIO4_4_GPIO_C_DEFAULT 0x44U

#define	GPIO_RX_ID_GPIO4_4_GPIO_C_ADDR 0x2CCU

#define	GPIO_RX_ID_GPIO4_4_GPIO_C_MASK 0x1FU

#define	GPIO_RX_ID_GPIO4_4_GPIO_C_POS 0U

#define	OVR_RES_CFG_GPIO4_4_GPIO_C_ADDR 0x2CCU

#define	OVR_RES_CFG_GPIO4_4_GPIO_C_MASK 0x80U

#define	OVR_RES_CFG_GPIO4_4_GPIO_C_POS 7U

#define	GPIO5_5_GPIO_A_ADDR 0x2CDU

#define	GPIO5_5_GPIO_A_DEFAULT 0x81U

#define	GPIO_OUT_DIS_GPIO5_5_GPIO_A_ADDR 0x2CDU

#define	GPIO_OUT_DIS_GPIO5_5_GPIO_A_MASK 0x01U

#define	GPIO_OUT_DIS_GPIO5_5_GPIO_A_POS 0U

#define	GPIO_TX_EN_GPIO5_5_GPIO_A_ADDR 0x2CDU

#define	GPIO_TX_EN_GPIO5_5_GPIO_A_MASK 0x02U

#define	GPIO_TX_EN_GPIO5_5_GPIO_A_POS 1U

#define	GPIO_RX_EN_GPIO5_5_GPIO_A_ADDR 0x2CDU

#define	GPIO_RX_EN_GPIO5_5_GPIO_A_MASK 0x04U

#define	GPIO_RX_EN_GPIO5_5_GPIO_A_POS 2U

#define	GPIO_IN_GPIO5_5_GPIO_A_ADDR 0x2CDU

#define	GPIO_IN_GPIO5_5_GPIO_A_MASK 0x08U

#define	GPIO_IN_GPIO5_5_GPIO_A_POS 3U

#define	GPIO_OUT_GPIO5_5_GPIO_A_ADDR 0x2CDU

#define	GPIO_OUT_GPIO5_5_GPIO_A_MASK 0x10U

#define	GPIO_OUT_GPIO5_5_GPIO_A_POS 4U

#define	TX_COMP_EN_GPIO5_5_GPIO_A_ADDR 0x2CDU

#define	TX_COMP_EN_GPIO5_5_GPIO_A_MASK 0x20U

#define	TX_COMP_EN_GPIO5_5_GPIO_A_POS 5U

#define	RES_CFG_GPIO5_5_GPIO_A_ADDR 0x2CDU

#define	RES_CFG_GPIO5_5_GPIO_A_MASK 0x80U

#define	RES_CFG_GPIO5_5_GPIO_A_POS 7U

#define	GPIO5_5_GPIO_B_ADDR 0x2CEU

#define	GPIO5_5_GPIO_B_DEFAULT 0xA5U

#define	GPIO_TX_ID_GPIO5_5_GPIO_B_ADDR 0x2CEU

#define	GPIO_TX_ID_GPIO5_5_GPIO_B_MASK 0x1FU

#define	GPIO_TX_ID_GPIO5_5_GPIO_B_POS 0U

#define	OUT_TYPE_GPIO5_5_GPIO_B_ADDR 0x2CEU

#define	OUT_TYPE_GPIO5_5_GPIO_B_MASK 0x20U

#define	OUT_TYPE_GPIO5_5_GPIO_B_POS 5U

#define	PULL_UPDN_SEL_GPIO5_5_GPIO_B_ADDR 0x2CEU

#define	PULL_UPDN_SEL_GPIO5_5_GPIO_B_MASK 0xC0U

#define	PULL_UPDN_SEL_GPIO5_5_GPIO_B_POS 6U

#define	GPIO5_5_GPIO_C_ADDR 0x2CFU

#define	GPIO5_5_GPIO_C_DEFAULT 0x45U

#define	GPIO_RX_ID_GPIO5_5_GPIO_C_ADDR 0x2CFU

#define	GPIO_RX_ID_GPIO5_5_GPIO_C_MASK 0x1FU

#define	GPIO_RX_ID_GPIO5_5_GPIO_C_POS 0U

#define	OVR_RES_CFG_GPIO5_5_GPIO_C_ADDR 0x2CFU

#define	OVR_RES_CFG_GPIO5_5_GPIO_C_MASK 0x80U

#define	OVR_RES_CFG_GPIO5_5_GPIO_C_POS 7U

#define	GPIO6_6_GPIO_A_ADDR 0x2D0U

#define	GPIO6_6_GPIO_A_DEFAULT 0x99U

#define	GPIO_OUT_DIS_GPIO6_6_GPIO_A_ADDR 0x2D0U

#define	GPIO_OUT_DIS_GPIO6_6_GPIO_A_MASK 0x01U

#define	GPIO_OUT_DIS_GPIO6_6_GPIO_A_POS 0U

#define	GPIO_TX_EN_GPIO6_6_GPIO_A_ADDR 0x2D0U

#define	GPIO_TX_EN_GPIO6_6_GPIO_A_MASK 0x02U

#define	GPIO_TX_EN_GPIO6_6_GPIO_A_POS 1U

#define	GPIO_RX_EN_GPIO6_6_GPIO_A_ADDR 0x2D0U

#define	GPIO_RX_EN_GPIO6_6_GPIO_A_MASK 0x04U

#define	GPIO_RX_EN_GPIO6_6_GPIO_A_POS 2U

#define	GPIO_IN_GPIO6_6_GPIO_A_ADDR 0x2D0U

#define	GPIO_IN_GPIO6_6_GPIO_A_MASK 0x08U

#define	GPIO_IN_GPIO6_6_GPIO_A_POS 3U

#define	GPIO_OUT_GPIO6_6_GPIO_A_ADDR 0x2D0U

#define	GPIO_OUT_GPIO6_6_GPIO_A_MASK 0x10U

#define	GPIO_OUT_GPIO6_6_GPIO_A_POS 4U

#define	TX_COMP_EN_GPIO6_6_GPIO_A_ADDR 0x2D0U

#define	TX_COMP_EN_GPIO6_6_GPIO_A_MASK 0x20U

#define	TX_COMP_EN_GPIO6_6_GPIO_A_POS 5U

#define	RES_CFG_GPIO6_6_GPIO_A_ADDR 0x2D0U

#define	RES_CFG_GPIO6_6_GPIO_A_MASK 0x80U

#define	RES_CFG_GPIO6_6_GPIO_A_POS 7U

#define	GPIO6_6_GPIO_B_ADDR 0x2D1U

#define	GPIO6_6_GPIO_B_DEFAULT 0xA6U

#define	GPIO_TX_ID_GPIO6_6_GPIO_B_ADDR 0x2D1U

#define	GPIO_TX_ID_GPIO6_6_GPIO_B_MASK 0x1FU

#define	GPIO_TX_ID_GPIO6_6_GPIO_B_POS 0U

#define	OUT_TYPE_GPIO6_6_GPIO_B_ADDR 0x2D1U

#define	OUT_TYPE_GPIO6_6_GPIO_B_MASK 0x20U

#define	OUT_TYPE_GPIO6_6_GPIO_B_POS 5U

#define	PULL_UPDN_SEL_GPIO6_6_GPIO_B_ADDR 0x2D1U

#define	PULL_UPDN_SEL_GPIO6_6_GPIO_B_MASK 0xC0U

#define	PULL_UPDN_SEL_GPIO6_6_GPIO_B_POS 6U

#define	GPIO6_6_GPIO_C_ADDR 0x2D2U

#define	GPIO6_6_GPIO_C_DEFAULT 0x46U

#define	GPIO_RX_ID_GPIO6_6_GPIO_C_ADDR 0x2D2U

#define	GPIO_RX_ID_GPIO6_6_GPIO_C_MASK 0x1FU

#define	GPIO_RX_ID_GPIO6_6_GPIO_C_POS 0U

#define	OVR_RES_CFG_GPIO6_6_GPIO_C_ADDR 0x2D2U

#define	OVR_RES_CFG_GPIO6_6_GPIO_C_MASK 0x80U

#define	OVR_RES_CFG_GPIO6_6_GPIO_C_POS 7U

#define	GPIO7_7_GPIO_A_ADDR 0x2D3U

#define	GPIO7_7_GPIO_A_DEFAULT 0x83U

#define	GPIO_OUT_DIS_GPIO7_7_GPIO_A_ADDR 0x2D3U

#define	GPIO_OUT_DIS_GPIO7_7_GPIO_A_MASK 0x01U

#define	GPIO_OUT_DIS_GPIO7_7_GPIO_A_POS 0U

#define	GPIO_TX_EN_GPIO7_7_GPIO_A_ADDR 0x2D3U

#define	GPIO_TX_EN_GPIO7_7_GPIO_A_MASK 0x02U

#define	GPIO_TX_EN_GPIO7_7_GPIO_A_POS 1U

#define	GPIO_RX_EN_GPIO7_7_GPIO_A_ADDR 0x2D3U

#define	GPIO_RX_EN_GPIO7_7_GPIO_A_MASK 0x04U

#define	GPIO_RX_EN_GPIO7_7_GPIO_A_POS 2U

#define	GPIO_IN_GPIO7_7_GPIO_A_ADDR 0x2D3U

#define	GPIO_IN_GPIO7_7_GPIO_A_MASK 0x08U

#define	GPIO_IN_GPIO7_7_GPIO_A_POS 3U

#define	GPIO_OUT_GPIO7_7_GPIO_A_ADDR 0x2D3U

#define	GPIO_OUT_GPIO7_7_GPIO_A_MASK 0x10U

#define	GPIO_OUT_GPIO7_7_GPIO_A_POS 4U

#define	TX_COMP_EN_GPIO7_7_GPIO_A_ADDR 0x2D3U

#define	TX_COMP_EN_GPIO7_7_GPIO_A_MASK 0x20U

#define	TX_COMP_EN_GPIO7_7_GPIO_A_POS 5U

#define	RES_CFG_GPIO7_7_GPIO_A_ADDR 0x2D3U

#define	RES_CFG_GPIO7_7_GPIO_A_MASK 0x80U

#define	RES_CFG_GPIO7_7_GPIO_A_POS 7U

#define	GPIO7_7_GPIO_B_ADDR 0x2D4U

#define	GPIO7_7_GPIO_B_DEFAULT 0xA7U

#define	GPIO_TX_ID_GPIO7_7_GPIO_B_ADDR 0x2D4U

#define	GPIO_TX_ID_GPIO7_7_GPIO_B_MASK 0x1FU

#define	GPIO_TX_ID_GPIO7_7_GPIO_B_POS 0U

#define	OUT_TYPE_GPIO7_7_GPIO_B_ADDR 0x2D4U

#define	OUT_TYPE_GPIO7_7_GPIO_B_MASK 0x20U

#define	OUT_TYPE_GPIO7_7_GPIO_B_POS 5U

#define	PULL_UPDN_SEL_GPIO7_7_GPIO_B_ADDR 0x2D4U

#define	PULL_UPDN_SEL_GPIO7_7_GPIO_B_MASK 0xC0U

#define	PULL_UPDN_SEL_GPIO7_7_GPIO_B_POS 6U

#define	GPIO7_7_GPIO_C_ADDR 0x2D5U

#define	GPIO7_7_GPIO_C_DEFAULT 0x47U

#define	GPIO_RX_ID_GPIO7_7_GPIO_C_ADDR 0x2D5U

#define	GPIO_RX_ID_GPIO7_7_GPIO_C_MASK 0x1FU

#define	GPIO_RX_ID_GPIO7_7_GPIO_C_POS 0U

#define	OVR_RES_CFG_GPIO7_7_GPIO_C_ADDR 0x2D5U

#define	OVR_RES_CFG_GPIO7_7_GPIO_C_MASK 0x80U

#define	OVR_RES_CFG_GPIO7_7_GPIO_C_POS 7U

#define	GPIO8_8_GPIO_A_ADDR 0x2D6U

#define	GPIO8_8_GPIO_A_DEFAULT 0x9CU

#define	GPIO_OUT_DIS_GPIO8_8_GPIO_A_ADDR 0x2D6U

#define	GPIO_OUT_DIS_GPIO8_8_GPIO_A_MASK 0x01U

#define	GPIO_OUT_DIS_GPIO8_8_GPIO_A_POS 0U

#define	GPIO_TX_EN_GPIO8_8_GPIO_A_ADDR 0x2D6U

#define	GPIO_TX_EN_GPIO8_8_GPIO_A_MASK 0x02U

#define	GPIO_TX_EN_GPIO8_8_GPIO_A_POS 1U

#define	GPIO_RX_EN_GPIO8_8_GPIO_A_ADDR 0x2D6U

#define	GPIO_RX_EN_GPIO8_8_GPIO_A_MASK 0x04U

#define	GPIO_RX_EN_GPIO8_8_GPIO_A_POS 2U

#define	GPIO_IN_GPIO8_8_GPIO_A_ADDR 0x2D6U

#define	GPIO_IN_GPIO8_8_GPIO_A_MASK 0x08U

#define	GPIO_IN_GPIO8_8_GPIO_A_POS 3U

#define	GPIO_OUT_GPIO8_8_GPIO_A_ADDR 0x2D6U

#define	GPIO_OUT_GPIO8_8_GPIO_A_MASK 0x10U

#define	GPIO_OUT_GPIO8_8_GPIO_A_POS 4U

#define	TX_COMP_EN_GPIO8_8_GPIO_A_ADDR 0x2D6U

#define	TX_COMP_EN_GPIO8_8_GPIO_A_MASK 0x20U

#define	TX_COMP_EN_GPIO8_8_GPIO_A_POS 5U

#define	RES_CFG_GPIO8_8_GPIO_A_ADDR 0x2D6U

#define	RES_CFG_GPIO8_8_GPIO_A_MASK 0x80U

#define	RES_CFG_GPIO8_8_GPIO_A_POS 7U

#define	GPIO8_8_GPIO_B_ADDR 0x2D7U

#define	GPIO8_8_GPIO_B_DEFAULT 0x28U

#define	GPIO_TX_ID_GPIO8_8_GPIO_B_ADDR 0x2D7U

#define	GPIO_TX_ID_GPIO8_8_GPIO_B_MASK 0x1FU

#define	GPIO_TX_ID_GPIO8_8_GPIO_B_POS 0U

#define	OUT_TYPE_GPIO8_8_GPIO_B_ADDR 0x2D7U

#define	OUT_TYPE_GPIO8_8_GPIO_B_MASK 0x20U

#define	OUT_TYPE_GPIO8_8_GPIO_B_POS 5U

#define	PULL_UPDN_SEL_GPIO8_8_GPIO_B_ADDR 0x2D7U

#define	PULL_UPDN_SEL_GPIO8_8_GPIO_B_MASK 0xC0U

#define	PULL_UPDN_SEL_GPIO8_8_GPIO_B_POS 6U

#define	GPIO8_8_GPIO_C_ADDR 0x2D8U

#define	GPIO8_8_GPIO_C_DEFAULT 0x48U

#define	GPIO_RX_ID_GPIO8_8_GPIO_C_ADDR 0x2D8U

#define	GPIO_RX_ID_GPIO8_8_GPIO_C_MASK 0x1FU

#define	GPIO_RX_ID_GPIO8_8_GPIO_C_POS 0U

#define	OVR_RES_CFG_GPIO8_8_GPIO_C_ADDR 0x2D8U

#define	OVR_RES_CFG_GPIO8_8_GPIO_C_MASK 0x80U

#define	OVR_RES_CFG_GPIO8_8_GPIO_C_POS 7U

#define	GPIO9_9_GPIO_A_ADDR 0x2D9U

#define	GPIO9_9_GPIO_A_DEFAULT 0x81U

#define	GPIO_OUT_DIS_GPIO9_9_GPIO_A_ADDR 0x2D9U

#define	GPIO_OUT_DIS_GPIO9_9_GPIO_A_MASK 0x01U

#define	GPIO_OUT_DIS_GPIO9_9_GPIO_A_POS 0U

#define	GPIO_TX_EN_GPIO9_9_GPIO_A_ADDR 0x2D9U

#define	GPIO_TX_EN_GPIO9_9_GPIO_A_MASK 0x02U

#define	GPIO_TX_EN_GPIO9_9_GPIO_A_POS 1U

#define	GPIO_RX_EN_GPIO9_9_GPIO_A_ADDR 0x2D9U

#define	GPIO_RX_EN_GPIO9_9_GPIO_A_MASK 0x04U

#define	GPIO_RX_EN_GPIO9_9_GPIO_A_POS 2U

#define	GPIO_IN_GPIO9_9_GPIO_A_ADDR 0x2D9U

#define	GPIO_IN_GPIO9_9_GPIO_A_MASK 0x08U

#define	GPIO_IN_GPIO9_9_GPIO_A_POS 3U

#define	GPIO_OUT_GPIO9_9_GPIO_A_ADDR 0x2D9U

#define	GPIO_OUT_GPIO9_9_GPIO_A_MASK 0x10U

#define	GPIO_OUT_GPIO9_9_GPIO_A_POS 4U

#define	TX_COMP_EN_GPIO9_9_GPIO_A_ADDR 0x2D9U

#define	TX_COMP_EN_GPIO9_9_GPIO_A_MASK 0x20U

#define	TX_COMP_EN_GPIO9_9_GPIO_A_POS 5U

#define	RES_CFG_GPIO9_9_GPIO_A_ADDR 0x2D9U

#define	RES_CFG_GPIO9_9_GPIO_A_MASK 0x80U

#define	RES_CFG_GPIO9_9_GPIO_A_POS 7U

#define	GPIO9_9_GPIO_B_ADDR 0x2DAU

#define	GPIO9_9_GPIO_B_DEFAULT 0xA9U

#define	GPIO_TX_ID_GPIO9_9_GPIO_B_ADDR 0x2DAU

#define	GPIO_TX_ID_GPIO9_9_GPIO_B_MASK 0x1FU

#define	GPIO_TX_ID_GPIO9_9_GPIO_B_POS 0U

#define	OUT_TYPE_GPIO9_9_GPIO_B_ADDR 0x2DAU

#define	OUT_TYPE_GPIO9_9_GPIO_B_MASK 0x20U

#define	OUT_TYPE_GPIO9_9_GPIO_B_POS 5U

#define	PULL_UPDN_SEL_GPIO9_9_GPIO_B_ADDR 0x2DAU

#define	PULL_UPDN_SEL_GPIO9_9_GPIO_B_MASK 0xC0U

#define	PULL_UPDN_SEL_GPIO9_9_GPIO_B_POS 6U

#define	GPIO9_9_GPIO_C_ADDR 0x2DBU

#define	GPIO9_9_GPIO_C_DEFAULT 0x49U

#define	GPIO_RX_ID_GPIO9_9_GPIO_C_ADDR 0x2DBU

#define	GPIO_RX_ID_GPIO9_9_GPIO_C_MASK 0x1FU

#define	GPIO_RX_ID_GPIO9_9_GPIO_C_POS 0U

#define	OVR_RES_CFG_GPIO9_9_GPIO_C_ADDR 0x2DBU

#define	OVR_RES_CFG_GPIO9_9_GPIO_C_MASK 0x80U

#define	OVR_RES_CFG_GPIO9_9_GPIO_C_POS 7U

#define	GPIO10_10_GPIO_A_ADDR 0x2DCU

#define	GPIO10_10_GPIO_A_DEFAULT 0x99U

#define	GPIO_OUT_DIS_GPIO10_10_GPIO_A_ADDR 0x2DCU

#define	GPIO_OUT_DIS_GPIO10_10_GPIO_A_MASK 0x01U

#define	GPIO_OUT_DIS_GPIO10_10_GPIO_A_POS 0U

#define	GPIO_TX_EN_GPIO10_10_GPIO_A_ADDR 0x2DCU

#define	GPIO_TX_EN_GPIO10_10_GPIO_A_MASK 0x02U

#define	GPIO_TX_EN_GPIO10_10_GPIO_A_POS 1U

#define	GPIO_RX_EN_GPIO10_10_GPIO_A_ADDR 0x2DCU

#define	GPIO_RX_EN_GPIO10_10_GPIO_A_MASK 0x04U

#define	GPIO_RX_EN_GPIO10_10_GPIO_A_POS 2U

#define	GPIO_IN_GPIO10_10_GPIO_A_ADDR 0x2DCU

#define	GPIO_IN_GPIO10_10_GPIO_A_MASK 0x08U

#define	GPIO_IN_GPIO10_10_GPIO_A_POS 3U

#define	GPIO_OUT_GPIO10_10_GPIO_A_ADDR 0x2DCU

#define	GPIO_OUT_GPIO10_10_GPIO_A_MASK 0x10U

#define	GPIO_OUT_GPIO10_10_GPIO_A_POS 4U

#define	TX_COMP_EN_GPIO10_10_GPIO_A_ADDR 0x2DCU

#define	TX_COMP_EN_GPIO10_10_GPIO_A_MASK 0x20U

#define	TX_COMP_EN_GPIO10_10_GPIO_A_POS 5U

#define	RES_CFG_GPIO10_10_GPIO_A_ADDR 0x2DCU

#define	RES_CFG_GPIO10_10_GPIO_A_MASK 0x80U

#define	RES_CFG_GPIO10_10_GPIO_A_POS 7U

#define	GPIO10_10_GPIO_B_ADDR 0x2DDU

#define	GPIO10_10_GPIO_B_DEFAULT 0x2AU

#define	GPIO_TX_ID_GPIO10_10_GPIO_B_ADDR 0x2DDU

#define	GPIO_TX_ID_GPIO10_10_GPIO_B_MASK 0x1FU

#define	GPIO_TX_ID_GPIO10_10_GPIO_B_POS 0U

#define	OUT_TYPE_GPIO10_10_GPIO_B_ADDR 0x2DDU

#define	OUT_TYPE_GPIO10_10_GPIO_B_MASK 0x20U

#define	OUT_TYPE_GPIO10_10_GPIO_B_POS 5U

#define	PULL_UPDN_SEL_GPIO10_10_GPIO_B_ADDR 0x2DDU

#define	PULL_UPDN_SEL_GPIO10_10_GPIO_B_MASK 0xC0U

#define	PULL_UPDN_SEL_GPIO10_10_GPIO_B_POS 6U

#define	GPIO10_10_GPIO_C_ADDR 0x2DEU

#define	GPIO10_10_GPIO_C_DEFAULT 0x4AU

#define	GPIO_RX_ID_GPIO10_10_GPIO_C_ADDR 0x2DEU

#define	GPIO_RX_ID_GPIO10_10_GPIO_C_MASK 0x1FU

#define	GPIO_RX_ID_GPIO10_10_GPIO_C_POS 0U

#define	OVR_RES_CFG_GPIO10_10_GPIO_C_ADDR 0x2DEU

#define	OVR_RES_CFG_GPIO10_10_GPIO_C_MASK 0x80U

#define	OVR_RES_CFG_GPIO10_10_GPIO_C_POS 7U

#define	CMU_CMU2_ADDR 0x302U

#define	CMU_CMU2_DEFAULT 0x00U

#define	PFDDIV_RSHORT_CMU_CMU2_ADDR 0x302U

#define	PFDDIV_RSHORT_CMU_CMU2_MASK 0x70U

#define	PFDDIV_RSHORT_CMU_CMU2_POS 4U

#define	FRONTTOP_FRONTTOP_0_ADDR 0x308U

#define	FRONTTOP_FRONTTOP_0_DEFAULT 0x64U

#define	START_PORTB_FRONTTOP_FRONTTOP_0_ADDR 0x308U

#define	START_PORTB_FRONTTOP_FRONTTOP_0_MASK 0x20U

#define	START_PORTB_FRONTTOP_FRONTTOP_0_POS 5U

#define	ENABLE_LINE_INFO_FRONTTOP_FRONTTOP_0_ADDR 0x308U

#define	ENABLE_LINE_INFO_FRONTTOP_FRONTTOP_0_MASK 0x40U

#define	ENABLE_LINE_INFO_FRONTTOP_FRONTTOP_0_POS 6U

#define	FRONTTOP_FRONTTOP_5_ADDR 0x30DU

#define	FRONTTOP_FRONTTOP_5_DEFAULT 0xFFU

#define	VC_SELZ_L_FRONTTOP_FRONTTOP_5_ADDR 0x30DU

#define	VC_SELZ_L_FRONTTOP_FRONTTOP_5_MASK 0xFFU

#define	VC_SELZ_L_FRONTTOP_FRONTTOP_5_POS 0U

#define	FRONTTOP_FRONTTOP_6_ADDR 0x30EU

#define	FRONTTOP_FRONTTOP_6_DEFAULT 0xFFU

#define	VC_SELZ_H_FRONTTOP_FRONTTOP_6_ADDR 0x30EU

#define	VC_SELZ_H_FRONTTOP_FRONTTOP_6_MASK 0xFFU

#define	VC_SELZ_H_FRONTTOP_FRONTTOP_6_POS 0U

#define	FRONTTOP_FRONTTOP_9_ADDR 0x311U

#define	FRONTTOP_FRONTTOP_9_DEFAULT 0x40U

#define	START_PORTBZ_FRONTTOP_FRONTTOP_9_ADDR 0x311U

#define	START_PORTBZ_FRONTTOP_FRONTTOP_9_MASK 0x40U

#define	START_PORTBZ_FRONTTOP_FRONTTOP_9_POS 6U

#define	FRONTTOP_FRONTTOP_10_ADDR 0x312U

#define	FRONTTOP_FRONTTOP_10_DEFAULT 0x00U

#define	BPP8DBLZ_FRONTTOP_FRONTTOP_10_ADDR 0x312U

#define	BPP8DBLZ_FRONTTOP_FRONTTOP_10_MASK 0x04U

#define	BPP8DBLZ_FRONTTOP_FRONTTOP_10_POS 2U

#define	FRONTTOP_FRONTTOP_11_ADDR 0x313U

#define	FRONTTOP_FRONTTOP_11_DEFAULT 0x00U

#define	BPP10DBLZ_FRONTTOP_FRONTTOP_11_ADDR 0x313U

#define	BPP10DBLZ_FRONTTOP_FRONTTOP_11_MASK 0x04U

#define	BPP10DBLZ_FRONTTOP_FRONTTOP_11_POS 2U

#define	BPP12DBLZ_FRONTTOP_FRONTTOP_11_ADDR 0x313U

#define	BPP12DBLZ_FRONTTOP_FRONTTOP_11_MASK 0x40U

#define	BPP12DBLZ_FRONTTOP_FRONTTOP_11_POS 6U

#define	FRONTTOP_FRONTTOP_16_ADDR 0x318U

#define	FRONTTOP_FRONTTOP_16_DEFAULT 0x00U

#define	MEM_DT1_SELZ_FRONTTOP_FRONTTOP_16_ADDR 0x318U

#define	MEM_DT1_SELZ_FRONTTOP_FRONTTOP_16_MASK 0x7FU

#define	MEM_DT1_SELZ_FRONTTOP_FRONTTOP_16_POS 0U

#define	FRONTTOP_FRONTTOP_17_ADDR 0x319U

#define	FRONTTOP_FRONTTOP_17_DEFAULT 0x00U

#define	MEM_DT2_SELZ_FRONTTOP_FRONTTOP_17_ADDR 0x319U

#define	MEM_DT2_SELZ_FRONTTOP_FRONTTOP_17_MASK 0x7FU

#define	MEM_DT2_SELZ_FRONTTOP_FRONTTOP_17_POS 0U

#define	FRONTTOP_FRONTTOP_22_ADDR 0x31EU

#define	FRONTTOP_FRONTTOP_22_DEFAULT 0x18U

#define	SOFT_BPPZ_FRONTTOP_FRONTTOP_22_ADDR 0x31EU

#define	SOFT_BPPZ_FRONTTOP_FRONTTOP_22_MASK 0x1FU

#define	SOFT_BPPZ_FRONTTOP_FRONTTOP_22_POS 0U

#define	SOFT_BPPZ_EN_FRONTTOP_FRONTTOP_22_ADDR 0x31EU

#define	SOFT_BPPZ_EN_FRONTTOP_FRONTTOP_22_MASK 0x20U

#define	SOFT_BPPZ_EN_FRONTTOP_FRONTTOP_22_POS 5U

#define	SOFT_VCZ_EN_FRONTTOP_FRONTTOP_22_ADDR 0x31EU

#define	SOFT_VCZ_EN_FRONTTOP_FRONTTOP_22_MASK 0x40U

#define	SOFT_VCZ_EN_FRONTTOP_FRONTTOP_22_POS 6U

#define	SOFT_DTZ_EN_FRONTTOP_FRONTTOP_22_ADDR 0x31EU

#define	SOFT_DTZ_EN_FRONTTOP_FRONTTOP_22_MASK 0x80U

#define	SOFT_DTZ_EN_FRONTTOP_FRONTTOP_22_POS 7U

#define	FRONTTOP_FRONTTOP_24_ADDR 0x320U

#define	FRONTTOP_FRONTTOP_24_DEFAULT 0x00U

#define	SOFT_VCZ_FRONTTOP_FRONTTOP_24_ADDR 0x320U

#define	SOFT_VCZ_FRONTTOP_FRONTTOP_24_MASK 0x30U

#define	SOFT_VCZ_FRONTTOP_FRONTTOP_24_POS 4U

#define	FRONTTOP_FRONTTOP_27_ADDR 0x323U

#define	FRONTTOP_FRONTTOP_27_DEFAULT 0x30U

#define	SOFT_DTZ_FRONTTOP_FRONTTOP_27_ADDR 0x323U

#define	SOFT_DTZ_FRONTTOP_FRONTTOP_27_MASK 0x3FU

#define	SOFT_DTZ_FRONTTOP_FRONTTOP_27_POS 0U

#define	FRONTTOP_FRONTTOP_29_ADDR 0x325U

#define	FRONTTOP_FRONTTOP_29_DEFAULT 0x00U

#define	FORCE_START_MIPI_FRONTTOP_FRONTTOP_FRONTTOP_29_ADDR 0x325U

#define	FORCE_START_MIPI_FRONTTOP_FRONTTOP_FRONTTOP_29_MASK 0x80U

#define	FORCE_START_MIPI_FRONTTOP_FRONTTOP_FRONTTOP_29_POS 7U

#define	MIPI_RX_MIPI_RX0_ADDR 0x330U

#define	MIPI_RX_MIPI_RX0_DEFAULT 0x00U

#define	MIPI_RX_RESET_MIPI_RX_MIPI_RX0_ADDR 0x330U

#define	MIPI_RX_RESET_MIPI_RX_MIPI_RX0_MASK 0x08U

#define	MIPI_RX_RESET_MIPI_RX_MIPI_RX0_POS 3U

#define	CTRL1_VC_MAP_EN_MIPI_RX_MIPI_RX0_ADDR 0x330U

#define	CTRL1_VC_MAP_EN_MIPI_RX_MIPI_RX0_MASK 0x20U

#define	CTRL1_VC_MAP_EN_MIPI_RX_MIPI_RX0_POS 5U

#define	MIPI_NONCONTCLK_EN_MIPI_RX_MIPI_RX0_ADDR 0x330U

#define	MIPI_NONCONTCLK_EN_MIPI_RX_MIPI_RX0_MASK 0x40U

#define	MIPI_NONCONTCLK_EN_MIPI_RX_MIPI_RX0_POS 6U

#define	MIPI_RX_MIPI_RX1_ADDR 0x331U

#define	MIPI_RX_MIPI_RX1_DEFAULT 0x30U

#define	CTRL1_NUM_LANES_MIPI_RX_MIPI_RX1_ADDR 0x331U

#define	CTRL1_NUM_LANES_MIPI_RX_MIPI_RX1_MASK 0x30U

#define	CTRL1_NUM_LANES_MIPI_RX_MIPI_RX1_POS 4U

#define	CTRL1_DESKEWEN_MIPI_RX_MIPI_RX1_ADDR 0x331U

#define	CTRL1_DESKEWEN_MIPI_RX_MIPI_RX1_MASK 0x40U

#define	CTRL1_DESKEWEN_MIPI_RX_MIPI_RX1_POS 6U

#define	CTRL1_VCX_EN_MIPI_RX_MIPI_RX1_ADDR 0x331U

#define	CTRL1_VCX_EN_MIPI_RX_MIPI_RX1_MASK 0x80U

#define	CTRL1_VCX_EN_MIPI_RX_MIPI_RX1_POS 7U

#define	MIPI_RX_MIPI_RX2_ADDR 0x332U

#define	MIPI_RX_MIPI_RX2_DEFAULT 0xE0U

#define	PHY1_LANE_MAP_MIPI_RX_MIPI_RX2_ADDR 0x332U

#define	PHY1_LANE_MAP_MIPI_RX_MIPI_RX2_MASK 0xF0U

#define	PHY1_LANE_MAP_MIPI_RX_MIPI_RX2_POS 4U

#define	MIPI_RX_MIPI_RX3_ADDR 0x333U

#define	MIPI_RX_MIPI_RX3_DEFAULT 0x04U

#define	PHY2_LANE_MAP_MIPI_RX_MIPI_RX3_ADDR 0x333U

#define	PHY2_LANE_MAP_MIPI_RX_MIPI_RX3_MASK 0x0FU

#define	PHY2_LANE_MAP_MIPI_RX_MIPI_RX3_POS 0U

#define	MIPI_RX_MIPI_RX4_ADDR 0x334U

#define	MIPI_RX_MIPI_RX4_DEFAULT 0x00U

#define	PHY1_POL_MAP_MIPI_RX_MIPI_RX4_ADDR 0x334U

#define	PHY1_POL_MAP_MIPI_RX_MIPI_RX4_MASK 0x70U

#define	PHY1_POL_MAP_MIPI_RX_MIPI_RX4_POS 4U

#define	MIPI_RX_MIPI_RX5_ADDR 0x335U

#define	MIPI_RX_MIPI_RX5_DEFAULT 0x00U

#define	PHY2_POL_MAP_MIPI_RX_MIPI_RX5_ADDR 0x335U

#define	PHY2_POL_MAP_MIPI_RX_MIPI_RX5_MASK 0x07U

#define	PHY2_POL_MAP_MIPI_RX_MIPI_RX5_POS 0U

#define	MIPI_RX_MIPI_RX7_ADDR 0x337U

#define	MIPI_RX_MIPI_RX7_DEFAULT 0x00U

#define	MIPI_RX_MIPI_RX8_ADDR 0x338U

#define	MIPI_RX_MIPI_RX8_DEFAULT 0x55U

#define	T_CLK_SETTLE_MIPI_RX_MIPI_RX8_ADDR 0x338U

#define	T_CLK_SETTLE_MIPI_RX_MIPI_RX8_MASK 0x03U

#define	T_CLK_SETTLE_MIPI_RX_MIPI_RX8_POS 0U

#define	T_HS_SETTLE_MIPI_RX_MIPI_RX8_ADDR 0x338U

#define	T_HS_SETTLE_MIPI_RX_MIPI_RX8_MASK 0x30U

#define	T_HS_SETTLE_MIPI_RX_MIPI_RX8_POS 4U

#define	T_HS_DEC_EN_MIPI_RX_MIPI_RX8_ADDR 0x338U

#define	T_HS_DEC_EN_MIPI_RX_MIPI_RX8_MASK 0xC0U

#define	T_HS_DEC_EN_MIPI_RX_MIPI_RX8_POS 6U

#define	MIPI_RX_MIPI_RX11_ADDR 0x33BU

#define	MIPI_RX_MIPI_RX11_DEFAULT 0x00U

#define	PHY1_LP_ERR_MIPI_RX_MIPI_RX11_ADDR 0x33BU

#define	PHY1_LP_ERR_MIPI_RX_MIPI_RX11_MASK 0x1FU

#define	PHY1_LP_ERR_MIPI_RX_MIPI_RX11_POS 0U

#define	MIPI_RX_MIPI_RX12_ADDR 0x33CU

#define	MIPI_RX_MIPI_RX12_DEFAULT 0x00U

#define	PHY1_HS_ERR_MIPI_RX_MIPI_RX12_ADDR 0x33CU

#define	PHY1_HS_ERR_MIPI_RX_MIPI_RX12_MASK 0xFFU

#define	PHY1_HS_ERR_MIPI_RX_MIPI_RX12_POS 0U

#define	MIPI_RX_MIPI_RX13_ADDR 0x33DU

#define	MIPI_RX_MIPI_RX13_DEFAULT 0x00U

#define	PHY2_LP_ERR_MIPI_RX_MIPI_RX13_ADDR 0x33DU

#define	PHY2_LP_ERR_MIPI_RX_MIPI_RX13_MASK 0x1FU

#define	PHY2_LP_ERR_MIPI_RX_MIPI_RX13_POS 0U

#define	MIPI_RX_MIPI_RX14_ADDR 0x33EU

#define	MIPI_RX_MIPI_RX14_DEFAULT 0x00U

#define	PHY2_HS_ERR_MIPI_RX_MIPI_RX14_ADDR 0x33EU

#define	PHY2_HS_ERR_MIPI_RX_MIPI_RX14_MASK 0xFFU

#define	PHY2_HS_ERR_MIPI_RX_MIPI_RX14_POS 0U

#define	MIPI_RX_MIPI_RX19_ADDR 0x343U

#define	MIPI_RX_MIPI_RX19_DEFAULT 0x00U

#define	CTRL1_CSI_ERR_L_MIPI_RX_MIPI_RX19_ADDR 0x343U

#define	CTRL1_CSI_ERR_L_MIPI_RX_MIPI_RX19_MASK 0xFFU

#define	CTRL1_CSI_ERR_L_MIPI_RX_MIPI_RX19_POS 0U

#define	MIPI_RX_MIPI_RX20_ADDR 0x344U

#define	MIPI_RX_MIPI_RX20_DEFAULT 0x00U

#define	CTRL1_CSI_ERR_H_MIPI_RX_MIPI_RX20_ADDR 0x344U

#define	CTRL1_CSI_ERR_H_MIPI_RX_MIPI_RX20_MASK 0x07U

#define	CTRL1_CSI_ERR_H_MIPI_RX_MIPI_RX20_POS 0U

#define	MIPI_RX_MIPI_RX21_ADDR 0x345U

#define	MIPI_RX_MIPI_RX21_DEFAULT 0x00U

#define	CTRL1_VC_MAP0_MIPI_RX_MIPI_RX21_ADDR 0x345U

#define	CTRL1_VC_MAP0_MIPI_RX_MIPI_RX21_MASK 0xF0U

#define	CTRL1_VC_MAP0_MIPI_RX_MIPI_RX21_POS 4U

#define	MIPI_RX_MIPI_RX22_ADDR 0x346U

#define	MIPI_RX_MIPI_RX22_DEFAULT 0x00U

#define	CTRL1_VC_MAP1_MIPI_RX_MIPI_RX22_ADDR 0x346U

#define	CTRL1_VC_MAP1_MIPI_RX_MIPI_RX22_MASK 0xF0U

#define	CTRL1_VC_MAP1_MIPI_RX_MIPI_RX22_POS 4U

#define	MIPI_RX_MIPI_RX23_ADDR 0x347U

#define	MIPI_RX_MIPI_RX23_DEFAULT 0x00U

#define	CTRL1_VC_MAP2_MIPI_RX_MIPI_RX23_ADDR 0x347U

#define	CTRL1_VC_MAP2_MIPI_RX_MIPI_RX23_MASK 0xF0U

#define	CTRL1_VC_MAP2_MIPI_RX_MIPI_RX23_POS 4U

#define	MIPI_RX_MIPI_RX60_ADDR 0x36CU

#define	MIPI_RX_MIPI_RX60_DEFAULT 0x00U

#define	CTRL1_VC_MAP3_MIPI_RX_MIPI_RX60_ADDR 0x36CU

#define	CTRL1_VC_MAP3_MIPI_RX_MIPI_RX60_MASK 0xF0U

#define	CTRL1_VC_MAP3_MIPI_RX_MIPI_RX60_POS 4U

#define	MIPI_RX_MIPI_RX61_ADDR 0x36DU

#define	MIPI_RX_MIPI_RX61_DEFAULT 0x00U

#define	CTRL1_VC_MAP4_MIPI_RX_MIPI_RX61_ADDR 0x36DU

#define	CTRL1_VC_MAP4_MIPI_RX_MIPI_RX61_MASK 0xF0U

#define	CTRL1_VC_MAP4_MIPI_RX_MIPI_RX61_POS 4U

#define	MIPI_RX_MIPI_RX62_ADDR 0x36EU

#define	MIPI_RX_MIPI_RX62_DEFAULT 0x00U

#define	CTRL1_VC_MAP5_MIPI_RX_MIPI_RX62_ADDR 0x36EU

#define	CTRL1_VC_MAP5_MIPI_RX_MIPI_RX62_MASK 0xF0U

#define	CTRL1_VC_MAP5_MIPI_RX_MIPI_RX62_POS 4U

#define	MIPI_RX_MIPI_RX63_ADDR 0x36FU

#define	MIPI_RX_MIPI_RX63_DEFAULT 0x00U

#define	CTRL1_VC_MAP6_MIPI_RX_MIPI_RX63_ADDR 0x36FU

#define	CTRL1_VC_MAP6_MIPI_RX_MIPI_RX63_MASK 0xF0U

#define	CTRL1_VC_MAP6_MIPI_RX_MIPI_RX63_POS 4U

#define	MIPI_RX_EXT_EXT00_ADDR 0x377U

#define	MIPI_RX_EXT_EXT00_DEFAULT 0x00U

#define	CTRL1_VC_MAP7_MIPI_RX_EXT_EXT00_ADDR 0x377U

#define	CTRL1_VC_MAP7_MIPI_RX_EXT_EXT00_MASK 0xF0U

#define	CTRL1_VC_MAP7_MIPI_RX_EXT_EXT00_POS 4U

#define	MIPI_RX_EXT_EXT0_ADDR 0x378U

#define	MIPI_RX_EXT_EXT0_DEFAULT 0x00U

#define	CTRL1_VC_MAP8_MIPI_RX_EXT_EXT0_ADDR 0x378U

#define	CTRL1_VC_MAP8_MIPI_RX_EXT_EXT0_MASK 0xF0U

#define	CTRL1_VC_MAP8_MIPI_RX_EXT_EXT0_POS 4U

#define	MIPI_RX_EXT_EXT1_ADDR 0x379U

#define	MIPI_RX_EXT_EXT1_DEFAULT 0x00U

#define	CTRL1_VC_MAP9_MIPI_RX_EXT_EXT1_ADDR 0x379U

#define	CTRL1_VC_MAP9_MIPI_RX_EXT_EXT1_MASK 0xF0U

#define	CTRL1_VC_MAP9_MIPI_RX_EXT_EXT1_POS 4U

#define	MIPI_RX_EXT_EXT2_ADDR 0x37AU

#define	MIPI_RX_EXT_EXT2_DEFAULT 0x00U

#define	CTRL1_VC_MAP10_MIPI_RX_EXT_EXT2_ADDR 0x37AU

#define	CTRL1_VC_MAP10_MIPI_RX_EXT_EXT2_MASK 0xF0U

#define	CTRL1_VC_MAP10_MIPI_RX_EXT_EXT2_POS 4U

#define	MIPI_RX_EXT_EXT3_ADDR 0x37BU

#define	MIPI_RX_EXT_EXT3_DEFAULT 0x00U

#define	CTRL1_VC_MAP11_MIPI_RX_EXT_EXT3_ADDR 0x37BU

#define	CTRL1_VC_MAP11_MIPI_RX_EXT_EXT3_MASK 0xF0U

#define	CTRL1_VC_MAP11_MIPI_RX_EXT_EXT3_POS 4U

#define	MIPI_RX_EXT_EXT4_ADDR 0x37CU

#define	MIPI_RX_EXT_EXT4_DEFAULT 0x00U

#define	CTRL1_VC_MAP12_MIPI_RX_EXT_EXT4_ADDR 0x37CU

#define	CTRL1_VC_MAP12_MIPI_RX_EXT_EXT4_MASK 0xF0U

#define	CTRL1_VC_MAP12_MIPI_RX_EXT_EXT4_POS 4U

#define	MIPI_RX_EXT_EXT5_ADDR 0x37DU

#define	MIPI_RX_EXT_EXT5_DEFAULT 0x00U

#define	CTRL1_VC_MAP13_MIPI_RX_EXT_EXT5_ADDR 0x37DU

#define	CTRL1_VC_MAP13_MIPI_RX_EXT_EXT5_MASK 0xF0U

#define	CTRL1_VC_MAP13_MIPI_RX_EXT_EXT5_POS 4U

#define	MIPI_RX_EXT_EXT6_ADDR 0x37EU

#define	MIPI_RX_EXT_EXT6_DEFAULT 0x00U

#define	CTRL1_VC_MAP14_MIPI_RX_EXT_EXT6_ADDR 0x37EU

#define	CTRL1_VC_MAP14_MIPI_RX_EXT_EXT6_MASK 0xF0U

#define	CTRL1_VC_MAP14_MIPI_RX_EXT_EXT6_POS 4U

#define	MIPI_RX_EXT_EXT7_ADDR 0x37FU

#define	MIPI_RX_EXT_EXT7_DEFAULT 0x00U

#define	CTRL1_VC_MAP15_MIPI_RX_EXT_EXT7_ADDR 0x37FU

#define	CTRL1_VC_MAP15_MIPI_RX_EXT_EXT7_MASK 0xF0U

#define	CTRL1_VC_MAP15_MIPI_RX_EXT_EXT7_POS 4U

#define	MIPI_RX_EXT_EXT8_ADDR 0x380U

#define	MIPI_RX_EXT_EXT8_DEFAULT 0x00U

#define	TUN_FIFO_OVERFLOW_MIPI_RX_EXT_EXT8_ADDR 0x380U

#define	TUN_FIFO_OVERFLOW_MIPI_RX_EXT_EXT8_MASK 0x01U

#define	TUN_FIFO_OVERFLOW_MIPI_RX_EXT_EXT8_POS 0U

#define	INVCODE_LN0_MIPI_RX_EXT_EXT8_ADDR 0x380U

#define	INVCODE_LN0_MIPI_RX_EXT_EXT8_MASK 0x02U

#define	INVCODE_LN0_MIPI_RX_EXT_EXT8_POS 1U

#define	INVCODE_LN1_MIPI_RX_EXT_EXT8_ADDR 0x380U

#define	INVCODE_LN1_MIPI_RX_EXT_EXT8_MASK 0x04U

#define	INVCODE_LN1_MIPI_RX_EXT_EXT8_POS 2U

#define	CPHY_HDR2_ERR_MIPI_RX_EXT_EXT8_ADDR 0x380U

#define	CPHY_HDR2_ERR_MIPI_RX_EXT_EXT8_MASK 0x18U

#define	CPHY_HDR2_ERR_MIPI_RX_EXT_EXT8_POS 3U

#define	CPHY_HDR1_ERR_MIPI_RX_EXT_EXT8_ADDR 0x380U

#define	CPHY_HDR1_ERR_MIPI_RX_EXT_EXT8_MASK 0x60U

#define	CPHY_HDR1_ERR_MIPI_RX_EXT_EXT8_POS 5U

#define	CPHY_HDR_ERR_MIPI_RX_EXT_EXT8_ADDR 0x380U

#define	CPHY_HDR_ERR_MIPI_RX_EXT_EXT8_MASK 0x80U

#define	CPHY_HDR_ERR_MIPI_RX_EXT_EXT8_POS 7U

#define	MIPI_RX_EXT_EXT9_ADDR 0x381U

#define	MIPI_RX_EXT_EXT9_DEFAULT 0x00U

#define	MIPI_RX_EXT_EXT11_ADDR 0x383U

#define	MIPI_RX_EXT_EXT11_DEFAULT 0x80U

#define	PHY1_CPHYCDRMASK_MIPI_RX_EXT_EXT11_ADDR 0x383U

#define	PHY1_CPHYCDRMASK_MIPI_RX_EXT_EXT11_MASK 0x03U

#define	PHY1_CPHYCDRMASK_MIPI_RX_EXT_EXT11_POS 0U

#define	CPHY_MODE_MIPI_RX_EXT_EXT11_ADDR 0x383U

#define	CPHY_MODE_MIPI_RX_EXT_EXT11_MASK 0x40U

#define	CPHY_MODE_MIPI_RX_EXT_EXT11_POS 6U

#define	TUN_MODE_MIPI_RX_EXT_EXT11_ADDR 0x383U

#define	TUN_MODE_MIPI_RX_EXT_EXT11_MASK 0x80U

#define	TUN_MODE_MIPI_RX_EXT_EXT11_POS 7U

#define	MIPI_RX_EXT_EXT21_ADDR 0x38DU

#define	MIPI_RX_EXT_EXT21_DEFAULT 0x00U

#define	PHY1_PKT_CNT_MIPI_RX_EXT_EXT21_ADDR 0x38DU

#define	PHY1_PKT_CNT_MIPI_RX_EXT_EXT21_MASK 0xFFU

#define	PHY1_PKT_CNT_MIPI_RX_EXT_EXT21_POS 0U

#define	MIPI_RX_EXT_EXT22_ADDR 0x38EU

#define	MIPI_RX_EXT_EXT22_DEFAULT 0x00U

#define	CSI1_PKT_CNT_MIPI_RX_EXT_EXT22_ADDR 0x38EU

#define	CSI1_PKT_CNT_MIPI_RX_EXT_EXT22_MASK 0xFFU

#define	CSI1_PKT_CNT_MIPI_RX_EXT_EXT22_POS 0U

#define	MIPI_RX_EXT_EXT23_ADDR 0x38FU

#define	MIPI_RX_EXT_EXT23_DEFAULT 0x00U

#define	TUN_PKT_CNT_MIPI_RX_EXT_EXT23_ADDR 0x38FU

#define	TUN_PKT_CNT_MIPI_RX_EXT_EXT23_MASK 0xFFU

#define	TUN_PKT_CNT_MIPI_RX_EXT_EXT23_POS 0U

#define	MIPI_RX_EXT_EXT24_ADDR 0x390U

#define	MIPI_RX_EXT_EXT24_DEFAULT 0x00U

#define	PHY_CLK_CNT_MIPI_RX_EXT_EXT24_ADDR 0x390U

#define	PHY_CLK_CNT_MIPI_RX_EXT_EXT24_MASK 0xFFU

#define	PHY_CLK_CNT_MIPI_RX_EXT_EXT24_POS 0U

#define	FRONTTOP_EXT_FRONTTOP_EXT8_ADDR 0x3C8U

#define	FRONTTOP_EXT_FRONTTOP_EXT8_DEFAULT 0x00U

#define	MEM_DT3_SELZ_FRONTTOP_EXT_FRONTTOP_EXT8_ADDR 0x3C8U

#define	MEM_DT3_SELZ_FRONTTOP_EXT_FRONTTOP_EXT8_MASK 0xFFU

#define	MEM_DT3_SELZ_FRONTTOP_EXT_FRONTTOP_EXT8_POS 0U

#define	FRONTTOP_EXT_FRONTTOP_EXT9_ADDR 0x3C9U

#define	FRONTTOP_EXT_FRONTTOP_EXT9_DEFAULT 0x00U

#define	MEM_DT4_SELZ_FRONTTOP_EXT_FRONTTOP_EXT9_ADDR 0x3C9U

#define	MEM_DT4_SELZ_FRONTTOP_EXT_FRONTTOP_EXT9_MASK 0xFFU

#define	MEM_DT4_SELZ_FRONTTOP_EXT_FRONTTOP_EXT9_POS 0U

#define	FRONTTOP_EXT_FRONTTOP_EXT10_ADDR 0x3CAU

#define	FRONTTOP_EXT_FRONTTOP_EXT10_DEFAULT 0x00U

#define	MEM_DT5_SELZ_FRONTTOP_EXT_FRONTTOP_EXT10_ADDR 0x3CAU

#define	MEM_DT5_SELZ_FRONTTOP_EXT_FRONTTOP_EXT10_MASK 0xFFU

#define	MEM_DT5_SELZ_FRONTTOP_EXT_FRONTTOP_EXT10_POS 0U

#define	FRONTTOP_EXT_FRONTTOP_EXT11_ADDR 0x3CBU

#define	FRONTTOP_EXT_FRONTTOP_EXT11_DEFAULT 0x00U

#define	MEM_DT6_SELZ_FRONTTOP_EXT_FRONTTOP_EXT11_ADDR 0x3CBU

#define	MEM_DT6_SELZ_FRONTTOP_EXT_FRONTTOP_EXT11_MASK 0xFFU

#define	MEM_DT6_SELZ_FRONTTOP_EXT_FRONTTOP_EXT11_POS 0U

#define	FRONTTOP_EXT_FRONTTOP_EXT17_ADDR 0x3D1U

#define	FRONTTOP_EXT_FRONTTOP_EXT17_DEFAULT 0x00U

#define	MEM_DT3_SELZ_EN_FRONTTOP_EXT_FRONTTOP_EXT17_ADDR 0x3D1U

#define	MEM_DT3_SELZ_EN_FRONTTOP_EXT_FRONTTOP_EXT17_MASK 0x01U

#define	MEM_DT3_SELZ_EN_FRONTTOP_EXT_FRONTTOP_EXT17_POS 0U

#define	MEM_DT4_SELZ_EN_FRONTTOP_EXT_FRONTTOP_EXT17_ADDR 0x3D1U

#define	MEM_DT4_SELZ_EN_FRONTTOP_EXT_FRONTTOP_EXT17_MASK 0x02U

#define	MEM_DT4_SELZ_EN_FRONTTOP_EXT_FRONTTOP_EXT17_POS 1U

#define	MEM_DT5_SELZ_EN_FRONTTOP_EXT_FRONTTOP_EXT17_ADDR 0x3D1U

#define	MEM_DT5_SELZ_EN_FRONTTOP_EXT_FRONTTOP_EXT17_MASK 0x04U

#define	MEM_DT5_SELZ_EN_FRONTTOP_EXT_FRONTTOP_EXT17_POS 2U

#define	MEM_DT6_SELZ_EN_FRONTTOP_EXT_FRONTTOP_EXT17_ADDR 0x3D1U

#define	MEM_DT6_SELZ_EN_FRONTTOP_EXT_FRONTTOP_EXT17_MASK 0x08U

#define	MEM_DT6_SELZ_EN_FRONTTOP_EXT_FRONTTOP_EXT17_POS 3U

#define	MIPI_RX_EXT2_EXTA_ADDR 0x3DCU

#define	MIPI_RX_EXT2_EXTA_DEFAULT 0x00U

#define	MEM_DT7_SELZ_MIPI_RX_EXT2_EXTA_ADDR 0x3DCU

#define	MEM_DT7_SELZ_MIPI_RX_EXT2_EXTA_MASK 0x7FU

#define	MEM_DT7_SELZ_MIPI_RX_EXT2_EXTA_POS 0U

#define	MIPI_RX_EXT2_EXTB_ADDR 0x3DDU

#define	MIPI_RX_EXT2_EXTB_DEFAULT 0x00U

#define	MEM_DT8_SELZ_MIPI_RX_EXT2_EXTB_ADDR 0x3DDU

#define	MEM_DT8_SELZ_MIPI_RX_EXT2_EXTB_MASK 0x7FU

#define	MEM_DT8_SELZ_MIPI_RX_EXT2_EXTB_POS 0U

#define	REF_VTG_VTX0_ADDR 0x3E0U

#define	REF_VTG_VTX0_DEFAULT 0x70U

#define	GEN_VS_REF_VTG_VTX0_ADDR 0x3E0U

#define	GEN_VS_REF_VTG_VTX0_MASK 0x01U

#define	GEN_VS_REF_VTG_VTX0_POS 0U

#define	VS_INV_REF_VTG_VTX0_ADDR 0x3E0U

#define	VS_INV_REF_VTG_VTX0_MASK 0x02U

#define	VS_INV_REF_VTG_VTX0_POS 1U

#define	GEN_HS_REF_VTG_VTX0_ADDR 0x3E0U

#define	GEN_HS_REF_VTG_VTX0_MASK 0x04U

#define	GEN_HS_REF_VTG_VTX0_POS 2U

#define	HS_INV_REF_VTG_VTX0_ADDR 0x3E0U

#define	HS_INV_REF_VTG_VTX0_MASK 0x08U

#define	HS_INV_REF_VTG_VTX0_POS 3U

#define	REF_VTG_MODE_REF_VTG_VTX0_ADDR 0x3E0U

#define	REF_VTG_MODE_REF_VTG_VTX0_MASK 0x30U

#define	REF_VTG_MODE_REF_VTG_VTX0_POS 4U

#define	VS_TRIG_REF_VTG_VTX0_ADDR 0x3E0U

#define	VS_TRIG_REF_VTG_VTX0_MASK 0x40U

#define	VS_TRIG_REF_VTG_VTX0_POS 6U

#define	REF_VTG_VTX5_ADDR 0x3E1U

#define	REF_VTG_VTX5_DEFAULT 0x00U

#define	VS_HIGH_2_REF_VTG_VTX5_ADDR 0x3E1U

#define	VS_HIGH_2_REF_VTG_VTX5_MASK 0xFFU

#define	VS_HIGH_2_REF_VTG_VTX5_POS 0U

#define	REF_VTG_VTX6_ADDR 0x3E2U

#define	REF_VTG_VTX6_DEFAULT 0x00U

#define	VS_HIGH_1_REF_VTG_VTX6_ADDR 0x3E2U

#define	VS_HIGH_1_REF_VTG_VTX6_MASK 0xFFU

#define	VS_HIGH_1_REF_VTG_VTX6_POS 0U

#define	REF_VTG_VTX7_ADDR 0x3E3U

#define	REF_VTG_VTX7_DEFAULT 0x00U

#define	VS_HIGH_0_REF_VTG_VTX7_ADDR 0x3E3U

#define	VS_HIGH_0_REF_VTG_VTX7_MASK 0xFFU

#define	VS_HIGH_0_REF_VTG_VTX7_POS 0U

#define	REF_VTG_VTX8_ADDR 0x3E4U

#define	REF_VTG_VTX8_DEFAULT 0x00U

#define	VS_LOW_2_REF_VTG_VTX8_ADDR 0x3E4U

#define	VS_LOW_2_REF_VTG_VTX8_MASK 0xFFU

#define	VS_LOW_2_REF_VTG_VTX8_POS 0U

#define	REF_VTG_VTX9_ADDR 0x3E5U

#define	REF_VTG_VTX9_DEFAULT 0x00U

#define	VS_LOW_1_REF_VTG_VTX9_ADDR 0x3E5U

#define	VS_LOW_1_REF_VTG_VTX9_MASK 0xFFU

#define	VS_LOW_1_REF_VTG_VTX9_POS 0U

#define	REF_VTG_VTX10_ADDR 0x3E6U

#define	REF_VTG_VTX10_DEFAULT 0x00U

#define	VS_LOW_0_REF_VTG_VTX10_ADDR 0x3E6U

#define	VS_LOW_0_REF_VTG_VTX10_MASK 0xFFU

#define	VS_LOW_0_REF_VTG_VTX10_POS 0U

#define	REF_VTG_VTX11_ADDR 0x3E7U

#define	REF_VTG_VTX11_DEFAULT 0x00U

#define	V2H_2_REF_VTG_VTX11_ADDR 0x3E7U

#define	V2H_2_REF_VTG_VTX11_MASK 0xFFU

#define	V2H_2_REF_VTG_VTX11_POS 0U

#define	REF_VTG_VTX12_ADDR 0x3E8U

#define	REF_VTG_VTX12_DEFAULT 0x00U

#define	V2H_1_REF_VTG_VTX12_ADDR 0x3E8U

#define	V2H_1_REF_VTG_VTX12_MASK 0xFFU

#define	V2H_1_REF_VTG_VTX12_POS 0U

#define	REF_VTG_VTX13_ADDR 0x3E9U

#define	REF_VTG_VTX13_DEFAULT 0x00U

#define	V2H_0_REF_VTG_VTX13_ADDR 0x3E9U

#define	V2H_0_REF_VTG_VTX13_MASK 0xFFU

#define	V2H_0_REF_VTG_VTX13_POS 0U

#define	REF_VTG_VTX14_ADDR 0x3EAU

#define	REF_VTG_VTX14_DEFAULT 0x00U

#define	HS_HIGH_1_REF_VTG_VTX14_ADDR 0x3EAU

#define	HS_HIGH_1_REF_VTG_VTX14_MASK 0xFFU

#define	HS_HIGH_1_REF_VTG_VTX14_POS 0U

#define	REF_VTG_VTX15_ADDR 0x3EBU

#define	REF_VTG_VTX15_DEFAULT 0x00U

#define	HS_HIGH_0_REF_VTG_VTX15_ADDR 0x3EBU

#define	HS_HIGH_0_REF_VTG_VTX15_MASK 0xFFU

#define	HS_HIGH_0_REF_VTG_VTX15_POS 0U

#define	REF_VTG_VTX16_ADDR 0x3ECU

#define	REF_VTG_VTX16_DEFAULT 0x00U

#define	HS_LOW_1_REF_VTG_VTX16_ADDR 0x3ECU

#define	HS_LOW_1_REF_VTG_VTX16_MASK 0xFFU

#define	HS_LOW_1_REF_VTG_VTX16_POS 0U

#define	REF_VTG_VTX17_ADDR 0x3EDU

#define	REF_VTG_VTX17_DEFAULT 0x00U

#define	HS_LOW_0_REF_VTG_VTX17_ADDR 0x3EDU

#define	HS_LOW_0_REF_VTG_VTX17_MASK 0xFFU

#define	HS_LOW_0_REF_VTG_VTX17_POS 0U

#define	REF_VTG_VTX18_ADDR 0x3EEU

#define	REF_VTG_VTX18_DEFAULT 0x00U

#define	HS_CNT_1_REF_VTG_VTX18_ADDR 0x3EEU

#define	HS_CNT_1_REF_VTG_VTX18_MASK 0xFFU

#define	HS_CNT_1_REF_VTG_VTX18_POS 0U

#define	REF_VTG_VTX19_ADDR 0x3EFU

#define	REF_VTG_VTX19_DEFAULT 0x00U

#define	HS_CNT_0_REF_VTG_VTX19_ADDR 0x3EFU

#define	HS_CNT_0_REF_VTG_VTX19_MASK 0xFFU

#define	HS_CNT_0_REF_VTG_VTX19_POS 0U

#define	REF_VTG_REF_VTG0_ADDR 0x3F0U

#define	REF_VTG_REF_VTG0_DEFAULT 0x50U

#define	REFGEN_EN_REF_VTG_REF_VTG0_ADDR 0x3F0U

#define	REFGEN_EN_REF_VTG_REF_VTG0_MASK 0x01U

#define	REFGEN_EN_REF_VTG_REF_VTG0_POS 0U

#define	REFGEN_RST_REF_VTG_REF_VTG0_ADDR 0x3F0U

#define	REFGEN_RST_REF_VTG_REF_VTG0_MASK 0x02U

#define	REFGEN_RST_REF_VTG_REF_VTG0_POS 1U

#define	REFGEN_PREDEF_FREQ_ALT_REF_VTG_REF_VTG0_ADDR 0x3F0U

#define	REFGEN_PREDEF_FREQ_ALT_REF_VTG_REF_VTG0_MASK 0x08U

#define	REFGEN_PREDEF_FREQ_ALT_REF_VTG_REF_VTG0_POS 3U

#define	REFGEN_PREDEF_FREQ_REF_VTG_REF_VTG0_ADDR 0x3F0U

#define	REFGEN_PREDEF_FREQ_REF_VTG_REF_VTG0_MASK 0x30U

#define	REFGEN_PREDEF_FREQ_REF_VTG_REF_VTG0_POS 4U

#define	REFGEN_PREDEF_EN_REF_VTG_REF_VTG0_ADDR 0x3F0U

#define	REFGEN_PREDEF_EN_REF_VTG_REF_VTG0_MASK 0x40U

#define	REFGEN_PREDEF_EN_REF_VTG_REF_VTG0_POS 6U

#define	REFGEN_LOCKED_REF_VTG_REF_VTG0_ADDR 0x3F0U

#define	REFGEN_LOCKED_REF_VTG_REF_VTG0_MASK 0x80U

#define	REFGEN_LOCKED_REF_VTG_REF_VTG0_POS 7U

#define	REF_VTG_REF_VTG1_ADDR 0x3F1U

#define	REF_VTG_REF_VTG1_DEFAULT 0x00U

#define	PCLKEN_REF_VTG_REF_VTG1_ADDR 0x3F1U

#define	PCLKEN_REF_VTG_REF_VTG1_MASK 0x01U

#define	PCLKEN_REF_VTG_REF_VTG1_POS 0U

#define	PCLK_GPIO_REF_VTG_REF_VTG1_ADDR 0x3F1U

#define	PCLK_GPIO_REF_VTG_REF_VTG1_MASK 0x3EU

#define	PCLK_GPIO_REF_VTG_REF_VTG1_POS 1U

#define	RCLKEN_Y_REF_VTG_REF_VTG1_ADDR 0x3F1U

#define	RCLKEN_Y_REF_VTG_REF_VTG1_MASK 0x80U

#define	RCLKEN_Y_REF_VTG_REF_VTG1_POS 7U

#define	REF_VTG_REF_VTG2_ADDR 0x3F2U

#define	REF_VTG_REF_VTG2_DEFAULT 0x00U

#define	HSEN_REF_VTG_REF_VTG2_ADDR 0x3F2U

#define	HSEN_REF_VTG_REF_VTG2_MASK 0x01U

#define	HSEN_REF_VTG_REF_VTG2_POS 0U

#define	HS_GPIO_REF_VTG_REF_VTG2_ADDR 0x3F2U

#define	HS_GPIO_REF_VTG_REF_VTG2_MASK 0x3EU

#define	HS_GPIO_REF_VTG_REF_VTG2_POS 1U

#define	REF_VTG_REF_VTG3_ADDR 0x3F3U

#define	REF_VTG_REF_VTG3_DEFAULT 0x00U

#define	VSEN_REF_VTG_REF_VTG3_ADDR 0x3F3U

#define	VSEN_REF_VTG_REF_VTG3_MASK 0x01U

#define	VSEN_REF_VTG_REF_VTG3_POS 0U

#define	VS_GPIO_REF_VTG_REF_VTG3_ADDR 0x3F3U

#define	VS_GPIO_REF_VTG_REF_VTG3_MASK 0x3EU

#define	VS_GPIO_REF_VTG_REF_VTG3_POS 1U

#define	REF_VTG_REF_VTG4_ADDR 0x3F4U

#define	REF_VTG_REF_VTG4_DEFAULT 0x00U

#define	REFGEN_FB_FRACT_L_REF_VTG_REF_VTG4_ADDR 0x3F4U

#define	REFGEN_FB_FRACT_L_REF_VTG_REF_VTG4_MASK 0xFFU

#define	REFGEN_FB_FRACT_L_REF_VTG_REF_VTG4_POS 0U

#define	REF_VTG_REF_VTG5_ADDR 0x3F5U

#define	REF_VTG_REF_VTG5_DEFAULT 0x00U

#define	REFGEN_FB_FRACT_H_REF_VTG_REF_VTG5_ADDR 0x3F5U

#define	REFGEN_FB_FRACT_H_REF_VTG_REF_VTG5_MASK 0x0FU

#define	REFGEN_FB_FRACT_H_REF_VTG_REF_VTG5_POS 0U

#define	REF_VTG_REF_VTG6_ADDR 0x3F6U

#define	REF_VTG_REF_VTG6_DEFAULT 0x00U

#define	VS_DLY_2_REF_VTG_REF_VTG6_ADDR 0x3F6U

#define	VS_DLY_2_REF_VTG_REF_VTG6_MASK 0xFFU

#define	VS_DLY_2_REF_VTG_REF_VTG6_POS 0U

#define	REF_VTG_REF_VTG7_ADDR 0x3F7U

#define	REF_VTG_REF_VTG7_DEFAULT 0x00U

#define	VS_DLY_1_REF_VTG_REF_VTG7_ADDR 0x3F7U

#define	VS_DLY_1_REF_VTG_REF_VTG7_MASK 0xFFU

#define	VS_DLY_1_REF_VTG_REF_VTG7_POS 0U

#define	REF_VTG_REF_VTG8_ADDR 0x3F8U

#define	REF_VTG_REF_VTG8_DEFAULT 0x00U

#define	VS_DLY_0_REF_VTG_REF_VTG8_ADDR 0x3F8U

#define	VS_DLY_0_REF_VTG_REF_VTG8_MASK 0xFFU

#define	VS_DLY_0_REF_VTG_REF_VTG8_POS 0U

#define	REF_VTG_REF_VTG9_ADDR 0x3F9U

#define	REF_VTG_REF_VTG9_DEFAULT 0x1EU

#define	REF_VTG_TRIG_ID_REF_VTG_REF_VTG9_ADDR 0x3F9U

#define	REF_VTG_TRIG_ID_REF_VTG_REF_VTG9_MASK 0x1FU

#define	REF_VTG_TRIG_ID_REF_VTG_REF_VTG9_POS 0U

#define	REF_VTG_TRIG_EN_REF_VTG_REF_VTG9_ADDR 0x3F9U

#define	REF_VTG_TRIG_EN_REF_VTG_REF_VTG9_MASK 0x80U

#define	REF_VTG_TRIG_EN_REF_VTG_REF_VTG9_POS 7U

#define	AFE_ADC_CTRL_0_ADDR 0x500U

#define	AFE_ADC_CTRL_0_DEFAULT 0x00U

#define	CPU_ADC_START_AFE_ADC_CTRL_0_ADDR 0x500U

#define	CPU_ADC_START_AFE_ADC_CTRL_0_MASK 0x01U

#define	CPU_ADC_START_AFE_ADC_CTRL_0_POS 0U

#define	ADC_PU_AFE_ADC_CTRL_0_ADDR 0x500U

#define	ADC_PU_AFE_ADC_CTRL_0_MASK 0x02U

#define	ADC_PU_AFE_ADC_CTRL_0_POS 1U

#define	BUF_PU_AFE_ADC_CTRL_0_ADDR 0x500U

#define	BUF_PU_AFE_ADC_CTRL_0_MASK 0x04U

#define	BUF_PU_AFE_ADC_CTRL_0_POS 2U

#define	ADC_REFBUF_PU_AFE_ADC_CTRL_0_ADDR 0x500U

#define	ADC_REFBUF_PU_AFE_ADC_CTRL_0_MASK 0x08U

#define	ADC_REFBUF_PU_AFE_ADC_CTRL_0_POS 3U

#define	ADC_CHGPUMP_PU_AFE_ADC_CTRL_0_ADDR 0x500U

#define	ADC_CHGPUMP_PU_AFE_ADC_CTRL_0_MASK 0x10U

#define	ADC_CHGPUMP_PU_AFE_ADC_CTRL_0_POS 4U

#define	BUF_BYPASS_AFE_ADC_CTRL_0_ADDR 0x500U

#define	BUF_BYPASS_AFE_ADC_CTRL_0_MASK 0x80U

#define	BUF_BYPASS_AFE_ADC_CTRL_0_POS 7U

#define	AFE_ADC_CTRL_1_ADDR 0x501U

#define	AFE_ADC_CTRL_1_DEFAULT 0x00U

#define	ADC_SCALE_AFE_ADC_CTRL_1_ADDR 0x501U

#define	ADC_SCALE_AFE_ADC_CTRL_1_MASK 0x02U

#define	ADC_SCALE_AFE_ADC_CTRL_1_POS 1U

#define	ADC_REFSEL_AFE_ADC_CTRL_1_ADDR 0x501U

#define	ADC_REFSEL_AFE_ADC_CTRL_1_MASK 0x04U

#define	ADC_REFSEL_AFE_ADC_CTRL_1_POS 2U

#define	ADC_CLK_EN_AFE_ADC_CTRL_1_ADDR 0x501U

#define	ADC_CLK_EN_AFE_ADC_CTRL_1_MASK 0x08U

#define	ADC_CLK_EN_AFE_ADC_CTRL_1_POS 3U

#define	ADC_CHSEL_AFE_ADC_CTRL_1_ADDR 0x501U

#define	ADC_CHSEL_AFE_ADC_CTRL_1_MASK 0xF0U

#define	ADC_CHSEL_AFE_ADC_CTRL_1_POS 4U

#define	AFE_ADC_CTRL_2_ADDR 0x502U

#define	AFE_ADC_CTRL_2_DEFAULT 0x00U

#define	INMUX_EN_AFE_ADC_CTRL_2_ADDR 0x502U

#define	INMUX_EN_AFE_ADC_CTRL_2_MASK 0x01U

#define	INMUX_EN_AFE_ADC_CTRL_2_POS 0U

#define	ADC_XREF_AFE_ADC_CTRL_2_ADDR 0x502U

#define	ADC_XREF_AFE_ADC_CTRL_2_MASK 0x02U

#define	ADC_XREF_AFE_ADC_CTRL_2_POS 1U

#define	ADC_DIV_AFE_ADC_CTRL_2_ADDR 0x502U

#define	ADC_DIV_AFE_ADC_CTRL_2_MASK 0x0CU

#define	ADC_DIV_AFE_ADC_CTRL_2_POS 2U

#define	AFE_ADC_DATA0_ADDR 0x508U

#define	AFE_ADC_DATA0_DEFAULT 0x00U

#define	ADC_DATA_L_AFE_ADC_DATA0_ADDR 0x508U

#define	ADC_DATA_L_AFE_ADC_DATA0_MASK 0xFFU

#define	ADC_DATA_L_AFE_ADC_DATA0_POS 0U

#define	AFE_ADC_DATA1_ADDR 0x509U

#define	AFE_ADC_DATA1_DEFAULT 0x00U

#define	ADC_DATA_H_AFE_ADC_DATA1_ADDR 0x509U

#define	ADC_DATA_H_AFE_ADC_DATA1_MASK 0x03U

#define	ADC_DATA_H_AFE_ADC_DATA1_POS 0U

#define	AFE_ADC_INTRIE0_ADDR 0x50CU

#define	AFE_ADC_INTRIE0_DEFAULT 0x00U

#define	ADC_DONE_IE_AFE_ADC_INTRIE0_ADDR 0x50CU

#define	ADC_DONE_IE_AFE_ADC_INTRIE0_MASK 0x01U

#define	ADC_DONE_IE_AFE_ADC_INTRIE0_POS 0U

#define	ADC_REF_READY_IE_AFE_ADC_INTRIE0_ADDR 0x50CU

#define	ADC_REF_READY_IE_AFE_ADC_INTRIE0_MASK 0x02U

#define	ADC_REF_READY_IE_AFE_ADC_INTRIE0_POS 1U

#define	ADC_HI_LIMIT_IE_AFE_ADC_INTRIE0_ADDR 0x50CU

#define	ADC_HI_LIMIT_IE_AFE_ADC_INTRIE0_MASK 0x04U

#define	ADC_HI_LIMIT_IE_AFE_ADC_INTRIE0_POS 2U

#define	ADC_LO_LIMIT_IE_AFE_ADC_INTRIE0_ADDR 0x50CU

#define	ADC_LO_LIMIT_IE_AFE_ADC_INTRIE0_MASK 0x08U

#define	ADC_LO_LIMIT_IE_AFE_ADC_INTRIE0_POS 3U

#define	ADC_TMON_CAL_OOD_IE_AFE_ADC_INTRIE0_ADDR 0x50CU

#define	ADC_TMON_CAL_OOD_IE_AFE_ADC_INTRIE0_MASK 0x20U

#define	ADC_TMON_CAL_OOD_IE_AFE_ADC_INTRIE0_POS 5U

#define	ADC_OVERRANGE_IE_AFE_ADC_INTRIE0_ADDR 0x50CU

#define	ADC_OVERRANGE_IE_AFE_ADC_INTRIE0_MASK 0x40U

#define	ADC_OVERRANGE_IE_AFE_ADC_INTRIE0_POS 6U

#define	ADC_CALDONE_IE_AFE_ADC_INTRIE0_ADDR 0x50CU

#define	ADC_CALDONE_IE_AFE_ADC_INTRIE0_MASK 0x80U

#define	ADC_CALDONE_IE_AFE_ADC_INTRIE0_POS 7U

#define	AFE_ADC_INTRIE1_ADDR 0x50DU

#define	AFE_ADC_INTRIE1_DEFAULT 0x00U

#define	CH0_HI_LIMIT_IE_AFE_ADC_INTRIE1_ADDR 0x50DU

#define	CH0_HI_LIMIT_IE_AFE_ADC_INTRIE1_MASK 0x01U

#define	CH0_HI_LIMIT_IE_AFE_ADC_INTRIE1_POS 0U

#define	CH1_HI_LIMIT_IE_AFE_ADC_INTRIE1_ADDR 0x50DU

#define	CH1_HI_LIMIT_IE_AFE_ADC_INTRIE1_MASK 0x02U

#define	CH1_HI_LIMIT_IE_AFE_ADC_INTRIE1_POS 1U

#define	CH2_HI_LIMIT_IE_AFE_ADC_INTRIE1_ADDR 0x50DU

#define	CH2_HI_LIMIT_IE_AFE_ADC_INTRIE1_MASK 0x04U

#define	CH2_HI_LIMIT_IE_AFE_ADC_INTRIE1_POS 2U

#define	CH3_HI_LIMIT_IE_AFE_ADC_INTRIE1_ADDR 0x50DU

#define	CH3_HI_LIMIT_IE_AFE_ADC_INTRIE1_MASK 0x08U

#define	CH3_HI_LIMIT_IE_AFE_ADC_INTRIE1_POS 3U

#define	CH4_HI_LIMIT_IE_AFE_ADC_INTRIE1_ADDR 0x50DU

#define	CH4_HI_LIMIT_IE_AFE_ADC_INTRIE1_MASK 0x10U

#define	CH4_HI_LIMIT_IE_AFE_ADC_INTRIE1_POS 4U

#define	CH5_HI_LIMIT_IE_AFE_ADC_INTRIE1_ADDR 0x50DU

#define	CH5_HI_LIMIT_IE_AFE_ADC_INTRIE1_MASK 0x20U

#define	CH5_HI_LIMIT_IE_AFE_ADC_INTRIE1_POS 5U

#define	CH6_HI_LIMIT_IE_AFE_ADC_INTRIE1_ADDR 0x50DU

#define	CH6_HI_LIMIT_IE_AFE_ADC_INTRIE1_MASK 0x40U

#define	CH6_HI_LIMIT_IE_AFE_ADC_INTRIE1_POS 6U

#define	CH7_HI_LIMIT_IE_AFE_ADC_INTRIE1_ADDR 0x50DU

#define	CH7_HI_LIMIT_IE_AFE_ADC_INTRIE1_MASK 0x80U

#define	CH7_HI_LIMIT_IE_AFE_ADC_INTRIE1_POS 7U

#define	AFE_ADC_INTRIE2_ADDR 0x50EU

#define	AFE_ADC_INTRIE2_DEFAULT 0x00U

#define	CH0_LO_LIMIT_IE_AFE_ADC_INTRIE2_ADDR 0x50EU

#define	CH0_LO_LIMIT_IE_AFE_ADC_INTRIE2_MASK 0x01U

#define	CH0_LO_LIMIT_IE_AFE_ADC_INTRIE2_POS 0U

#define	CH1_LO_LIMIT_IE_AFE_ADC_INTRIE2_ADDR 0x50EU

#define	CH1_LO_LIMIT_IE_AFE_ADC_INTRIE2_MASK 0x02U

#define	CH1_LO_LIMIT_IE_AFE_ADC_INTRIE2_POS 1U

#define	CH2_LO_LIMIT_IE_AFE_ADC_INTRIE2_ADDR 0x50EU

#define	CH2_LO_LIMIT_IE_AFE_ADC_INTRIE2_MASK 0x04U

#define	CH2_LO_LIMIT_IE_AFE_ADC_INTRIE2_POS 2U

#define	CH3_LO_LIMIT_IE_AFE_ADC_INTRIE2_ADDR 0x50EU

#define	CH3_LO_LIMIT_IE_AFE_ADC_INTRIE2_MASK 0x08U

#define	CH3_LO_LIMIT_IE_AFE_ADC_INTRIE2_POS 3U

#define	CH4_LO_LIMIT_IE_AFE_ADC_INTRIE2_ADDR 0x50EU

#define	CH4_LO_LIMIT_IE_AFE_ADC_INTRIE2_MASK 0x10U

#define	CH4_LO_LIMIT_IE_AFE_ADC_INTRIE2_POS 4U

#define	CH5_LO_LIMIT_IE_AFE_ADC_INTRIE2_ADDR 0x50EU

#define	CH5_LO_LIMIT_IE_AFE_ADC_INTRIE2_MASK 0x20U

#define	CH5_LO_LIMIT_IE_AFE_ADC_INTRIE2_POS 5U

#define	CH6_LO_LIMIT_IE_AFE_ADC_INTRIE2_ADDR 0x50EU

#define	CH6_LO_LIMIT_IE_AFE_ADC_INTRIE2_MASK 0x40U

#define	CH6_LO_LIMIT_IE_AFE_ADC_INTRIE2_POS 6U

#define	CH7_LO_LIMIT_IE_AFE_ADC_INTRIE2_ADDR 0x50EU

#define	CH7_LO_LIMIT_IE_AFE_ADC_INTRIE2_MASK 0x80U

#define	CH7_LO_LIMIT_IE_AFE_ADC_INTRIE2_POS 7U

#define	AFE_ADC_INTRIE3_ADDR 0x50FU

#define	AFE_ADC_INTRIE3_DEFAULT 0x00U

#define	TMON_ERR_IE_AFE_ADC_INTRIE3_ADDR 0x50FU

#define	TMON_ERR_IE_AFE_ADC_INTRIE3_MASK 0x02U

#define	TMON_ERR_IE_AFE_ADC_INTRIE3_POS 1U

#define	REFLIMSCL3_IE_AFE_ADC_INTRIE3_ADDR 0x50FU

#define	REFLIMSCL3_IE_AFE_ADC_INTRIE3_MASK 0x08U

#define	REFLIMSCL3_IE_AFE_ADC_INTRIE3_POS 3U

#define	REFLIMSCL2_IE_AFE_ADC_INTRIE3_ADDR 0x50FU

#define	REFLIMSCL2_IE_AFE_ADC_INTRIE3_MASK 0x10U

#define	REFLIMSCL2_IE_AFE_ADC_INTRIE3_POS 4U

#define	REFLIMSCL1_IE_AFE_ADC_INTRIE3_ADDR 0x50FU

#define	REFLIMSCL1_IE_AFE_ADC_INTRIE3_MASK 0x20U

#define	REFLIMSCL1_IE_AFE_ADC_INTRIE3_POS 5U

#define	REFLIM_IE_AFE_ADC_INTRIE3_ADDR 0x50FU

#define	REFLIM_IE_AFE_ADC_INTRIE3_MASK 0x40U

#define	REFLIM_IE_AFE_ADC_INTRIE3_POS 6U

#define	AFE_ADC_INTR0_ADDR 0x510U

#define	AFE_ADC_INTR0_DEFAULT 0x00U

#define	ADC_DONE_IF_AFE_ADC_INTR0_ADDR 0x510U

#define	ADC_DONE_IF_AFE_ADC_INTR0_MASK 0x01U

#define	ADC_DONE_IF_AFE_ADC_INTR0_POS 0U

#define	ADC_REF_READY_IF_AFE_ADC_INTR0_ADDR 0x510U

#define	ADC_REF_READY_IF_AFE_ADC_INTR0_MASK 0x02U

#define	ADC_REF_READY_IF_AFE_ADC_INTR0_POS 1U

#define	ADC_HI_LIMIT_IF_AFE_ADC_INTR0_ADDR 0x510U

#define	ADC_HI_LIMIT_IF_AFE_ADC_INTR0_MASK 0x04U

#define	ADC_HI_LIMIT_IF_AFE_ADC_INTR0_POS 2U

#define	ADC_LO_LIMIT_IF_AFE_ADC_INTR0_ADDR 0x510U

#define	ADC_LO_LIMIT_IF_AFE_ADC_INTR0_MASK 0x08U

#define	ADC_LO_LIMIT_IF_AFE_ADC_INTR0_POS 3U

#define	ADC_TMON_CAL_OOD_IF_AFE_ADC_INTR0_ADDR 0x510U

#define	ADC_TMON_CAL_OOD_IF_AFE_ADC_INTR0_MASK 0x20U

#define	ADC_TMON_CAL_OOD_IF_AFE_ADC_INTR0_POS 5U

#define	ADC_OVERRANGE_IF_AFE_ADC_INTR0_ADDR 0x510U

#define	ADC_OVERRANGE_IF_AFE_ADC_INTR0_MASK 0x40U

#define	ADC_OVERRANGE_IF_AFE_ADC_INTR0_POS 6U

#define	ADC_CALDONE_IF_AFE_ADC_INTR0_ADDR 0x510U

#define	ADC_CALDONE_IF_AFE_ADC_INTR0_MASK 0x80U

#define	ADC_CALDONE_IF_AFE_ADC_INTR0_POS 7U

#define	AFE_ADC_INTR1_ADDR 0x511U

#define	AFE_ADC_INTR1_DEFAULT 0x00U

#define	CH0_HI_LIMIT_IF_AFE_ADC_INTR1_ADDR 0x511U

#define	CH0_HI_LIMIT_IF_AFE_ADC_INTR1_MASK 0x01U

#define	CH0_HI_LIMIT_IF_AFE_ADC_INTR1_POS 0U

#define	CH1_HI_LIMIT_IF_AFE_ADC_INTR1_ADDR 0x511U

#define	CH1_HI_LIMIT_IF_AFE_ADC_INTR1_MASK 0x02U

#define	CH1_HI_LIMIT_IF_AFE_ADC_INTR1_POS 1U

#define	CH2_HI_LIMIT_IF_AFE_ADC_INTR1_ADDR 0x511U

#define	CH2_HI_LIMIT_IF_AFE_ADC_INTR1_MASK 0x04U

#define	CH2_HI_LIMIT_IF_AFE_ADC_INTR1_POS 2U

#define	CH3_HI_LIMIT_IF_AFE_ADC_INTR1_ADDR 0x511U

#define	CH3_HI_LIMIT_IF_AFE_ADC_INTR1_MASK 0x08U

#define	CH3_HI_LIMIT_IF_AFE_ADC_INTR1_POS 3U

#define	CH4_HI_LIMIT_IF_AFE_ADC_INTR1_ADDR 0x511U

#define	CH4_HI_LIMIT_IF_AFE_ADC_INTR1_MASK 0x10U

#define	CH4_HI_LIMIT_IF_AFE_ADC_INTR1_POS 4U

#define	CH5_HI_LIMIT_IF_AFE_ADC_INTR1_ADDR 0x511U

#define	CH5_HI_LIMIT_IF_AFE_ADC_INTR1_MASK 0x20U

#define	CH5_HI_LIMIT_IF_AFE_ADC_INTR1_POS 5U

#define	CH6_HI_LIMIT_IF_AFE_ADC_INTR1_ADDR 0x511U

#define	CH6_HI_LIMIT_IF_AFE_ADC_INTR1_MASK 0x40U

#define	CH6_HI_LIMIT_IF_AFE_ADC_INTR1_POS 6U

#define	CH7_HI_LIMIT_IF_AFE_ADC_INTR1_ADDR 0x511U

#define	CH7_HI_LIMIT_IF_AFE_ADC_INTR1_MASK 0x80U

#define	CH7_HI_LIMIT_IF_AFE_ADC_INTR1_POS 7U

#define	AFE_ADC_INTR2_ADDR 0x512U

#define	AFE_ADC_INTR2_DEFAULT 0x00U

#define	CH0_LO_LIMIT_IF_AFE_ADC_INTR2_ADDR 0x512U

#define	CH0_LO_LIMIT_IF_AFE_ADC_INTR2_MASK 0x01U

#define	CH0_LO_LIMIT_IF_AFE_ADC_INTR2_POS 0U

#define	CH1_LO_LIMIT_IF_AFE_ADC_INTR2_ADDR 0x512U

#define	CH1_LO_LIMIT_IF_AFE_ADC_INTR2_MASK 0x02U

#define	CH1_LO_LIMIT_IF_AFE_ADC_INTR2_POS 1U

#define	CH2_LO_LIMIT_IF_AFE_ADC_INTR2_ADDR 0x512U

#define	CH2_LO_LIMIT_IF_AFE_ADC_INTR2_MASK 0x04U

#define	CH2_LO_LIMIT_IF_AFE_ADC_INTR2_POS 2U

#define	CH3_LO_LIMIT_IF_AFE_ADC_INTR2_ADDR 0x512U

#define	CH3_LO_LIMIT_IF_AFE_ADC_INTR2_MASK 0x08U

#define	CH3_LO_LIMIT_IF_AFE_ADC_INTR2_POS 3U

#define	CH4_LO_LIMIT_IF_AFE_ADC_INTR2_ADDR 0x512U

#define	CH4_LO_LIMIT_IF_AFE_ADC_INTR2_MASK 0x10U

#define	CH4_LO_LIMIT_IF_AFE_ADC_INTR2_POS 4U

#define	CH5_LO_LIMIT_IF_AFE_ADC_INTR2_ADDR 0x512U

#define	CH5_LO_LIMIT_IF_AFE_ADC_INTR2_MASK 0x20U

#define	CH5_LO_LIMIT_IF_AFE_ADC_INTR2_POS 5U

#define	CH6_LO_LIMIT_IF_AFE_ADC_INTR2_ADDR 0x512U

#define	CH6_LO_LIMIT_IF_AFE_ADC_INTR2_MASK 0x40U

#define	CH6_LO_LIMIT_IF_AFE_ADC_INTR2_POS 6U

#define	CH7_LO_LIMIT_IF_AFE_ADC_INTR2_ADDR 0x512U

#define	CH7_LO_LIMIT_IF_AFE_ADC_INTR2_MASK 0x80U

#define	CH7_LO_LIMIT_IF_AFE_ADC_INTR2_POS 7U

#define	AFE_ADC_INTR3_ADDR 0x513U

#define	AFE_ADC_INTR3_DEFAULT 0x00U

#define	TMON_ERR_IF_AFE_ADC_INTR3_ADDR 0x513U

#define	TMON_ERR_IF_AFE_ADC_INTR3_MASK 0x02U

#define	TMON_ERR_IF_AFE_ADC_INTR3_POS 1U

#define	REFLIMSCL3_IF_AFE_ADC_INTR3_ADDR 0x513U

#define	REFLIMSCL3_IF_AFE_ADC_INTR3_MASK 0x08U

#define	REFLIMSCL3_IF_AFE_ADC_INTR3_POS 3U

#define	REFLIMSCL2_IF_AFE_ADC_INTR3_ADDR 0x513U

#define	REFLIMSCL2_IF_AFE_ADC_INTR3_MASK 0x10U

#define	REFLIMSCL2_IF_AFE_ADC_INTR3_POS 4U

#define	REFLIMSCL1_IF_AFE_ADC_INTR3_ADDR 0x513U

#define	REFLIMSCL1_IF_AFE_ADC_INTR3_MASK 0x20U

#define	REFLIMSCL1_IF_AFE_ADC_INTR3_POS 5U

#define	REFLIM_IF_AFE_ADC_INTR3_ADDR 0x513U

#define	REFLIM_IF_AFE_ADC_INTR3_MASK 0x40U

#define	REFLIM_IF_AFE_ADC_INTR3_POS 6U

#define	AFE_ADC_LIMIT0_0_ADDR 0x514U

#define	AFE_ADC_LIMIT0_0_DEFAULT 0x00U

#define	CHLOLIMIT_L0_AFE_ADC_LIMIT0_0_ADDR 0x514U

#define	CHLOLIMIT_L0_AFE_ADC_LIMIT0_0_MASK 0xFFU

#define	CHLOLIMIT_L0_AFE_ADC_LIMIT0_0_POS 0U

#define	AFE_ADC_LIMIT0_1_ADDR 0x515U

#define	AFE_ADC_LIMIT0_1_DEFAULT 0xF0U

#define	CHLOLIMIT_H0_AFE_ADC_LIMIT0_1_ADDR 0x515U

#define	CHLOLIMIT_H0_AFE_ADC_LIMIT0_1_MASK 0x03U

#define	CHLOLIMIT_H0_AFE_ADC_LIMIT0_1_POS 0U

#define	CHHILIMIT_L0_AFE_ADC_LIMIT0_1_ADDR 0x515U

#define	CHHILIMIT_L0_AFE_ADC_LIMIT0_1_MASK 0xF0U

#define	CHHILIMIT_L0_AFE_ADC_LIMIT0_1_POS 4U

#define	AFE_ADC_LIMIT0_2_ADDR 0x516U

#define	AFE_ADC_LIMIT0_2_DEFAULT 0x3FU

#define	CHHILIMIT_H0_AFE_ADC_LIMIT0_2_ADDR 0x516U

#define	CHHILIMIT_H0_AFE_ADC_LIMIT0_2_MASK 0x3FU

#define	CHHILIMIT_H0_AFE_ADC_LIMIT0_2_POS 0U

#define	AFE_ADC_LIMIT0_3_ADDR 0x517U

#define	AFE_ADC_LIMIT0_3_DEFAULT 0x03U

#define	CH_SEL0_AFE_ADC_LIMIT0_3_ADDR 0x517U

#define	CH_SEL0_AFE_ADC_LIMIT0_3_MASK 0x0FU

#define	CH_SEL0_AFE_ADC_LIMIT0_3_POS 0U

#define	DIV_SEL0_AFE_ADC_LIMIT0_3_ADDR 0x517U

#define	DIV_SEL0_AFE_ADC_LIMIT0_3_MASK 0x30U

#define	DIV_SEL0_AFE_ADC_LIMIT0_3_POS 4U

#define	AFE_ADC_LIMIT1_0_ADDR 0x518U

#define	AFE_ADC_LIMIT1_0_DEFAULT 0x00U

#define	CHLOLIMIT_L1_AFE_ADC_LIMIT1_0_ADDR 0x518U

#define	CHLOLIMIT_L1_AFE_ADC_LIMIT1_0_MASK 0xFFU

#define	CHLOLIMIT_L1_AFE_ADC_LIMIT1_0_POS 0U

#define	AFE_ADC_LIMIT1_1_ADDR 0x519U

#define	AFE_ADC_LIMIT1_1_DEFAULT 0xF0U

#define	CHLOLIMIT_H1_AFE_ADC_LIMIT1_1_ADDR 0x519U

#define	CHLOLIMIT_H1_AFE_ADC_LIMIT1_1_MASK 0x03U

#define	CHLOLIMIT_H1_AFE_ADC_LIMIT1_1_POS 0U

#define	CHHILIMIT_L1_AFE_ADC_LIMIT1_1_ADDR 0x519U

#define	CHHILIMIT_L1_AFE_ADC_LIMIT1_1_MASK 0xF0U

#define	CHHILIMIT_L1_AFE_ADC_LIMIT1_1_POS 4U

#define	AFE_ADC_LIMIT1_2_ADDR 0x51AU

#define	AFE_ADC_LIMIT1_2_DEFAULT 0x3FU

#define	CHHILIMIT_H1_AFE_ADC_LIMIT1_2_ADDR 0x51AU

#define	CHHILIMIT_H1_AFE_ADC_LIMIT1_2_MASK 0x3FU

#define	CHHILIMIT_H1_AFE_ADC_LIMIT1_2_POS 0U

#define	AFE_ADC_LIMIT1_3_ADDR 0x51BU

#define	AFE_ADC_LIMIT1_3_DEFAULT 0x03U

#define	CH_SEL1_AFE_ADC_LIMIT1_3_ADDR 0x51BU

#define	CH_SEL1_AFE_ADC_LIMIT1_3_MASK 0x0FU

#define	CH_SEL1_AFE_ADC_LIMIT1_3_POS 0U

#define	DIV_SEL1_AFE_ADC_LIMIT1_3_ADDR 0x51BU

#define	DIV_SEL1_AFE_ADC_LIMIT1_3_MASK 0x30U

#define	DIV_SEL1_AFE_ADC_LIMIT1_3_POS 4U

#define	AFE_ADC_LIMIT2_0_ADDR 0x51CU

#define	AFE_ADC_LIMIT2_0_DEFAULT 0x00U

#define	CHLOLIMIT_L2_AFE_ADC_LIMIT2_0_ADDR 0x51CU

#define	CHLOLIMIT_L2_AFE_ADC_LIMIT2_0_MASK 0xFFU

#define	CHLOLIMIT_L2_AFE_ADC_LIMIT2_0_POS 0U

#define	AFE_ADC_LIMIT2_1_ADDR 0x51DU

#define	AFE_ADC_LIMIT2_1_DEFAULT 0xF0U

#define	CHLOLIMIT_H2_AFE_ADC_LIMIT2_1_ADDR 0x51DU

#define	CHLOLIMIT_H2_AFE_ADC_LIMIT2_1_MASK 0x03U

#define	CHLOLIMIT_H2_AFE_ADC_LIMIT2_1_POS 0U

#define	CHHILIMIT_L2_AFE_ADC_LIMIT2_1_ADDR 0x51DU

#define	CHHILIMIT_L2_AFE_ADC_LIMIT2_1_MASK 0xF0U

#define	CHHILIMIT_L2_AFE_ADC_LIMIT2_1_POS 4U

#define	AFE_ADC_LIMIT2_2_ADDR 0x51EU

#define	AFE_ADC_LIMIT2_2_DEFAULT 0x3FU

#define	CHHILIMIT_H2_AFE_ADC_LIMIT2_2_ADDR 0x51EU

#define	CHHILIMIT_H2_AFE_ADC_LIMIT2_2_MASK 0x3FU

#define	CHHILIMIT_H2_AFE_ADC_LIMIT2_2_POS 0U

#define	AFE_ADC_LIMIT2_3_ADDR 0x51FU

#define	AFE_ADC_LIMIT2_3_DEFAULT 0x03U

#define	CH_SEL2_AFE_ADC_LIMIT2_3_ADDR 0x51FU

#define	CH_SEL2_AFE_ADC_LIMIT2_3_MASK 0x0FU

#define	CH_SEL2_AFE_ADC_LIMIT2_3_POS 0U

#define	DIV_SEL2_AFE_ADC_LIMIT2_3_ADDR 0x51FU

#define	DIV_SEL2_AFE_ADC_LIMIT2_3_MASK 0x30U

#define	DIV_SEL2_AFE_ADC_LIMIT2_3_POS 4U

#define	AFE_ADC_LIMIT3_0_ADDR 0x520U

#define	AFE_ADC_LIMIT3_0_DEFAULT 0x00U

#define	CHLOLIMIT_L3_AFE_ADC_LIMIT3_0_ADDR 0x520U

#define	CHLOLIMIT_L3_AFE_ADC_LIMIT3_0_MASK 0xFFU

#define	CHLOLIMIT_L3_AFE_ADC_LIMIT3_0_POS 0U

#define	AFE_ADC_LIMIT3_1_ADDR 0x521U

#define	AFE_ADC_LIMIT3_1_DEFAULT 0xF0U

#define	CHLOLIMIT_H3_AFE_ADC_LIMIT3_1_ADDR 0x521U

#define	CHLOLIMIT_H3_AFE_ADC_LIMIT3_1_MASK 0x03U

#define	CHLOLIMIT_H3_AFE_ADC_LIMIT3_1_POS 0U

#define	CHHILIMIT_L3_AFE_ADC_LIMIT3_1_ADDR 0x521U

#define	CHHILIMIT_L3_AFE_ADC_LIMIT3_1_MASK 0xF0U

#define	CHHILIMIT_L3_AFE_ADC_LIMIT3_1_POS 4U

#define	AFE_ADC_LIMIT3_2_ADDR 0x522U

#define	AFE_ADC_LIMIT3_2_DEFAULT 0x3FU

#define	CHHILIMIT_H3_AFE_ADC_LIMIT3_2_ADDR 0x522U

#define	CHHILIMIT_H3_AFE_ADC_LIMIT3_2_MASK 0x3FU

#define	CHHILIMIT_H3_AFE_ADC_LIMIT3_2_POS 0U

#define	AFE_ADC_LIMIT3_3_ADDR 0x523U

#define	AFE_ADC_LIMIT3_3_DEFAULT 0x03U

#define	CH_SEL3_AFE_ADC_LIMIT3_3_ADDR 0x523U

#define	CH_SEL3_AFE_ADC_LIMIT3_3_MASK 0x0FU

#define	CH_SEL3_AFE_ADC_LIMIT3_3_POS 0U

#define	DIV_SEL3_AFE_ADC_LIMIT3_3_ADDR 0x523U

#define	DIV_SEL3_AFE_ADC_LIMIT3_3_MASK 0x30U

#define	DIV_SEL3_AFE_ADC_LIMIT3_3_POS 4U

#define	AFE_ADC_LIMIT4_0_ADDR 0x524U

#define	AFE_ADC_LIMIT4_0_DEFAULT 0x00U

#define	CHLOLIMIT_L4_AFE_ADC_LIMIT4_0_ADDR 0x524U

#define	CHLOLIMIT_L4_AFE_ADC_LIMIT4_0_MASK 0xFFU

#define	CHLOLIMIT_L4_AFE_ADC_LIMIT4_0_POS 0U

#define	AFE_ADC_LIMIT4_1_ADDR 0x525U

#define	AFE_ADC_LIMIT4_1_DEFAULT 0xF0U

#define	CHLOLIMIT_H4_AFE_ADC_LIMIT4_1_ADDR 0x525U

#define	CHLOLIMIT_H4_AFE_ADC_LIMIT4_1_MASK 0x03U

#define	CHLOLIMIT_H4_AFE_ADC_LIMIT4_1_POS 0U

#define	CHHILIMIT_L4_AFE_ADC_LIMIT4_1_ADDR 0x525U

#define	CHHILIMIT_L4_AFE_ADC_LIMIT4_1_MASK 0xF0U

#define	CHHILIMIT_L4_AFE_ADC_LIMIT4_1_POS 4U

#define	AFE_ADC_LIMIT4_2_ADDR 0x526U

#define	AFE_ADC_LIMIT4_2_DEFAULT 0x3FU

#define	CHHILIMIT_H4_AFE_ADC_LIMIT4_2_ADDR 0x526U

#define	CHHILIMIT_H4_AFE_ADC_LIMIT4_2_MASK 0x3FU

#define	CHHILIMIT_H4_AFE_ADC_LIMIT4_2_POS 0U

#define	AFE_ADC_LIMIT4_3_ADDR 0x527U

#define	AFE_ADC_LIMIT4_3_DEFAULT 0x03U

#define	CH_SEL4_AFE_ADC_LIMIT4_3_ADDR 0x527U

#define	CH_SEL4_AFE_ADC_LIMIT4_3_MASK 0x0FU

#define	CH_SEL4_AFE_ADC_LIMIT4_3_POS 0U

#define	DIV_SEL4_AFE_ADC_LIMIT4_3_ADDR 0x527U

#define	DIV_SEL4_AFE_ADC_LIMIT4_3_MASK 0x30U

#define	DIV_SEL4_AFE_ADC_LIMIT4_3_POS 4U

#define	AFE_ADC_LIMIT5_0_ADDR 0x528U

#define	AFE_ADC_LIMIT5_0_DEFAULT 0x00U

#define	CHLOLIMIT_L5_AFE_ADC_LIMIT5_0_ADDR 0x528U

#define	CHLOLIMIT_L5_AFE_ADC_LIMIT5_0_MASK 0xFFU

#define	CHLOLIMIT_L5_AFE_ADC_LIMIT5_0_POS 0U

#define	AFE_ADC_LIMIT5_1_ADDR 0x529U

#define	AFE_ADC_LIMIT5_1_DEFAULT 0xF0U

#define	CHLOLIMIT_H5_AFE_ADC_LIMIT5_1_ADDR 0x529U

#define	CHLOLIMIT_H5_AFE_ADC_LIMIT5_1_MASK 0x03U

#define	CHLOLIMIT_H5_AFE_ADC_LIMIT5_1_POS 0U

#define	CHHILIMIT_L5_AFE_ADC_LIMIT5_1_ADDR 0x529U

#define	CHHILIMIT_L5_AFE_ADC_LIMIT5_1_MASK 0xF0U

#define	CHHILIMIT_L5_AFE_ADC_LIMIT5_1_POS 4U

#define	AFE_ADC_LIMIT5_2_ADDR 0x52AU

#define	AFE_ADC_LIMIT5_2_DEFAULT 0x3FU

#define	CHHILIMIT_H5_AFE_ADC_LIMIT5_2_ADDR 0x52AU

#define	CHHILIMIT_H5_AFE_ADC_LIMIT5_2_MASK 0x3FU

#define	CHHILIMIT_H5_AFE_ADC_LIMIT5_2_POS 0U

#define	AFE_ADC_LIMIT5_3_ADDR 0x52BU

#define	AFE_ADC_LIMIT5_3_DEFAULT 0x03U

#define	CH_SEL5_AFE_ADC_LIMIT5_3_ADDR 0x52BU

#define	CH_SEL5_AFE_ADC_LIMIT5_3_MASK 0x0FU

#define	CH_SEL5_AFE_ADC_LIMIT5_3_POS 0U

#define	DIV_SEL5_AFE_ADC_LIMIT5_3_ADDR 0x52BU

#define	DIV_SEL5_AFE_ADC_LIMIT5_3_MASK 0x30U

#define	DIV_SEL5_AFE_ADC_LIMIT5_3_POS 4U

#define	AFE_ADC_LIMIT6_0_ADDR 0x52CU

#define	AFE_ADC_LIMIT6_0_DEFAULT 0x00U

#define	CHLOLIMIT_L6_AFE_ADC_LIMIT6_0_ADDR 0x52CU

#define	CHLOLIMIT_L6_AFE_ADC_LIMIT6_0_MASK 0xFFU

#define	CHLOLIMIT_L6_AFE_ADC_LIMIT6_0_POS 0U

#define	AFE_ADC_LIMIT6_1_ADDR 0x52DU

#define	AFE_ADC_LIMIT6_1_DEFAULT 0xF0U

#define	CHLOLIMIT_H6_AFE_ADC_LIMIT6_1_ADDR 0x52DU

#define	CHLOLIMIT_H6_AFE_ADC_LIMIT6_1_MASK 0x03U

#define	CHLOLIMIT_H6_AFE_ADC_LIMIT6_1_POS 0U

#define	CHHILIMIT_L6_AFE_ADC_LIMIT6_1_ADDR 0x52DU

#define	CHHILIMIT_L6_AFE_ADC_LIMIT6_1_MASK 0xF0U

#define	CHHILIMIT_L6_AFE_ADC_LIMIT6_1_POS 4U

#define	AFE_ADC_LIMIT6_2_ADDR 0x52EU

#define	AFE_ADC_LIMIT6_2_DEFAULT 0x3FU

#define	CHHILIMIT_H6_AFE_ADC_LIMIT6_2_ADDR 0x52EU

#define	CHHILIMIT_H6_AFE_ADC_LIMIT6_2_MASK 0x3FU

#define	CHHILIMIT_H6_AFE_ADC_LIMIT6_2_POS 0U

#define	AFE_ADC_LIMIT6_3_ADDR 0x52FU

#define	AFE_ADC_LIMIT6_3_DEFAULT 0x03U

#define	CH_SEL6_AFE_ADC_LIMIT6_3_ADDR 0x52FU

#define	CH_SEL6_AFE_ADC_LIMIT6_3_MASK 0x0FU

#define	CH_SEL6_AFE_ADC_LIMIT6_3_POS 0U

#define	DIV_SEL6_AFE_ADC_LIMIT6_3_ADDR 0x52FU

#define	DIV_SEL6_AFE_ADC_LIMIT6_3_MASK 0x30U

#define	DIV_SEL6_AFE_ADC_LIMIT6_3_POS 4U

#define	AFE_ADC_LIMIT7_0_ADDR 0x530U

#define	AFE_ADC_LIMIT7_0_DEFAULT 0x00U

#define	CHLOLIMIT_L7_AFE_ADC_LIMIT7_0_ADDR 0x530U

#define	CHLOLIMIT_L7_AFE_ADC_LIMIT7_0_MASK 0xFFU

#define	CHLOLIMIT_L7_AFE_ADC_LIMIT7_0_POS 0U

#define	AFE_ADC_LIMIT7_1_ADDR 0x531U

#define	AFE_ADC_LIMIT7_1_DEFAULT 0xF0U

#define	CHLOLIMIT_H7_AFE_ADC_LIMIT7_1_ADDR 0x531U

#define	CHLOLIMIT_H7_AFE_ADC_LIMIT7_1_MASK 0x03U

#define	CHLOLIMIT_H7_AFE_ADC_LIMIT7_1_POS 0U

#define	CHHILIMIT_L7_AFE_ADC_LIMIT7_1_ADDR 0x531U

#define	CHHILIMIT_L7_AFE_ADC_LIMIT7_1_MASK 0xF0U

#define	CHHILIMIT_L7_AFE_ADC_LIMIT7_1_POS 4U

#define	AFE_ADC_LIMIT7_2_ADDR 0x532U

#define	AFE_ADC_LIMIT7_2_DEFAULT 0x3FU

#define	CHHILIMIT_H7_AFE_ADC_LIMIT7_2_ADDR 0x532U

#define	CHHILIMIT_H7_AFE_ADC_LIMIT7_2_MASK 0x3FU

#define	CHHILIMIT_H7_AFE_ADC_LIMIT7_2_POS 0U

#define	AFE_ADC_LIMIT7_3_ADDR 0x533U

#define	AFE_ADC_LIMIT7_3_DEFAULT 0x03U

#define	CH_SEL7_AFE_ADC_LIMIT7_3_ADDR 0x533U

#define	CH_SEL7_AFE_ADC_LIMIT7_3_MASK 0x0FU

#define	CH_SEL7_AFE_ADC_LIMIT7_3_POS 0U

#define	DIV_SEL7_AFE_ADC_LIMIT7_3_ADDR 0x533U

#define	DIV_SEL7_AFE_ADC_LIMIT7_3_MASK 0x30U

#define	DIV_SEL7_AFE_ADC_LIMIT7_3_POS 4U

#define	AFE_ADC_RR_CTRL0_ADDR 0x534U

#define	AFE_ADC_RR_CTRL0_DEFAULT 0x00U

#define	ADC_RR_RUN_AFE_ADC_RR_CTRL0_ADDR 0x534U

#define	ADC_RR_RUN_AFE_ADC_RR_CTRL0_MASK 0x01U

#define	ADC_RR_RUN_AFE_ADC_RR_CTRL0_POS 0U

#define	AFE_ADC_CTRL_4_ADDR 0x53EU

#define	AFE_ADC_CTRL_4_DEFAULT 0x00U

#define	ADC_PIN_EN_AFE_ADC_CTRL_4_ADDR 0x53EU

#define	ADC_PIN_EN_AFE_ADC_CTRL_4_MASK 0x07U

#define	ADC_PIN_EN_AFE_ADC_CTRL_4_POS 0U

#define	MISC_UART_PT_0_ADDR 0x548U

#define	MISC_UART_PT_0_DEFAULT 0xDCU

#define	BITLEN_PT_1_L_MISC_UART_PT_0_ADDR 0x548U

#define	BITLEN_PT_1_L_MISC_UART_PT_0_MASK 0xFFU

#define	BITLEN_PT_1_L_MISC_UART_PT_0_POS 0U

#define	MISC_UART_PT_1_ADDR 0x549U

#define	MISC_UART_PT_1_DEFAULT 0x05U

#define	BITLEN_PT_1_H_MISC_UART_PT_1_ADDR 0x549U

#define	BITLEN_PT_1_H_MISC_UART_PT_1_MASK 0x3FU

#define	BITLEN_PT_1_H_MISC_UART_PT_1_POS 0U

#define	MISC_UART_PT_2_ADDR 0x54AU

#define	MISC_UART_PT_2_DEFAULT 0xDCU

#define	BITLEN_PT_2_L_MISC_UART_PT_2_ADDR 0x54AU

#define	BITLEN_PT_2_L_MISC_UART_PT_2_MASK 0xFFU

#define	BITLEN_PT_2_L_MISC_UART_PT_2_POS 0U

#define	MISC_UART_PT_3_ADDR 0x54BU

#define	MISC_UART_PT_3_DEFAULT 0x05U

#define	BITLEN_PT_2_H_MISC_UART_PT_3_ADDR 0x54BU

#define	BITLEN_PT_2_H_MISC_UART_PT_3_MASK 0x3FU

#define	BITLEN_PT_2_H_MISC_UART_PT_3_POS 0U

#define	MISC_I2C_PT_4_ADDR 0x550U

#define	MISC_I2C_PT_4_DEFAULT 0x00U

#define	SRC_A_1_MISC_I2C_PT_4_ADDR 0x550U

#define	SRC_A_1_MISC_I2C_PT_4_MASK 0xFEU

#define	SRC_A_1_MISC_I2C_PT_4_POS 1U

#define	MISC_I2C_PT_5_ADDR 0x551U

#define	MISC_I2C_PT_5_DEFAULT 0x00U

#define	DST_A_1_MISC_I2C_PT_5_ADDR 0x551U

#define	DST_A_1_MISC_I2C_PT_5_MASK 0xFEU

#define	DST_A_1_MISC_I2C_PT_5_POS 1U

#define	MISC_I2C_PT_6_ADDR 0x552U

#define	MISC_I2C_PT_6_DEFAULT 0x00U

#define	SRC_B_1_MISC_I2C_PT_6_ADDR 0x552U

#define	SRC_B_1_MISC_I2C_PT_6_MASK 0xFEU

#define	SRC_B_1_MISC_I2C_PT_6_POS 1U

#define	MISC_I2C_PT_7_ADDR 0x553U

#define	MISC_I2C_PT_7_DEFAULT 0x00U

#define	DST_B_1_MISC_I2C_PT_7_ADDR 0x553U

#define	DST_B_1_MISC_I2C_PT_7_MASK 0xFEU

#define	DST_B_1_MISC_I2C_PT_7_POS 1U

#define	MISC_I2C_PT_8_ADDR 0x554U

#define	MISC_I2C_PT_8_DEFAULT 0x00U

#define	SRC_A_2_MISC_I2C_PT_8_ADDR 0x554U

#define	SRC_A_2_MISC_I2C_PT_8_MASK 0xFEU

#define	SRC_A_2_MISC_I2C_PT_8_POS 1U

#define	MISC_I2C_PT_9_ADDR 0x555U

#define	MISC_I2C_PT_9_DEFAULT 0x00U

#define	DST_A_2_MISC_I2C_PT_9_ADDR 0x555U

#define	DST_A_2_MISC_I2C_PT_9_MASK 0xFEU

#define	DST_A_2_MISC_I2C_PT_9_POS 1U

#define	MISC_I2C_PT_10_ADDR 0x556U

#define	MISC_I2C_PT_10_DEFAULT 0x00U

#define	SRC_B_2_MISC_I2C_PT_10_ADDR 0x556U

#define	SRC_B_2_MISC_I2C_PT_10_MASK 0xFEU

#define	SRC_B_2_MISC_I2C_PT_10_POS 1U

#define	MISC_I2C_PT_11_ADDR 0x557U

#define	MISC_I2C_PT_11_DEFAULT 0x00U

#define	DST_B_2_MISC_I2C_PT_11_ADDR 0x557U

#define	DST_B_2_MISC_I2C_PT_11_MASK 0xFEU

#define	DST_B_2_MISC_I2C_PT_11_POS 1U

#define	MISC_HS_VS_Z_ADDR 0x55FU

#define	MISC_HS_VS_Z_DEFAULT 0x00U

#define	HS_POL_Z_MISC_HS_VS_Z_ADDR 0x55FU

#define	HS_POL_Z_MISC_HS_VS_Z_MASK 0x01U

#define	HS_POL_Z_MISC_HS_VS_Z_POS 0U

#define	VS_POL_Z_MISC_HS_VS_Z_ADDR 0x55FU

#define	VS_POL_Z_MISC_HS_VS_Z_MASK 0x02U

#define	VS_POL_Z_MISC_HS_VS_Z_POS 1U

#define	HS_DET_Z_MISC_HS_VS_Z_ADDR 0x55FU

#define	HS_DET_Z_MISC_HS_VS_Z_MASK 0x10U

#define	HS_DET_Z_MISC_HS_VS_Z_POS 4U

#define	VS_DET_Z_MISC_HS_VS_Z_ADDR 0x55FU

#define	VS_DET_Z_MISC_HS_VS_Z_MASK 0x20U

#define	VS_DET_Z_MISC_HS_VS_Z_POS 5U

#define	DE_DET_Z_MISC_HS_VS_Z_ADDR 0x55FU

#define	DE_DET_Z_MISC_HS_VS_Z_MASK 0x40U

#define	DE_DET_Z_MISC_HS_VS_Z_POS 6U

#define	MISC_UNLOCK_KEY_ADDR 0x56EU

#define	MISC_UNLOCK_KEY_DEFAULT 0xBBU

#define	UNLOCK_KEY_MISC_UNLOCK_KEY_ADDR 0x56EU

#define	UNLOCK_KEY_MISC_UNLOCK_KEY_MASK 0xFFU

#define	UNLOCK_KEY_MISC_UNLOCK_KEY_POS 0U

#define	MISC_PIO_SLEW_0_ADDR 0x56FU

#define	MISC_PIO_SLEW_0_DEFAULT 0x3EU

#define	PIO00_SLEW_MISC_PIO_SLEW_0_ADDR 0x56FU

#define	PIO00_SLEW_MISC_PIO_SLEW_0_MASK 0x03U

#define	PIO00_SLEW_MISC_PIO_SLEW_0_POS 0U

#define	PIO01_SLEW_MISC_PIO_SLEW_0_ADDR 0x56FU

#define	PIO01_SLEW_MISC_PIO_SLEW_0_MASK 0x0CU

#define	PIO01_SLEW_MISC_PIO_SLEW_0_POS 2U

#define	PIO02_SLEW_MISC_PIO_SLEW_0_ADDR 0x56FU

#define	PIO02_SLEW_MISC_PIO_SLEW_0_MASK 0x30U

#define	PIO02_SLEW_MISC_PIO_SLEW_0_POS 4U

#define	MISC_PIO_SLEW_1_ADDR 0x570U

#define	MISC_PIO_SLEW_1_DEFAULT 0x3CU

#define	PIO05_SLEW_MISC_PIO_SLEW_1_ADDR 0x570U

#define	PIO05_SLEW_MISC_PIO_SLEW_1_MASK 0x0CU

#define	PIO05_SLEW_MISC_PIO_SLEW_1_POS 2U

#define	PIO06_SLEW_MISC_PIO_SLEW_1_ADDR 0x570U

#define	PIO06_SLEW_MISC_PIO_SLEW_1_MASK 0x30U

#define	PIO06_SLEW_MISC_PIO_SLEW_1_POS 4U

#define	MISC_PIO_SLEW_2_ADDR 0x571U

#define	MISC_PIO_SLEW_2_DEFAULT 0xFCU

#define	PIO010_SLEW_MISC_PIO_SLEW_2_ADDR 0x571U

#define	PIO010_SLEW_MISC_PIO_SLEW_2_MASK 0x30U

#define	PIO010_SLEW_MISC_PIO_SLEW_2_POS 4U

#define	PIO011_SLEW_MISC_PIO_SLEW_2_ADDR 0x571U

#define	PIO011_SLEW_MISC_PIO_SLEW_2_MASK 0xC0U

#define	PIO011_SLEW_MISC_PIO_SLEW_2_POS 6U

#define	MIPI_RX_EXT3_EXT4_ADDR 0x584U

#define	MIPI_RX_EXT3_EXT4_DEFAULT 0x00U

#define	CTRL1_FS_CNT_L_MIPI_RX_EXT3_EXT4_ADDR 0x584U

#define	CTRL1_FS_CNT_L_MIPI_RX_EXT3_EXT4_MASK 0xFFU

#define	CTRL1_FS_CNT_L_MIPI_RX_EXT3_EXT4_POS 0U

#define	MIPI_RX_EXT3_EXT5_ADDR 0x585U

#define	MIPI_RX_EXT3_EXT5_DEFAULT 0x00U

#define	CTRL1_FS_CNT_H_MIPI_RX_EXT3_EXT5_ADDR 0x585U

#define	CTRL1_FS_CNT_H_MIPI_RX_EXT3_EXT5_MASK 0xFFU

#define	CTRL1_FS_CNT_H_MIPI_RX_EXT3_EXT5_POS 0U

#define	MIPI_RX_EXT3_EXT6_ADDR 0x586U

#define	MIPI_RX_EXT3_EXT6_DEFAULT 0x00U

#define	CTRL1_FE_CNT_L_MIPI_RX_EXT3_EXT6_ADDR 0x586U

#define	CTRL1_FE_CNT_L_MIPI_RX_EXT3_EXT6_MASK 0xFFU

#define	CTRL1_FE_CNT_L_MIPI_RX_EXT3_EXT6_POS 0U

#define	MIPI_RX_EXT3_EXT7_ADDR 0x587U

#define	MIPI_RX_EXT3_EXT7_DEFAULT 0x00U

#define	CTRL1_FE_CNT_H_MIPI_RX_EXT3_EXT7_ADDR 0x587U

#define	CTRL1_FE_CNT_H_MIPI_RX_EXT3_EXT7_MASK 0xFFU

#define	CTRL1_FE_CNT_H_MIPI_RX_EXT3_EXT7_POS 0U

#define	MIPI_RX_EXT3_EXT8_ADDR 0x588U

#define	MIPI_RX_EXT3_EXT8_DEFAULT 0x00U

#define	CTRL1_FS_VC_SEL_MIPI_RX_EXT3_EXT8_ADDR 0x588U

#define	CTRL1_FS_VC_SEL_MIPI_RX_EXT3_EXT8_MASK 0x0FU

#define	CTRL1_FS_VC_SEL_MIPI_RX_EXT3_EXT8_POS 0U

#define	SPI_CC_WR_SPI_CC_WR__ADDR 0x1300U

#define	SPI_CC_WR_SPI_CC_WR__DEFAULT 0x00U

#define	SPI_CC_RD_SPI_CC_RD__ADDR 0x1380U

#define	SPI_CC_RD_SPI_CC_RD__DEFAULT 0x00U

#define	RLMS_A_RLMS4_ADDR 0x1404U

#define	RLMS_A_RLMS4_DEFAULT 0x4BU

#define	EOM_EN_RLMS_A_RLMS4_ADDR 0x1404U

#define	EOM_EN_RLMS_A_RLMS4_MASK 0x01U

#define	EOM_EN_RLMS_A_RLMS4_POS 0U

#define	EOM_PER_MODE_RLMS_A_RLMS4_ADDR 0x1404U

#define	EOM_PER_MODE_RLMS_A_RLMS4_MASK 0x02U

#define	EOM_PER_MODE_RLMS_A_RLMS4_POS 1U

#define	EOM_CHK_THR_RLMS_A_RLMS4_ADDR 0x1404U

#define	EOM_CHK_THR_RLMS_A_RLMS4_MASK 0x0CU

#define	EOM_CHK_THR_RLMS_A_RLMS4_POS 2U

#define	EOM_CHK_AMOUNT_RLMS_A_RLMS4_ADDR 0x1404U

#define	EOM_CHK_AMOUNT_RLMS_A_RLMS4_MASK 0xF0U

#define	EOM_CHK_AMOUNT_RLMS_A_RLMS4_POS 4U

#define	RLMS_A_RLMS5_ADDR 0x1405U

#define	RLMS_A_RLMS5_DEFAULT 0x10U

#define	EOM_MIN_THR_RLMS_A_RLMS5_ADDR 0x1405U

#define	EOM_MIN_THR_RLMS_A_RLMS5_MASK 0x7FU

#define	EOM_MIN_THR_RLMS_A_RLMS5_POS 0U

#define	EOM_MAN_TRG_REQ_RLMS_A_RLMS5_ADDR 0x1405U

#define	EOM_MAN_TRG_REQ_RLMS_A_RLMS5_MASK 0x80U

#define	EOM_MAN_TRG_REQ_RLMS_A_RLMS5_POS 7U

#define	RLMS_A_RLMS6_ADDR 0x1406U

#define	RLMS_A_RLMS6_DEFAULT 0x80U

#define	EOM_PV_MODE_RLMS_A_RLMS6_ADDR 0x1406U

#define	EOM_PV_MODE_RLMS_A_RLMS6_MASK 0x80U

#define	EOM_PV_MODE_RLMS_A_RLMS6_POS 7U

#define	RLMS_A_RLMS7_ADDR 0x1407U

#define	RLMS_A_RLMS7_DEFAULT 0x00U

#define	EOM_RLMS_A_RLMS7_ADDR 0x1407U

#define	EOM_RLMS_A_RLMS7_MASK 0x7FU

#define	EOM_RLMS_A_RLMS7_POS 0U

#define	EOM_DONE_RLMS_A_RLMS7_ADDR 0x1407U

#define	EOM_DONE_RLMS_A_RLMS7_MASK 0x80U

#define	EOM_DONE_RLMS_A_RLMS7_POS 7U

#define	RLMS_A_RLMS17_ADDR 0x1417U

#define	RLMS_A_RLMS17_DEFAULT 0x00U

#define	AGCEN_RLMS_A_RLMS17_ADDR 0x1417U

#define	AGCEN_RLMS_A_RLMS17_MASK 0x01U

#define	AGCEN_RLMS_A_RLMS17_POS 0U

#define	BSTEN_RLMS_A_RLMS17_ADDR 0x1417U

#define	BSTEN_RLMS_A_RLMS17_MASK 0x02U

#define	BSTEN_RLMS_A_RLMS17_POS 1U

#define	BSTENOV_RLMS_A_RLMS17_ADDR 0x1417U

#define	BSTENOV_RLMS_A_RLMS17_MASK 0x04U

#define	BSTENOV_RLMS_A_RLMS17_POS 2U

#define	DFE1EN_RLMS_A_RLMS17_ADDR 0x1417U

#define	DFE1EN_RLMS_A_RLMS17_MASK 0x08U

#define	DFE1EN_RLMS_A_RLMS17_POS 3U

#define	DFE2EN_RLMS_A_RLMS17_ADDR 0x1417U

#define	DFE2EN_RLMS_A_RLMS17_MASK 0x10U

#define	DFE2EN_RLMS_A_RLMS17_POS 4U

#define	DFE3EN_RLMS_A_RLMS17_ADDR 0x1417U

#define	DFE3EN_RLMS_A_RLMS17_MASK 0x20U

#define	DFE3EN_RLMS_A_RLMS17_POS 5U

#define	DFE4EN_RLMS_A_RLMS17_ADDR 0x1417U

#define	DFE4EN_RLMS_A_RLMS17_MASK 0x40U

#define	DFE4EN_RLMS_A_RLMS17_POS 6U

#define	DFE5EN_RLMS_A_RLMS17_ADDR 0x1417U

#define	DFE5EN_RLMS_A_RLMS17_MASK 0x80U

#define	DFE5EN_RLMS_A_RLMS17_POS 7U

#define	RLMS_A_RLMS1C_ADDR 0x141CU

#define	RLMS_A_RLMS1C_DEFAULT 0x00U

#define	AGCMUL_RLMS_A_RLMS1C_ADDR 0x141CU

#define	AGCMUL_RLMS_A_RLMS1C_MASK 0xFFU

#define	AGCMUL_RLMS_A_RLMS1C_POS 0U

#define	RLMS_A_RLMS1D_ADDR 0x141DU

#define	RLMS_A_RLMS1D_DEFAULT 0x02U

#define	AGCMUH_RLMS_A_RLMS1D_ADDR 0x141DU

#define	AGCMUH_RLMS_A_RLMS1D_MASK 0x3FU

#define	AGCMUH_RLMS_A_RLMS1D_POS 0U

#define	RLMS_A_RLMS1F_ADDR 0x141FU

#define	RLMS_A_RLMS1F_DEFAULT 0x00U

#define	AGCINIT_RLMS_A_RLMS1F_ADDR 0x141FU

#define	AGCINIT_RLMS_A_RLMS1F_MASK 0xFFU

#define	AGCINIT_RLMS_A_RLMS1F_POS 0U

#define	RLMS_A_RLMS32_ADDR 0x1432U

#define	RLMS_A_RLMS32_DEFAULT 0x7FU

#define	OSNMODE_RLMS_A_RLMS32_ADDR 0x1432U

#define	OSNMODE_RLMS_A_RLMS32_MASK 0x80U

#define	OSNMODE_RLMS_A_RLMS32_POS 7U

#define	RLMS_A_RLMS3A_ADDR 0x143AU

#define	RLMS_A_RLMS3A_DEFAULT 0x00U

#define	EYEMONVALCNTL_RLMS_A_RLMS3A_ADDR 0x143AU

#define	EYEMONVALCNTL_RLMS_A_RLMS3A_MASK 0xFFU

#define	EYEMONVALCNTL_RLMS_A_RLMS3A_POS 0U

#define	RLMS_A_RLMS3B_ADDR 0x143BU

#define	RLMS_A_RLMS3B_DEFAULT 0x00U

#define	EYEMONVALCNTH_RLMS_A_RLMS3B_ADDR 0x143BU

#define	EYEMONVALCNTH_RLMS_A_RLMS3B_MASK 0xFFU

#define	EYEMONVALCNTH_RLMS_A_RLMS3B_POS 0U

#define	RLMS_A_RLMS64_ADDR 0x1464U

#define	RLMS_A_RLMS64_DEFAULT 0x90U

#define	TXSSCMODE_RLMS_A_RLMS64_ADDR 0x1464U

#define	TXSSCMODE_RLMS_A_RLMS64_MASK 0x03U

#define	TXSSCMODE_RLMS_A_RLMS64_POS 0U

#define	RLMS_A_RLMS70_ADDR 0x1470U

#define	RLMS_A_RLMS70_DEFAULT 0x01U

#define	TXSSCFRQCTRL_RLMS_A_RLMS70_ADDR 0x1470U

#define	TXSSCFRQCTRL_RLMS_A_RLMS70_MASK 0x7FU

#define	TXSSCFRQCTRL_RLMS_A_RLMS70_POS 0U

#define	RLMS_A_RLMS71_ADDR 0x1471U

#define	RLMS_A_RLMS71_DEFAULT 0x02U

#define	TXSSCEN_RLMS_A_RLMS71_ADDR 0x1471U

#define	TXSSCEN_RLMS_A_RLMS71_MASK 0x01U

#define	TXSSCEN_RLMS_A_RLMS71_POS 0U

#define	TXSSCCENSPRST_RLMS_A_RLMS71_ADDR 0x1471U

#define	TXSSCCENSPRST_RLMS_A_RLMS71_MASK 0x7EU

#define	TXSSCCENSPRST_RLMS_A_RLMS71_POS 1U

#define	RLMS_A_RLMS72_ADDR 0x1472U

#define	RLMS_A_RLMS72_DEFAULT 0xCFU

#define	TXSSCPRESCLL_RLMS_A_RLMS72_ADDR 0x1472U

#define	TXSSCPRESCLL_RLMS_A_RLMS72_MASK 0xFFU

#define	TXSSCPRESCLL_RLMS_A_RLMS72_POS 0U

#define	RLMS_A_RLMS73_ADDR 0x1473U

#define	RLMS_A_RLMS73_DEFAULT 0x00U

#define	TXSSCPRESCLH_RLMS_A_RLMS73_ADDR 0x1473U

#define	TXSSCPRESCLH_RLMS_A_RLMS73_MASK 0x07U

#define	TXSSCPRESCLH_RLMS_A_RLMS73_POS 0U

#define	RLMS_A_RLMS74_ADDR 0x1474U

#define	RLMS_A_RLMS74_DEFAULT 0x00U

#define	TXSSCPHL_RLMS_A_RLMS74_ADDR 0x1474U

#define	TXSSCPHL_RLMS_A_RLMS74_MASK 0xFFU

#define	TXSSCPHL_RLMS_A_RLMS74_POS 0U

#define	RLMS_A_RLMS75_ADDR 0x1475U

#define	RLMS_A_RLMS75_DEFAULT 0x00U

#define	TXSSCPHH_RLMS_A_RLMS75_ADDR 0x1475U

#define	TXSSCPHH_RLMS_A_RLMS75_MASK 0x7FU

#define	TXSSCPHH_RLMS_A_RLMS75_POS 0U

#define	RLMS_A_RLMS76_ADDR 0x1476U

#define	RLMS_A_RLMS76_DEFAULT 0x00U

#define	TXSSCPHQUAD_RLMS_A_RLMS76_ADDR 0x1476U

#define	TXSSCPHQUAD_RLMS_A_RLMS76_MASK 0x03U

#define	TXSSCPHQUAD_RLMS_A_RLMS76_POS 0U

#define	RLMS_A_RLMSA8_ADDR 0x14A8U

#define	RLMS_A_RLMSA8_DEFAULT 0x00U

#define	FW_PHY_RSTB_RLMS_A_RLMSA8_ADDR 0x14A8U

#define	FW_PHY_RSTB_RLMS_A_RLMSA8_MASK 0x20U

#define	FW_PHY_RSTB_RLMS_A_RLMSA8_POS 5U

#define	FW_PHY_PU_TX_RLMS_A_RLMSA8_ADDR 0x14A8U

#define	FW_PHY_PU_TX_RLMS_A_RLMSA8_MASK 0x40U

#define	FW_PHY_PU_TX_RLMS_A_RLMSA8_POS 6U

#define	FW_PHY_CTRL_RLMS_A_RLMSA8_ADDR 0x14A8U

#define	FW_PHY_CTRL_RLMS_A_RLMSA8_MASK 0x80U

#define	FW_PHY_CTRL_RLMS_A_RLMSA8_POS 7U

#define	RLMS_A_RLMSA9_ADDR 0x14A9U

#define	RLMS_A_RLMSA9_DEFAULT 0x00U

#define	FW_RXD_EN_RLMS_A_RLMSA9_ADDR 0x14A9U

#define	FW_RXD_EN_RLMS_A_RLMSA9_MASK 0x08U

#define	FW_RXD_EN_RLMS_A_RLMSA9_POS 3U

#define	FW_TXD_EN_RLMS_A_RLMSA9_ADDR 0x14A9U

#define	FW_TXD_EN_RLMS_A_RLMSA9_MASK 0x10U

#define	FW_TXD_EN_RLMS_A_RLMSA9_POS 4U

#define	FW_TXD_SQUELCH_RLMS_A_RLMSA9_ADDR 0x14A9U

#define	FW_TXD_SQUELCH_RLMS_A_RLMSA9_MASK 0x20U

#define	FW_TXD_SQUELCH_RLMS_A_RLMSA9_POS 5U

#define	FW_REPCAL_RSTB_RLMS_A_RLMSA9_ADDR 0x14A9U

#define	FW_REPCAL_RSTB_RLMS_A_RLMSA9_MASK 0x80U

#define	FW_REPCAL_RSTB_RLMS_A_RLMSA9_POS 7U

#define	RLMS_A_RLMSAA_ADDR 0x14AAU

#define	RLMS_A_RLMSAA_DEFAULT 0x90U

#define	ROR_CLK_DET_RLMS_A_RLMSAA_ADDR 0x14AAU

#define	ROR_CLK_DET_RLMS_A_RLMSAA_MASK 0x20U

#define	ROR_CLK_DET_RLMS_A_RLMSAA_POS 5U

#define	RLMS_A_RLMSCE_ADDR 0x14CEU

#define	RLMS_A_RLMSCE_DEFAULT 0x01U

#define	ENFFE_RLMS_A_RLMSCE_ADDR 0x14CEU

#define	ENFFE_RLMS_A_RLMSCE_MASK 0x01U

#define	ENFFE_RLMS_A_RLMSCE_POS 0U

#define	ENMINUS_MAN_RLMS_A_RLMSCE_ADDR 0x14CEU

#define	ENMINUS_MAN_RLMS_A_RLMSCE_MASK 0x08U

#define	ENMINUS_MAN_RLMS_A_RLMSCE_POS 3U

#define	ENMINUS_REG_RLMS_A_RLMSCE_ADDR 0x14CEU

#define	ENMINUS_REG_RLMS_A_RLMSCE_MASK 0x10U

#define	ENMINUS_REG_RLMS_A_RLMSCE_POS 4U

#define	DPLL_REF_DPLL_0_ADDR 0x1A00U

#define	DPLL_REF_DPLL_0_DEFAULT 0xF5U

#define	CONFIG_SOFT_RST_N_DPLL_REF_DPLL_0_ADDR 0x1A00U

#define	CONFIG_SOFT_RST_N_DPLL_REF_DPLL_0_MASK 0x01U

#define	CONFIG_SOFT_RST_N_DPLL_REF_DPLL_0_POS 0U

#define	DPLL_REF_DPLL_3_ADDR 0x1A03U

#define	DPLL_REF_DPLL_3_DEFAULT 0x82U

#define	CONFIG_SPREAD_BIT_RATIO_DPLL_REF_DPLL_3_ADDR 0x1A03U

#define	CONFIG_SPREAD_BIT_RATIO_DPLL_REF_DPLL_3_MASK 0x07U

#define	CONFIG_SPREAD_BIT_RATIO_DPLL_REF_DPLL_3_POS 0U

#define	CONFIG_USE_INTERNAL_DIVIDER_VALUES_DPLL_REF_DPLL_3_ADDR 0x1A03U

#define	CONFIG_USE_INTERNAL_DIVIDER_VALUES_DPLL_REF_DPLL_3_MASK 0x10U

#define	CONFIG_USE_INTERNAL_DIVIDER_VALUES_DPLL_REF_DPLL_3_POS 4U

#define	CONFIG_SEL_CLOCK_OUT_USE_EXTERNAL_DPLL_REF_DPLL_3_ADDR 0x1A03U

#define	CONFIG_SEL_CLOCK_OUT_USE_EXTERNAL_DPLL_REF_DPLL_3_MASK 0x80U

#define	CONFIG_SEL_CLOCK_OUT_USE_EXTERNAL_DPLL_REF_DPLL_3_POS 7U

#define	DPLL_REF_DPLL_7_ADDR 0x1A07U

#define	DPLL_REF_DPLL_7_DEFAULT 0x04U

#define	CONFIG_DIV_IN_DPLL_REF_DPLL_7_ADDR 0x1A07U

#define	CONFIG_DIV_IN_DPLL_REF_DPLL_7_MASK 0x7CU

#define	CONFIG_DIV_IN_DPLL_REF_DPLL_7_POS 2U

#define	CONFIG_DIV_FB_L_DPLL_REF_DPLL_7_ADDR 0x1A07U

#define	CONFIG_DIV_FB_L_DPLL_REF_DPLL_7_MASK 0x80U

#define	CONFIG_DIV_FB_L_DPLL_REF_DPLL_7_POS 7U

#define	DPLL_REF_DPLL_8_ADDR 0x1A08U

#define	DPLL_REF_DPLL_8_DEFAULT 0x14U

#define	CONFIG_DIV_FB_H_DPLL_REF_DPLL_8_ADDR 0x1A08U

#define	CONFIG_DIV_FB_H_DPLL_REF_DPLL_8_MASK 0xFFU

#define	CONFIG_DIV_FB_H_DPLL_REF_DPLL_8_POS 0U

#define	DPLL_REF_DPLL_9_ADDR 0x1A09U

#define	DPLL_REF_DPLL_9_DEFAULT 0x40U

#define	CONFIG_DIV_FB_EXP_DPLL_REF_DPLL_9_ADDR 0x1A09U

#define	CONFIG_DIV_FB_EXP_DPLL_REF_DPLL_9_MASK 0x07U

#define	CONFIG_DIV_FB_EXP_DPLL_REF_DPLL_9_POS 0U

#define	CONFIG_DIV_OUT_L_DPLL_REF_DPLL_9_ADDR 0x1A09U

#define	CONFIG_DIV_OUT_L_DPLL_REF_DPLL_9_MASK 0xF8U

#define	CONFIG_DIV_OUT_L_DPLL_REF_DPLL_9_POS 3U

#define	DPLL_REF_DPLL_10_ADDR 0x1A0AU

#define	DPLL_REF_DPLL_10_DEFAULT 0x81U

#define	CONFIG_DIV_OUT_H_DPLL_REF_DPLL_10_ADDR 0x1A0AU

#define	CONFIG_DIV_OUT_H_DPLL_REF_DPLL_10_MASK 0x0FU

#define	CONFIG_DIV_OUT_H_DPLL_REF_DPLL_10_POS 0U

#define	CONFIG_DIV_OUT_EXP_DPLL_REF_DPLL_10_ADDR 0x1A0AU

#define	CONFIG_DIV_OUT_EXP_DPLL_REF_DPLL_10_MASK 0x70U

#define	CONFIG_DIV_OUT_EXP_DPLL_REF_DPLL_10_POS 4U

#define	CONFIG_ALLOW_COARSE_CHANGE_DPLL_REF_DPLL_10_ADDR 0x1A0AU

#define	CONFIG_ALLOW_COARSE_CHANGE_DPLL_REF_DPLL_10_MASK 0x80U

#define	CONFIG_ALLOW_COARSE_CHANGE_DPLL_REF_DPLL_10_POS 7U

#define	EFUSE_EFUSE80_ADDR 0x1C50U

#define	EFUSE_EFUSE80_DEFAULT 0x00U

#define	SERIAL_NUMBER_0_EFUSE_EFUSE80_ADDR 0x1C50U

#define	SERIAL_NUMBER_0_EFUSE_EFUSE80_MASK 0xFFU

#define	SERIAL_NUMBER_0_EFUSE_EFUSE80_POS 0U

#define	EFUSE_EFUSE81_ADDR 0x1C51U

#define	EFUSE_EFUSE81_DEFAULT 0x00U

#define	SERIAL_NUMBER_1_EFUSE_EFUSE81_ADDR 0x1C51U

#define	SERIAL_NUMBER_1_EFUSE_EFUSE81_MASK 0xFFU

#define	SERIAL_NUMBER_1_EFUSE_EFUSE81_POS 0U

#define	EFUSE_EFUSE82_ADDR 0x1C52U

#define	EFUSE_EFUSE82_DEFAULT 0x00U

#define	SERIAL_NUMBER_2_EFUSE_EFUSE82_ADDR 0x1C52U

#define	SERIAL_NUMBER_2_EFUSE_EFUSE82_MASK 0xFFU

#define	SERIAL_NUMBER_2_EFUSE_EFUSE82_POS 0U

#define	EFUSE_EFUSE83_ADDR 0x1C53U

#define	EFUSE_EFUSE83_DEFAULT 0x00U

#define	SERIAL_NUMBER_3_EFUSE_EFUSE83_ADDR 0x1C53U

#define	SERIAL_NUMBER_3_EFUSE_EFUSE83_MASK 0xFFU

#define	SERIAL_NUMBER_3_EFUSE_EFUSE83_POS 0U

#define	EFUSE_EFUSE84_ADDR 0x1C54U

#define	EFUSE_EFUSE84_DEFAULT 0x00U

#define	SERIAL_NUMBER_4_EFUSE_EFUSE84_ADDR 0x1C54U

#define	SERIAL_NUMBER_4_EFUSE_EFUSE84_MASK 0xFFU

#define	SERIAL_NUMBER_4_EFUSE_EFUSE84_POS 0U

#define	EFUSE_EFUSE85_ADDR 0x1C55U

#define	EFUSE_EFUSE85_DEFAULT 0x00U

#define	SERIAL_NUMBER_5_EFUSE_EFUSE85_ADDR 0x1C55U

#define	SERIAL_NUMBER_5_EFUSE_EFUSE85_MASK 0xFFU

#define	SERIAL_NUMBER_5_EFUSE_EFUSE85_POS 0U

#define	EFUSE_EFUSE86_ADDR 0x1C56U

#define	EFUSE_EFUSE86_DEFAULT 0x00U

#define	SERIAL_NUMBER_6_EFUSE_EFUSE86_ADDR 0x1C56U

#define	SERIAL_NUMBER_6_EFUSE_EFUSE86_MASK 0xFFU

#define	SERIAL_NUMBER_6_EFUSE_EFUSE86_POS 0U

#define	EFUSE_EFUSE87_ADDR 0x1C57U

#define	EFUSE_EFUSE87_DEFAULT 0x00U

#define	SERIAL_NUMBER_7_EFUSE_EFUSE87_ADDR 0x1C57U

#define	SERIAL_NUMBER_7_EFUSE_EFUSE87_MASK 0xFFU

#define	SERIAL_NUMBER_7_EFUSE_EFUSE87_POS 0U

#define	EFUSE_EFUSE88_ADDR 0x1C58U

#define	EFUSE_EFUSE88_DEFAULT 0x00U

#define	SERIAL_NUMBER_8_EFUSE_EFUSE88_ADDR 0x1C58U

#define	SERIAL_NUMBER_8_EFUSE_EFUSE88_MASK 0xFFU

#define	SERIAL_NUMBER_8_EFUSE_EFUSE88_POS 0U

#define	EFUSE_EFUSE89_ADDR 0x1C59U

#define	EFUSE_EFUSE89_DEFAULT 0x00U

#define	SERIAL_NUMBER_9_EFUSE_EFUSE89_ADDR 0x1C59U

#define	SERIAL_NUMBER_9_EFUSE_EFUSE89_MASK 0xFFU

#define	SERIAL_NUMBER_9_EFUSE_EFUSE89_POS 0U

#define	EFUSE_EFUSE90_ADDR 0x1C5AU

#define	EFUSE_EFUSE90_DEFAULT 0x00U

#define	SERIAL_NUMBER_10_EFUSE_EFUSE90_ADDR 0x1C5AU

#define	SERIAL_NUMBER_10_EFUSE_EFUSE90_MASK 0xFFU

#define	SERIAL_NUMBER_10_EFUSE_EFUSE90_POS 0U

#define	EFUSE_EFUSE91_ADDR 0x1C5BU

#define	EFUSE_EFUSE91_DEFAULT 0x00U

#define	SERIAL_NUMBER_11_EFUSE_EFUSE91_ADDR 0x1C5BU

#define	SERIAL_NUMBER_11_EFUSE_EFUSE91_MASK 0xFFU

#define	SERIAL_NUMBER_11_EFUSE_EFUSE91_POS 0U

#define	EFUSE_EFUSE92_ADDR 0x1C5CU

#define	EFUSE_EFUSE92_DEFAULT 0x00U

#define	SERIAL_NUMBER_12_EFUSE_EFUSE92_ADDR 0x1C5CU

#define	SERIAL_NUMBER_12_EFUSE_EFUSE92_MASK 0xFFU

#define	SERIAL_NUMBER_12_EFUSE_EFUSE92_POS 0U

#define	EFUSE_EFUSE93_ADDR 0x1C5DU

#define	EFUSE_EFUSE93_DEFAULT 0x00U

#define	SERIAL_NUMBER_13_EFUSE_EFUSE93_ADDR 0x1C5DU

#define	SERIAL_NUMBER_13_EFUSE_EFUSE93_MASK 0xFFU

#define	SERIAL_NUMBER_13_EFUSE_EFUSE93_POS 0U

#define	EFUSE_EFUSE94_ADDR 0x1C5EU

#define	EFUSE_EFUSE94_DEFAULT 0x00U

#define	SERIAL_NUMBER_14_EFUSE_EFUSE94_ADDR 0x1C5EU

#define	SERIAL_NUMBER_14_EFUSE_EFUSE94_MASK 0xFFU

#define	SERIAL_NUMBER_14_EFUSE_EFUSE94_POS 0U

#define	EFUSE_EFUSE95_ADDR 0x1C5FU

#define	EFUSE_EFUSE95_DEFAULT 0x00U

#define	SERIAL_NUMBER_15_EFUSE_EFUSE95_ADDR 0x1C5FU

#define	SERIAL_NUMBER_15_EFUSE_EFUSE95_MASK 0xFFU

#define	SERIAL_NUMBER_15_EFUSE_EFUSE95_POS 0U

#define	EFUSE_EFUSE96_ADDR 0x1C60U

#define	EFUSE_EFUSE96_DEFAULT 0x00U

#define	SERIAL_NUMBER_16_EFUSE_EFUSE96_ADDR 0x1C60U

#define	SERIAL_NUMBER_16_EFUSE_EFUSE96_MASK 0xFFU

#define	SERIAL_NUMBER_16_EFUSE_EFUSE96_POS 0U

#define	EFUSE_EFUSE97_ADDR 0x1C61U

#define	EFUSE_EFUSE97_DEFAULT 0x00U

#define	SERIAL_NUMBER_17_EFUSE_EFUSE97_ADDR 0x1C61U

#define	SERIAL_NUMBER_17_EFUSE_EFUSE97_MASK 0xFFU

#define	SERIAL_NUMBER_17_EFUSE_EFUSE97_POS 0U

#define	EFUSE_EFUSE98_ADDR 0x1C62U

#define	EFUSE_EFUSE98_DEFAULT 0x00U

#define	SERIAL_NUMBER_18_EFUSE_EFUSE98_ADDR 0x1C62U

#define	SERIAL_NUMBER_18_EFUSE_EFUSE98_MASK 0xFFU

#define	SERIAL_NUMBER_18_EFUSE_EFUSE98_POS 0U

#define	EFUSE_EFUSE99_ADDR 0x1C63U

#define	EFUSE_EFUSE99_DEFAULT 0x00U

#define	SERIAL_NUMBER_19_EFUSE_EFUSE99_ADDR 0x1C63U

#define	SERIAL_NUMBER_19_EFUSE_EFUSE99_MASK 0xFFU

#define	SERIAL_NUMBER_19_EFUSE_EFUSE99_POS 0U

#define	EFUSE_EFUSE100_ADDR 0x1C64U

#define	EFUSE_EFUSE100_DEFAULT 0x00U

#define	SERIAL_NUMBER_20_EFUSE_EFUSE100_ADDR 0x1C64U

#define	SERIAL_NUMBER_20_EFUSE_EFUSE100_MASK 0xFFU

#define	SERIAL_NUMBER_20_EFUSE_EFUSE100_POS 0U

#define	EFUSE_EFUSE101_ADDR 0x1C65U

#define	EFUSE_EFUSE101_DEFAULT 0x00U

#define	SERIAL_NUMBER_21_EFUSE_EFUSE101_ADDR 0x1C65U

#define	SERIAL_NUMBER_21_EFUSE_EFUSE101_MASK 0xFFU

#define	SERIAL_NUMBER_21_EFUSE_EFUSE101_POS 0U

#define	EFUSE_EFUSE102_ADDR 0x1C66U

#define	EFUSE_EFUSE102_DEFAULT 0x00U

#define	SERIAL_NUMBER_22_EFUSE_EFUSE102_ADDR 0x1C66U

#define	SERIAL_NUMBER_22_EFUSE_EFUSE102_MASK 0xFFU

#define	SERIAL_NUMBER_22_EFUSE_EFUSE102_POS 0U

#define	EFUSE_EFUSE103_ADDR 0x1C67U

#define	EFUSE_EFUSE103_DEFAULT 0x00U

#define	SERIAL_NUMBER_23_EFUSE_EFUSE103_ADDR 0x1C67U

#define	SERIAL_NUMBER_23_EFUSE_EFUSE103_MASK 0xFFU

#define	SERIAL_NUMBER_23_EFUSE_EFUSE103_POS 0U

#define	FUNC_SAFE_REGCRC0_ADDR 0x1D00U

#define	FUNC_SAFE_REGCRC0_DEFAULT 0x00U

#define	RESET_CRC_FUNC_SAFE_REGCRC0_ADDR 0x1D00U

#define	RESET_CRC_FUNC_SAFE_REGCRC0_MASK 0x01U

#define	RESET_CRC_FUNC_SAFE_REGCRC0_POS 0U

#define	CHECK_CRC_FUNC_SAFE_REGCRC0_ADDR 0x1D00U

#define	CHECK_CRC_FUNC_SAFE_REGCRC0_MASK 0x02U

#define	CHECK_CRC_FUNC_SAFE_REGCRC0_POS 1U

#define	PERIODIC_COMPUTE_FUNC_SAFE_REGCRC0_ADDR 0x1D00U

#define	PERIODIC_COMPUTE_FUNC_SAFE_REGCRC0_MASK 0x04U

#define	PERIODIC_COMPUTE_FUNC_SAFE_REGCRC0_POS 2U

#define	I2C_WR_COMPUTE_FUNC_SAFE_REGCRC0_ADDR 0x1D00U

#define	I2C_WR_COMPUTE_FUNC_SAFE_REGCRC0_MASK 0x08U

#define	I2C_WR_COMPUTE_FUNC_SAFE_REGCRC0_POS 3U

#define	GEN_ROLLING_CRC_FUNC_SAFE_REGCRC0_ADDR 0x1D00U

#define	GEN_ROLLING_CRC_FUNC_SAFE_REGCRC0_MASK 0x10U

#define	GEN_ROLLING_CRC_FUNC_SAFE_REGCRC0_POS 4U

#define	FUNC_SAFE_REGCRC1_ADDR 0x1D01U

#define	FUNC_SAFE_REGCRC1_DEFAULT 0x00U

#define	CRC_PERIOD_FUNC_SAFE_REGCRC1_ADDR 0x1D01U

#define	CRC_PERIOD_FUNC_SAFE_REGCRC1_MASK 0xFFU

#define	CRC_PERIOD_FUNC_SAFE_REGCRC1_POS 0U

#define	FUNC_SAFE_REGCRC2_ADDR 0x1D02U

#define	FUNC_SAFE_REGCRC2_DEFAULT 0x00U

#define	REGCRC_LSB_FUNC_SAFE_REGCRC2_ADDR 0x1D02U

#define	REGCRC_LSB_FUNC_SAFE_REGCRC2_MASK 0xFFU

#define	REGCRC_LSB_FUNC_SAFE_REGCRC2_POS 0U

#define	FUNC_SAFE_REGCRC3_ADDR 0x1D03U

#define	FUNC_SAFE_REGCRC3_DEFAULT 0x00U

#define	REGCRC_MSB_FUNC_SAFE_REGCRC3_ADDR 0x1D03U

#define	REGCRC_MSB_FUNC_SAFE_REGCRC3_MASK 0xFFU

#define	REGCRC_MSB_FUNC_SAFE_REGCRC3_POS 0U

#define	FUNC_SAFE_I2C_UART_CRC0_ADDR 0x1D08U

#define	FUNC_SAFE_I2C_UART_CRC0_DEFAULT 0x00U

#define	RESET_MSGCNTR_FUNC_SAFE_I2C_UART_CRC0_ADDR 0x1D08U

#define	RESET_MSGCNTR_FUNC_SAFE_I2C_UART_CRC0_MASK 0x01U

#define	RESET_MSGCNTR_FUNC_SAFE_I2C_UART_CRC0_POS 0U

#define	FUNC_SAFE_I2C_UART_CRC1_ADDR 0x1D09U

#define	FUNC_SAFE_I2C_UART_CRC1_DEFAULT 0x00U

#define	RESET_CRC_ERR_CNT_FUNC_SAFE_I2C_UART_CRC1_ADDR 0x1D09U

#define	RESET_CRC_ERR_CNT_FUNC_SAFE_I2C_UART_CRC1_MASK 0x01U

#define	RESET_CRC_ERR_CNT_FUNC_SAFE_I2C_UART_CRC1_POS 0U

#define	RESET_MSGCNTR_ERR_CNT_FUNC_SAFE_I2C_UART_CRC1_ADDR 0x1D09U

#define	RESET_MSGCNTR_ERR_CNT_FUNC_SAFE_I2C_UART_CRC1_MASK 0x02U

#define	RESET_MSGCNTR_ERR_CNT_FUNC_SAFE_I2C_UART_CRC1_POS 1U

#define	FUNC_SAFE_I2C_UART_CRC2_ADDR 0x1D0AU

#define	FUNC_SAFE_I2C_UART_CRC2_DEFAULT 0x00U

#define	CRC_VAL_FUNC_SAFE_I2C_UART_CRC2_ADDR 0x1D0AU

#define	CRC_VAL_FUNC_SAFE_I2C_UART_CRC2_MASK 0xFFU

#define	CRC_VAL_FUNC_SAFE_I2C_UART_CRC2_POS 0U

#define	FUNC_SAFE_I2C_UART_CRC3_ADDR 0x1D0BU

#define	FUNC_SAFE_I2C_UART_CRC3_DEFAULT 0x00U

#define	MSGCNTR_LSB_FUNC_SAFE_I2C_UART_CRC3_ADDR 0x1D0BU

#define	MSGCNTR_LSB_FUNC_SAFE_I2C_UART_CRC3_MASK 0xFFU

#define	MSGCNTR_LSB_FUNC_SAFE_I2C_UART_CRC3_POS 0U

#define	FUNC_SAFE_I2C_UART_CRC4_ADDR 0x1D0CU

#define	FUNC_SAFE_I2C_UART_CRC4_DEFAULT 0x00U

#define	MSGCNTR_MSB_FUNC_SAFE_I2C_UART_CRC4_ADDR 0x1D0CU

#define	MSGCNTR_MSB_FUNC_SAFE_I2C_UART_CRC4_MASK 0xFFU

#define	MSGCNTR_MSB_FUNC_SAFE_I2C_UART_CRC4_POS 0U

#define	FUNC_SAFE_FS_INTR0_ADDR 0x1D12U

#define	FUNC_SAFE_FS_INTR0_DEFAULT 0xE0U

#define	REG_CRC_ERR_OEN_FUNC_SAFE_FS_INTR0_ADDR 0x1D12U

#define	REG_CRC_ERR_OEN_FUNC_SAFE_FS_INTR0_MASK 0x01U

#define	REG_CRC_ERR_OEN_FUNC_SAFE_FS_INTR0_POS 0U

#define	MEM_ECC_ERR1_OEN_FUNC_SAFE_FS_INTR0_ADDR 0x1D12U

#define	MEM_ECC_ERR1_OEN_FUNC_SAFE_FS_INTR0_MASK 0x10U

#define	MEM_ECC_ERR1_OEN_FUNC_SAFE_FS_INTR0_POS 4U

#define	MEM_ECC_ERR2_OEN_FUNC_SAFE_FS_INTR0_ADDR 0x1D12U

#define	MEM_ECC_ERR2_OEN_FUNC_SAFE_FS_INTR0_MASK 0x20U

#define	MEM_ECC_ERR2_OEN_FUNC_SAFE_FS_INTR0_POS 5U

#define	I2C_UART_CRC_ERR_OEN_FUNC_SAFE_FS_INTR0_ADDR 0x1D12U

#define	I2C_UART_CRC_ERR_OEN_FUNC_SAFE_FS_INTR0_MASK 0x40U

#define	I2C_UART_CRC_ERR_OEN_FUNC_SAFE_FS_INTR0_POS 6U

#define	I2C_UART_MSGCNTR_ERR_OEN_FUNC_SAFE_FS_INTR0_ADDR 0x1D12U

#define	I2C_UART_MSGCNTR_ERR_OEN_FUNC_SAFE_FS_INTR0_MASK 0x80U

#define	I2C_UART_MSGCNTR_ERR_OEN_FUNC_SAFE_FS_INTR0_POS 7U

#define	FUNC_SAFE_FS_INTR1_ADDR 0x1D13U

#define	FUNC_SAFE_FS_INTR1_DEFAULT 0x00U

#define	REG_CRC_ERR_FLAG_FUNC_SAFE_FS_INTR1_ADDR 0x1D13U

#define	REG_CRC_ERR_FLAG_FUNC_SAFE_FS_INTR1_MASK 0x01U

#define	REG_CRC_ERR_FLAG_FUNC_SAFE_FS_INTR1_POS 0U

#define	MEM_ECC_ERR1_INT_FUNC_SAFE_FS_INTR1_ADDR 0x1D13U

#define	MEM_ECC_ERR1_INT_FUNC_SAFE_FS_INTR1_MASK 0x10U

#define	MEM_ECC_ERR1_INT_FUNC_SAFE_FS_INTR1_POS 4U

#define	MEM_ECC_ERR2_INT_FUNC_SAFE_FS_INTR1_ADDR 0x1D13U

#define	MEM_ECC_ERR2_INT_FUNC_SAFE_FS_INTR1_MASK 0x20U

#define	MEM_ECC_ERR2_INT_FUNC_SAFE_FS_INTR1_POS 5U

#define	I2C_UART_CRC_ERR_INT_FUNC_SAFE_FS_INTR1_ADDR 0x1D13U

#define	I2C_UART_CRC_ERR_INT_FUNC_SAFE_FS_INTR1_MASK 0x40U

#define	I2C_UART_CRC_ERR_INT_FUNC_SAFE_FS_INTR1_POS 6U

#define	I2C_UART_MSGCNTR_ERR_INT_FUNC_SAFE_FS_INTR1_ADDR 0x1D13U

#define	I2C_UART_MSGCNTR_ERR_INT_FUNC_SAFE_FS_INTR1_MASK 0x80U

#define	I2C_UART_MSGCNTR_ERR_INT_FUNC_SAFE_FS_INTR1_POS 7U

#define	FUNC_SAFE_MEM_ECC0_ADDR 0x1D14U

#define	FUNC_SAFE_MEM_ECC0_DEFAULT 0x00U

#define	RESET_MEM_ECC_ERR1_CNT_FUNC_SAFE_MEM_ECC0_ADDR 0x1D14U

#define	RESET_MEM_ECC_ERR1_CNT_FUNC_SAFE_MEM_ECC0_MASK 0x01U

#define	RESET_MEM_ECC_ERR1_CNT_FUNC_SAFE_MEM_ECC0_POS 0U

#define	RESET_MEM_ECC_ERR2_CNT_FUNC_SAFE_MEM_ECC0_ADDR 0x1D14U

#define	RESET_MEM_ECC_ERR2_CNT_FUNC_SAFE_MEM_ECC0_MASK 0x02U

#define	RESET_MEM_ECC_ERR2_CNT_FUNC_SAFE_MEM_ECC0_POS 1U

#define	FUNC_SAFE_REG_POST0_ADDR 0x1D20U

#define	FUNC_SAFE_REG_POST0_DEFAULT 0x00U

#define	POST_LBIST_PASSED_FUNC_SAFE_REG_POST0_ADDR 0x1D20U

#define	POST_LBIST_PASSED_FUNC_SAFE_REG_POST0_MASK 0x20U

#define	POST_LBIST_PASSED_FUNC_SAFE_REG_POST0_POS 5U

#define	POST_MBIST_PASSED_FUNC_SAFE_REG_POST0_ADDR 0x1D20U

#define	POST_MBIST_PASSED_FUNC_SAFE_REG_POST0_MASK 0x40U

#define	POST_MBIST_PASSED_FUNC_SAFE_REG_POST0_POS 6U

#define	POST_DONE_FUNC_SAFE_REG_POST0_ADDR 0x1D20U

#define	POST_DONE_FUNC_SAFE_REG_POST0_MASK 0x80U

#define	POST_DONE_FUNC_SAFE_REG_POST0_POS 7U

#define	FUNC_SAFE_REGADCBIST0_ADDR 0x1D28U

#define	FUNC_SAFE_REGADCBIST0_DEFAULT 0x00U

#define	RUN_TMON_CAL_FUNC_SAFE_REGADCBIST0_ADDR 0x1D28U

#define	RUN_TMON_CAL_FUNC_SAFE_REGADCBIST0_MASK 0x01U

#define	RUN_TMON_CAL_FUNC_SAFE_REGADCBIST0_POS 0U

#define	RUN_ACCURACY_FUNC_SAFE_REGADCBIST0_ADDR 0x1D28U

#define	RUN_ACCURACY_FUNC_SAFE_REGADCBIST0_MASK 0x04U

#define	RUN_ACCURACY_FUNC_SAFE_REGADCBIST0_POS 2U

#define	MUXVER_EN_FUNC_SAFE_REGADCBIST0_ADDR 0x1D28U

#define	MUXVER_EN_FUNC_SAFE_REGADCBIST0_MASK 0x10U

#define	MUXVER_EN_FUNC_SAFE_REGADCBIST0_POS 4U

#define	RR_ACCURACY_FUNC_SAFE_REGADCBIST0_ADDR 0x1D28U

#define	RR_ACCURACY_FUNC_SAFE_REGADCBIST0_MASK 0x80U

#define	RR_ACCURACY_FUNC_SAFE_REGADCBIST0_POS 7U

#define	FUNC_SAFE_REGADCBIST3_ADDR 0x1D31U

#define	FUNC_SAFE_REGADCBIST3_DEFAULT 0x0FU

#define	REFLIM_FUNC_SAFE_REGADCBIST3_ADDR 0x1D31U

#define	REFLIM_FUNC_SAFE_REGADCBIST3_MASK 0xFFU

#define	REFLIM_FUNC_SAFE_REGADCBIST3_POS 0U

#define	FUNC_SAFE_REGADCBIST4_ADDR 0x1D32U

#define	FUNC_SAFE_REGADCBIST4_DEFAULT 0x0FU

#define	REFLIMSCL1_FUNC_SAFE_REGADCBIST4_ADDR 0x1D32U

#define	REFLIMSCL1_FUNC_SAFE_REGADCBIST4_MASK 0xFFU

#define	REFLIMSCL1_FUNC_SAFE_REGADCBIST4_POS 0U

#define	FUNC_SAFE_REGADCBIST5_ADDR 0x1D33U

#define	FUNC_SAFE_REGADCBIST5_DEFAULT 0x07U

#define	REFLIMSCL2_FUNC_SAFE_REGADCBIST5_ADDR 0x1D33U

#define	REFLIMSCL2_FUNC_SAFE_REGADCBIST5_MASK 0xFFU

#define	REFLIMSCL2_FUNC_SAFE_REGADCBIST5_POS 0U

#define	FUNC_SAFE_REGADCBIST6_ADDR 0x1D34U

#define	FUNC_SAFE_REGADCBIST6_DEFAULT 0x07U

#define	REFLIMSCL3_FUNC_SAFE_REGADCBIST6_ADDR 0x1D34U

#define	REFLIMSCL3_FUNC_SAFE_REGADCBIST6_MASK 0xFFU

#define	REFLIMSCL3_FUNC_SAFE_REGADCBIST6_POS 0U

#define	FUNC_SAFE_REGADCBIST7_ADDR 0x1D35U

#define	FUNC_SAFE_REGADCBIST7_DEFAULT 0x03U

#define	TLIMIT_FUNC_SAFE_REGADCBIST7_ADDR 0x1D35U

#define	TLIMIT_FUNC_SAFE_REGADCBIST7_MASK 0xFFU

#define	TLIMIT_FUNC_SAFE_REGADCBIST7_POS 0U

#define	FUNC_SAFE_REGADCBIST9_ADDR 0x1D37U

#define	FUNC_SAFE_REGADCBIST9_DEFAULT 0x00U

#define	MUXV_CTRL_FUNC_SAFE_REGADCBIST9_ADDR 0x1D37U

#define	MUXV_CTRL_FUNC_SAFE_REGADCBIST9_MASK 0xFFU

#define	MUXV_CTRL_FUNC_SAFE_REGADCBIST9_POS 0U

#define	FUNC_SAFE_REGADCBIST12_ADDR 0x1D3AU

#define	FUNC_SAFE_REGADCBIST12_DEFAULT 0xFFU

#define	TMONCAL_OOD_WAIT_B2_FUNC_SAFE_REGADCBIST12_ADDR 0x1D3AU

#define	TMONCAL_OOD_WAIT_B2_FUNC_SAFE_REGADCBIST12_MASK 0xFFU

#define	TMONCAL_OOD_WAIT_B2_FUNC_SAFE_REGADCBIST12_POS 0U

#define	FUNC_SAFE_REGADCBIST13_ADDR 0x1D3BU

#define	FUNC_SAFE_REGADCBIST13_DEFAULT 0xFFU

#define	T_EST_OUT_B0_FUNC_SAFE_REGADCBIST13_ADDR 0x1D3BU

#define	T_EST_OUT_B0_FUNC_SAFE_REGADCBIST13_MASK 0xFFU

#define	T_EST_OUT_B0_FUNC_SAFE_REGADCBIST13_POS 0U

#define	FUNC_SAFE_REGADCBIST14_ADDR 0x1D3CU

#define	FUNC_SAFE_REGADCBIST14_DEFAULT 0xC3U

#define	ALT_T_EST_OUT_B1_FUNC_SAFE_REGADCBIST14_ADDR 0x1D3CU

#define	ALT_T_EST_OUT_B1_FUNC_SAFE_REGADCBIST14_MASK 0x03U

#define	ALT_T_EST_OUT_B1_FUNC_SAFE_REGADCBIST14_POS 0U

#define	T_EST_OUT_B1_FUNC_SAFE_REGADCBIST14_ADDR 0x1D3CU

#define	T_EST_OUT_B1_FUNC_SAFE_REGADCBIST14_MASK 0xC0U

#define	T_EST_OUT_B1_FUNC_SAFE_REGADCBIST14_POS 6U

#define	FUNC_SAFE_REGADCBIST15_ADDR 0x1D3DU

#define	FUNC_SAFE_REGADCBIST15_DEFAULT 0xFFU

#define	ALT_T_EST_OUT_B0_FUNC_SAFE_REGADCBIST15_ADDR 0x1D3DU

#define	ALT_T_EST_OUT_B0_FUNC_SAFE_REGADCBIST15_MASK 0xFFU

#define	ALT_T_EST_OUT_B0_FUNC_SAFE_REGADCBIST15_POS 0U

#define	FUNC_SAFE_CC_RTTN_ERR_ADDR 0x1D5FU

#define	FUNC_SAFE_CC_RTTN_ERR_DEFAULT 0x00U

#define	INJECT_RTTN_CRC_ERR_FUNC_SAFE_CC_RTTN_ERR_ADDR 0x1D5FU

#define	INJECT_RTTN_CRC_ERR_FUNC_SAFE_CC_RTTN_ERR_MASK 0x01U

#define	INJECT_RTTN_CRC_ERR_FUNC_SAFE_CC_RTTN_ERR_POS 0U

#define	INJECT_EFUSE_CRC_ERR_FUNC_SAFE_CC_RTTN_ERR_ADDR 0x1D5FU

#define	INJECT_EFUSE_CRC_ERR_FUNC_SAFE_CC_RTTN_ERR_MASK 0x02U

#define	INJECT_EFUSE_CRC_ERR_FUNC_SAFE_CC_RTTN_ERR_POS 1U

#define	RESET_EFUSE_CRC_ERR_FUNC_SAFE_CC_RTTN_ERR_ADDR 0x1D5FU

#define	RESET_EFUSE_CRC_ERR_FUNC_SAFE_CC_RTTN_ERR_MASK 0x04U

#define	RESET_EFUSE_CRC_ERR_FUNC_SAFE_CC_RTTN_ERR_POS 2U

Macro Definition Documentation

◆ ADC_CALDONE_IE_AFE_ADC_INTRIE0_ADDR

#define ADC_CALDONE_IE_AFE_ADC_INTRIE0_ADDR 0x50CU

◆ ADC_CALDONE_IE_AFE_ADC_INTRIE0_MASK

#define ADC_CALDONE_IE_AFE_ADC_INTRIE0_MASK 0x80U

◆ ADC_CALDONE_IE_AFE_ADC_INTRIE0_POS

#define ADC_CALDONE_IE_AFE_ADC_INTRIE0_POS 7U

◆ ADC_CALDONE_IF_AFE_ADC_INTR0_ADDR

#define ADC_CALDONE_IF_AFE_ADC_INTR0_ADDR 0x510U

◆ ADC_CALDONE_IF_AFE_ADC_INTR0_MASK

#define ADC_CALDONE_IF_AFE_ADC_INTR0_MASK 0x80U

◆ ADC_CALDONE_IF_AFE_ADC_INTR0_POS

#define ADC_CALDONE_IF_AFE_ADC_INTR0_POS 7U

◆ ADC_CHGPUMP_PU_AFE_ADC_CTRL_0_ADDR

#define ADC_CHGPUMP_PU_AFE_ADC_CTRL_0_ADDR 0x500U

◆ ADC_CHGPUMP_PU_AFE_ADC_CTRL_0_MASK

#define ADC_CHGPUMP_PU_AFE_ADC_CTRL_0_MASK 0x10U

◆ ADC_CHGPUMP_PU_AFE_ADC_CTRL_0_POS

#define ADC_CHGPUMP_PU_AFE_ADC_CTRL_0_POS 4U

◆ ADC_CHSEL_AFE_ADC_CTRL_1_ADDR

#define ADC_CHSEL_AFE_ADC_CTRL_1_ADDR 0x501U

◆ ADC_CHSEL_AFE_ADC_CTRL_1_MASK

#define ADC_CHSEL_AFE_ADC_CTRL_1_MASK 0xF0U

◆ ADC_CHSEL_AFE_ADC_CTRL_1_POS

#define ADC_CHSEL_AFE_ADC_CTRL_1_POS 4U

◆ ADC_CLK_EN_AFE_ADC_CTRL_1_ADDR

#define ADC_CLK_EN_AFE_ADC_CTRL_1_ADDR 0x501U

◆ ADC_CLK_EN_AFE_ADC_CTRL_1_MASK

#define ADC_CLK_EN_AFE_ADC_CTRL_1_MASK 0x08U

◆ ADC_CLK_EN_AFE_ADC_CTRL_1_POS

#define ADC_CLK_EN_AFE_ADC_CTRL_1_POS 3U

◆ ADC_DATA_H_AFE_ADC_DATA1_ADDR

#define ADC_DATA_H_AFE_ADC_DATA1_ADDR 0x509U

◆ ADC_DATA_H_AFE_ADC_DATA1_MASK

#define ADC_DATA_H_AFE_ADC_DATA1_MASK 0x03U

◆ ADC_DATA_H_AFE_ADC_DATA1_POS

#define ADC_DATA_H_AFE_ADC_DATA1_POS 0U

◆ ADC_DATA_L_AFE_ADC_DATA0_ADDR

#define ADC_DATA_L_AFE_ADC_DATA0_ADDR 0x508U

◆ ADC_DATA_L_AFE_ADC_DATA0_MASK

#define ADC_DATA_L_AFE_ADC_DATA0_MASK 0xFFU

◆ ADC_DATA_L_AFE_ADC_DATA0_POS

#define ADC_DATA_L_AFE_ADC_DATA0_POS 0U

◆ ADC_DIV_AFE_ADC_CTRL_2_ADDR

#define ADC_DIV_AFE_ADC_CTRL_2_ADDR 0x502U

◆ ADC_DIV_AFE_ADC_CTRL_2_MASK

#define ADC_DIV_AFE_ADC_CTRL_2_MASK 0x0CU

◆ ADC_DIV_AFE_ADC_CTRL_2_POS

#define ADC_DIV_AFE_ADC_CTRL_2_POS 2U

◆ ADC_DONE_IE_AFE_ADC_INTRIE0_ADDR

#define ADC_DONE_IE_AFE_ADC_INTRIE0_ADDR 0x50CU

◆ ADC_DONE_IE_AFE_ADC_INTRIE0_MASK

#define ADC_DONE_IE_AFE_ADC_INTRIE0_MASK 0x01U

◆ ADC_DONE_IE_AFE_ADC_INTRIE0_POS

#define ADC_DONE_IE_AFE_ADC_INTRIE0_POS 0U

◆ ADC_DONE_IF_AFE_ADC_INTR0_ADDR

#define ADC_DONE_IF_AFE_ADC_INTR0_ADDR 0x510U

◆ ADC_DONE_IF_AFE_ADC_INTR0_MASK

#define ADC_DONE_IF_AFE_ADC_INTR0_MASK 0x01U

◆ ADC_DONE_IF_AFE_ADC_INTR0_POS

#define ADC_DONE_IF_AFE_ADC_INTR0_POS 0U

◆ ADC_HI_LIMIT_IE_AFE_ADC_INTRIE0_ADDR

#define ADC_HI_LIMIT_IE_AFE_ADC_INTRIE0_ADDR 0x50CU

◆ ADC_HI_LIMIT_IE_AFE_ADC_INTRIE0_MASK

#define ADC_HI_LIMIT_IE_AFE_ADC_INTRIE0_MASK 0x04U

◆ ADC_HI_LIMIT_IE_AFE_ADC_INTRIE0_POS

#define ADC_HI_LIMIT_IE_AFE_ADC_INTRIE0_POS 2U

◆ ADC_HI_LIMIT_IF_AFE_ADC_INTR0_ADDR

#define ADC_HI_LIMIT_IF_AFE_ADC_INTR0_ADDR 0x510U

◆ ADC_HI_LIMIT_IF_AFE_ADC_INTR0_MASK

#define ADC_HI_LIMIT_IF_AFE_ADC_INTR0_MASK 0x04U

◆ ADC_HI_LIMIT_IF_AFE_ADC_INTR0_POS

#define ADC_HI_LIMIT_IF_AFE_ADC_INTR0_POS 2U

◆ ADC_INT_FLAG_TCTRL_INTR7_ADDR

#define ADC_INT_FLAG_TCTRL_INTR7_ADDR 0x1FU

◆ ADC_INT_FLAG_TCTRL_INTR7_MASK

#define ADC_INT_FLAG_TCTRL_INTR7_MASK 0x04U

◆ ADC_INT_FLAG_TCTRL_INTR7_POS

#define ADC_INT_FLAG_TCTRL_INTR7_POS 2U

◆ ADC_INT_OEN_TCTRL_INTR6_ADDR

#define ADC_INT_OEN_TCTRL_INTR6_ADDR 0x1EU

◆ ADC_INT_OEN_TCTRL_INTR6_MASK

#define ADC_INT_OEN_TCTRL_INTR6_MASK 0x04U

◆ ADC_INT_OEN_TCTRL_INTR6_POS

#define ADC_INT_OEN_TCTRL_INTR6_POS 2U

◆ ADC_LO_LIMIT_IE_AFE_ADC_INTRIE0_ADDR

#define ADC_LO_LIMIT_IE_AFE_ADC_INTRIE0_ADDR 0x50CU

◆ ADC_LO_LIMIT_IE_AFE_ADC_INTRIE0_MASK

#define ADC_LO_LIMIT_IE_AFE_ADC_INTRIE0_MASK 0x08U

◆ ADC_LO_LIMIT_IE_AFE_ADC_INTRIE0_POS

#define ADC_LO_LIMIT_IE_AFE_ADC_INTRIE0_POS 3U

◆ ADC_LO_LIMIT_IF_AFE_ADC_INTR0_ADDR

#define ADC_LO_LIMIT_IF_AFE_ADC_INTR0_ADDR 0x510U

◆ ADC_LO_LIMIT_IF_AFE_ADC_INTR0_MASK

#define ADC_LO_LIMIT_IF_AFE_ADC_INTR0_MASK 0x08U

◆ ADC_LO_LIMIT_IF_AFE_ADC_INTR0_POS

#define ADC_LO_LIMIT_IF_AFE_ADC_INTR0_POS 3U

◆ ADC_OVERRANGE_IE_AFE_ADC_INTRIE0_ADDR

#define ADC_OVERRANGE_IE_AFE_ADC_INTRIE0_ADDR 0x50CU

◆ ADC_OVERRANGE_IE_AFE_ADC_INTRIE0_MASK

#define ADC_OVERRANGE_IE_AFE_ADC_INTRIE0_MASK 0x40U

◆ ADC_OVERRANGE_IE_AFE_ADC_INTRIE0_POS

#define ADC_OVERRANGE_IE_AFE_ADC_INTRIE0_POS 6U

◆ ADC_OVERRANGE_IF_AFE_ADC_INTR0_ADDR

#define ADC_OVERRANGE_IF_AFE_ADC_INTR0_ADDR 0x510U

◆ ADC_OVERRANGE_IF_AFE_ADC_INTR0_MASK

#define ADC_OVERRANGE_IF_AFE_ADC_INTR0_MASK 0x40U

◆ ADC_OVERRANGE_IF_AFE_ADC_INTR0_POS

#define ADC_OVERRANGE_IF_AFE_ADC_INTR0_POS 6U

◆ ADC_PIN_EN_AFE_ADC_CTRL_4_ADDR

#define ADC_PIN_EN_AFE_ADC_CTRL_4_ADDR 0x53EU

◆ ADC_PIN_EN_AFE_ADC_CTRL_4_MASK

#define ADC_PIN_EN_AFE_ADC_CTRL_4_MASK 0x07U

◆ ADC_PIN_EN_AFE_ADC_CTRL_4_POS

#define ADC_PIN_EN_AFE_ADC_CTRL_4_POS 0U

◆ ADC_PU_AFE_ADC_CTRL_0_ADDR

#define ADC_PU_AFE_ADC_CTRL_0_ADDR 0x500U

◆ ADC_PU_AFE_ADC_CTRL_0_MASK

#define ADC_PU_AFE_ADC_CTRL_0_MASK 0x02U

◆ ADC_PU_AFE_ADC_CTRL_0_POS

#define ADC_PU_AFE_ADC_CTRL_0_POS 1U

◆ ADC_REF_READY_IE_AFE_ADC_INTRIE0_ADDR

#define ADC_REF_READY_IE_AFE_ADC_INTRIE0_ADDR 0x50CU

◆ ADC_REF_READY_IE_AFE_ADC_INTRIE0_MASK

#define ADC_REF_READY_IE_AFE_ADC_INTRIE0_MASK 0x02U

◆ ADC_REF_READY_IE_AFE_ADC_INTRIE0_POS

#define ADC_REF_READY_IE_AFE_ADC_INTRIE0_POS 1U

◆ ADC_REF_READY_IF_AFE_ADC_INTR0_ADDR

#define ADC_REF_READY_IF_AFE_ADC_INTR0_ADDR 0x510U

◆ ADC_REF_READY_IF_AFE_ADC_INTR0_MASK

#define ADC_REF_READY_IF_AFE_ADC_INTR0_MASK 0x02U

◆ ADC_REF_READY_IF_AFE_ADC_INTR0_POS

#define ADC_REF_READY_IF_AFE_ADC_INTR0_POS 1U

◆ ADC_REFBUF_PU_AFE_ADC_CTRL_0_ADDR

#define ADC_REFBUF_PU_AFE_ADC_CTRL_0_ADDR 0x500U

◆ ADC_REFBUF_PU_AFE_ADC_CTRL_0_MASK

#define ADC_REFBUF_PU_AFE_ADC_CTRL_0_MASK 0x08U

◆ ADC_REFBUF_PU_AFE_ADC_CTRL_0_POS

#define ADC_REFBUF_PU_AFE_ADC_CTRL_0_POS 3U

◆ ADC_REFSEL_AFE_ADC_CTRL_1_ADDR

#define ADC_REFSEL_AFE_ADC_CTRL_1_ADDR 0x501U

◆ ADC_REFSEL_AFE_ADC_CTRL_1_MASK

#define ADC_REFSEL_AFE_ADC_CTRL_1_MASK 0x04U

◆ ADC_REFSEL_AFE_ADC_CTRL_1_POS

#define ADC_REFSEL_AFE_ADC_CTRL_1_POS 2U

◆ ADC_RR_RUN_AFE_ADC_RR_CTRL0_ADDR

#define ADC_RR_RUN_AFE_ADC_RR_CTRL0_ADDR 0x534U

◆ ADC_RR_RUN_AFE_ADC_RR_CTRL0_MASK

#define ADC_RR_RUN_AFE_ADC_RR_CTRL0_MASK 0x01U

◆ ADC_RR_RUN_AFE_ADC_RR_CTRL0_POS

#define ADC_RR_RUN_AFE_ADC_RR_CTRL0_POS 0U

◆ ADC_SCALE_AFE_ADC_CTRL_1_ADDR

#define ADC_SCALE_AFE_ADC_CTRL_1_ADDR 0x501U

◆ ADC_SCALE_AFE_ADC_CTRL_1_MASK

#define ADC_SCALE_AFE_ADC_CTRL_1_MASK 0x02U

◆ ADC_SCALE_AFE_ADC_CTRL_1_POS

#define ADC_SCALE_AFE_ADC_CTRL_1_POS 1U

◆ ADC_TMON_CAL_OOD_IE_AFE_ADC_INTRIE0_ADDR

#define ADC_TMON_CAL_OOD_IE_AFE_ADC_INTRIE0_ADDR 0x50CU

◆ ADC_TMON_CAL_OOD_IE_AFE_ADC_INTRIE0_MASK

#define ADC_TMON_CAL_OOD_IE_AFE_ADC_INTRIE0_MASK 0x20U

◆ ADC_TMON_CAL_OOD_IE_AFE_ADC_INTRIE0_POS

#define ADC_TMON_CAL_OOD_IE_AFE_ADC_INTRIE0_POS 5U

◆ ADC_TMON_CAL_OOD_IF_AFE_ADC_INTR0_ADDR

#define ADC_TMON_CAL_OOD_IF_AFE_ADC_INTR0_ADDR 0x510U

◆ ADC_TMON_CAL_OOD_IF_AFE_ADC_INTR0_MASK

#define ADC_TMON_CAL_OOD_IF_AFE_ADC_INTR0_MASK 0x20U

◆ ADC_TMON_CAL_OOD_IF_AFE_ADC_INTR0_POS

#define ADC_TMON_CAL_OOD_IF_AFE_ADC_INTR0_POS 5U

◆ ADC_XREF_AFE_ADC_CTRL_2_ADDR

#define ADC_XREF_AFE_ADC_CTRL_2_ADDR 0x502U

◆ ADC_XREF_AFE_ADC_CTRL_2_MASK

#define ADC_XREF_AFE_ADC_CTRL_2_MASK 0x02U

◆ ADC_XREF_AFE_ADC_CTRL_2_POS

#define ADC_XREF_AFE_ADC_CTRL_2_POS 1U

◆ AFE_ADC_CTRL_0_ADDR

#define AFE_ADC_CTRL_0_ADDR 0x500U

◆ AFE_ADC_CTRL_0_DEFAULT

#define AFE_ADC_CTRL_0_DEFAULT 0x00U

◆ AFE_ADC_CTRL_1_ADDR

#define AFE_ADC_CTRL_1_ADDR 0x501U

◆ AFE_ADC_CTRL_1_DEFAULT

#define AFE_ADC_CTRL_1_DEFAULT 0x00U

◆ AFE_ADC_CTRL_2_ADDR

#define AFE_ADC_CTRL_2_ADDR 0x502U

◆ AFE_ADC_CTRL_2_DEFAULT

#define AFE_ADC_CTRL_2_DEFAULT 0x00U

◆ AFE_ADC_CTRL_4_ADDR

#define AFE_ADC_CTRL_4_ADDR 0x53EU

◆ AFE_ADC_CTRL_4_DEFAULT

#define AFE_ADC_CTRL_4_DEFAULT 0x00U

◆ AFE_ADC_DATA0_ADDR

#define AFE_ADC_DATA0_ADDR 0x508U

◆ AFE_ADC_DATA0_DEFAULT

#define AFE_ADC_DATA0_DEFAULT 0x00U

◆ AFE_ADC_DATA1_ADDR

#define AFE_ADC_DATA1_ADDR 0x509U

◆ AFE_ADC_DATA1_DEFAULT

#define AFE_ADC_DATA1_DEFAULT 0x00U

◆ AFE_ADC_INTR0_ADDR

#define AFE_ADC_INTR0_ADDR 0x510U

◆ AFE_ADC_INTR0_DEFAULT

#define AFE_ADC_INTR0_DEFAULT 0x00U

◆ AFE_ADC_INTR1_ADDR

#define AFE_ADC_INTR1_ADDR 0x511U

◆ AFE_ADC_INTR1_DEFAULT

#define AFE_ADC_INTR1_DEFAULT 0x00U

◆ AFE_ADC_INTR2_ADDR

#define AFE_ADC_INTR2_ADDR 0x512U

◆ AFE_ADC_INTR2_DEFAULT

#define AFE_ADC_INTR2_DEFAULT 0x00U

◆ AFE_ADC_INTR3_ADDR

#define AFE_ADC_INTR3_ADDR 0x513U

◆ AFE_ADC_INTR3_DEFAULT

#define AFE_ADC_INTR3_DEFAULT 0x00U

◆ AFE_ADC_INTRIE0_ADDR

#define AFE_ADC_INTRIE0_ADDR 0x50CU

◆ AFE_ADC_INTRIE0_DEFAULT

#define AFE_ADC_INTRIE0_DEFAULT 0x00U

◆ AFE_ADC_INTRIE1_ADDR

#define AFE_ADC_INTRIE1_ADDR 0x50DU

◆ AFE_ADC_INTRIE1_DEFAULT

#define AFE_ADC_INTRIE1_DEFAULT 0x00U

◆ AFE_ADC_INTRIE2_ADDR

#define AFE_ADC_INTRIE2_ADDR 0x50EU

◆ AFE_ADC_INTRIE2_DEFAULT

#define AFE_ADC_INTRIE2_DEFAULT 0x00U

◆ AFE_ADC_INTRIE3_ADDR

#define AFE_ADC_INTRIE3_ADDR 0x50FU

◆ AFE_ADC_INTRIE3_DEFAULT

#define AFE_ADC_INTRIE3_DEFAULT 0x00U

◆ AFE_ADC_LIMIT0_0_ADDR

#define AFE_ADC_LIMIT0_0_ADDR 0x514U

◆ AFE_ADC_LIMIT0_0_DEFAULT

#define AFE_ADC_LIMIT0_0_DEFAULT 0x00U

◆ AFE_ADC_LIMIT0_1_ADDR

#define AFE_ADC_LIMIT0_1_ADDR 0x515U

◆ AFE_ADC_LIMIT0_1_DEFAULT

#define AFE_ADC_LIMIT0_1_DEFAULT 0xF0U

◆ AFE_ADC_LIMIT0_2_ADDR

#define AFE_ADC_LIMIT0_2_ADDR 0x516U

◆ AFE_ADC_LIMIT0_2_DEFAULT

#define AFE_ADC_LIMIT0_2_DEFAULT 0x3FU

◆ AFE_ADC_LIMIT0_3_ADDR

#define AFE_ADC_LIMIT0_3_ADDR 0x517U

◆ AFE_ADC_LIMIT0_3_DEFAULT

#define AFE_ADC_LIMIT0_3_DEFAULT 0x03U

◆ AFE_ADC_LIMIT1_0_ADDR

#define AFE_ADC_LIMIT1_0_ADDR 0x518U

◆ AFE_ADC_LIMIT1_0_DEFAULT

#define AFE_ADC_LIMIT1_0_DEFAULT 0x00U

◆ AFE_ADC_LIMIT1_1_ADDR

#define AFE_ADC_LIMIT1_1_ADDR 0x519U

◆ AFE_ADC_LIMIT1_1_DEFAULT

#define AFE_ADC_LIMIT1_1_DEFAULT 0xF0U

◆ AFE_ADC_LIMIT1_2_ADDR

#define AFE_ADC_LIMIT1_2_ADDR 0x51AU

◆ AFE_ADC_LIMIT1_2_DEFAULT

#define AFE_ADC_LIMIT1_2_DEFAULT 0x3FU

◆ AFE_ADC_LIMIT1_3_ADDR

#define AFE_ADC_LIMIT1_3_ADDR 0x51BU

◆ AFE_ADC_LIMIT1_3_DEFAULT

#define AFE_ADC_LIMIT1_3_DEFAULT 0x03U

◆ AFE_ADC_LIMIT2_0_ADDR

#define AFE_ADC_LIMIT2_0_ADDR 0x51CU

◆ AFE_ADC_LIMIT2_0_DEFAULT

#define AFE_ADC_LIMIT2_0_DEFAULT 0x00U

◆ AFE_ADC_LIMIT2_1_ADDR

#define AFE_ADC_LIMIT2_1_ADDR 0x51DU

◆ AFE_ADC_LIMIT2_1_DEFAULT

#define AFE_ADC_LIMIT2_1_DEFAULT 0xF0U

◆ AFE_ADC_LIMIT2_2_ADDR

#define AFE_ADC_LIMIT2_2_ADDR 0x51EU

◆ AFE_ADC_LIMIT2_2_DEFAULT

#define AFE_ADC_LIMIT2_2_DEFAULT 0x3FU

◆ AFE_ADC_LIMIT2_3_ADDR

#define AFE_ADC_LIMIT2_3_ADDR 0x51FU

◆ AFE_ADC_LIMIT2_3_DEFAULT

#define AFE_ADC_LIMIT2_3_DEFAULT 0x03U

◆ AFE_ADC_LIMIT3_0_ADDR

#define AFE_ADC_LIMIT3_0_ADDR 0x520U

◆ AFE_ADC_LIMIT3_0_DEFAULT

#define AFE_ADC_LIMIT3_0_DEFAULT 0x00U

◆ AFE_ADC_LIMIT3_1_ADDR

#define AFE_ADC_LIMIT3_1_ADDR 0x521U

◆ AFE_ADC_LIMIT3_1_DEFAULT

#define AFE_ADC_LIMIT3_1_DEFAULT 0xF0U

◆ AFE_ADC_LIMIT3_2_ADDR

#define AFE_ADC_LIMIT3_2_ADDR 0x522U

◆ AFE_ADC_LIMIT3_2_DEFAULT

#define AFE_ADC_LIMIT3_2_DEFAULT 0x3FU

◆ AFE_ADC_LIMIT3_3_ADDR

#define AFE_ADC_LIMIT3_3_ADDR 0x523U

◆ AFE_ADC_LIMIT3_3_DEFAULT

#define AFE_ADC_LIMIT3_3_DEFAULT 0x03U

◆ AFE_ADC_LIMIT4_0_ADDR

#define AFE_ADC_LIMIT4_0_ADDR 0x524U

◆ AFE_ADC_LIMIT4_0_DEFAULT

#define AFE_ADC_LIMIT4_0_DEFAULT 0x00U

◆ AFE_ADC_LIMIT4_1_ADDR

#define AFE_ADC_LIMIT4_1_ADDR 0x525U

◆ AFE_ADC_LIMIT4_1_DEFAULT

#define AFE_ADC_LIMIT4_1_DEFAULT 0xF0U

◆ AFE_ADC_LIMIT4_2_ADDR

#define AFE_ADC_LIMIT4_2_ADDR 0x526U

◆ AFE_ADC_LIMIT4_2_DEFAULT

#define AFE_ADC_LIMIT4_2_DEFAULT 0x3FU

◆ AFE_ADC_LIMIT4_3_ADDR

#define AFE_ADC_LIMIT4_3_ADDR 0x527U

◆ AFE_ADC_LIMIT4_3_DEFAULT

#define AFE_ADC_LIMIT4_3_DEFAULT 0x03U

◆ AFE_ADC_LIMIT5_0_ADDR

#define AFE_ADC_LIMIT5_0_ADDR 0x528U

◆ AFE_ADC_LIMIT5_0_DEFAULT

#define AFE_ADC_LIMIT5_0_DEFAULT 0x00U

◆ AFE_ADC_LIMIT5_1_ADDR

#define AFE_ADC_LIMIT5_1_ADDR 0x529U

◆ AFE_ADC_LIMIT5_1_DEFAULT

#define AFE_ADC_LIMIT5_1_DEFAULT 0xF0U

◆ AFE_ADC_LIMIT5_2_ADDR

#define AFE_ADC_LIMIT5_2_ADDR 0x52AU

◆ AFE_ADC_LIMIT5_2_DEFAULT

#define AFE_ADC_LIMIT5_2_DEFAULT 0x3FU

◆ AFE_ADC_LIMIT5_3_ADDR

#define AFE_ADC_LIMIT5_3_ADDR 0x52BU

◆ AFE_ADC_LIMIT5_3_DEFAULT

#define AFE_ADC_LIMIT5_3_DEFAULT 0x03U

◆ AFE_ADC_LIMIT6_0_ADDR

#define AFE_ADC_LIMIT6_0_ADDR 0x52CU

◆ AFE_ADC_LIMIT6_0_DEFAULT

#define AFE_ADC_LIMIT6_0_DEFAULT 0x00U

◆ AFE_ADC_LIMIT6_1_ADDR

#define AFE_ADC_LIMIT6_1_ADDR 0x52DU

◆ AFE_ADC_LIMIT6_1_DEFAULT

#define AFE_ADC_LIMIT6_1_DEFAULT 0xF0U

◆ AFE_ADC_LIMIT6_2_ADDR

#define AFE_ADC_LIMIT6_2_ADDR 0x52EU

◆ AFE_ADC_LIMIT6_2_DEFAULT

#define AFE_ADC_LIMIT6_2_DEFAULT 0x3FU

◆ AFE_ADC_LIMIT6_3_ADDR

#define AFE_ADC_LIMIT6_3_ADDR 0x52FU

◆ AFE_ADC_LIMIT6_3_DEFAULT

#define AFE_ADC_LIMIT6_3_DEFAULT 0x03U

◆ AFE_ADC_LIMIT7_0_ADDR

#define AFE_ADC_LIMIT7_0_ADDR 0x530U

◆ AFE_ADC_LIMIT7_0_DEFAULT

#define AFE_ADC_LIMIT7_0_DEFAULT 0x00U

◆ AFE_ADC_LIMIT7_1_ADDR

#define AFE_ADC_LIMIT7_1_ADDR 0x531U

◆ AFE_ADC_LIMIT7_1_DEFAULT

#define AFE_ADC_LIMIT7_1_DEFAULT 0xF0U

◆ AFE_ADC_LIMIT7_2_ADDR

#define AFE_ADC_LIMIT7_2_ADDR 0x532U

◆ AFE_ADC_LIMIT7_2_DEFAULT

#define AFE_ADC_LIMIT7_2_DEFAULT 0x3FU

◆ AFE_ADC_LIMIT7_3_ADDR

#define AFE_ADC_LIMIT7_3_ADDR 0x533U

◆ AFE_ADC_LIMIT7_3_DEFAULT

#define AFE_ADC_LIMIT7_3_DEFAULT 0x03U

◆ AFE_ADC_RR_CTRL0_ADDR

#define AFE_ADC_RR_CTRL0_ADDR 0x534U

◆ AFE_ADC_RR_CTRL0_DEFAULT

#define AFE_ADC_RR_CTRL0_DEFAULT 0x00U

◆ AGCEN_RLMS_A_RLMS17_ADDR

#define AGCEN_RLMS_A_RLMS17_ADDR 0x1417U

◆ AGCEN_RLMS_A_RLMS17_MASK

#define AGCEN_RLMS_A_RLMS17_MASK 0x01U

◆ AGCEN_RLMS_A_RLMS17_POS

#define AGCEN_RLMS_A_RLMS17_POS 0U

◆ AGCINIT_RLMS_A_RLMS1F_ADDR

#define AGCINIT_RLMS_A_RLMS1F_ADDR 0x141FU

◆ AGCINIT_RLMS_A_RLMS1F_MASK

#define AGCINIT_RLMS_A_RLMS1F_MASK 0xFFU

◆ AGCINIT_RLMS_A_RLMS1F_POS

#define AGCINIT_RLMS_A_RLMS1F_POS 0U

◆ AGCMUH_RLMS_A_RLMS1D_ADDR

#define AGCMUH_RLMS_A_RLMS1D_ADDR 0x141DU

◆ AGCMUH_RLMS_A_RLMS1D_MASK

#define AGCMUH_RLMS_A_RLMS1D_MASK 0x3FU

◆ AGCMUH_RLMS_A_RLMS1D_POS

#define AGCMUH_RLMS_A_RLMS1D_POS 0U

◆ AGCMUL_RLMS_A_RLMS1C_ADDR

#define AGCMUL_RLMS_A_RLMS1C_ADDR 0x141CU

◆ AGCMUL_RLMS_A_RLMS1C_MASK

#define AGCMUL_RLMS_A_RLMS1C_MASK 0xFFU

◆ AGCMUL_RLMS_A_RLMS1C_POS

#define AGCMUL_RLMS_A_RLMS1C_POS 0U

◆ ALT_ERRB_EN_DEV_REG5_ADDR

#define ALT_ERRB_EN_DEV_REG5_ADDR 0x05U

◆ ALT_ERRB_EN_DEV_REG5_MASK

#define ALT_ERRB_EN_DEV_REG5_MASK 0x10U

◆ ALT_ERRB_EN_DEV_REG5_POS

#define ALT_ERRB_EN_DEV_REG5_POS 4U

◆ ALT_LOCK_EN_DEV_REG5_ADDR

#define ALT_LOCK_EN_DEV_REG5_ADDR 0x05U

◆ ALT_LOCK_EN_DEV_REG5_MASK

#define ALT_LOCK_EN_DEV_REG5_MASK 0x20U

◆ ALT_LOCK_EN_DEV_REG5_POS

#define ALT_LOCK_EN_DEV_REG5_POS 5U

◆ ALT_T_EST_OUT_B0_FUNC_SAFE_REGADCBIST15_ADDR

#define ALT_T_EST_OUT_B0_FUNC_SAFE_REGADCBIST15_ADDR 0x1D3DU

◆ ALT_T_EST_OUT_B0_FUNC_SAFE_REGADCBIST15_MASK

#define ALT_T_EST_OUT_B0_FUNC_SAFE_REGADCBIST15_MASK 0xFFU

◆ ALT_T_EST_OUT_B0_FUNC_SAFE_REGADCBIST15_POS

#define ALT_T_EST_OUT_B0_FUNC_SAFE_REGADCBIST15_POS 0U

◆ ALT_T_EST_OUT_B1_FUNC_SAFE_REGADCBIST14_ADDR

#define ALT_T_EST_OUT_B1_FUNC_SAFE_REGADCBIST14_ADDR 0x1D3CU

◆ ALT_T_EST_OUT_B1_FUNC_SAFE_REGADCBIST14_MASK

#define ALT_T_EST_OUT_B1_FUNC_SAFE_REGADCBIST14_MASK 0x03U

◆ ALT_T_EST_OUT_B1_FUNC_SAFE_REGADCBIST14_POS

#define ALT_T_EST_OUT_B1_FUNC_SAFE_REGADCBIST14_POS 0U

◆ ARQ0_EN_CFGL_GPIO_ARQ0_ADDR

#define ARQ0_EN_CFGL_GPIO_ARQ0_ADDR 0x95U

◆ ARQ0_EN_CFGL_GPIO_ARQ0_MASK

#define ARQ0_EN_CFGL_GPIO_ARQ0_MASK 0x08U

◆ ARQ0_EN_CFGL_GPIO_ARQ0_POS

#define ARQ0_EN_CFGL_GPIO_ARQ0_POS 3U

◆ ARQ0_EN_CFGL_IIC_X_ARQ0_ADDR

#define ARQ0_EN_CFGL_IIC_X_ARQ0_ADDR 0xA5U

◆ ARQ0_EN_CFGL_IIC_X_ARQ0_MASK

#define ARQ0_EN_CFGL_IIC_X_ARQ0_MASK 0x08U

◆ ARQ0_EN_CFGL_IIC_X_ARQ0_POS

#define ARQ0_EN_CFGL_IIC_X_ARQ0_POS 3U

◆ ARQ0_EN_CFGL_IIC_Y_ARQ0_ADDR

#define ARQ0_EN_CFGL_IIC_Y_ARQ0_ADDR 0xADU

◆ ARQ0_EN_CFGL_IIC_Y_ARQ0_MASK

#define ARQ0_EN_CFGL_IIC_Y_ARQ0_MASK 0x08U

◆ ARQ0_EN_CFGL_IIC_Y_ARQ0_POS

#define ARQ0_EN_CFGL_IIC_Y_ARQ0_POS 3U

◆ ARQ0_EN_CFGL_SPI_ARQ0_ADDR

#define ARQ0_EN_CFGL_SPI_ARQ0_ADDR 0x85U

◆ ARQ0_EN_CFGL_SPI_ARQ0_MASK

#define ARQ0_EN_CFGL_SPI_ARQ0_MASK 0x08U

◆ ARQ0_EN_CFGL_SPI_ARQ0_POS

#define ARQ0_EN_CFGL_SPI_ARQ0_POS 3U

◆ AUTO_BPP_VID_TX_Z_VIDEO_TX0_ADDR

#define AUTO_BPP_VID_TX_Z_VIDEO_TX0_ADDR 0x110U

◆ AUTO_BPP_VID_TX_Z_VIDEO_TX0_MASK

#define AUTO_BPP_VID_TX_Z_VIDEO_TX0_MASK 0x08U

◆ AUTO_BPP_VID_TX_Z_VIDEO_TX0_POS

#define AUTO_BPP_VID_TX_Z_VIDEO_TX0_POS 3U

◆ AUTO_CNT_RST_EN_TCTRL_INTR1_ADDR

#define AUTO_CNT_RST_EN_TCTRL_INTR1_ADDR 0x19U

◆ AUTO_CNT_RST_EN_TCTRL_INTR1_MASK

#define AUTO_CNT_RST_EN_TCTRL_INTR1_MASK 0x08U

◆ AUTO_CNT_RST_EN_TCTRL_INTR1_POS

#define AUTO_CNT_RST_EN_TCTRL_INTR1_POS 3U

◆ AUTO_ERR_RST_EN_TCTRL_INTR0_ADDR

#define AUTO_ERR_RST_EN_TCTRL_INTR0_ADDR 0x18U

◆ AUTO_ERR_RST_EN_TCTRL_INTR0_MASK

#define AUTO_ERR_RST_EN_TCTRL_INTR0_MASK 0x08U

◆ AUTO_ERR_RST_EN_TCTRL_INTR0_POS

#define AUTO_ERR_RST_EN_TCTRL_INTR0_POS 3U

◆ BITLEN_MAN_CFG_1_CC_UART_PT_0_ADDR

#define BITLEN_MAN_CFG_1_CC_UART_PT_0_ADDR 0x4FU

◆ BITLEN_MAN_CFG_1_CC_UART_PT_0_MASK

#define BITLEN_MAN_CFG_1_CC_UART_PT_0_MASK 0x08U

◆ BITLEN_MAN_CFG_1_CC_UART_PT_0_POS

#define BITLEN_MAN_CFG_1_CC_UART_PT_0_POS 3U

◆ BITLEN_MAN_CFG_2_CC_UART_PT_0_ADDR

#define BITLEN_MAN_CFG_2_CC_UART_PT_0_ADDR 0x4FU

◆ BITLEN_MAN_CFG_2_CC_UART_PT_0_MASK

#define BITLEN_MAN_CFG_2_CC_UART_PT_0_MASK 0x80U

◆ BITLEN_MAN_CFG_2_CC_UART_PT_0_POS

#define BITLEN_MAN_CFG_2_CC_UART_PT_0_POS 7U

◆ BITLEN_PT_1_H_MISC_UART_PT_1_ADDR

#define BITLEN_PT_1_H_MISC_UART_PT_1_ADDR 0x549U

◆ BITLEN_PT_1_H_MISC_UART_PT_1_MASK

#define BITLEN_PT_1_H_MISC_UART_PT_1_MASK 0x3FU

◆ BITLEN_PT_1_H_MISC_UART_PT_1_POS

#define BITLEN_PT_1_H_MISC_UART_PT_1_POS 0U

◆ BITLEN_PT_1_L_MISC_UART_PT_0_ADDR

#define BITLEN_PT_1_L_MISC_UART_PT_0_ADDR 0x548U

◆ BITLEN_PT_1_L_MISC_UART_PT_0_MASK

#define BITLEN_PT_1_L_MISC_UART_PT_0_MASK 0xFFU

◆ BITLEN_PT_1_L_MISC_UART_PT_0_POS

#define BITLEN_PT_1_L_MISC_UART_PT_0_POS 0U

◆ BITLEN_PT_2_H_MISC_UART_PT_3_ADDR

#define BITLEN_PT_2_H_MISC_UART_PT_3_ADDR 0x54BU

◆ BITLEN_PT_2_H_MISC_UART_PT_3_MASK

#define BITLEN_PT_2_H_MISC_UART_PT_3_MASK 0x3FU

◆ BITLEN_PT_2_H_MISC_UART_PT_3_POS

#define BITLEN_PT_2_H_MISC_UART_PT_3_POS 0U

◆ BITLEN_PT_2_L_MISC_UART_PT_2_ADDR

#define BITLEN_PT_2_L_MISC_UART_PT_2_ADDR 0x54AU

◆ BITLEN_PT_2_L_MISC_UART_PT_2_MASK

#define BITLEN_PT_2_L_MISC_UART_PT_2_MASK 0xFFU

◆ BITLEN_PT_2_L_MISC_UART_PT_2_POS

#define BITLEN_PT_2_L_MISC_UART_PT_2_POS 0U

◆ BNE_IO_EN_SPI_SPI_6_ADDR

#define BNE_IO_EN_SPI_SPI_6_ADDR 0x176U

◆ BNE_IO_EN_SPI_SPI_6_MASK

#define BNE_IO_EN_SPI_SPI_6_MASK 0x02U

◆ BNE_IO_EN_SPI_SPI_6_POS

#define BNE_IO_EN_SPI_SPI_6_POS 1U

◆ BNE_SPI_SPI_6_ADDR

#define BNE_SPI_SPI_6_ADDR 0x176U

◆ BNE_SPI_SPI_6_MASK

#define BNE_SPI_SPI_6_MASK 0x20U

◆ BNE_SPI_SPI_6_POS

#define BNE_SPI_SPI_6_POS 5U

◆ BPP10DBLZ_FRONTTOP_FRONTTOP_11_ADDR

#define BPP10DBLZ_FRONTTOP_FRONTTOP_11_ADDR 0x313U

◆ BPP10DBLZ_FRONTTOP_FRONTTOP_11_MASK

#define BPP10DBLZ_FRONTTOP_FRONTTOP_11_MASK 0x04U

◆ BPP10DBLZ_FRONTTOP_FRONTTOP_11_POS

#define BPP10DBLZ_FRONTTOP_FRONTTOP_11_POS 2U

◆ BPP12DBLZ_FRONTTOP_FRONTTOP_11_ADDR

#define BPP12DBLZ_FRONTTOP_FRONTTOP_11_ADDR 0x313U

◆ BPP12DBLZ_FRONTTOP_FRONTTOP_11_MASK

#define BPP12DBLZ_FRONTTOP_FRONTTOP_11_MASK 0x40U

◆ BPP12DBLZ_FRONTTOP_FRONTTOP_11_POS

#define BPP12DBLZ_FRONTTOP_FRONTTOP_11_POS 6U

◆ BPP8DBLZ_FRONTTOP_FRONTTOP_10_ADDR

#define BPP8DBLZ_FRONTTOP_FRONTTOP_10_ADDR 0x312U

◆ BPP8DBLZ_FRONTTOP_FRONTTOP_10_MASK

#define BPP8DBLZ_FRONTTOP_FRONTTOP_10_MASK 0x04U

◆ BPP8DBLZ_FRONTTOP_FRONTTOP_10_POS

#define BPP8DBLZ_FRONTTOP_FRONTTOP_10_POS 2U

◆ BPP_VID_TX_Z_VIDEO_TX1_ADDR

#define BPP_VID_TX_Z_VIDEO_TX1_ADDR 0x111U

◆ BPP_VID_TX_Z_VIDEO_TX1_MASK

#define BPP_VID_TX_Z_VIDEO_TX1_MASK 0x3FU

◆ BPP_VID_TX_Z_VIDEO_TX1_POS

#define BPP_VID_TX_Z_VIDEO_TX1_POS 0U

◆ BSTEN_RLMS_A_RLMS17_ADDR

#define BSTEN_RLMS_A_RLMS17_ADDR 0x1417U

◆ BSTEN_RLMS_A_RLMS17_MASK

#define BSTEN_RLMS_A_RLMS17_MASK 0x02U

◆ BSTEN_RLMS_A_RLMS17_POS

#define BSTEN_RLMS_A_RLMS17_POS 1U

◆ BSTENOV_RLMS_A_RLMS17_ADDR

#define BSTENOV_RLMS_A_RLMS17_ADDR 0x1417U

◆ BSTENOV_RLMS_A_RLMS17_MASK

#define BSTENOV_RLMS_A_RLMS17_MASK 0x04U

◆ BSTENOV_RLMS_A_RLMS17_POS

#define BSTENOV_RLMS_A_RLMS17_POS 2U

◆ BUF_BYPASS_AFE_ADC_CTRL_0_ADDR

#define BUF_BYPASS_AFE_ADC_CTRL_0_ADDR 0x500U

◆ BUF_BYPASS_AFE_ADC_CTRL_0_MASK

#define BUF_BYPASS_AFE_ADC_CTRL_0_MASK 0x80U

◆ BUF_BYPASS_AFE_ADC_CTRL_0_POS

#define BUF_BYPASS_AFE_ADC_CTRL_0_POS 7U

◆ BUF_PU_AFE_ADC_CTRL_0_ADDR

#define BUF_PU_AFE_ADC_CTRL_0_ADDR 0x500U

◆ BUF_PU_AFE_ADC_CTRL_0_MASK

#define BUF_PU_AFE_ADC_CTRL_0_MASK 0x04U

◆ BUF_PU_AFE_ADC_CTRL_0_POS

#define BUF_PU_AFE_ADC_CTRL_0_POS 2U

◆ BYPASS_DIS_PAR_CC_UART_0_ADDR

#define BYPASS_DIS_PAR_CC_UART_0_ADDR 0x48U

◆ BYPASS_DIS_PAR_CC_UART_0_MASK

#define BYPASS_DIS_PAR_CC_UART_0_MASK 0x08U

◆ BYPASS_DIS_PAR_CC_UART_0_POS

#define BYPASS_DIS_PAR_CC_UART_0_POS 3U

◆ BYPASS_EN_CC_UART_0_ADDR

#define BYPASS_EN_CC_UART_0_ADDR 0x48U

◆ BYPASS_EN_CC_UART_0_MASK

#define BYPASS_EN_CC_UART_0_MASK 0x01U

◆ BYPASS_EN_CC_UART_0_POS

#define BYPASS_EN_CC_UART_0_POS 0U

◆ BYPASS_TO_CC_UART_0_ADDR

#define BYPASS_TO_CC_UART_0_ADDR 0x48U

◆ BYPASS_TO_CC_UART_0_MASK

#define BYPASS_TO_CC_UART_0_MASK 0x06U

◆ BYPASS_TO_CC_UART_0_POS

#define BYPASS_TO_CC_UART_0_POS 1U

◆ CC_CRC_EN_DEV_REG4_ADDR

#define CC_CRC_EN_DEV_REG4_ADDR 0x04U

◆ CC_CRC_EN_DEV_REG4_MASK

#define CC_CRC_EN_DEV_REG4_MASK 0x08U

◆ CC_CRC_EN_DEV_REG4_POS

#define CC_CRC_EN_DEV_REG4_POS 3U

◆ CC_CRC_MSGCNTR_OVR_DEV_REG4_ADDR

#define CC_CRC_MSGCNTR_OVR_DEV_REG4_ADDR 0x04U

◆ CC_CRC_MSGCNTR_OVR_DEV_REG4_MASK

#define CC_CRC_MSGCNTR_OVR_DEV_REG4_MASK 0x04U

◆ CC_CRC_MSGCNTR_OVR_DEV_REG4_POS

#define CC_CRC_MSGCNTR_OVR_DEV_REG4_POS 2U

◆ CC_I2C_0_ADDR

#define CC_I2C_0_ADDR 0x40U

◆ CC_I2C_0_DEFAULT

#define CC_I2C_0_DEFAULT 0x26U

◆ CC_I2C_1_ADDR

#define CC_I2C_1_ADDR 0x41U

◆ CC_I2C_1_DEFAULT

#define CC_I2C_1_DEFAULT 0x56U

◆ CC_I2C_2_ADDR

#define CC_I2C_2_ADDR 0x42U

◆ CC_I2C_2_DEFAULT

#define CC_I2C_2_DEFAULT 0x00U

◆ CC_I2C_3_ADDR

#define CC_I2C_3_ADDR 0x43U

◆ CC_I2C_3_DEFAULT

#define CC_I2C_3_DEFAULT 0x00U

◆ CC_I2C_4_ADDR

#define CC_I2C_4_ADDR 0x44U

◆ CC_I2C_4_DEFAULT

#define CC_I2C_4_DEFAULT 0x00U

◆ CC_I2C_5_ADDR

#define CC_I2C_5_ADDR 0x45U

◆ CC_I2C_5_DEFAULT

#define CC_I2C_5_DEFAULT 0x00U

◆ CC_I2C_PT_0_ADDR

#define CC_I2C_PT_0_ADDR 0x4CU

◆ CC_I2C_PT_0_DEFAULT

#define CC_I2C_PT_0_DEFAULT 0x26U

◆ CC_I2C_PT_1_ADDR

#define CC_I2C_PT_1_ADDR 0x4DU

◆ CC_I2C_PT_1_DEFAULT

#define CC_I2C_PT_1_DEFAULT 0x56U

◆ CC_MSGCNTR_EN_DEV_REG4_ADDR

#define CC_MSGCNTR_EN_DEV_REG4_ADDR 0x04U

◆ CC_MSGCNTR_EN_DEV_REG4_MASK

#define CC_MSGCNTR_EN_DEV_REG4_MASK 0x10U

◆ CC_MSGCNTR_EN_DEV_REG4_POS

#define CC_MSGCNTR_EN_DEV_REG4_POS 4U

◆ CC_UART_0_ADDR

#define CC_UART_0_ADDR 0x48U

◆ CC_UART_0_DEFAULT

#define CC_UART_0_DEFAULT 0x42U

◆ CC_UART_PT_0_ADDR

#define CC_UART_PT_0_ADDR 0x4FU

◆ CC_UART_PT_0_DEFAULT

#define CC_UART_PT_0_DEFAULT 0x00U

◆ CFG_BLOCK_DEV_REG0_ADDR

#define CFG_BLOCK_DEV_REG0_ADDR 0x00U

◆ CFG_BLOCK_DEV_REG0_MASK

#define CFG_BLOCK_DEV_REG0_MASK 0x01U

◆ CFG_BLOCK_DEV_REG0_POS

#define CFG_BLOCK_DEV_REG0_POS 0U

◆ CFGI_INFOFR_TR0_ADDR

#define CFGI_INFOFR_TR0_ADDR 0x78U

◆ CFGI_INFOFR_TR0_DEFAULT

#define CFGI_INFOFR_TR0_DEFAULT 0xF0U

◆ CFGI_INFOFR_TR3_ADDR

#define CFGI_INFOFR_TR3_ADDR 0x7BU

◆ CFGI_INFOFR_TR3_DEFAULT

#define CFGI_INFOFR_TR3_DEFAULT 0x00U

◆ CFGI_INFOFR_TR4_ADDR

#define CFGI_INFOFR_TR4_ADDR 0x7CU

◆ CFGI_INFOFR_TR4_DEFAULT

#define CFGI_INFOFR_TR4_DEFAULT 0xFFU

◆ CFGL_GPIO_ARQ0_ADDR

#define CFGL_GPIO_ARQ0_ADDR 0x95U

◆ CFGL_GPIO_ARQ0_DEFAULT

#define CFGL_GPIO_ARQ0_DEFAULT 0x98U

◆ CFGL_GPIO_ARQ1_ADDR

#define CFGL_GPIO_ARQ1_ADDR 0x96U

◆ CFGL_GPIO_ARQ1_DEFAULT

#define CFGL_GPIO_ARQ1_DEFAULT 0x72U

◆ CFGL_GPIO_ARQ2_ADDR

#define CFGL_GPIO_ARQ2_ADDR 0x97U

◆ CFGL_GPIO_ARQ2_DEFAULT

#define CFGL_GPIO_ARQ2_DEFAULT 0x00U

◆ CFGL_GPIO_ARQ2_MASK

#define CFGL_GPIO_ARQ2_MASK (0xFFU)

◆ CFGL_GPIO_TR0_ADDR

#define CFGL_GPIO_TR0_ADDR 0x90U

◆ CFGL_GPIO_TR0_DEFAULT

#define CFGL_GPIO_TR0_DEFAULT 0xF0U

◆ CFGL_GPIO_TR3_ADDR

#define CFGL_GPIO_TR3_ADDR 0x93U

◆ CFGL_GPIO_TR3_DEFAULT

#define CFGL_GPIO_TR3_DEFAULT 0x00U

◆ CFGL_GPIO_TR4_ADDR

#define CFGL_GPIO_TR4_ADDR 0x94U

◆ CFGL_GPIO_TR4_DEFAULT

#define CFGL_GPIO_TR4_DEFAULT 0xFFU

◆ CFGL_IIC_X_ARQ0_ADDR

#define CFGL_IIC_X_ARQ0_ADDR 0xA5U

◆ CFGL_IIC_X_ARQ0_DEFAULT

#define CFGL_IIC_X_ARQ0_DEFAULT 0x98U

◆ CFGL_IIC_X_ARQ1_ADDR

#define CFGL_IIC_X_ARQ1_ADDR 0xA6U

◆ CFGL_IIC_X_ARQ1_DEFAULT

#define CFGL_IIC_X_ARQ1_DEFAULT 0x72U

◆ CFGL_IIC_X_ARQ2_ADDR

#define CFGL_IIC_X_ARQ2_ADDR 0xA7U

◆ CFGL_IIC_X_ARQ2_DEFAULT

#define CFGL_IIC_X_ARQ2_DEFAULT 0x00U

◆ CFGL_IIC_X_ARQ2_MASK

#define CFGL_IIC_X_ARQ2_MASK (0xFFU)

◆ CFGL_IIC_X_TR0_ADDR

#define CFGL_IIC_X_TR0_ADDR 0xA0U

◆ CFGL_IIC_X_TR0_DEFAULT

#define CFGL_IIC_X_TR0_DEFAULT 0xF0U

◆ CFGL_IIC_X_TR3_ADDR

#define CFGL_IIC_X_TR3_ADDR 0xA3U

◆ CFGL_IIC_X_TR3_DEFAULT

#define CFGL_IIC_X_TR3_DEFAULT 0x00U

◆ CFGL_IIC_X_TR4_ADDR

#define CFGL_IIC_X_TR4_ADDR 0xA4U

◆ CFGL_IIC_X_TR4_DEFAULT

#define CFGL_IIC_X_TR4_DEFAULT 0xFFU

◆ CFGL_IIC_Y_ARQ0_ADDR

#define CFGL_IIC_Y_ARQ0_ADDR 0xADU

◆ CFGL_IIC_Y_ARQ0_DEFAULT

#define CFGL_IIC_Y_ARQ0_DEFAULT 0x98U

◆ CFGL_IIC_Y_ARQ1_ADDR

#define CFGL_IIC_Y_ARQ1_ADDR 0xAEU

◆ CFGL_IIC_Y_ARQ1_DEFAULT

#define CFGL_IIC_Y_ARQ1_DEFAULT 0x72U

◆ CFGL_IIC_Y_ARQ2_ADDR

#define CFGL_IIC_Y_ARQ2_ADDR 0xAFU

◆ CFGL_IIC_Y_ARQ2_DEFAULT

#define CFGL_IIC_Y_ARQ2_DEFAULT 0x00U

◆ CFGL_IIC_Y_ARQ2_MASK

#define CFGL_IIC_Y_ARQ2_MASK (0xFFU)

◆ CFGL_IIC_Y_TR0_ADDR

#define CFGL_IIC_Y_TR0_ADDR 0xA8U

◆ CFGL_IIC_Y_TR0_DEFAULT

#define CFGL_IIC_Y_TR0_DEFAULT 0xF0U

◆ CFGL_IIC_Y_TR3_ADDR

#define CFGL_IIC_Y_TR3_ADDR 0xABU

◆ CFGL_IIC_Y_TR3_DEFAULT

#define CFGL_IIC_Y_TR3_DEFAULT 0x00U

◆ CFGL_IIC_Y_TR4_ADDR

#define CFGL_IIC_Y_TR4_ADDR 0xACU

◆ CFGL_IIC_Y_TR4_DEFAULT

#define CFGL_IIC_Y_TR4_DEFAULT 0xFFU

◆ CFGL_SPI_ARQ0_ADDR

#define CFGL_SPI_ARQ0_ADDR 0x85U

◆ CFGL_SPI_ARQ0_DEFAULT

#define CFGL_SPI_ARQ0_DEFAULT 0x98U

◆ CFGL_SPI_ARQ1_ADDR

#define CFGL_SPI_ARQ1_ADDR 0x86U

◆ CFGL_SPI_ARQ1_DEFAULT

#define CFGL_SPI_ARQ1_DEFAULT 0x72U

◆ CFGL_SPI_ARQ2_ADDR

#define CFGL_SPI_ARQ2_ADDR 0x87U

◆ CFGL_SPI_ARQ2_DEFAULT

#define CFGL_SPI_ARQ2_DEFAULT 0x00U

◆ CFGL_SPI_ARQ2_MASK

#define CFGL_SPI_ARQ2_MASK (0xFFU)

◆ CFGL_SPI_TR0_ADDR

#define CFGL_SPI_TR0_ADDR 0x80U

◆ CFGL_SPI_TR0_DEFAULT

#define CFGL_SPI_TR0_DEFAULT 0xF0U

◆ CFGL_SPI_TR3_ADDR

#define CFGL_SPI_TR3_ADDR 0x83U

◆ CFGL_SPI_TR3_DEFAULT

#define CFGL_SPI_TR3_DEFAULT 0x00U

◆ CFGL_SPI_TR4_ADDR

#define CFGL_SPI_TR4_ADDR 0x84U

◆ CFGL_SPI_TR4_DEFAULT

#define CFGL_SPI_TR4_DEFAULT 0xFFU

◆ CFGV_VIDEO_Z_TX0_ADDR

#define CFGV_VIDEO_Z_TX0_ADDR 0x58U

◆ CFGV_VIDEO_Z_TX0_DEFAULT

#define CFGV_VIDEO_Z_TX0_DEFAULT 0x30U

◆ CFGV_VIDEO_Z_TX3_ADDR

#define CFGV_VIDEO_Z_TX3_ADDR 0x5BU

◆ CFGV_VIDEO_Z_TX3_DEFAULT

#define CFGV_VIDEO_Z_TX3_DEFAULT 0x02U

◆ CH0_HI_LIMIT_IE_AFE_ADC_INTRIE1_ADDR

#define CH0_HI_LIMIT_IE_AFE_ADC_INTRIE1_ADDR 0x50DU

◆ CH0_HI_LIMIT_IE_AFE_ADC_INTRIE1_MASK

#define CH0_HI_LIMIT_IE_AFE_ADC_INTRIE1_MASK 0x01U

◆ CH0_HI_LIMIT_IE_AFE_ADC_INTRIE1_POS

#define CH0_HI_LIMIT_IE_AFE_ADC_INTRIE1_POS 0U

◆ CH0_HI_LIMIT_IF_AFE_ADC_INTR1_ADDR

#define CH0_HI_LIMIT_IF_AFE_ADC_INTR1_ADDR 0x511U

◆ CH0_HI_LIMIT_IF_AFE_ADC_INTR1_MASK

#define CH0_HI_LIMIT_IF_AFE_ADC_INTR1_MASK 0x01U

◆ CH0_HI_LIMIT_IF_AFE_ADC_INTR1_POS

#define CH0_HI_LIMIT_IF_AFE_ADC_INTR1_POS 0U

◆ CH0_LO_LIMIT_IE_AFE_ADC_INTRIE2_ADDR

#define CH0_LO_LIMIT_IE_AFE_ADC_INTRIE2_ADDR 0x50EU

◆ CH0_LO_LIMIT_IE_AFE_ADC_INTRIE2_MASK

#define CH0_LO_LIMIT_IE_AFE_ADC_INTRIE2_MASK 0x01U

◆ CH0_LO_LIMIT_IE_AFE_ADC_INTRIE2_POS

#define CH0_LO_LIMIT_IE_AFE_ADC_INTRIE2_POS 0U

◆ CH0_LO_LIMIT_IF_AFE_ADC_INTR2_ADDR

#define CH0_LO_LIMIT_IF_AFE_ADC_INTR2_ADDR 0x512U

◆ CH0_LO_LIMIT_IF_AFE_ADC_INTR2_MASK

#define CH0_LO_LIMIT_IF_AFE_ADC_INTR2_MASK 0x01U

◆ CH0_LO_LIMIT_IF_AFE_ADC_INTR2_POS

#define CH0_LO_LIMIT_IF_AFE_ADC_INTR2_POS 0U

◆ CH1_HI_LIMIT_IE_AFE_ADC_INTRIE1_ADDR

#define CH1_HI_LIMIT_IE_AFE_ADC_INTRIE1_ADDR 0x50DU

◆ CH1_HI_LIMIT_IE_AFE_ADC_INTRIE1_MASK

#define CH1_HI_LIMIT_IE_AFE_ADC_INTRIE1_MASK 0x02U

◆ CH1_HI_LIMIT_IE_AFE_ADC_INTRIE1_POS

#define CH1_HI_LIMIT_IE_AFE_ADC_INTRIE1_POS 1U

◆ CH1_HI_LIMIT_IF_AFE_ADC_INTR1_ADDR

#define CH1_HI_LIMIT_IF_AFE_ADC_INTR1_ADDR 0x511U

◆ CH1_HI_LIMIT_IF_AFE_ADC_INTR1_MASK

#define CH1_HI_LIMIT_IF_AFE_ADC_INTR1_MASK 0x02U

◆ CH1_HI_LIMIT_IF_AFE_ADC_INTR1_POS

#define CH1_HI_LIMIT_IF_AFE_ADC_INTR1_POS 1U

◆ CH1_LO_LIMIT_IE_AFE_ADC_INTRIE2_ADDR

#define CH1_LO_LIMIT_IE_AFE_ADC_INTRIE2_ADDR 0x50EU

◆ CH1_LO_LIMIT_IE_AFE_ADC_INTRIE2_MASK

#define CH1_LO_LIMIT_IE_AFE_ADC_INTRIE2_MASK 0x02U

◆ CH1_LO_LIMIT_IE_AFE_ADC_INTRIE2_POS

#define CH1_LO_LIMIT_IE_AFE_ADC_INTRIE2_POS 1U

◆ CH1_LO_LIMIT_IF_AFE_ADC_INTR2_ADDR

#define CH1_LO_LIMIT_IF_AFE_ADC_INTR2_ADDR 0x512U

◆ CH1_LO_LIMIT_IF_AFE_ADC_INTR2_MASK

#define CH1_LO_LIMIT_IF_AFE_ADC_INTR2_MASK 0x02U

◆ CH1_LO_LIMIT_IF_AFE_ADC_INTR2_POS

#define CH1_LO_LIMIT_IF_AFE_ADC_INTR2_POS 1U

◆ CH2_HI_LIMIT_IE_AFE_ADC_INTRIE1_ADDR

#define CH2_HI_LIMIT_IE_AFE_ADC_INTRIE1_ADDR 0x50DU

◆ CH2_HI_LIMIT_IE_AFE_ADC_INTRIE1_MASK

#define CH2_HI_LIMIT_IE_AFE_ADC_INTRIE1_MASK 0x04U

◆ CH2_HI_LIMIT_IE_AFE_ADC_INTRIE1_POS

#define CH2_HI_LIMIT_IE_AFE_ADC_INTRIE1_POS 2U

◆ CH2_HI_LIMIT_IF_AFE_ADC_INTR1_ADDR

#define CH2_HI_LIMIT_IF_AFE_ADC_INTR1_ADDR 0x511U

◆ CH2_HI_LIMIT_IF_AFE_ADC_INTR1_MASK

#define CH2_HI_LIMIT_IF_AFE_ADC_INTR1_MASK 0x04U

◆ CH2_HI_LIMIT_IF_AFE_ADC_INTR1_POS

#define CH2_HI_LIMIT_IF_AFE_ADC_INTR1_POS 2U

◆ CH2_LO_LIMIT_IE_AFE_ADC_INTRIE2_ADDR

#define CH2_LO_LIMIT_IE_AFE_ADC_INTRIE2_ADDR 0x50EU

◆ CH2_LO_LIMIT_IE_AFE_ADC_INTRIE2_MASK

#define CH2_LO_LIMIT_IE_AFE_ADC_INTRIE2_MASK 0x04U

◆ CH2_LO_LIMIT_IE_AFE_ADC_INTRIE2_POS

#define CH2_LO_LIMIT_IE_AFE_ADC_INTRIE2_POS 2U

◆ CH2_LO_LIMIT_IF_AFE_ADC_INTR2_ADDR

#define CH2_LO_LIMIT_IF_AFE_ADC_INTR2_ADDR 0x512U

◆ CH2_LO_LIMIT_IF_AFE_ADC_INTR2_MASK

#define CH2_LO_LIMIT_IF_AFE_ADC_INTR2_MASK 0x04U

◆ CH2_LO_LIMIT_IF_AFE_ADC_INTR2_POS

#define CH2_LO_LIMIT_IF_AFE_ADC_INTR2_POS 2U

◆ CH3_HI_LIMIT_IE_AFE_ADC_INTRIE1_ADDR

#define CH3_HI_LIMIT_IE_AFE_ADC_INTRIE1_ADDR 0x50DU

◆ CH3_HI_LIMIT_IE_AFE_ADC_INTRIE1_MASK

#define CH3_HI_LIMIT_IE_AFE_ADC_INTRIE1_MASK 0x08U

◆ CH3_HI_LIMIT_IE_AFE_ADC_INTRIE1_POS

#define CH3_HI_LIMIT_IE_AFE_ADC_INTRIE1_POS 3U

◆ CH3_HI_LIMIT_IF_AFE_ADC_INTR1_ADDR

#define CH3_HI_LIMIT_IF_AFE_ADC_INTR1_ADDR 0x511U

◆ CH3_HI_LIMIT_IF_AFE_ADC_INTR1_MASK

#define CH3_HI_LIMIT_IF_AFE_ADC_INTR1_MASK 0x08U

◆ CH3_HI_LIMIT_IF_AFE_ADC_INTR1_POS

#define CH3_HI_LIMIT_IF_AFE_ADC_INTR1_POS 3U

◆ CH3_LO_LIMIT_IE_AFE_ADC_INTRIE2_ADDR

#define CH3_LO_LIMIT_IE_AFE_ADC_INTRIE2_ADDR 0x50EU

◆ CH3_LO_LIMIT_IE_AFE_ADC_INTRIE2_MASK

#define CH3_LO_LIMIT_IE_AFE_ADC_INTRIE2_MASK 0x08U

◆ CH3_LO_LIMIT_IE_AFE_ADC_INTRIE2_POS

#define CH3_LO_LIMIT_IE_AFE_ADC_INTRIE2_POS 3U

◆ CH3_LO_LIMIT_IF_AFE_ADC_INTR2_ADDR

#define CH3_LO_LIMIT_IF_AFE_ADC_INTR2_ADDR 0x512U

◆ CH3_LO_LIMIT_IF_AFE_ADC_INTR2_MASK

#define CH3_LO_LIMIT_IF_AFE_ADC_INTR2_MASK 0x08U

◆ CH3_LO_LIMIT_IF_AFE_ADC_INTR2_POS

#define CH3_LO_LIMIT_IF_AFE_ADC_INTR2_POS 3U

◆ CH4_HI_LIMIT_IE_AFE_ADC_INTRIE1_ADDR

#define CH4_HI_LIMIT_IE_AFE_ADC_INTRIE1_ADDR 0x50DU

◆ CH4_HI_LIMIT_IE_AFE_ADC_INTRIE1_MASK

#define CH4_HI_LIMIT_IE_AFE_ADC_INTRIE1_MASK 0x10U

◆ CH4_HI_LIMIT_IE_AFE_ADC_INTRIE1_POS

#define CH4_HI_LIMIT_IE_AFE_ADC_INTRIE1_POS 4U

◆ CH4_HI_LIMIT_IF_AFE_ADC_INTR1_ADDR

#define CH4_HI_LIMIT_IF_AFE_ADC_INTR1_ADDR 0x511U

◆ CH4_HI_LIMIT_IF_AFE_ADC_INTR1_MASK

#define CH4_HI_LIMIT_IF_AFE_ADC_INTR1_MASK 0x10U

◆ CH4_HI_LIMIT_IF_AFE_ADC_INTR1_POS

#define CH4_HI_LIMIT_IF_AFE_ADC_INTR1_POS 4U

◆ CH4_LO_LIMIT_IE_AFE_ADC_INTRIE2_ADDR

#define CH4_LO_LIMIT_IE_AFE_ADC_INTRIE2_ADDR 0x50EU

◆ CH4_LO_LIMIT_IE_AFE_ADC_INTRIE2_MASK

#define CH4_LO_LIMIT_IE_AFE_ADC_INTRIE2_MASK 0x10U

◆ CH4_LO_LIMIT_IE_AFE_ADC_INTRIE2_POS

#define CH4_LO_LIMIT_IE_AFE_ADC_INTRIE2_POS 4U

◆ CH4_LO_LIMIT_IF_AFE_ADC_INTR2_ADDR

#define CH4_LO_LIMIT_IF_AFE_ADC_INTR2_ADDR 0x512U

◆ CH4_LO_LIMIT_IF_AFE_ADC_INTR2_MASK

#define CH4_LO_LIMIT_IF_AFE_ADC_INTR2_MASK 0x10U

◆ CH4_LO_LIMIT_IF_AFE_ADC_INTR2_POS

#define CH4_LO_LIMIT_IF_AFE_ADC_INTR2_POS 4U

◆ CH5_HI_LIMIT_IE_AFE_ADC_INTRIE1_ADDR

#define CH5_HI_LIMIT_IE_AFE_ADC_INTRIE1_ADDR 0x50DU

◆ CH5_HI_LIMIT_IE_AFE_ADC_INTRIE1_MASK

#define CH5_HI_LIMIT_IE_AFE_ADC_INTRIE1_MASK 0x20U

◆ CH5_HI_LIMIT_IE_AFE_ADC_INTRIE1_POS

#define CH5_HI_LIMIT_IE_AFE_ADC_INTRIE1_POS 5U

◆ CH5_HI_LIMIT_IF_AFE_ADC_INTR1_ADDR

#define CH5_HI_LIMIT_IF_AFE_ADC_INTR1_ADDR 0x511U

◆ CH5_HI_LIMIT_IF_AFE_ADC_INTR1_MASK

#define CH5_HI_LIMIT_IF_AFE_ADC_INTR1_MASK 0x20U

◆ CH5_HI_LIMIT_IF_AFE_ADC_INTR1_POS

#define CH5_HI_LIMIT_IF_AFE_ADC_INTR1_POS 5U

◆ CH5_LO_LIMIT_IE_AFE_ADC_INTRIE2_ADDR

#define CH5_LO_LIMIT_IE_AFE_ADC_INTRIE2_ADDR 0x50EU

◆ CH5_LO_LIMIT_IE_AFE_ADC_INTRIE2_MASK

#define CH5_LO_LIMIT_IE_AFE_ADC_INTRIE2_MASK 0x20U

◆ CH5_LO_LIMIT_IE_AFE_ADC_INTRIE2_POS

#define CH5_LO_LIMIT_IE_AFE_ADC_INTRIE2_POS 5U

◆ CH5_LO_LIMIT_IF_AFE_ADC_INTR2_ADDR

#define CH5_LO_LIMIT_IF_AFE_ADC_INTR2_ADDR 0x512U

◆ CH5_LO_LIMIT_IF_AFE_ADC_INTR2_MASK

#define CH5_LO_LIMIT_IF_AFE_ADC_INTR2_MASK 0x20U

◆ CH5_LO_LIMIT_IF_AFE_ADC_INTR2_POS

#define CH5_LO_LIMIT_IF_AFE_ADC_INTR2_POS 5U

◆ CH6_HI_LIMIT_IE_AFE_ADC_INTRIE1_ADDR

#define CH6_HI_LIMIT_IE_AFE_ADC_INTRIE1_ADDR 0x50DU

◆ CH6_HI_LIMIT_IE_AFE_ADC_INTRIE1_MASK

#define CH6_HI_LIMIT_IE_AFE_ADC_INTRIE1_MASK 0x40U

◆ CH6_HI_LIMIT_IE_AFE_ADC_INTRIE1_POS

#define CH6_HI_LIMIT_IE_AFE_ADC_INTRIE1_POS 6U

◆ CH6_HI_LIMIT_IF_AFE_ADC_INTR1_ADDR

#define CH6_HI_LIMIT_IF_AFE_ADC_INTR1_ADDR 0x511U

◆ CH6_HI_LIMIT_IF_AFE_ADC_INTR1_MASK

#define CH6_HI_LIMIT_IF_AFE_ADC_INTR1_MASK 0x40U

◆ CH6_HI_LIMIT_IF_AFE_ADC_INTR1_POS

#define CH6_HI_LIMIT_IF_AFE_ADC_INTR1_POS 6U

◆ CH6_LO_LIMIT_IE_AFE_ADC_INTRIE2_ADDR

#define CH6_LO_LIMIT_IE_AFE_ADC_INTRIE2_ADDR 0x50EU

◆ CH6_LO_LIMIT_IE_AFE_ADC_INTRIE2_MASK

#define CH6_LO_LIMIT_IE_AFE_ADC_INTRIE2_MASK 0x40U

◆ CH6_LO_LIMIT_IE_AFE_ADC_INTRIE2_POS

#define CH6_LO_LIMIT_IE_AFE_ADC_INTRIE2_POS 6U

◆ CH6_LO_LIMIT_IF_AFE_ADC_INTR2_ADDR

#define CH6_LO_LIMIT_IF_AFE_ADC_INTR2_ADDR 0x512U

◆ CH6_LO_LIMIT_IF_AFE_ADC_INTR2_MASK

#define CH6_LO_LIMIT_IF_AFE_ADC_INTR2_MASK 0x40U

◆ CH6_LO_LIMIT_IF_AFE_ADC_INTR2_POS

#define CH6_LO_LIMIT_IF_AFE_ADC_INTR2_POS 6U

◆ CH7_HI_LIMIT_IE_AFE_ADC_INTRIE1_ADDR

#define CH7_HI_LIMIT_IE_AFE_ADC_INTRIE1_ADDR 0x50DU

◆ CH7_HI_LIMIT_IE_AFE_ADC_INTRIE1_MASK

#define CH7_HI_LIMIT_IE_AFE_ADC_INTRIE1_MASK 0x80U

◆ CH7_HI_LIMIT_IE_AFE_ADC_INTRIE1_POS

#define CH7_HI_LIMIT_IE_AFE_ADC_INTRIE1_POS 7U

◆ CH7_HI_LIMIT_IF_AFE_ADC_INTR1_ADDR

#define CH7_HI_LIMIT_IF_AFE_ADC_INTR1_ADDR 0x511U

◆ CH7_HI_LIMIT_IF_AFE_ADC_INTR1_MASK

#define CH7_HI_LIMIT_IF_AFE_ADC_INTR1_MASK 0x80U

◆ CH7_HI_LIMIT_IF_AFE_ADC_INTR1_POS

#define CH7_HI_LIMIT_IF_AFE_ADC_INTR1_POS 7U

◆ CH7_LO_LIMIT_IE_AFE_ADC_INTRIE2_ADDR

#define CH7_LO_LIMIT_IE_AFE_ADC_INTRIE2_ADDR 0x50EU

◆ CH7_LO_LIMIT_IE_AFE_ADC_INTRIE2_MASK

#define CH7_LO_LIMIT_IE_AFE_ADC_INTRIE2_MASK 0x80U

◆ CH7_LO_LIMIT_IE_AFE_ADC_INTRIE2_POS

#define CH7_LO_LIMIT_IE_AFE_ADC_INTRIE2_POS 7U

◆ CH7_LO_LIMIT_IF_AFE_ADC_INTR2_ADDR

#define CH7_LO_LIMIT_IF_AFE_ADC_INTR2_ADDR 0x512U

◆ CH7_LO_LIMIT_IF_AFE_ADC_INTR2_MASK

#define CH7_LO_LIMIT_IF_AFE_ADC_INTR2_MASK 0x80U

◆ CH7_LO_LIMIT_IF_AFE_ADC_INTR2_POS

#define CH7_LO_LIMIT_IF_AFE_ADC_INTR2_POS 7U

◆ CH_SEL0_AFE_ADC_LIMIT0_3_ADDR

#define CH_SEL0_AFE_ADC_LIMIT0_3_ADDR 0x517U

◆ CH_SEL0_AFE_ADC_LIMIT0_3_MASK

#define CH_SEL0_AFE_ADC_LIMIT0_3_MASK 0x0FU

◆ CH_SEL0_AFE_ADC_LIMIT0_3_POS

#define CH_SEL0_AFE_ADC_LIMIT0_3_POS 0U

◆ CH_SEL1_AFE_ADC_LIMIT1_3_ADDR

#define CH_SEL1_AFE_ADC_LIMIT1_3_ADDR 0x51BU

◆ CH_SEL1_AFE_ADC_LIMIT1_3_MASK

#define CH_SEL1_AFE_ADC_LIMIT1_3_MASK 0x0FU

◆ CH_SEL1_AFE_ADC_LIMIT1_3_POS

#define CH_SEL1_AFE_ADC_LIMIT1_3_POS 0U

◆ CH_SEL2_AFE_ADC_LIMIT2_3_ADDR

#define CH_SEL2_AFE_ADC_LIMIT2_3_ADDR 0x51FU

◆ CH_SEL2_AFE_ADC_LIMIT2_3_MASK

#define CH_SEL2_AFE_ADC_LIMIT2_3_MASK 0x0FU

◆ CH_SEL2_AFE_ADC_LIMIT2_3_POS

#define CH_SEL2_AFE_ADC_LIMIT2_3_POS 0U

◆ CH_SEL3_AFE_ADC_LIMIT3_3_ADDR

#define CH_SEL3_AFE_ADC_LIMIT3_3_ADDR 0x523U

◆ CH_SEL3_AFE_ADC_LIMIT3_3_MASK

#define CH_SEL3_AFE_ADC_LIMIT3_3_MASK 0x0FU

◆ CH_SEL3_AFE_ADC_LIMIT3_3_POS

#define CH_SEL3_AFE_ADC_LIMIT3_3_POS 0U

◆ CH_SEL4_AFE_ADC_LIMIT4_3_ADDR

#define CH_SEL4_AFE_ADC_LIMIT4_3_ADDR 0x527U

◆ CH_SEL4_AFE_ADC_LIMIT4_3_MASK

#define CH_SEL4_AFE_ADC_LIMIT4_3_MASK 0x0FU

◆ CH_SEL4_AFE_ADC_LIMIT4_3_POS

#define CH_SEL4_AFE_ADC_LIMIT4_3_POS 0U

◆ CH_SEL5_AFE_ADC_LIMIT5_3_ADDR

#define CH_SEL5_AFE_ADC_LIMIT5_3_ADDR 0x52BU

◆ CH_SEL5_AFE_ADC_LIMIT5_3_MASK

#define CH_SEL5_AFE_ADC_LIMIT5_3_MASK 0x0FU

◆ CH_SEL5_AFE_ADC_LIMIT5_3_POS

#define CH_SEL5_AFE_ADC_LIMIT5_3_POS 0U

◆ CH_SEL6_AFE_ADC_LIMIT6_3_ADDR

#define CH_SEL6_AFE_ADC_LIMIT6_3_ADDR 0x52FU

◆ CH_SEL6_AFE_ADC_LIMIT6_3_MASK

#define CH_SEL6_AFE_ADC_LIMIT6_3_MASK 0x0FU

◆ CH_SEL6_AFE_ADC_LIMIT6_3_POS

#define CH_SEL6_AFE_ADC_LIMIT6_3_POS 0U

◆ CH_SEL7_AFE_ADC_LIMIT7_3_ADDR

#define CH_SEL7_AFE_ADC_LIMIT7_3_ADDR 0x533U

◆ CH_SEL7_AFE_ADC_LIMIT7_3_MASK

#define CH_SEL7_AFE_ADC_LIMIT7_3_MASK 0x0FU

◆ CH_SEL7_AFE_ADC_LIMIT7_3_POS

#define CH_SEL7_AFE_ADC_LIMIT7_3_POS 0U

◆ CHECK_CRC_FUNC_SAFE_REGCRC0_ADDR

#define CHECK_CRC_FUNC_SAFE_REGCRC0_ADDR 0x1D00U

◆ CHECK_CRC_FUNC_SAFE_REGCRC0_MASK

#define CHECK_CRC_FUNC_SAFE_REGCRC0_MASK 0x02U

◆ CHECK_CRC_FUNC_SAFE_REGCRC0_POS

#define CHECK_CRC_FUNC_SAFE_REGCRC0_POS 1U

◆ CHHILIMIT_H0_AFE_ADC_LIMIT0_2_ADDR

#define CHHILIMIT_H0_AFE_ADC_LIMIT0_2_ADDR 0x516U

◆ CHHILIMIT_H0_AFE_ADC_LIMIT0_2_MASK

#define CHHILIMIT_H0_AFE_ADC_LIMIT0_2_MASK 0x3FU

◆ CHHILIMIT_H0_AFE_ADC_LIMIT0_2_POS

#define CHHILIMIT_H0_AFE_ADC_LIMIT0_2_POS 0U

◆ CHHILIMIT_H1_AFE_ADC_LIMIT1_2_ADDR

#define CHHILIMIT_H1_AFE_ADC_LIMIT1_2_ADDR 0x51AU

◆ CHHILIMIT_H1_AFE_ADC_LIMIT1_2_MASK

#define CHHILIMIT_H1_AFE_ADC_LIMIT1_2_MASK 0x3FU

◆ CHHILIMIT_H1_AFE_ADC_LIMIT1_2_POS

#define CHHILIMIT_H1_AFE_ADC_LIMIT1_2_POS 0U

◆ CHHILIMIT_H2_AFE_ADC_LIMIT2_2_ADDR

#define CHHILIMIT_H2_AFE_ADC_LIMIT2_2_ADDR 0x51EU

◆ CHHILIMIT_H2_AFE_ADC_LIMIT2_2_MASK

#define CHHILIMIT_H2_AFE_ADC_LIMIT2_2_MASK 0x3FU

◆ CHHILIMIT_H2_AFE_ADC_LIMIT2_2_POS

#define CHHILIMIT_H2_AFE_ADC_LIMIT2_2_POS 0U

◆ CHHILIMIT_H3_AFE_ADC_LIMIT3_2_ADDR

#define CHHILIMIT_H3_AFE_ADC_LIMIT3_2_ADDR 0x522U

◆ CHHILIMIT_H3_AFE_ADC_LIMIT3_2_MASK

#define CHHILIMIT_H3_AFE_ADC_LIMIT3_2_MASK 0x3FU

◆ CHHILIMIT_H3_AFE_ADC_LIMIT3_2_POS

#define CHHILIMIT_H3_AFE_ADC_LIMIT3_2_POS 0U

◆ CHHILIMIT_H4_AFE_ADC_LIMIT4_2_ADDR

#define CHHILIMIT_H4_AFE_ADC_LIMIT4_2_ADDR 0x526U

◆ CHHILIMIT_H4_AFE_ADC_LIMIT4_2_MASK

#define CHHILIMIT_H4_AFE_ADC_LIMIT4_2_MASK 0x3FU

◆ CHHILIMIT_H4_AFE_ADC_LIMIT4_2_POS

#define CHHILIMIT_H4_AFE_ADC_LIMIT4_2_POS 0U

◆ CHHILIMIT_H5_AFE_ADC_LIMIT5_2_ADDR

#define CHHILIMIT_H5_AFE_ADC_LIMIT5_2_ADDR 0x52AU

◆ CHHILIMIT_H5_AFE_ADC_LIMIT5_2_MASK

#define CHHILIMIT_H5_AFE_ADC_LIMIT5_2_MASK 0x3FU

◆ CHHILIMIT_H5_AFE_ADC_LIMIT5_2_POS

#define CHHILIMIT_H5_AFE_ADC_LIMIT5_2_POS 0U

◆ CHHILIMIT_H6_AFE_ADC_LIMIT6_2_ADDR

#define CHHILIMIT_H6_AFE_ADC_LIMIT6_2_ADDR 0x52EU

◆ CHHILIMIT_H6_AFE_ADC_LIMIT6_2_MASK

#define CHHILIMIT_H6_AFE_ADC_LIMIT6_2_MASK 0x3FU

◆ CHHILIMIT_H6_AFE_ADC_LIMIT6_2_POS

#define CHHILIMIT_H6_AFE_ADC_LIMIT6_2_POS 0U

◆ CHHILIMIT_H7_AFE_ADC_LIMIT7_2_ADDR

#define CHHILIMIT_H7_AFE_ADC_LIMIT7_2_ADDR 0x532U

◆ CHHILIMIT_H7_AFE_ADC_LIMIT7_2_MASK

#define CHHILIMIT_H7_AFE_ADC_LIMIT7_2_MASK 0x3FU

◆ CHHILIMIT_H7_AFE_ADC_LIMIT7_2_POS

#define CHHILIMIT_H7_AFE_ADC_LIMIT7_2_POS 0U

◆ CHHILIMIT_L0_AFE_ADC_LIMIT0_1_ADDR

#define CHHILIMIT_L0_AFE_ADC_LIMIT0_1_ADDR 0x515U

◆ CHHILIMIT_L0_AFE_ADC_LIMIT0_1_MASK

#define CHHILIMIT_L0_AFE_ADC_LIMIT0_1_MASK 0xF0U

◆ CHHILIMIT_L0_AFE_ADC_LIMIT0_1_POS

#define CHHILIMIT_L0_AFE_ADC_LIMIT0_1_POS 4U

◆ CHHILIMIT_L1_AFE_ADC_LIMIT1_1_ADDR

#define CHHILIMIT_L1_AFE_ADC_LIMIT1_1_ADDR 0x519U

◆ CHHILIMIT_L1_AFE_ADC_LIMIT1_1_MASK

#define CHHILIMIT_L1_AFE_ADC_LIMIT1_1_MASK 0xF0U

◆ CHHILIMIT_L1_AFE_ADC_LIMIT1_1_POS

#define CHHILIMIT_L1_AFE_ADC_LIMIT1_1_POS 4U

◆ CHHILIMIT_L2_AFE_ADC_LIMIT2_1_ADDR

#define CHHILIMIT_L2_AFE_ADC_LIMIT2_1_ADDR 0x51DU

◆ CHHILIMIT_L2_AFE_ADC_LIMIT2_1_MASK

#define CHHILIMIT_L2_AFE_ADC_LIMIT2_1_MASK 0xF0U

◆ CHHILIMIT_L2_AFE_ADC_LIMIT2_1_POS

#define CHHILIMIT_L2_AFE_ADC_LIMIT2_1_POS 4U

◆ CHHILIMIT_L3_AFE_ADC_LIMIT3_1_ADDR

#define CHHILIMIT_L3_AFE_ADC_LIMIT3_1_ADDR 0x521U

◆ CHHILIMIT_L3_AFE_ADC_LIMIT3_1_MASK

#define CHHILIMIT_L3_AFE_ADC_LIMIT3_1_MASK 0xF0U

◆ CHHILIMIT_L3_AFE_ADC_LIMIT3_1_POS

#define CHHILIMIT_L3_AFE_ADC_LIMIT3_1_POS 4U

◆ CHHILIMIT_L4_AFE_ADC_LIMIT4_1_ADDR

#define CHHILIMIT_L4_AFE_ADC_LIMIT4_1_ADDR 0x525U

◆ CHHILIMIT_L4_AFE_ADC_LIMIT4_1_MASK

#define CHHILIMIT_L4_AFE_ADC_LIMIT4_1_MASK 0xF0U

◆ CHHILIMIT_L4_AFE_ADC_LIMIT4_1_POS

#define CHHILIMIT_L4_AFE_ADC_LIMIT4_1_POS 4U

◆ CHHILIMIT_L5_AFE_ADC_LIMIT5_1_ADDR

#define CHHILIMIT_L5_AFE_ADC_LIMIT5_1_ADDR 0x529U

◆ CHHILIMIT_L5_AFE_ADC_LIMIT5_1_MASK

#define CHHILIMIT_L5_AFE_ADC_LIMIT5_1_MASK 0xF0U

◆ CHHILIMIT_L5_AFE_ADC_LIMIT5_1_POS

#define CHHILIMIT_L5_AFE_ADC_LIMIT5_1_POS 4U

◆ CHHILIMIT_L6_AFE_ADC_LIMIT6_1_ADDR

#define CHHILIMIT_L6_AFE_ADC_LIMIT6_1_ADDR 0x52DU

◆ CHHILIMIT_L6_AFE_ADC_LIMIT6_1_MASK

#define CHHILIMIT_L6_AFE_ADC_LIMIT6_1_MASK 0xF0U

◆ CHHILIMIT_L6_AFE_ADC_LIMIT6_1_POS

#define CHHILIMIT_L6_AFE_ADC_LIMIT6_1_POS 4U

◆ CHHILIMIT_L7_AFE_ADC_LIMIT7_1_ADDR

#define CHHILIMIT_L7_AFE_ADC_LIMIT7_1_ADDR 0x531U

◆ CHHILIMIT_L7_AFE_ADC_LIMIT7_1_MASK

#define CHHILIMIT_L7_AFE_ADC_LIMIT7_1_MASK 0xF0U

◆ CHHILIMIT_L7_AFE_ADC_LIMIT7_1_POS

#define CHHILIMIT_L7_AFE_ADC_LIMIT7_1_POS 4U

◆ CHKR_A_H_VTX_Z_VTX33_ADDR

#define CHKR_A_H_VTX_Z_VTX33_ADDR 0x26FU

◆ CHKR_A_H_VTX_Z_VTX33_MASK

#define CHKR_A_H_VTX_Z_VTX33_MASK 0xFFU

◆ CHKR_A_H_VTX_Z_VTX33_POS

#define CHKR_A_H_VTX_Z_VTX33_POS 0U

◆ CHKR_A_L_VTX_Z_VTX31_ADDR

#define CHKR_A_L_VTX_Z_VTX31_ADDR 0x26DU

◆ CHKR_A_L_VTX_Z_VTX31_MASK

#define CHKR_A_L_VTX_Z_VTX31_MASK 0xFFU

◆ CHKR_A_L_VTX_Z_VTX31_POS

#define CHKR_A_L_VTX_Z_VTX31_POS 0U

◆ CHKR_A_M_VTX_Z_VTX32_ADDR

#define CHKR_A_M_VTX_Z_VTX32_ADDR 0x26EU

◆ CHKR_A_M_VTX_Z_VTX32_MASK

#define CHKR_A_M_VTX_Z_VTX32_MASK 0xFFU

◆ CHKR_A_M_VTX_Z_VTX32_POS

#define CHKR_A_M_VTX_Z_VTX32_POS 0U

◆ CHKR_ALT_VTX_Z_VTX39_ADDR

#define CHKR_ALT_VTX_Z_VTX39_ADDR 0x275U

◆ CHKR_ALT_VTX_Z_VTX39_MASK

#define CHKR_ALT_VTX_Z_VTX39_MASK 0xFFU

◆ CHKR_ALT_VTX_Z_VTX39_POS

#define CHKR_ALT_VTX_Z_VTX39_POS 0U

◆ CHKR_B_H_VTX_Z_VTX36_ADDR

#define CHKR_B_H_VTX_Z_VTX36_ADDR 0x272U

◆ CHKR_B_H_VTX_Z_VTX36_MASK

#define CHKR_B_H_VTX_Z_VTX36_MASK 0xFFU

◆ CHKR_B_H_VTX_Z_VTX36_POS

#define CHKR_B_H_VTX_Z_VTX36_POS 0U

◆ CHKR_B_L_VTX_Z_VTX34_ADDR

#define CHKR_B_L_VTX_Z_VTX34_ADDR 0x270U

◆ CHKR_B_L_VTX_Z_VTX34_MASK

#define CHKR_B_L_VTX_Z_VTX34_MASK 0xFFU

◆ CHKR_B_L_VTX_Z_VTX34_POS

#define CHKR_B_L_VTX_Z_VTX34_POS 0U

◆ CHKR_B_M_VTX_Z_VTX35_ADDR

#define CHKR_B_M_VTX_Z_VTX35_ADDR 0x271U

◆ CHKR_B_M_VTX_Z_VTX35_MASK

#define CHKR_B_M_VTX_Z_VTX35_MASK 0xFFU

◆ CHKR_B_M_VTX_Z_VTX35_POS

#define CHKR_B_M_VTX_Z_VTX35_POS 0U

◆ CHKR_RPT_A_VTX_Z_VTX37_ADDR

#define CHKR_RPT_A_VTX_Z_VTX37_ADDR 0x273U

◆ CHKR_RPT_A_VTX_Z_VTX37_MASK

#define CHKR_RPT_A_VTX_Z_VTX37_MASK 0xFFU

◆ CHKR_RPT_A_VTX_Z_VTX37_POS

#define CHKR_RPT_A_VTX_Z_VTX37_POS 0U

◆ CHKR_RPT_B_VTX_Z_VTX38_ADDR

#define CHKR_RPT_B_VTX_Z_VTX38_ADDR 0x274U

◆ CHKR_RPT_B_VTX_Z_VTX38_MASK

#define CHKR_RPT_B_VTX_Z_VTX38_MASK 0xFFU

◆ CHKR_RPT_B_VTX_Z_VTX38_POS

#define CHKR_RPT_B_VTX_Z_VTX38_POS 0U

◆ CHLOLIMIT_H0_AFE_ADC_LIMIT0_1_ADDR

#define CHLOLIMIT_H0_AFE_ADC_LIMIT0_1_ADDR 0x515U

◆ CHLOLIMIT_H0_AFE_ADC_LIMIT0_1_MASK

#define CHLOLIMIT_H0_AFE_ADC_LIMIT0_1_MASK 0x03U

◆ CHLOLIMIT_H0_AFE_ADC_LIMIT0_1_POS

#define CHLOLIMIT_H0_AFE_ADC_LIMIT0_1_POS 0U

◆ CHLOLIMIT_H1_AFE_ADC_LIMIT1_1_ADDR

#define CHLOLIMIT_H1_AFE_ADC_LIMIT1_1_ADDR 0x519U

◆ CHLOLIMIT_H1_AFE_ADC_LIMIT1_1_MASK

#define CHLOLIMIT_H1_AFE_ADC_LIMIT1_1_MASK 0x03U

◆ CHLOLIMIT_H1_AFE_ADC_LIMIT1_1_POS

#define CHLOLIMIT_H1_AFE_ADC_LIMIT1_1_POS 0U

◆ CHLOLIMIT_H2_AFE_ADC_LIMIT2_1_ADDR

#define CHLOLIMIT_H2_AFE_ADC_LIMIT2_1_ADDR 0x51DU

◆ CHLOLIMIT_H2_AFE_ADC_LIMIT2_1_MASK

#define CHLOLIMIT_H2_AFE_ADC_LIMIT2_1_MASK 0x03U

◆ CHLOLIMIT_H2_AFE_ADC_LIMIT2_1_POS

#define CHLOLIMIT_H2_AFE_ADC_LIMIT2_1_POS 0U

◆ CHLOLIMIT_H3_AFE_ADC_LIMIT3_1_ADDR

#define CHLOLIMIT_H3_AFE_ADC_LIMIT3_1_ADDR 0x521U

◆ CHLOLIMIT_H3_AFE_ADC_LIMIT3_1_MASK

#define CHLOLIMIT_H3_AFE_ADC_LIMIT3_1_MASK 0x03U

◆ CHLOLIMIT_H3_AFE_ADC_LIMIT3_1_POS

#define CHLOLIMIT_H3_AFE_ADC_LIMIT3_1_POS 0U

◆ CHLOLIMIT_H4_AFE_ADC_LIMIT4_1_ADDR

#define CHLOLIMIT_H4_AFE_ADC_LIMIT4_1_ADDR 0x525U

◆ CHLOLIMIT_H4_AFE_ADC_LIMIT4_1_MASK

#define CHLOLIMIT_H4_AFE_ADC_LIMIT4_1_MASK 0x03U

◆ CHLOLIMIT_H4_AFE_ADC_LIMIT4_1_POS

#define CHLOLIMIT_H4_AFE_ADC_LIMIT4_1_POS 0U

◆ CHLOLIMIT_H5_AFE_ADC_LIMIT5_1_ADDR

#define CHLOLIMIT_H5_AFE_ADC_LIMIT5_1_ADDR 0x529U

◆ CHLOLIMIT_H5_AFE_ADC_LIMIT5_1_MASK

#define CHLOLIMIT_H5_AFE_ADC_LIMIT5_1_MASK 0x03U

◆ CHLOLIMIT_H5_AFE_ADC_LIMIT5_1_POS

#define CHLOLIMIT_H5_AFE_ADC_LIMIT5_1_POS 0U

◆ CHLOLIMIT_H6_AFE_ADC_LIMIT6_1_ADDR

#define CHLOLIMIT_H6_AFE_ADC_LIMIT6_1_ADDR 0x52DU

◆ CHLOLIMIT_H6_AFE_ADC_LIMIT6_1_MASK

#define CHLOLIMIT_H6_AFE_ADC_LIMIT6_1_MASK 0x03U

◆ CHLOLIMIT_H6_AFE_ADC_LIMIT6_1_POS

#define CHLOLIMIT_H6_AFE_ADC_LIMIT6_1_POS 0U

◆ CHLOLIMIT_H7_AFE_ADC_LIMIT7_1_ADDR

#define CHLOLIMIT_H7_AFE_ADC_LIMIT7_1_ADDR 0x531U

◆ CHLOLIMIT_H7_AFE_ADC_LIMIT7_1_MASK

#define CHLOLIMIT_H7_AFE_ADC_LIMIT7_1_MASK 0x03U

◆ CHLOLIMIT_H7_AFE_ADC_LIMIT7_1_POS

#define CHLOLIMIT_H7_AFE_ADC_LIMIT7_1_POS 0U

◆ CHLOLIMIT_L0_AFE_ADC_LIMIT0_0_ADDR

#define CHLOLIMIT_L0_AFE_ADC_LIMIT0_0_ADDR 0x514U

◆ CHLOLIMIT_L0_AFE_ADC_LIMIT0_0_MASK

#define CHLOLIMIT_L0_AFE_ADC_LIMIT0_0_MASK 0xFFU

◆ CHLOLIMIT_L0_AFE_ADC_LIMIT0_0_POS

#define CHLOLIMIT_L0_AFE_ADC_LIMIT0_0_POS 0U

◆ CHLOLIMIT_L1_AFE_ADC_LIMIT1_0_ADDR

#define CHLOLIMIT_L1_AFE_ADC_LIMIT1_0_ADDR 0x518U

◆ CHLOLIMIT_L1_AFE_ADC_LIMIT1_0_MASK

#define CHLOLIMIT_L1_AFE_ADC_LIMIT1_0_MASK 0xFFU

◆ CHLOLIMIT_L1_AFE_ADC_LIMIT1_0_POS

#define CHLOLIMIT_L1_AFE_ADC_LIMIT1_0_POS 0U

◆ CHLOLIMIT_L2_AFE_ADC_LIMIT2_0_ADDR

#define CHLOLIMIT_L2_AFE_ADC_LIMIT2_0_ADDR 0x51CU

◆ CHLOLIMIT_L2_AFE_ADC_LIMIT2_0_MASK

#define CHLOLIMIT_L2_AFE_ADC_LIMIT2_0_MASK 0xFFU

◆ CHLOLIMIT_L2_AFE_ADC_LIMIT2_0_POS

#define CHLOLIMIT_L2_AFE_ADC_LIMIT2_0_POS 0U

◆ CHLOLIMIT_L3_AFE_ADC_LIMIT3_0_ADDR

#define CHLOLIMIT_L3_AFE_ADC_LIMIT3_0_ADDR 0x520U

◆ CHLOLIMIT_L3_AFE_ADC_LIMIT3_0_MASK

#define CHLOLIMIT_L3_AFE_ADC_LIMIT3_0_MASK 0xFFU

◆ CHLOLIMIT_L3_AFE_ADC_LIMIT3_0_POS

#define CHLOLIMIT_L3_AFE_ADC_LIMIT3_0_POS 0U

◆ CHLOLIMIT_L4_AFE_ADC_LIMIT4_0_ADDR

#define CHLOLIMIT_L4_AFE_ADC_LIMIT4_0_ADDR 0x524U

◆ CHLOLIMIT_L4_AFE_ADC_LIMIT4_0_MASK

#define CHLOLIMIT_L4_AFE_ADC_LIMIT4_0_MASK 0xFFU

◆ CHLOLIMIT_L4_AFE_ADC_LIMIT4_0_POS

#define CHLOLIMIT_L4_AFE_ADC_LIMIT4_0_POS 0U

◆ CHLOLIMIT_L5_AFE_ADC_LIMIT5_0_ADDR

#define CHLOLIMIT_L5_AFE_ADC_LIMIT5_0_ADDR 0x528U

◆ CHLOLIMIT_L5_AFE_ADC_LIMIT5_0_MASK

#define CHLOLIMIT_L5_AFE_ADC_LIMIT5_0_MASK 0xFFU

◆ CHLOLIMIT_L5_AFE_ADC_LIMIT5_0_POS

#define CHLOLIMIT_L5_AFE_ADC_LIMIT5_0_POS 0U

◆ CHLOLIMIT_L6_AFE_ADC_LIMIT6_0_ADDR

#define CHLOLIMIT_L6_AFE_ADC_LIMIT6_0_ADDR 0x52CU

◆ CHLOLIMIT_L6_AFE_ADC_LIMIT6_0_MASK

#define CHLOLIMIT_L6_AFE_ADC_LIMIT6_0_MASK 0xFFU

◆ CHLOLIMIT_L6_AFE_ADC_LIMIT6_0_POS

#define CHLOLIMIT_L6_AFE_ADC_LIMIT6_0_POS 0U

◆ CHLOLIMIT_L7_AFE_ADC_LIMIT7_0_ADDR

#define CHLOLIMIT_L7_AFE_ADC_LIMIT7_0_ADDR 0x530U

◆ CHLOLIMIT_L7_AFE_ADC_LIMIT7_0_MASK

#define CHLOLIMIT_L7_AFE_ADC_LIMIT7_0_MASK 0xFFU

◆ CHLOLIMIT_L7_AFE_ADC_LIMIT7_0_POS

#define CHLOLIMIT_L7_AFE_ADC_LIMIT7_0_POS 0U

◆ CLK_SELZ_FRONTTOP_FRONTTOP_0_MASK

#define CLK_SELZ_FRONTTOP_FRONTTOP_0_MASK (0x04U)

◆ CLK_SELZ_FRONTTOP_FRONTTOP_0_POS

#define CLK_SELZ_FRONTTOP_FRONTTOP_0_POS (2U)

◆ CLKDET_BYP_VID_TX_Z_VIDEO_TX0_ADDR

#define CLKDET_BYP_VID_TX_Z_VIDEO_TX0_ADDR 0x110U

◆ CLKDET_BYP_VID_TX_Z_VIDEO_TX0_MASK

#define CLKDET_BYP_VID_TX_Z_VIDEO_TX0_MASK 0x04U

◆ CLKDET_BYP_VID_TX_Z_VIDEO_TX0_POS

#define CLKDET_BYP_VID_TX_Z_VIDEO_TX0_POS 2U

◆ CMP_STATUS_TCTRL_PWR0_ADDR

#define CMP_STATUS_TCTRL_PWR0_ADDR 0x08U

◆ CMP_STATUS_TCTRL_PWR0_MASK

#define CMP_STATUS_TCTRL_PWR0_MASK 0x1FU

◆ CMP_STATUS_TCTRL_PWR0_POS

#define CMP_STATUS_TCTRL_PWR0_POS 0U

◆ CMU_CMU2_ADDR

#define CMU_CMU2_ADDR 0x302U

◆ CMU_CMU2_DEFAULT

#define CMU_CMU2_DEFAULT 0x00U

◆ CMU_LOCKED_TCTRL_CTRL3_ADDR

#define CMU_LOCKED_TCTRL_CTRL3_ADDR 0x13U

◆ CMU_LOCKED_TCTRL_CTRL3_MASK

#define CMU_LOCKED_TCTRL_CTRL3_MASK 0x02U

◆ CMU_LOCKED_TCTRL_CTRL3_POS

#define CMU_LOCKED_TCTRL_CTRL3_POS 1U

◆ CONFIG_ALLOW_COARSE_CHANGE_DPLL_REF_DPLL_10_ADDR

#define CONFIG_ALLOW_COARSE_CHANGE_DPLL_REF_DPLL_10_ADDR 0x1A0AU

◆ CONFIG_ALLOW_COARSE_CHANGE_DPLL_REF_DPLL_10_MASK

#define CONFIG_ALLOW_COARSE_CHANGE_DPLL_REF_DPLL_10_MASK 0x80U

◆ CONFIG_ALLOW_COARSE_CHANGE_DPLL_REF_DPLL_10_POS

#define CONFIG_ALLOW_COARSE_CHANGE_DPLL_REF_DPLL_10_POS 7U

◆ CONFIG_DIV_FB_EXP_DPLL_REF_DPLL_9_ADDR

#define CONFIG_DIV_FB_EXP_DPLL_REF_DPLL_9_ADDR 0x1A09U

◆ CONFIG_DIV_FB_EXP_DPLL_REF_DPLL_9_MASK

#define CONFIG_DIV_FB_EXP_DPLL_REF_DPLL_9_MASK 0x07U

◆ CONFIG_DIV_FB_EXP_DPLL_REF_DPLL_9_POS

#define CONFIG_DIV_FB_EXP_DPLL_REF_DPLL_9_POS 0U

◆ CONFIG_DIV_FB_H_DPLL_REF_DPLL_8_ADDR

#define CONFIG_DIV_FB_H_DPLL_REF_DPLL_8_ADDR 0x1A08U

◆ CONFIG_DIV_FB_H_DPLL_REF_DPLL_8_MASK

#define CONFIG_DIV_FB_H_DPLL_REF_DPLL_8_MASK 0xFFU

◆ CONFIG_DIV_FB_H_DPLL_REF_DPLL_8_POS

#define CONFIG_DIV_FB_H_DPLL_REF_DPLL_8_POS 0U

◆ CONFIG_DIV_FB_L_DPLL_REF_DPLL_7_ADDR

#define CONFIG_DIV_FB_L_DPLL_REF_DPLL_7_ADDR 0x1A07U

◆ CONFIG_DIV_FB_L_DPLL_REF_DPLL_7_MASK

#define CONFIG_DIV_FB_L_DPLL_REF_DPLL_7_MASK 0x80U

◆ CONFIG_DIV_FB_L_DPLL_REF_DPLL_7_POS

#define CONFIG_DIV_FB_L_DPLL_REF_DPLL_7_POS 7U

◆ CONFIG_DIV_IN_DPLL_REF_DPLL_7_ADDR

#define CONFIG_DIV_IN_DPLL_REF_DPLL_7_ADDR 0x1A07U

◆ CONFIG_DIV_IN_DPLL_REF_DPLL_7_MASK

#define CONFIG_DIV_IN_DPLL_REF_DPLL_7_MASK 0x7CU

◆ CONFIG_DIV_IN_DPLL_REF_DPLL_7_POS

#define CONFIG_DIV_IN_DPLL_REF_DPLL_7_POS 2U

◆ CONFIG_DIV_OUT_EXP_DPLL_REF_DPLL_10_ADDR

#define CONFIG_DIV_OUT_EXP_DPLL_REF_DPLL_10_ADDR 0x1A0AU

◆ CONFIG_DIV_OUT_EXP_DPLL_REF_DPLL_10_MASK

#define CONFIG_DIV_OUT_EXP_DPLL_REF_DPLL_10_MASK 0x70U

◆ CONFIG_DIV_OUT_EXP_DPLL_REF_DPLL_10_POS

#define CONFIG_DIV_OUT_EXP_DPLL_REF_DPLL_10_POS 4U

◆ CONFIG_DIV_OUT_H_DPLL_REF_DPLL_10_ADDR

#define CONFIG_DIV_OUT_H_DPLL_REF_DPLL_10_ADDR 0x1A0AU

◆ CONFIG_DIV_OUT_H_DPLL_REF_DPLL_10_MASK

#define CONFIG_DIV_OUT_H_DPLL_REF_DPLL_10_MASK 0x0FU

◆ CONFIG_DIV_OUT_H_DPLL_REF_DPLL_10_POS

#define CONFIG_DIV_OUT_H_DPLL_REF_DPLL_10_POS 0U

◆ CONFIG_DIV_OUT_L_DPLL_REF_DPLL_9_ADDR

#define CONFIG_DIV_OUT_L_DPLL_REF_DPLL_9_ADDR 0x1A09U

◆ CONFIG_DIV_OUT_L_DPLL_REF_DPLL_9_MASK

#define CONFIG_DIV_OUT_L_DPLL_REF_DPLL_9_MASK 0xF8U

◆ CONFIG_DIV_OUT_L_DPLL_REF_DPLL_9_POS

#define CONFIG_DIV_OUT_L_DPLL_REF_DPLL_9_POS 3U

◆ CONFIG_SEL_CLOCK_OUT_USE_EXTERNAL_DPLL_REF_DPLL_3_ADDR

#define CONFIG_SEL_CLOCK_OUT_USE_EXTERNAL_DPLL_REF_DPLL_3_ADDR 0x1A03U

◆ CONFIG_SEL_CLOCK_OUT_USE_EXTERNAL_DPLL_REF_DPLL_3_MASK

#define CONFIG_SEL_CLOCK_OUT_USE_EXTERNAL_DPLL_REF_DPLL_3_MASK 0x80U

◆ CONFIG_SEL_CLOCK_OUT_USE_EXTERNAL_DPLL_REF_DPLL_3_POS

#define CONFIG_SEL_CLOCK_OUT_USE_EXTERNAL_DPLL_REF_DPLL_3_POS 7U

◆ CONFIG_SOFT_RST_N_DPLL_REF_DPLL_0_ADDR

#define CONFIG_SOFT_RST_N_DPLL_REF_DPLL_0_ADDR 0x1A00U

◆ CONFIG_SOFT_RST_N_DPLL_REF_DPLL_0_MASK

#define CONFIG_SOFT_RST_N_DPLL_REF_DPLL_0_MASK 0x01U

◆ CONFIG_SOFT_RST_N_DPLL_REF_DPLL_0_POS

#define CONFIG_SOFT_RST_N_DPLL_REF_DPLL_0_POS 0U

◆ CONFIG_SPREAD_BIT_RATIO_DPLL_REF_DPLL_3_ADDR

#define CONFIG_SPREAD_BIT_RATIO_DPLL_REF_DPLL_3_ADDR 0x1A03U

◆ CONFIG_SPREAD_BIT_RATIO_DPLL_REF_DPLL_3_MASK

#define CONFIG_SPREAD_BIT_RATIO_DPLL_REF_DPLL_3_MASK 0x07U

◆ CONFIG_SPREAD_BIT_RATIO_DPLL_REF_DPLL_3_POS

#define CONFIG_SPREAD_BIT_RATIO_DPLL_REF_DPLL_3_POS 0U

◆ CONFIG_USE_INTERNAL_DIVIDER_VALUES_DPLL_REF_DPLL_3_ADDR

#define CONFIG_USE_INTERNAL_DIVIDER_VALUES_DPLL_REF_DPLL_3_ADDR 0x1A03U

◆ CONFIG_USE_INTERNAL_DIVIDER_VALUES_DPLL_REF_DPLL_3_MASK

#define CONFIG_USE_INTERNAL_DIVIDER_VALUES_DPLL_REF_DPLL_3_MASK 0x10U

◆ CONFIG_USE_INTERNAL_DIVIDER_VALUES_DPLL_REF_DPLL_3_POS

#define CONFIG_USE_INTERNAL_DIVIDER_VALUES_DPLL_REF_DPLL_3_POS 4U

◆ CPHY_HDR1_ERR_MIPI_RX_EXT_EXT8_ADDR

#define CPHY_HDR1_ERR_MIPI_RX_EXT_EXT8_ADDR 0x380U

◆ CPHY_HDR1_ERR_MIPI_RX_EXT_EXT8_MASK

#define CPHY_HDR1_ERR_MIPI_RX_EXT_EXT8_MASK 0x60U

◆ CPHY_HDR1_ERR_MIPI_RX_EXT_EXT8_POS

#define CPHY_HDR1_ERR_MIPI_RX_EXT_EXT8_POS 5U

◆ CPHY_HDR2_ERR_MIPI_RX_EXT_EXT8_ADDR

#define CPHY_HDR2_ERR_MIPI_RX_EXT_EXT8_ADDR 0x380U

◆ CPHY_HDR2_ERR_MIPI_RX_EXT_EXT8_MASK

#define CPHY_HDR2_ERR_MIPI_RX_EXT_EXT8_MASK 0x18U

◆ CPHY_HDR2_ERR_MIPI_RX_EXT_EXT8_POS

#define CPHY_HDR2_ERR_MIPI_RX_EXT_EXT8_POS 3U

◆ CPHY_HDR_ERR_MIPI_RX_EXT_EXT8_ADDR

#define CPHY_HDR_ERR_MIPI_RX_EXT_EXT8_ADDR 0x380U

◆ CPHY_HDR_ERR_MIPI_RX_EXT_EXT8_MASK

#define CPHY_HDR_ERR_MIPI_RX_EXT_EXT8_MASK 0x80U

◆ CPHY_HDR_ERR_MIPI_RX_EXT_EXT8_POS

#define CPHY_HDR_ERR_MIPI_RX_EXT_EXT8_POS 7U

◆ CPHY_MODE_MIPI_RX_EXT_EXT11_ADDR

#define CPHY_MODE_MIPI_RX_EXT_EXT11_ADDR 0x383U

◆ CPHY_MODE_MIPI_RX_EXT_EXT11_MASK

#define CPHY_MODE_MIPI_RX_EXT_EXT11_MASK 0x40U

◆ CPHY_MODE_MIPI_RX_EXT_EXT11_POS

#define CPHY_MODE_MIPI_RX_EXT_EXT11_POS 6U

◆ CPU_ADC_START_AFE_ADC_CTRL_0_ADDR

#define CPU_ADC_START_AFE_ADC_CTRL_0_ADDR 0x500U

◆ CPU_ADC_START_AFE_ADC_CTRL_0_MASK

#define CPU_ADC_START_AFE_ADC_CTRL_0_MASK 0x01U

◆ CPU_ADC_START_AFE_ADC_CTRL_0_POS

#define CPU_ADC_START_AFE_ADC_CTRL_0_POS 0U

◆ CRC_PERIOD_FUNC_SAFE_REGCRC1_ADDR

#define CRC_PERIOD_FUNC_SAFE_REGCRC1_ADDR 0x1D01U

◆ CRC_PERIOD_FUNC_SAFE_REGCRC1_MASK

#define CRC_PERIOD_FUNC_SAFE_REGCRC1_MASK 0xFFU

◆ CRC_PERIOD_FUNC_SAFE_REGCRC1_POS

#define CRC_PERIOD_FUNC_SAFE_REGCRC1_POS 0U

◆ CRC_VAL_FUNC_SAFE_I2C_UART_CRC2_ADDR

#define CRC_VAL_FUNC_SAFE_I2C_UART_CRC2_ADDR 0x1D0AU

◆ CRC_VAL_FUNC_SAFE_I2C_UART_CRC2_MASK

#define CRC_VAL_FUNC_SAFE_I2C_UART_CRC2_MASK 0xFFU

◆ CRC_VAL_FUNC_SAFE_I2C_UART_CRC2_POS

#define CRC_VAL_FUNC_SAFE_I2C_UART_CRC2_POS 0U

◆ CROSS0_F_VTX_Z_CROSS_0_ADDR

#define CROSS0_F_VTX_Z_CROSS_0_ADDR 0x236U

◆ CROSS0_F_VTX_Z_CROSS_0_MASK

#define CROSS0_F_VTX_Z_CROSS_0_MASK 0x20U

◆ CROSS0_F_VTX_Z_CROSS_0_POS

#define CROSS0_F_VTX_Z_CROSS_0_POS 5U

◆ CROSS0_I_VTX_Z_CROSS_0_ADDR

#define CROSS0_I_VTX_Z_CROSS_0_ADDR 0x236U

◆ CROSS0_I_VTX_Z_CROSS_0_MASK

#define CROSS0_I_VTX_Z_CROSS_0_MASK 0x40U

◆ CROSS0_I_VTX_Z_CROSS_0_POS

#define CROSS0_I_VTX_Z_CROSS_0_POS 6U

◆ CROSS0_VTX_Z_CROSS_0_ADDR

#define CROSS0_VTX_Z_CROSS_0_ADDR 0x236U

◆ CROSS0_VTX_Z_CROSS_0_MASK

#define CROSS0_VTX_Z_CROSS_0_MASK 0x1FU

◆ CROSS0_VTX_Z_CROSS_0_POS

#define CROSS0_VTX_Z_CROSS_0_POS 0U

◆ CROSS10_F_VTX_Z_CROSS_10_ADDR

#define CROSS10_F_VTX_Z_CROSS_10_ADDR 0x240U

◆ CROSS10_F_VTX_Z_CROSS_10_MASK

#define CROSS10_F_VTX_Z_CROSS_10_MASK 0x20U

◆ CROSS10_F_VTX_Z_CROSS_10_POS

#define CROSS10_F_VTX_Z_CROSS_10_POS 5U

◆ CROSS10_I_VTX_Z_CROSS_10_ADDR

#define CROSS10_I_VTX_Z_CROSS_10_ADDR 0x240U

◆ CROSS10_I_VTX_Z_CROSS_10_MASK

#define CROSS10_I_VTX_Z_CROSS_10_MASK 0x40U

◆ CROSS10_I_VTX_Z_CROSS_10_POS

#define CROSS10_I_VTX_Z_CROSS_10_POS 6U

◆ CROSS10_VTX_Z_CROSS_10_ADDR

#define CROSS10_VTX_Z_CROSS_10_ADDR 0x240U

◆ CROSS10_VTX_Z_CROSS_10_MASK

#define CROSS10_VTX_Z_CROSS_10_MASK 0x1FU

◆ CROSS10_VTX_Z_CROSS_10_POS

#define CROSS10_VTX_Z_CROSS_10_POS 0U

◆ CROSS11_F_VTX_Z_CROSS_11_ADDR

#define CROSS11_F_VTX_Z_CROSS_11_ADDR 0x241U

◆ CROSS11_F_VTX_Z_CROSS_11_MASK

#define CROSS11_F_VTX_Z_CROSS_11_MASK 0x20U

◆ CROSS11_F_VTX_Z_CROSS_11_POS

#define CROSS11_F_VTX_Z_CROSS_11_POS 5U

◆ CROSS11_I_VTX_Z_CROSS_11_ADDR

#define CROSS11_I_VTX_Z_CROSS_11_ADDR 0x241U

◆ CROSS11_I_VTX_Z_CROSS_11_MASK

#define CROSS11_I_VTX_Z_CROSS_11_MASK 0x40U

◆ CROSS11_I_VTX_Z_CROSS_11_POS

#define CROSS11_I_VTX_Z_CROSS_11_POS 6U

◆ CROSS11_VTX_Z_CROSS_11_ADDR

#define CROSS11_VTX_Z_CROSS_11_ADDR 0x241U

◆ CROSS11_VTX_Z_CROSS_11_MASK

#define CROSS11_VTX_Z_CROSS_11_MASK 0x1FU

◆ CROSS11_VTX_Z_CROSS_11_POS

#define CROSS11_VTX_Z_CROSS_11_POS 0U

◆ CROSS12_F_VTX_Z_CROSS_12_ADDR

#define CROSS12_F_VTX_Z_CROSS_12_ADDR 0x242U

◆ CROSS12_F_VTX_Z_CROSS_12_MASK

#define CROSS12_F_VTX_Z_CROSS_12_MASK 0x20U

◆ CROSS12_F_VTX_Z_CROSS_12_POS

#define CROSS12_F_VTX_Z_CROSS_12_POS 5U

◆ CROSS12_I_VTX_Z_CROSS_12_ADDR

#define CROSS12_I_VTX_Z_CROSS_12_ADDR 0x242U

◆ CROSS12_I_VTX_Z_CROSS_12_MASK

#define CROSS12_I_VTX_Z_CROSS_12_MASK 0x40U

◆ CROSS12_I_VTX_Z_CROSS_12_POS

#define CROSS12_I_VTX_Z_CROSS_12_POS 6U

◆ CROSS12_VTX_Z_CROSS_12_ADDR

#define CROSS12_VTX_Z_CROSS_12_ADDR 0x242U

◆ CROSS12_VTX_Z_CROSS_12_MASK

#define CROSS12_VTX_Z_CROSS_12_MASK 0x1FU

◆ CROSS12_VTX_Z_CROSS_12_POS

#define CROSS12_VTX_Z_CROSS_12_POS 0U

◆ CROSS13_F_VTX_Z_CROSS_13_ADDR

#define CROSS13_F_VTX_Z_CROSS_13_ADDR 0x243U

◆ CROSS13_F_VTX_Z_CROSS_13_MASK

#define CROSS13_F_VTX_Z_CROSS_13_MASK 0x20U

◆ CROSS13_F_VTX_Z_CROSS_13_POS

#define CROSS13_F_VTX_Z_CROSS_13_POS 5U

◆ CROSS13_I_VTX_Z_CROSS_13_ADDR

#define CROSS13_I_VTX_Z_CROSS_13_ADDR 0x243U

◆ CROSS13_I_VTX_Z_CROSS_13_MASK

#define CROSS13_I_VTX_Z_CROSS_13_MASK 0x40U

◆ CROSS13_I_VTX_Z_CROSS_13_POS

#define CROSS13_I_VTX_Z_CROSS_13_POS 6U

◆ CROSS13_VTX_Z_CROSS_13_ADDR

#define CROSS13_VTX_Z_CROSS_13_ADDR 0x243U

◆ CROSS13_VTX_Z_CROSS_13_MASK

#define CROSS13_VTX_Z_CROSS_13_MASK 0x1FU

◆ CROSS13_VTX_Z_CROSS_13_POS

#define CROSS13_VTX_Z_CROSS_13_POS 0U

◆ CROSS14_F_VTX_Z_CROSS_14_ADDR

#define CROSS14_F_VTX_Z_CROSS_14_ADDR 0x244U

◆ CROSS14_F_VTX_Z_CROSS_14_MASK

#define CROSS14_F_VTX_Z_CROSS_14_MASK 0x20U

◆ CROSS14_F_VTX_Z_CROSS_14_POS

#define CROSS14_F_VTX_Z_CROSS_14_POS 5U

◆ CROSS14_I_VTX_Z_CROSS_14_ADDR

#define CROSS14_I_VTX_Z_CROSS_14_ADDR 0x244U

◆ CROSS14_I_VTX_Z_CROSS_14_MASK

#define CROSS14_I_VTX_Z_CROSS_14_MASK 0x40U

◆ CROSS14_I_VTX_Z_CROSS_14_POS

#define CROSS14_I_VTX_Z_CROSS_14_POS 6U

◆ CROSS14_VTX_Z_CROSS_14_ADDR

#define CROSS14_VTX_Z_CROSS_14_ADDR 0x244U

◆ CROSS14_VTX_Z_CROSS_14_MASK

#define CROSS14_VTX_Z_CROSS_14_MASK 0x1FU

◆ CROSS14_VTX_Z_CROSS_14_POS

#define CROSS14_VTX_Z_CROSS_14_POS 0U

◆ CROSS15_F_VTX_Z_CROSS_15_ADDR

#define CROSS15_F_VTX_Z_CROSS_15_ADDR 0x245U

◆ CROSS15_F_VTX_Z_CROSS_15_MASK

#define CROSS15_F_VTX_Z_CROSS_15_MASK 0x20U

◆ CROSS15_F_VTX_Z_CROSS_15_POS

#define CROSS15_F_VTX_Z_CROSS_15_POS 5U

◆ CROSS15_I_VTX_Z_CROSS_15_ADDR

#define CROSS15_I_VTX_Z_CROSS_15_ADDR 0x245U

◆ CROSS15_I_VTX_Z_CROSS_15_MASK

#define CROSS15_I_VTX_Z_CROSS_15_MASK 0x40U

◆ CROSS15_I_VTX_Z_CROSS_15_POS

#define CROSS15_I_VTX_Z_CROSS_15_POS 6U

◆ CROSS15_VTX_Z_CROSS_15_ADDR

#define CROSS15_VTX_Z_CROSS_15_ADDR 0x245U

◆ CROSS15_VTX_Z_CROSS_15_MASK

#define CROSS15_VTX_Z_CROSS_15_MASK 0x1FU

◆ CROSS15_VTX_Z_CROSS_15_POS

#define CROSS15_VTX_Z_CROSS_15_POS 0U

◆ CROSS16_F_VTX_Z_CROSS_16_ADDR

#define CROSS16_F_VTX_Z_CROSS_16_ADDR 0x246U

◆ CROSS16_F_VTX_Z_CROSS_16_MASK

#define CROSS16_F_VTX_Z_CROSS_16_MASK 0x20U

◆ CROSS16_F_VTX_Z_CROSS_16_POS

#define CROSS16_F_VTX_Z_CROSS_16_POS 5U

◆ CROSS16_I_VTX_Z_CROSS_16_ADDR

#define CROSS16_I_VTX_Z_CROSS_16_ADDR 0x246U

◆ CROSS16_I_VTX_Z_CROSS_16_MASK

#define CROSS16_I_VTX_Z_CROSS_16_MASK 0x40U

◆ CROSS16_I_VTX_Z_CROSS_16_POS

#define CROSS16_I_VTX_Z_CROSS_16_POS 6U

◆ CROSS16_VTX_Z_CROSS_16_ADDR

#define CROSS16_VTX_Z_CROSS_16_ADDR 0x246U

◆ CROSS16_VTX_Z_CROSS_16_MASK

#define CROSS16_VTX_Z_CROSS_16_MASK 0x1FU

◆ CROSS16_VTX_Z_CROSS_16_POS

#define CROSS16_VTX_Z_CROSS_16_POS 0U

◆ CROSS17_F_VTX_Z_CROSS_17_ADDR

#define CROSS17_F_VTX_Z_CROSS_17_ADDR 0x247U

◆ CROSS17_F_VTX_Z_CROSS_17_MASK

#define CROSS17_F_VTX_Z_CROSS_17_MASK 0x20U

◆ CROSS17_F_VTX_Z_CROSS_17_POS

#define CROSS17_F_VTX_Z_CROSS_17_POS 5U

◆ CROSS17_I_VTX_Z_CROSS_17_ADDR

#define CROSS17_I_VTX_Z_CROSS_17_ADDR 0x247U

◆ CROSS17_I_VTX_Z_CROSS_17_MASK

#define CROSS17_I_VTX_Z_CROSS_17_MASK 0x40U

◆ CROSS17_I_VTX_Z_CROSS_17_POS

#define CROSS17_I_VTX_Z_CROSS_17_POS 6U

◆ CROSS17_VTX_Z_CROSS_17_ADDR

#define CROSS17_VTX_Z_CROSS_17_ADDR 0x247U

◆ CROSS17_VTX_Z_CROSS_17_MASK

#define CROSS17_VTX_Z_CROSS_17_MASK 0x1FU

◆ CROSS17_VTX_Z_CROSS_17_POS

#define CROSS17_VTX_Z_CROSS_17_POS 0U

◆ CROSS18_F_VTX_Z_CROSS_18_ADDR

#define CROSS18_F_VTX_Z_CROSS_18_ADDR 0x248U

◆ CROSS18_F_VTX_Z_CROSS_18_MASK

#define CROSS18_F_VTX_Z_CROSS_18_MASK 0x20U

◆ CROSS18_F_VTX_Z_CROSS_18_POS

#define CROSS18_F_VTX_Z_CROSS_18_POS 5U

◆ CROSS18_I_VTX_Z_CROSS_18_ADDR

#define CROSS18_I_VTX_Z_CROSS_18_ADDR 0x248U

◆ CROSS18_I_VTX_Z_CROSS_18_MASK

#define CROSS18_I_VTX_Z_CROSS_18_MASK 0x40U

◆ CROSS18_I_VTX_Z_CROSS_18_POS

#define CROSS18_I_VTX_Z_CROSS_18_POS 6U

◆ CROSS18_VTX_Z_CROSS_18_ADDR

#define CROSS18_VTX_Z_CROSS_18_ADDR 0x248U

◆ CROSS18_VTX_Z_CROSS_18_MASK

#define CROSS18_VTX_Z_CROSS_18_MASK 0x1FU

◆ CROSS18_VTX_Z_CROSS_18_POS

#define CROSS18_VTX_Z_CROSS_18_POS 0U

◆ CROSS19_F_VTX_Z_CROSS_19_ADDR

#define CROSS19_F_VTX_Z_CROSS_19_ADDR 0x249U

◆ CROSS19_F_VTX_Z_CROSS_19_MASK

#define CROSS19_F_VTX_Z_CROSS_19_MASK 0x20U

◆ CROSS19_F_VTX_Z_CROSS_19_POS

#define CROSS19_F_VTX_Z_CROSS_19_POS 5U

◆ CROSS19_I_VTX_Z_CROSS_19_ADDR

#define CROSS19_I_VTX_Z_CROSS_19_ADDR 0x249U

◆ CROSS19_I_VTX_Z_CROSS_19_MASK

#define CROSS19_I_VTX_Z_CROSS_19_MASK 0x40U

◆ CROSS19_I_VTX_Z_CROSS_19_POS

#define CROSS19_I_VTX_Z_CROSS_19_POS 6U

◆ CROSS19_VTX_Z_CROSS_19_ADDR

#define CROSS19_VTX_Z_CROSS_19_ADDR 0x249U

◆ CROSS19_VTX_Z_CROSS_19_MASK

#define CROSS19_VTX_Z_CROSS_19_MASK 0x1FU

◆ CROSS19_VTX_Z_CROSS_19_POS

#define CROSS19_VTX_Z_CROSS_19_POS 0U

◆ CROSS1_F_VTX_Z_CROSS_1_ADDR

#define CROSS1_F_VTX_Z_CROSS_1_ADDR 0x237U

◆ CROSS1_F_VTX_Z_CROSS_1_MASK

#define CROSS1_F_VTX_Z_CROSS_1_MASK 0x20U

◆ CROSS1_F_VTX_Z_CROSS_1_POS

#define CROSS1_F_VTX_Z_CROSS_1_POS 5U

◆ CROSS1_I_VTX_Z_CROSS_1_ADDR

#define CROSS1_I_VTX_Z_CROSS_1_ADDR 0x237U

◆ CROSS1_I_VTX_Z_CROSS_1_MASK

#define CROSS1_I_VTX_Z_CROSS_1_MASK 0x40U

◆ CROSS1_I_VTX_Z_CROSS_1_POS

#define CROSS1_I_VTX_Z_CROSS_1_POS 6U

◆ CROSS1_VTX_Z_CROSS_1_ADDR

#define CROSS1_VTX_Z_CROSS_1_ADDR 0x237U

◆ CROSS1_VTX_Z_CROSS_1_MASK

#define CROSS1_VTX_Z_CROSS_1_MASK 0x1FU

◆ CROSS1_VTX_Z_CROSS_1_POS

#define CROSS1_VTX_Z_CROSS_1_POS 0U

◆ CROSS20_F_VTX_Z_CROSS_20_ADDR

#define CROSS20_F_VTX_Z_CROSS_20_ADDR 0x24AU

◆ CROSS20_F_VTX_Z_CROSS_20_MASK

#define CROSS20_F_VTX_Z_CROSS_20_MASK 0x20U

◆ CROSS20_F_VTX_Z_CROSS_20_POS

#define CROSS20_F_VTX_Z_CROSS_20_POS 5U

◆ CROSS20_I_VTX_Z_CROSS_20_ADDR

#define CROSS20_I_VTX_Z_CROSS_20_ADDR 0x24AU

◆ CROSS20_I_VTX_Z_CROSS_20_MASK

#define CROSS20_I_VTX_Z_CROSS_20_MASK 0x40U

◆ CROSS20_I_VTX_Z_CROSS_20_POS

#define CROSS20_I_VTX_Z_CROSS_20_POS 6U

◆ CROSS20_VTX_Z_CROSS_20_ADDR

#define CROSS20_VTX_Z_CROSS_20_ADDR 0x24AU

◆ CROSS20_VTX_Z_CROSS_20_MASK

#define CROSS20_VTX_Z_CROSS_20_MASK 0x1FU

◆ CROSS20_VTX_Z_CROSS_20_POS

#define CROSS20_VTX_Z_CROSS_20_POS 0U

◆ CROSS21_F_VTX_Z_CROSS_21_ADDR

#define CROSS21_F_VTX_Z_CROSS_21_ADDR 0x24BU

◆ CROSS21_F_VTX_Z_CROSS_21_MASK

#define CROSS21_F_VTX_Z_CROSS_21_MASK 0x20U

◆ CROSS21_F_VTX_Z_CROSS_21_POS

#define CROSS21_F_VTX_Z_CROSS_21_POS 5U

◆ CROSS21_I_VTX_Z_CROSS_21_ADDR

#define CROSS21_I_VTX_Z_CROSS_21_ADDR 0x24BU

◆ CROSS21_I_VTX_Z_CROSS_21_MASK

#define CROSS21_I_VTX_Z_CROSS_21_MASK 0x40U

◆ CROSS21_I_VTX_Z_CROSS_21_POS

#define CROSS21_I_VTX_Z_CROSS_21_POS 6U

◆ CROSS21_VTX_Z_CROSS_21_ADDR

#define CROSS21_VTX_Z_CROSS_21_ADDR 0x24BU

◆ CROSS21_VTX_Z_CROSS_21_MASK

#define CROSS21_VTX_Z_CROSS_21_MASK 0x1FU

◆ CROSS21_VTX_Z_CROSS_21_POS

#define CROSS21_VTX_Z_CROSS_21_POS 0U

◆ CROSS22_F_VTX_Z_CROSS_22_ADDR

#define CROSS22_F_VTX_Z_CROSS_22_ADDR 0x24CU

◆ CROSS22_F_VTX_Z_CROSS_22_MASK

#define CROSS22_F_VTX_Z_CROSS_22_MASK 0x20U

◆ CROSS22_F_VTX_Z_CROSS_22_POS

#define CROSS22_F_VTX_Z_CROSS_22_POS 5U

◆ CROSS22_I_VTX_Z_CROSS_22_ADDR

#define CROSS22_I_VTX_Z_CROSS_22_ADDR 0x24CU

◆ CROSS22_I_VTX_Z_CROSS_22_MASK

#define CROSS22_I_VTX_Z_CROSS_22_MASK 0x40U

◆ CROSS22_I_VTX_Z_CROSS_22_POS

#define CROSS22_I_VTX_Z_CROSS_22_POS 6U

◆ CROSS22_VTX_Z_CROSS_22_ADDR

#define CROSS22_VTX_Z_CROSS_22_ADDR 0x24CU

◆ CROSS22_VTX_Z_CROSS_22_MASK

#define CROSS22_VTX_Z_CROSS_22_MASK 0x1FU

◆ CROSS22_VTX_Z_CROSS_22_POS

#define CROSS22_VTX_Z_CROSS_22_POS 0U

◆ CROSS23_F_VTX_Z_CROSS_23_ADDR

#define CROSS23_F_VTX_Z_CROSS_23_ADDR 0x24DU

◆ CROSS23_F_VTX_Z_CROSS_23_MASK

#define CROSS23_F_VTX_Z_CROSS_23_MASK 0x20U

◆ CROSS23_F_VTX_Z_CROSS_23_POS

#define CROSS23_F_VTX_Z_CROSS_23_POS 5U

◆ CROSS23_I_VTX_Z_CROSS_23_ADDR

#define CROSS23_I_VTX_Z_CROSS_23_ADDR 0x24DU

◆ CROSS23_I_VTX_Z_CROSS_23_MASK

#define CROSS23_I_VTX_Z_CROSS_23_MASK 0x40U

◆ CROSS23_I_VTX_Z_CROSS_23_POS

#define CROSS23_I_VTX_Z_CROSS_23_POS 6U

◆ CROSS23_VTX_Z_CROSS_23_ADDR

#define CROSS23_VTX_Z_CROSS_23_ADDR 0x24DU

◆ CROSS23_VTX_Z_CROSS_23_MASK

#define CROSS23_VTX_Z_CROSS_23_MASK 0x1FU

◆ CROSS23_VTX_Z_CROSS_23_POS

#define CROSS23_VTX_Z_CROSS_23_POS 0U

◆ CROSS2_F_VTX_Z_CROSS_2_ADDR

#define CROSS2_F_VTX_Z_CROSS_2_ADDR 0x238U

◆ CROSS2_F_VTX_Z_CROSS_2_MASK

#define CROSS2_F_VTX_Z_CROSS_2_MASK 0x20U

◆ CROSS2_F_VTX_Z_CROSS_2_POS

#define CROSS2_F_VTX_Z_CROSS_2_POS 5U

◆ CROSS2_I_VTX_Z_CROSS_2_ADDR

#define CROSS2_I_VTX_Z_CROSS_2_ADDR 0x238U

◆ CROSS2_I_VTX_Z_CROSS_2_MASK

#define CROSS2_I_VTX_Z_CROSS_2_MASK 0x40U

◆ CROSS2_I_VTX_Z_CROSS_2_POS

#define CROSS2_I_VTX_Z_CROSS_2_POS 6U

◆ CROSS2_VTX_Z_CROSS_2_ADDR

#define CROSS2_VTX_Z_CROSS_2_ADDR 0x238U

◆ CROSS2_VTX_Z_CROSS_2_MASK

#define CROSS2_VTX_Z_CROSS_2_MASK 0x1FU

◆ CROSS2_VTX_Z_CROSS_2_POS

#define CROSS2_VTX_Z_CROSS_2_POS 0U

◆ CROSS3_F_VTX_Z_CROSS_3_ADDR

#define CROSS3_F_VTX_Z_CROSS_3_ADDR 0x239U

◆ CROSS3_F_VTX_Z_CROSS_3_MASK

#define CROSS3_F_VTX_Z_CROSS_3_MASK 0x20U

◆ CROSS3_F_VTX_Z_CROSS_3_POS

#define CROSS3_F_VTX_Z_CROSS_3_POS 5U

◆ CROSS3_I_VTX_Z_CROSS_3_ADDR

#define CROSS3_I_VTX_Z_CROSS_3_ADDR 0x239U

◆ CROSS3_I_VTX_Z_CROSS_3_MASK

#define CROSS3_I_VTX_Z_CROSS_3_MASK 0x40U

◆ CROSS3_I_VTX_Z_CROSS_3_POS

#define CROSS3_I_VTX_Z_CROSS_3_POS 6U

◆ CROSS3_VTX_Z_CROSS_3_ADDR

#define CROSS3_VTX_Z_CROSS_3_ADDR 0x239U

◆ CROSS3_VTX_Z_CROSS_3_MASK

#define CROSS3_VTX_Z_CROSS_3_MASK 0x1FU

◆ CROSS3_VTX_Z_CROSS_3_POS

#define CROSS3_VTX_Z_CROSS_3_POS 0U

◆ CROSS4_F_VTX_Z_CROSS_4_ADDR

#define CROSS4_F_VTX_Z_CROSS_4_ADDR 0x23AU

◆ CROSS4_F_VTX_Z_CROSS_4_MASK

#define CROSS4_F_VTX_Z_CROSS_4_MASK 0x20U

◆ CROSS4_F_VTX_Z_CROSS_4_POS

#define CROSS4_F_VTX_Z_CROSS_4_POS 5U

◆ CROSS4_I_VTX_Z_CROSS_4_ADDR

#define CROSS4_I_VTX_Z_CROSS_4_ADDR 0x23AU

◆ CROSS4_I_VTX_Z_CROSS_4_MASK

#define CROSS4_I_VTX_Z_CROSS_4_MASK 0x40U

◆ CROSS4_I_VTX_Z_CROSS_4_POS

#define CROSS4_I_VTX_Z_CROSS_4_POS 6U

◆ CROSS4_VTX_Z_CROSS_4_ADDR

#define CROSS4_VTX_Z_CROSS_4_ADDR 0x23AU

◆ CROSS4_VTX_Z_CROSS_4_MASK

#define CROSS4_VTX_Z_CROSS_4_MASK 0x1FU

◆ CROSS4_VTX_Z_CROSS_4_POS

#define CROSS4_VTX_Z_CROSS_4_POS 0U

◆ CROSS5_F_VTX_Z_CROSS_5_ADDR

#define CROSS5_F_VTX_Z_CROSS_5_ADDR 0x23BU

◆ CROSS5_F_VTX_Z_CROSS_5_MASK

#define CROSS5_F_VTX_Z_CROSS_5_MASK 0x20U

◆ CROSS5_F_VTX_Z_CROSS_5_POS

#define CROSS5_F_VTX_Z_CROSS_5_POS 5U

◆ CROSS5_I_VTX_Z_CROSS_5_ADDR

#define CROSS5_I_VTX_Z_CROSS_5_ADDR 0x23BU

◆ CROSS5_I_VTX_Z_CROSS_5_MASK

#define CROSS5_I_VTX_Z_CROSS_5_MASK 0x40U

◆ CROSS5_I_VTX_Z_CROSS_5_POS

#define CROSS5_I_VTX_Z_CROSS_5_POS 6U

◆ CROSS5_VTX_Z_CROSS_5_ADDR

#define CROSS5_VTX_Z_CROSS_5_ADDR 0x23BU

◆ CROSS5_VTX_Z_CROSS_5_MASK

#define CROSS5_VTX_Z_CROSS_5_MASK 0x1FU

◆ CROSS5_VTX_Z_CROSS_5_POS

#define CROSS5_VTX_Z_CROSS_5_POS 0U

◆ CROSS6_F_VTX_Z_CROSS_6_ADDR

#define CROSS6_F_VTX_Z_CROSS_6_ADDR 0x23CU

◆ CROSS6_F_VTX_Z_CROSS_6_MASK

#define CROSS6_F_VTX_Z_CROSS_6_MASK 0x20U

◆ CROSS6_F_VTX_Z_CROSS_6_POS

#define CROSS6_F_VTX_Z_CROSS_6_POS 5U

◆ CROSS6_I_VTX_Z_CROSS_6_ADDR

#define CROSS6_I_VTX_Z_CROSS_6_ADDR 0x23CU

◆ CROSS6_I_VTX_Z_CROSS_6_MASK

#define CROSS6_I_VTX_Z_CROSS_6_MASK 0x40U

◆ CROSS6_I_VTX_Z_CROSS_6_POS

#define CROSS6_I_VTX_Z_CROSS_6_POS 6U

◆ CROSS6_VTX_Z_CROSS_6_ADDR

#define CROSS6_VTX_Z_CROSS_6_ADDR 0x23CU

◆ CROSS6_VTX_Z_CROSS_6_MASK

#define CROSS6_VTX_Z_CROSS_6_MASK 0x1FU

◆ CROSS6_VTX_Z_CROSS_6_POS

#define CROSS6_VTX_Z_CROSS_6_POS 0U

◆ CROSS7_F_VTX_Z_CROSS_7_ADDR

#define CROSS7_F_VTX_Z_CROSS_7_ADDR 0x23DU

◆ CROSS7_F_VTX_Z_CROSS_7_MASK

#define CROSS7_F_VTX_Z_CROSS_7_MASK 0x20U

◆ CROSS7_F_VTX_Z_CROSS_7_POS

#define CROSS7_F_VTX_Z_CROSS_7_POS 5U

◆ CROSS7_I_VTX_Z_CROSS_7_ADDR

#define CROSS7_I_VTX_Z_CROSS_7_ADDR 0x23DU

◆ CROSS7_I_VTX_Z_CROSS_7_MASK

#define CROSS7_I_VTX_Z_CROSS_7_MASK 0x40U

◆ CROSS7_I_VTX_Z_CROSS_7_POS

#define CROSS7_I_VTX_Z_CROSS_7_POS 6U

◆ CROSS7_VTX_Z_CROSS_7_ADDR

#define CROSS7_VTX_Z_CROSS_7_ADDR 0x23DU

◆ CROSS7_VTX_Z_CROSS_7_MASK

#define CROSS7_VTX_Z_CROSS_7_MASK 0x1FU

◆ CROSS7_VTX_Z_CROSS_7_POS

#define CROSS7_VTX_Z_CROSS_7_POS 0U

◆ CROSS8_F_VTX_Z_CROSS_8_ADDR

#define CROSS8_F_VTX_Z_CROSS_8_ADDR 0x23EU

◆ CROSS8_F_VTX_Z_CROSS_8_MASK

#define CROSS8_F_VTX_Z_CROSS_8_MASK 0x20U

◆ CROSS8_F_VTX_Z_CROSS_8_POS

#define CROSS8_F_VTX_Z_CROSS_8_POS 5U

◆ CROSS8_I_VTX_Z_CROSS_8_ADDR

#define CROSS8_I_VTX_Z_CROSS_8_ADDR 0x23EU

◆ CROSS8_I_VTX_Z_CROSS_8_MASK

#define CROSS8_I_VTX_Z_CROSS_8_MASK 0x40U

◆ CROSS8_I_VTX_Z_CROSS_8_POS

#define CROSS8_I_VTX_Z_CROSS_8_POS 6U

◆ CROSS8_VTX_Z_CROSS_8_ADDR

#define CROSS8_VTX_Z_CROSS_8_ADDR 0x23EU

◆ CROSS8_VTX_Z_CROSS_8_MASK

#define CROSS8_VTX_Z_CROSS_8_MASK 0x1FU

◆ CROSS8_VTX_Z_CROSS_8_POS

#define CROSS8_VTX_Z_CROSS_8_POS 0U

◆ CROSS9_F_VTX_Z_CROSS_9_ADDR

#define CROSS9_F_VTX_Z_CROSS_9_ADDR 0x23FU

◆ CROSS9_F_VTX_Z_CROSS_9_MASK

#define CROSS9_F_VTX_Z_CROSS_9_MASK 0x20U

◆ CROSS9_F_VTX_Z_CROSS_9_POS

#define CROSS9_F_VTX_Z_CROSS_9_POS 5U

◆ CROSS9_I_VTX_Z_CROSS_9_ADDR

#define CROSS9_I_VTX_Z_CROSS_9_ADDR 0x23FU

◆ CROSS9_I_VTX_Z_CROSS_9_MASK

#define CROSS9_I_VTX_Z_CROSS_9_MASK 0x40U

◆ CROSS9_I_VTX_Z_CROSS_9_POS

#define CROSS9_I_VTX_Z_CROSS_9_POS 6U

◆ CROSS9_VTX_Z_CROSS_9_ADDR

#define CROSS9_VTX_Z_CROSS_9_ADDR 0x23FU

◆ CROSS9_VTX_Z_CROSS_9_MASK

#define CROSS9_VTX_Z_CROSS_9_MASK 0x1FU

◆ CROSS9_VTX_Z_CROSS_9_POS

#define CROSS9_VTX_Z_CROSS_9_POS 0U

◆ CROSSDE_F_VTX_Z_VTX42_ADDR

#define CROSSDE_F_VTX_Z_VTX42_ADDR 0x278U

◆ CROSSDE_F_VTX_Z_VTX42_MASK

#define CROSSDE_F_VTX_Z_VTX42_MASK 0x20U

◆ CROSSDE_F_VTX_Z_VTX42_POS

#define CROSSDE_F_VTX_Z_VTX42_POS 5U

◆ CROSSDE_I_VTX_Z_VTX42_ADDR

#define CROSSDE_I_VTX_Z_VTX42_ADDR 0x278U

◆ CROSSDE_I_VTX_Z_VTX42_MASK

#define CROSSDE_I_VTX_Z_VTX42_MASK 0x40U

◆ CROSSDE_I_VTX_Z_VTX42_POS

#define CROSSDE_I_VTX_Z_VTX42_POS 6U

◆ CROSSDE_VTX_Z_VTX42_ADDR

#define CROSSDE_VTX_Z_VTX42_ADDR 0x278U

◆ CROSSDE_VTX_Z_VTX42_MASK

#define CROSSDE_VTX_Z_VTX42_MASK 0x1FU

◆ CROSSDE_VTX_Z_VTX42_POS

#define CROSSDE_VTX_Z_VTX42_POS 0U

◆ CROSSHS_F_VTX_Z_VTX40_ADDR

#define CROSSHS_F_VTX_Z_VTX40_ADDR 0x276U

◆ CROSSHS_F_VTX_Z_VTX40_MASK

#define CROSSHS_F_VTX_Z_VTX40_MASK 0x20U

◆ CROSSHS_F_VTX_Z_VTX40_POS

#define CROSSHS_F_VTX_Z_VTX40_POS 5U

◆ CROSSHS_I_VTX_Z_VTX40_ADDR

#define CROSSHS_I_VTX_Z_VTX40_ADDR 0x276U

◆ CROSSHS_I_VTX_Z_VTX40_MASK

#define CROSSHS_I_VTX_Z_VTX40_MASK 0x40U

◆ CROSSHS_I_VTX_Z_VTX40_POS

#define CROSSHS_I_VTX_Z_VTX40_POS 6U

◆ CROSSHS_VTX_Z_VTX40_ADDR

#define CROSSHS_VTX_Z_VTX40_ADDR 0x276U

◆ CROSSHS_VTX_Z_VTX40_MASK

#define CROSSHS_VTX_Z_VTX40_MASK 0x1FU

◆ CROSSHS_VTX_Z_VTX40_POS

#define CROSSHS_VTX_Z_VTX40_POS 0U

◆ CROSSVS_F_VTX_Z_VTX41_ADDR

#define CROSSVS_F_VTX_Z_VTX41_ADDR 0x277U

◆ CROSSVS_F_VTX_Z_VTX41_MASK

#define CROSSVS_F_VTX_Z_VTX41_MASK 0x20U

◆ CROSSVS_F_VTX_Z_VTX41_POS

#define CROSSVS_F_VTX_Z_VTX41_POS 5U

◆ CROSSVS_I_VTX_Z_VTX41_ADDR

#define CROSSVS_I_VTX_Z_VTX41_ADDR 0x277U

◆ CROSSVS_I_VTX_Z_VTX41_MASK

#define CROSSVS_I_VTX_Z_VTX41_MASK 0x40U

◆ CROSSVS_I_VTX_Z_VTX41_POS

#define CROSSVS_I_VTX_Z_VTX41_POS 6U

◆ CROSSVS_VTX_Z_VTX41_ADDR

#define CROSSVS_VTX_Z_VTX41_ADDR 0x277U

◆ CROSSVS_VTX_Z_VTX41_MASK

#define CROSSVS_VTX_Z_VTX41_MASK 0x1FU

◆ CROSSVS_VTX_Z_VTX41_POS

#define CROSSVS_VTX_Z_VTX41_POS 0U

◆ CSI1_PKT_CNT_MIPI_RX_EXT_EXT22_ADDR

#define CSI1_PKT_CNT_MIPI_RX_EXT_EXT22_ADDR 0x38EU

◆ CSI1_PKT_CNT_MIPI_RX_EXT_EXT22_MASK

#define CSI1_PKT_CNT_MIPI_RX_EXT_EXT22_MASK 0xFFU

◆ CSI1_PKT_CNT_MIPI_RX_EXT_EXT22_POS

#define CSI1_PKT_CNT_MIPI_RX_EXT_EXT22_POS 0U

◆ CTRL1_CSI_ERR_H_MIPI_RX_MIPI_RX20_ADDR

#define CTRL1_CSI_ERR_H_MIPI_RX_MIPI_RX20_ADDR 0x344U

◆ CTRL1_CSI_ERR_H_MIPI_RX_MIPI_RX20_ALL_MASK

#define CTRL1_CSI_ERR_H_MIPI_RX_MIPI_RX20_ALL_MASK (0xFFU)

◆ CTRL1_CSI_ERR_H_MIPI_RX_MIPI_RX20_FRAME_CNT_ERR_MASK

#define CTRL1_CSI_ERR_H_MIPI_RX_MIPI_RX20_FRAME_CNT_ERR_MASK (0x02U)

◆ CTRL1_CSI_ERR_H_MIPI_RX_MIPI_RX20_FRAME_CNT_ERR_POS

#define CTRL1_CSI_ERR_H_MIPI_RX_MIPI_RX20_FRAME_CNT_ERR_POS (1U)

◆ CTRL1_CSI_ERR_H_MIPI_RX_MIPI_RX20_MASK

#define CTRL1_CSI_ERR_H_MIPI_RX_MIPI_RX20_MASK 0x07U

◆ CTRL1_CSI_ERR_H_MIPI_RX_MIPI_RX20_PKT_TERM_EARLY_ERR_MASK

#define CTRL1_CSI_ERR_H_MIPI_RX_MIPI_RX20_PKT_TERM_EARLY_ERR_MASK (0x01U)

◆ CTRL1_CSI_ERR_H_MIPI_RX_MIPI_RX20_PKT_TERM_EARLY_ERR_POS

#define CTRL1_CSI_ERR_H_MIPI_RX_MIPI_RX20_PKT_TERM_EARLY_ERR_POS (0U)

◆ CTRL1_CSI_ERR_H_MIPI_RX_MIPI_RX20_POS

#define CTRL1_CSI_ERR_H_MIPI_RX_MIPI_RX20_POS 0U

◆ CTRL1_CSI_ERR_L_MIPI_RX_MIPI_RX19_1B_ECC_ERR_MASK

#define CTRL1_CSI_ERR_L_MIPI_RX_MIPI_RX19_1B_ECC_ERR_MASK (0x01U)

◆ CTRL1_CSI_ERR_L_MIPI_RX_MIPI_RX19_1B_ECC_ERR_POS

#define CTRL1_CSI_ERR_L_MIPI_RX_MIPI_RX19_1B_ECC_ERR_POS (0U)

◆ CTRL1_CSI_ERR_L_MIPI_RX_MIPI_RX19_2B_ECC_ERR_MASK

#define CTRL1_CSI_ERR_L_MIPI_RX_MIPI_RX19_2B_ECC_ERR_MASK (0x02U)

◆ CTRL1_CSI_ERR_L_MIPI_RX_MIPI_RX19_2B_ECC_ERR_POS

#define CTRL1_CSI_ERR_L_MIPI_RX_MIPI_RX19_2B_ECC_ERR_POS (1U)

◆ CTRL1_CSI_ERR_L_MIPI_RX_MIPI_RX19_ADDR

#define CTRL1_CSI_ERR_L_MIPI_RX_MIPI_RX19_ADDR 0x343U

◆ CTRL1_CSI_ERR_L_MIPI_RX_MIPI_RX19_CRC_ERR_MASK

#define CTRL1_CSI_ERR_L_MIPI_RX_MIPI_RX19_CRC_ERR_MASK (0x80U)

◆ CTRL1_CSI_ERR_L_MIPI_RX_MIPI_RX19_CRC_ERR_POS

#define CTRL1_CSI_ERR_L_MIPI_RX_MIPI_RX19_CRC_ERR_POS (7U)

◆ CTRL1_CSI_ERR_L_MIPI_RX_MIPI_RX19_MASK

#define CTRL1_CSI_ERR_L_MIPI_RX_MIPI_RX19_MASK 0xFFU

◆ CTRL1_CSI_ERR_L_MIPI_RX_MIPI_RX19_POS

#define CTRL1_CSI_ERR_L_MIPI_RX_MIPI_RX19_POS 0U

◆ CTRL1_DESKEWEN_MIPI_RX_MIPI_RX1_ADDR

#define CTRL1_DESKEWEN_MIPI_RX_MIPI_RX1_ADDR 0x331U

◆ CTRL1_DESKEWEN_MIPI_RX_MIPI_RX1_MASK

#define CTRL1_DESKEWEN_MIPI_RX_MIPI_RX1_MASK 0x40U

◆ CTRL1_DESKEWEN_MIPI_RX_MIPI_RX1_POS

#define CTRL1_DESKEWEN_MIPI_RX_MIPI_RX1_POS 6U

◆ CTRL1_FE_CNT_H_MIPI_RX_EXT3_EXT7_ADDR

#define CTRL1_FE_CNT_H_MIPI_RX_EXT3_EXT7_ADDR 0x587U

◆ CTRL1_FE_CNT_H_MIPI_RX_EXT3_EXT7_MASK

#define CTRL1_FE_CNT_H_MIPI_RX_EXT3_EXT7_MASK 0xFFU

◆ CTRL1_FE_CNT_H_MIPI_RX_EXT3_EXT7_POS

#define CTRL1_FE_CNT_H_MIPI_RX_EXT3_EXT7_POS 0U

◆ CTRL1_FE_CNT_L_MIPI_RX_EXT3_EXT6_ADDR

#define CTRL1_FE_CNT_L_MIPI_RX_EXT3_EXT6_ADDR 0x586U

◆ CTRL1_FE_CNT_L_MIPI_RX_EXT3_EXT6_MASK

#define CTRL1_FE_CNT_L_MIPI_RX_EXT3_EXT6_MASK 0xFFU

◆ CTRL1_FE_CNT_L_MIPI_RX_EXT3_EXT6_POS

#define CTRL1_FE_CNT_L_MIPI_RX_EXT3_EXT6_POS 0U

◆ CTRL1_FS_CNT_H_MIPI_RX_EXT3_EXT5_ADDR

#define CTRL1_FS_CNT_H_MIPI_RX_EXT3_EXT5_ADDR 0x585U

◆ CTRL1_FS_CNT_H_MIPI_RX_EXT3_EXT5_MASK

#define CTRL1_FS_CNT_H_MIPI_RX_EXT3_EXT5_MASK 0xFFU

◆ CTRL1_FS_CNT_H_MIPI_RX_EXT3_EXT5_POS

#define CTRL1_FS_CNT_H_MIPI_RX_EXT3_EXT5_POS 0U

◆ CTRL1_FS_CNT_L_MIPI_RX_EXT3_EXT4_ADDR

#define CTRL1_FS_CNT_L_MIPI_RX_EXT3_EXT4_ADDR 0x584U

◆ CTRL1_FS_CNT_L_MIPI_RX_EXT3_EXT4_MASK

#define CTRL1_FS_CNT_L_MIPI_RX_EXT3_EXT4_MASK 0xFFU

◆ CTRL1_FS_CNT_L_MIPI_RX_EXT3_EXT4_POS

#define CTRL1_FS_CNT_L_MIPI_RX_EXT3_EXT4_POS 0U

◆ CTRL1_FS_VC_SEL_MIPI_RX_EXT3_EXT8_ADDR

#define CTRL1_FS_VC_SEL_MIPI_RX_EXT3_EXT8_ADDR 0x588U

◆ CTRL1_FS_VC_SEL_MIPI_RX_EXT3_EXT8_MASK

#define CTRL1_FS_VC_SEL_MIPI_RX_EXT3_EXT8_MASK 0x0FU

◆ CTRL1_FS_VC_SEL_MIPI_RX_EXT3_EXT8_POS

#define CTRL1_FS_VC_SEL_MIPI_RX_EXT3_EXT8_POS 0U

◆ CTRL1_NUM_LANES_MIPI_RX_MIPI_RX1_ADDR

#define CTRL1_NUM_LANES_MIPI_RX_MIPI_RX1_ADDR 0x331U

◆ CTRL1_NUM_LANES_MIPI_RX_MIPI_RX1_MASK

#define CTRL1_NUM_LANES_MIPI_RX_MIPI_RX1_MASK 0x30U

◆ CTRL1_NUM_LANES_MIPI_RX_MIPI_RX1_POS

#define CTRL1_NUM_LANES_MIPI_RX_MIPI_RX1_POS 4U

◆ CTRL1_VC_MAP0_MIPI_RX_MIPI_RX21_ADDR

#define CTRL1_VC_MAP0_MIPI_RX_MIPI_RX21_ADDR 0x345U

◆ CTRL1_VC_MAP0_MIPI_RX_MIPI_RX21_MASK

#define CTRL1_VC_MAP0_MIPI_RX_MIPI_RX21_MASK 0xF0U

◆ CTRL1_VC_MAP0_MIPI_RX_MIPI_RX21_POS

#define CTRL1_VC_MAP0_MIPI_RX_MIPI_RX21_POS 4U

◆ CTRL1_VC_MAP10_MIPI_RX_EXT_EXT2_ADDR

#define CTRL1_VC_MAP10_MIPI_RX_EXT_EXT2_ADDR 0x37AU

◆ CTRL1_VC_MAP10_MIPI_RX_EXT_EXT2_MASK

#define CTRL1_VC_MAP10_MIPI_RX_EXT_EXT2_MASK 0xF0U

◆ CTRL1_VC_MAP10_MIPI_RX_EXT_EXT2_POS

#define CTRL1_VC_MAP10_MIPI_RX_EXT_EXT2_POS 4U

◆ CTRL1_VC_MAP11_MIPI_RX_EXT_EXT3_ADDR

#define CTRL1_VC_MAP11_MIPI_RX_EXT_EXT3_ADDR 0x37BU

◆ CTRL1_VC_MAP11_MIPI_RX_EXT_EXT3_MASK

#define CTRL1_VC_MAP11_MIPI_RX_EXT_EXT3_MASK 0xF0U

◆ CTRL1_VC_MAP11_MIPI_RX_EXT_EXT3_POS

#define CTRL1_VC_MAP11_MIPI_RX_EXT_EXT3_POS 4U

◆ CTRL1_VC_MAP12_MIPI_RX_EXT_EXT4_ADDR

#define CTRL1_VC_MAP12_MIPI_RX_EXT_EXT4_ADDR 0x37CU

◆ CTRL1_VC_MAP12_MIPI_RX_EXT_EXT4_MASK

#define CTRL1_VC_MAP12_MIPI_RX_EXT_EXT4_MASK 0xF0U

◆ CTRL1_VC_MAP12_MIPI_RX_EXT_EXT4_POS

#define CTRL1_VC_MAP12_MIPI_RX_EXT_EXT4_POS 4U

◆ CTRL1_VC_MAP13_MIPI_RX_EXT_EXT5_ADDR

#define CTRL1_VC_MAP13_MIPI_RX_EXT_EXT5_ADDR 0x37DU

◆ CTRL1_VC_MAP13_MIPI_RX_EXT_EXT5_MASK

#define CTRL1_VC_MAP13_MIPI_RX_EXT_EXT5_MASK 0xF0U

◆ CTRL1_VC_MAP13_MIPI_RX_EXT_EXT5_POS

#define CTRL1_VC_MAP13_MIPI_RX_EXT_EXT5_POS 4U

◆ CTRL1_VC_MAP14_MIPI_RX_EXT_EXT6_ADDR

#define CTRL1_VC_MAP14_MIPI_RX_EXT_EXT6_ADDR 0x37EU

◆ CTRL1_VC_MAP14_MIPI_RX_EXT_EXT6_MASK

#define CTRL1_VC_MAP14_MIPI_RX_EXT_EXT6_MASK 0xF0U

◆ CTRL1_VC_MAP14_MIPI_RX_EXT_EXT6_POS

#define CTRL1_VC_MAP14_MIPI_RX_EXT_EXT6_POS 4U

◆ CTRL1_VC_MAP15_MIPI_RX_EXT_EXT7_ADDR

#define CTRL1_VC_MAP15_MIPI_RX_EXT_EXT7_ADDR 0x37FU

◆ CTRL1_VC_MAP15_MIPI_RX_EXT_EXT7_MASK

#define CTRL1_VC_MAP15_MIPI_RX_EXT_EXT7_MASK 0xF0U

◆ CTRL1_VC_MAP15_MIPI_RX_EXT_EXT7_POS

#define CTRL1_VC_MAP15_MIPI_RX_EXT_EXT7_POS 4U

◆ CTRL1_VC_MAP1_MIPI_RX_MIPI_RX22_ADDR

#define CTRL1_VC_MAP1_MIPI_RX_MIPI_RX22_ADDR 0x346U

◆ CTRL1_VC_MAP1_MIPI_RX_MIPI_RX22_MASK

#define CTRL1_VC_MAP1_MIPI_RX_MIPI_RX22_MASK 0xF0U

◆ CTRL1_VC_MAP1_MIPI_RX_MIPI_RX22_POS

#define CTRL1_VC_MAP1_MIPI_RX_MIPI_RX22_POS 4U

◆ CTRL1_VC_MAP2_MIPI_RX_MIPI_RX23_ADDR

#define CTRL1_VC_MAP2_MIPI_RX_MIPI_RX23_ADDR 0x347U

◆ CTRL1_VC_MAP2_MIPI_RX_MIPI_RX23_MASK

#define CTRL1_VC_MAP2_MIPI_RX_MIPI_RX23_MASK 0xF0U

◆ CTRL1_VC_MAP2_MIPI_RX_MIPI_RX23_POS

#define CTRL1_VC_MAP2_MIPI_RX_MIPI_RX23_POS 4U

◆ CTRL1_VC_MAP3_MIPI_RX_MIPI_RX60_ADDR

#define CTRL1_VC_MAP3_MIPI_RX_MIPI_RX60_ADDR 0x36CU

◆ CTRL1_VC_MAP3_MIPI_RX_MIPI_RX60_MASK

#define CTRL1_VC_MAP3_MIPI_RX_MIPI_RX60_MASK 0xF0U

◆ CTRL1_VC_MAP3_MIPI_RX_MIPI_RX60_POS

#define CTRL1_VC_MAP3_MIPI_RX_MIPI_RX60_POS 4U

◆ CTRL1_VC_MAP4_MIPI_RX_MIPI_RX61_ADDR

#define CTRL1_VC_MAP4_MIPI_RX_MIPI_RX61_ADDR 0x36DU

◆ CTRL1_VC_MAP4_MIPI_RX_MIPI_RX61_MASK

#define CTRL1_VC_MAP4_MIPI_RX_MIPI_RX61_MASK 0xF0U

◆ CTRL1_VC_MAP4_MIPI_RX_MIPI_RX61_POS

#define CTRL1_VC_MAP4_MIPI_RX_MIPI_RX61_POS 4U

◆ CTRL1_VC_MAP5_MIPI_RX_MIPI_RX62_ADDR

#define CTRL1_VC_MAP5_MIPI_RX_MIPI_RX62_ADDR 0x36EU

◆ CTRL1_VC_MAP5_MIPI_RX_MIPI_RX62_MASK

#define CTRL1_VC_MAP5_MIPI_RX_MIPI_RX62_MASK 0xF0U

◆ CTRL1_VC_MAP5_MIPI_RX_MIPI_RX62_POS

#define CTRL1_VC_MAP5_MIPI_RX_MIPI_RX62_POS 4U

◆ CTRL1_VC_MAP6_MIPI_RX_MIPI_RX63_ADDR

#define CTRL1_VC_MAP6_MIPI_RX_MIPI_RX63_ADDR 0x36FU

◆ CTRL1_VC_MAP6_MIPI_RX_MIPI_RX63_MASK

#define CTRL1_VC_MAP6_MIPI_RX_MIPI_RX63_MASK 0xF0U

◆ CTRL1_VC_MAP6_MIPI_RX_MIPI_RX63_POS

#define CTRL1_VC_MAP6_MIPI_RX_MIPI_RX63_POS 4U

◆ CTRL1_VC_MAP7_MIPI_RX_EXT_EXT00_ADDR

#define CTRL1_VC_MAP7_MIPI_RX_EXT_EXT00_ADDR 0x377U

◆ CTRL1_VC_MAP7_MIPI_RX_EXT_EXT00_MASK

#define CTRL1_VC_MAP7_MIPI_RX_EXT_EXT00_MASK 0xF0U

◆ CTRL1_VC_MAP7_MIPI_RX_EXT_EXT00_POS

#define CTRL1_VC_MAP7_MIPI_RX_EXT_EXT00_POS 4U

◆ CTRL1_VC_MAP8_MIPI_RX_EXT_EXT0_ADDR

#define CTRL1_VC_MAP8_MIPI_RX_EXT_EXT0_ADDR 0x378U

◆ CTRL1_VC_MAP8_MIPI_RX_EXT_EXT0_MASK

#define CTRL1_VC_MAP8_MIPI_RX_EXT_EXT0_MASK 0xF0U

◆ CTRL1_VC_MAP8_MIPI_RX_EXT_EXT0_POS

#define CTRL1_VC_MAP8_MIPI_RX_EXT_EXT0_POS 4U

◆ CTRL1_VC_MAP9_MIPI_RX_EXT_EXT1_ADDR

#define CTRL1_VC_MAP9_MIPI_RX_EXT_EXT1_ADDR 0x379U

◆ CTRL1_VC_MAP9_MIPI_RX_EXT_EXT1_MASK

#define CTRL1_VC_MAP9_MIPI_RX_EXT_EXT1_MASK 0xF0U

◆ CTRL1_VC_MAP9_MIPI_RX_EXT_EXT1_POS

#define CTRL1_VC_MAP9_MIPI_RX_EXT_EXT1_POS 4U

◆ CTRL1_VC_MAP_EN_MIPI_RX_MIPI_RX0_ADDR

#define CTRL1_VC_MAP_EN_MIPI_RX_MIPI_RX0_ADDR 0x330U

◆ CTRL1_VC_MAP_EN_MIPI_RX_MIPI_RX0_MASK

#define CTRL1_VC_MAP_EN_MIPI_RX_MIPI_RX0_MASK 0x20U

◆ CTRL1_VC_MAP_EN_MIPI_RX_MIPI_RX0_POS

#define CTRL1_VC_MAP_EN_MIPI_RX_MIPI_RX0_POS 5U

◆ CTRL1_VCX_EN_MIPI_RX_MIPI_RX1_ADDR

#define CTRL1_VCX_EN_MIPI_RX_MIPI_RX1_ADDR 0x331U

◆ CTRL1_VCX_EN_MIPI_RX_MIPI_RX1_MASK

#define CTRL1_VCX_EN_MIPI_RX_MIPI_RX1_MASK 0x80U

◆ CTRL1_VCX_EN_MIPI_RX_MIPI_RX1_POS

#define CTRL1_VCX_EN_MIPI_RX_MIPI_RX1_POS 7U

◆ CXTP_A_TCTRL_CTRL1_ADDR

#define CXTP_A_TCTRL_CTRL1_ADDR 0x11U

◆ CXTP_A_TCTRL_CTRL1_MASK

#define CXTP_A_TCTRL_CTRL1_MASK 0x01U

◆ CXTP_A_TCTRL_CTRL1_POS

#define CXTP_A_TCTRL_CTRL1_POS 0U

◆ DATA_TYPE_ENABLE_MASK

#define DATA_TYPE_ENABLE_MASK (0x40U)

◆ DATA_TYPE_ENABLE_POS

#define DATA_TYPE_ENABLE_POS (6U)

◆ DATA_TYPE_MASK

#define DATA_TYPE_MASK (0x3FU)

◆ DE_CNT_0_VTX_Z_VTX28_ADDR

#define DE_CNT_0_VTX_Z_VTX28_ADDR 0x26AU

◆ DE_CNT_0_VTX_Z_VTX28_MASK

#define DE_CNT_0_VTX_Z_VTX28_MASK 0xFFU

◆ DE_CNT_0_VTX_Z_VTX28_POS

#define DE_CNT_0_VTX_Z_VTX28_POS 0U

◆ DE_CNT_1_VTX_Z_VTX27_ADDR

#define DE_CNT_1_VTX_Z_VTX27_ADDR 0x269U

◆ DE_CNT_1_VTX_Z_VTX27_MASK

#define DE_CNT_1_VTX_Z_VTX27_MASK 0xFFU

◆ DE_CNT_1_VTX_Z_VTX27_POS

#define DE_CNT_1_VTX_Z_VTX27_POS 0U

◆ DE_DET_Z_MISC_HS_VS_Z_ADDR

#define DE_DET_Z_MISC_HS_VS_Z_ADDR 0x55FU

◆ DE_DET_Z_MISC_HS_VS_Z_MASK

#define DE_DET_Z_MISC_HS_VS_Z_MASK 0x40U

◆ DE_DET_Z_MISC_HS_VS_Z_POS

#define DE_DET_Z_MISC_HS_VS_Z_POS 6U

◆ DE_HIGH_0_VTX_Z_VTX24_ADDR

#define DE_HIGH_0_VTX_Z_VTX24_ADDR 0x266U

◆ DE_HIGH_0_VTX_Z_VTX24_MASK

#define DE_HIGH_0_VTX_Z_VTX24_MASK 0xFFU

◆ DE_HIGH_0_VTX_Z_VTX24_POS

#define DE_HIGH_0_VTX_Z_VTX24_POS 0U

◆ DE_HIGH_1_VTX_Z_VTX23_ADDR

#define DE_HIGH_1_VTX_Z_VTX23_ADDR 0x265U

◆ DE_HIGH_1_VTX_Z_VTX23_MASK

#define DE_HIGH_1_VTX_Z_VTX23_MASK 0xFFU

◆ DE_HIGH_1_VTX_Z_VTX23_POS

#define DE_HIGH_1_VTX_Z_VTX23_POS 0U

◆ DE_INV_VTX_Z_VTX0_ADDR

#define DE_INV_VTX_Z_VTX0_ADDR 0x24EU

◆ DE_INV_VTX_Z_VTX0_MASK

#define DE_INV_VTX_Z_VTX0_MASK 0x04U

◆ DE_INV_VTX_Z_VTX0_POS

#define DE_INV_VTX_Z_VTX0_POS 2U

◆ DE_LOW_0_VTX_Z_VTX26_ADDR

#define DE_LOW_0_VTX_Z_VTX26_ADDR 0x268U

◆ DE_LOW_0_VTX_Z_VTX26_MASK

#define DE_LOW_0_VTX_Z_VTX26_MASK 0xFFU

◆ DE_LOW_0_VTX_Z_VTX26_POS

#define DE_LOW_0_VTX_Z_VTX26_POS 0U

◆ DE_LOW_1_VTX_Z_VTX25_ADDR

#define DE_LOW_1_VTX_Z_VTX25_ADDR 0x267U

◆ DE_LOW_1_VTX_Z_VTX25_MASK

#define DE_LOW_1_VTX_Z_VTX25_MASK 0xFFU

◆ DE_LOW_1_VTX_Z_VTX25_POS

#define DE_LOW_1_VTX_Z_VTX25_POS 0U

◆ DEC_ERR_A_TCTRL_CNT0_ADDR

#define DEC_ERR_A_TCTRL_CNT0_ADDR 0x22U

◆ DEC_ERR_A_TCTRL_CNT0_MASK

#define DEC_ERR_A_TCTRL_CNT0_MASK 0xFFU

◆ DEC_ERR_A_TCTRL_CNT0_POS

#define DEC_ERR_A_TCTRL_CNT0_POS 0U

◆ DEC_ERR_FLAG_A_TCTRL_INTR3_ADDR

#define DEC_ERR_FLAG_A_TCTRL_INTR3_ADDR 0x1BU

◆ DEC_ERR_FLAG_A_TCTRL_INTR3_MASK

#define DEC_ERR_FLAG_A_TCTRL_INTR3_MASK 0x01U

◆ DEC_ERR_FLAG_A_TCTRL_INTR3_POS

#define DEC_ERR_FLAG_A_TCTRL_INTR3_POS 0U

◆ DEC_ERR_OEN_A_TCTRL_INTR2_ADDR

#define DEC_ERR_OEN_A_TCTRL_INTR2_ADDR 0x1AU

◆ DEC_ERR_OEN_A_TCTRL_INTR2_MASK

#define DEC_ERR_OEN_A_TCTRL_INTR2_MASK 0x01U

◆ DEC_ERR_OEN_A_TCTRL_INTR2_POS

#define DEC_ERR_OEN_A_TCTRL_INTR2_POS 0U

◆ DEC_ERR_THR_TCTRL_INTR0_ADDR

#define DEC_ERR_THR_TCTRL_INTR0_ADDR 0x18U

◆ DEC_ERR_THR_TCTRL_INTR0_MASK

#define DEC_ERR_THR_TCTRL_INTR0_MASK 0x07U

◆ DEC_ERR_THR_TCTRL_INTR0_POS

#define DEC_ERR_THR_TCTRL_INTR0_POS 0U

◆ DEV_ADDR_DEV_REG0_ADDR

#define DEV_ADDR_DEV_REG0_ADDR 0x00U

◆ DEV_ADDR_DEV_REG0_MASK

#define DEV_ADDR_DEV_REG0_MASK 0xFEU

◆ DEV_ADDR_DEV_REG0_POS

#define DEV_ADDR_DEV_REG0_POS 1U

◆ DEV_ID_DEV_REG13_ADDR

#define DEV_ID_DEV_REG13_ADDR 0x0DU

◆ DEV_ID_DEV_REG13_MASK

#define DEV_ID_DEV_REG13_MASK 0xFFU

◆ DEV_ID_DEV_REG13_POS

#define DEV_ID_DEV_REG13_POS 0U

◆ DEV_REG0_ADDR

#define DEV_REG0_ADDR 0x00U

◆ DEV_REG0_DEFAULT

#define DEV_REG0_DEFAULT 0x80U

◆ DEV_REG13_ADDR

#define DEV_REG13_ADDR 0x0DU

◆ DEV_REG13_DEFAULT

#define DEV_REG13_DEFAULT 0xB7U

◆ DEV_REG14_ADDR

#define DEV_REG14_ADDR 0x0EU

◆ DEV_REG14_DEFAULT

#define DEV_REG14_DEFAULT 0x06U

◆ DEV_REG1_ADDR

#define DEV_REG1_ADDR 0x01U

◆ DEV_REG1_DEFAULT

#define DEV_REG1_DEFAULT 0x08U

◆ DEV_REG26_ADDR

#define DEV_REG26_ADDR 0x26U

◆ DEV_REG26_DEFAULT

#define DEV_REG26_DEFAULT 0x22U

◆ DEV_REG2_ADDR

#define DEV_REG2_ADDR 0x02U

◆ DEV_REG2_DEFAULT

#define DEV_REG2_DEFAULT 0x43U

◆ DEV_REG3_ADDR

#define DEV_REG3_ADDR 0x03U

◆ DEV_REG3_DEFAULT

#define DEV_REG3_DEFAULT 0x00U

◆ DEV_REG4_ADDR

#define DEV_REG4_ADDR 0x04U

◆ DEV_REG4_DEFAULT

#define DEV_REG4_DEFAULT 0x18U

◆ DEV_REG5_ADDR

#define DEV_REG5_ADDR 0x05U

◆ DEV_REG5_DEFAULT

#define DEV_REG5_DEFAULT 0x00U

◆ DEV_REG6_ADDR

#define DEV_REG6_ADDR 0x06U

◆ DEV_REG6_DEFAULT

#define DEV_REG6_DEFAULT 0x80U

◆ DEV_REV_DEV_REG14_ADDR

#define DEV_REV_DEV_REG14_ADDR 0x0EU

◆ DEV_REV_DEV_REG14_MASK

#define DEV_REV_DEV_REG14_MASK 0x0FU

◆ DEV_REV_DEV_REG14_POS

#define DEV_REV_DEV_REG14_POS 0U

◆ DFE1EN_RLMS_A_RLMS17_ADDR

#define DFE1EN_RLMS_A_RLMS17_ADDR 0x1417U

◆ DFE1EN_RLMS_A_RLMS17_MASK

#define DFE1EN_RLMS_A_RLMS17_MASK 0x08U

◆ DFE1EN_RLMS_A_RLMS17_POS

#define DFE1EN_RLMS_A_RLMS17_POS 3U

◆ DFE2EN_RLMS_A_RLMS17_ADDR

#define DFE2EN_RLMS_A_RLMS17_ADDR 0x1417U

◆ DFE2EN_RLMS_A_RLMS17_MASK

#define DFE2EN_RLMS_A_RLMS17_MASK 0x10U

◆ DFE2EN_RLMS_A_RLMS17_POS

#define DFE2EN_RLMS_A_RLMS17_POS 4U

◆ DFE3EN_RLMS_A_RLMS17_ADDR

#define DFE3EN_RLMS_A_RLMS17_ADDR 0x1417U

◆ DFE3EN_RLMS_A_RLMS17_MASK

#define DFE3EN_RLMS_A_RLMS17_MASK 0x20U

◆ DFE3EN_RLMS_A_RLMS17_POS

#define DFE3EN_RLMS_A_RLMS17_POS 5U

◆ DFE4EN_RLMS_A_RLMS17_ADDR

#define DFE4EN_RLMS_A_RLMS17_ADDR 0x1417U

◆ DFE4EN_RLMS_A_RLMS17_MASK

#define DFE4EN_RLMS_A_RLMS17_MASK 0x40U

◆ DFE4EN_RLMS_A_RLMS17_POS

#define DFE4EN_RLMS_A_RLMS17_POS 6U

◆ DFE5EN_RLMS_A_RLMS17_ADDR

#define DFE5EN_RLMS_A_RLMS17_ADDR 0x1417U

◆ DFE5EN_RLMS_A_RLMS17_MASK

#define DFE5EN_RLMS_A_RLMS17_MASK 0x80U

◆ DFE5EN_RLMS_A_RLMS17_POS

#define DFE5EN_RLMS_A_RLMS17_POS 7U

◆ DIS_DBL_ACK_RETX_CFGL_GPIO_ARQ0_ADDR

#define DIS_DBL_ACK_RETX_CFGL_GPIO_ARQ0_ADDR 0x95U

◆ DIS_DBL_ACK_RETX_CFGL_GPIO_ARQ0_MASK

#define DIS_DBL_ACK_RETX_CFGL_GPIO_ARQ0_MASK 0x04U

◆ DIS_DBL_ACK_RETX_CFGL_GPIO_ARQ0_POS

#define DIS_DBL_ACK_RETX_CFGL_GPIO_ARQ0_POS 2U

◆ DIS_DBL_ACK_RETX_CFGL_IIC_X_ARQ0_ADDR

#define DIS_DBL_ACK_RETX_CFGL_IIC_X_ARQ0_ADDR 0xA5U

◆ DIS_DBL_ACK_RETX_CFGL_IIC_X_ARQ0_MASK

#define DIS_DBL_ACK_RETX_CFGL_IIC_X_ARQ0_MASK 0x04U

◆ DIS_DBL_ACK_RETX_CFGL_IIC_X_ARQ0_POS

#define DIS_DBL_ACK_RETX_CFGL_IIC_X_ARQ0_POS 2U

◆ DIS_DBL_ACK_RETX_CFGL_IIC_Y_ARQ0_ADDR

#define DIS_DBL_ACK_RETX_CFGL_IIC_Y_ARQ0_ADDR 0xADU

◆ DIS_DBL_ACK_RETX_CFGL_IIC_Y_ARQ0_MASK

#define DIS_DBL_ACK_RETX_CFGL_IIC_Y_ARQ0_MASK 0x04U

◆ DIS_DBL_ACK_RETX_CFGL_IIC_Y_ARQ0_POS

#define DIS_DBL_ACK_RETX_CFGL_IIC_Y_ARQ0_POS 2U

◆ DIS_DBL_ACK_RETX_CFGL_SPI_ARQ0_ADDR

#define DIS_DBL_ACK_RETX_CFGL_SPI_ARQ0_ADDR 0x85U

◆ DIS_DBL_ACK_RETX_CFGL_SPI_ARQ0_MASK

#define DIS_DBL_ACK_RETX_CFGL_SPI_ARQ0_MASK 0x04U

◆ DIS_DBL_ACK_RETX_CFGL_SPI_ARQ0_POS

#define DIS_DBL_ACK_RETX_CFGL_SPI_ARQ0_POS 2U

◆ DIS_ENC_GMSL_TX1_ADDR

#define DIS_ENC_GMSL_TX1_ADDR 0x29U

◆ DIS_ENC_GMSL_TX1_MASK

#define DIS_ENC_GMSL_TX1_MASK 0x01U

◆ DIS_ENC_GMSL_TX1_POS

#define DIS_ENC_GMSL_TX1_POS 0U

◆ DIS_LOCAL_CC_DEV_REG1_ADDR

#define DIS_LOCAL_CC_DEV_REG1_ADDR 0x01U

◆ DIS_LOCAL_CC_DEV_REG1_MASK

#define DIS_LOCAL_CC_DEV_REG1_MASK 0x20U

◆ DIS_LOCAL_CC_DEV_REG1_POS

#define DIS_LOCAL_CC_DEV_REG1_POS 5U

◆ DIS_LOCAL_WAKE_TCTRL_PWR4_ADDR

#define DIS_LOCAL_WAKE_TCTRL_PWR4_ADDR 0x0CU

◆ DIS_LOCAL_WAKE_TCTRL_PWR4_MASK

#define DIS_LOCAL_WAKE_TCTRL_PWR4_MASK 0x40U

◆ DIS_LOCAL_WAKE_TCTRL_PWR4_POS

#define DIS_LOCAL_WAKE_TCTRL_PWR4_POS 6U

◆ DIS_PAR_1_CC_UART_PT_0_ADDR

#define DIS_PAR_1_CC_UART_PT_0_ADDR 0x4FU

◆ DIS_PAR_1_CC_UART_PT_0_MASK

#define DIS_PAR_1_CC_UART_PT_0_MASK 0x04U

◆ DIS_PAR_1_CC_UART_PT_0_POS

#define DIS_PAR_1_CC_UART_PT_0_POS 2U

◆ DIS_PAR_2_CC_UART_PT_0_ADDR

#define DIS_PAR_2_CC_UART_PT_0_ADDR 0x4FU

◆ DIS_PAR_2_CC_UART_PT_0_MASK

#define DIS_PAR_2_CC_UART_PT_0_MASK 0x40U

◆ DIS_PAR_2_CC_UART_PT_0_POS

#define DIS_PAR_2_CC_UART_PT_0_POS 6U

◆ DIS_REM_CC_DEV_REG1_ADDR

#define DIS_REM_CC_DEV_REG1_ADDR 0x01U

◆ DIS_REM_CC_DEV_REG1_MASK

#define DIS_REM_CC_DEV_REG1_MASK 0x10U

◆ DIS_REM_CC_DEV_REG1_POS

#define DIS_REM_CC_DEV_REG1_POS 4U

◆ DIS_SCR_GMSL_TX1_ADDR

#define DIS_SCR_GMSL_TX1_ADDR 0x29U

◆ DIS_SCR_GMSL_TX1_MASK

#define DIS_SCR_GMSL_TX1_MASK 0x02U

◆ DIS_SCR_GMSL_TX1_POS

#define DIS_SCR_GMSL_TX1_POS 1U

◆ DIV_SEL0_AFE_ADC_LIMIT0_3_ADDR

#define DIV_SEL0_AFE_ADC_LIMIT0_3_ADDR 0x517U

◆ DIV_SEL0_AFE_ADC_LIMIT0_3_MASK

#define DIV_SEL0_AFE_ADC_LIMIT0_3_MASK 0x30U

◆ DIV_SEL0_AFE_ADC_LIMIT0_3_POS

#define DIV_SEL0_AFE_ADC_LIMIT0_3_POS 4U

◆ DIV_SEL1_AFE_ADC_LIMIT1_3_ADDR

#define DIV_SEL1_AFE_ADC_LIMIT1_3_ADDR 0x51BU

◆ DIV_SEL1_AFE_ADC_LIMIT1_3_MASK

#define DIV_SEL1_AFE_ADC_LIMIT1_3_MASK 0x30U

◆ DIV_SEL1_AFE_ADC_LIMIT1_3_POS

#define DIV_SEL1_AFE_ADC_LIMIT1_3_POS 4U

◆ DIV_SEL2_AFE_ADC_LIMIT2_3_ADDR

#define DIV_SEL2_AFE_ADC_LIMIT2_3_ADDR 0x51FU

◆ DIV_SEL2_AFE_ADC_LIMIT2_3_MASK

#define DIV_SEL2_AFE_ADC_LIMIT2_3_MASK 0x30U

◆ DIV_SEL2_AFE_ADC_LIMIT2_3_POS

#define DIV_SEL2_AFE_ADC_LIMIT2_3_POS 4U

◆ DIV_SEL3_AFE_ADC_LIMIT3_3_ADDR

#define DIV_SEL3_AFE_ADC_LIMIT3_3_ADDR 0x523U

◆ DIV_SEL3_AFE_ADC_LIMIT3_3_MASK

#define DIV_SEL3_AFE_ADC_LIMIT3_3_MASK 0x30U

◆ DIV_SEL3_AFE_ADC_LIMIT3_3_POS

#define DIV_SEL3_AFE_ADC_LIMIT3_3_POS 4U

◆ DIV_SEL4_AFE_ADC_LIMIT4_3_ADDR

#define DIV_SEL4_AFE_ADC_LIMIT4_3_ADDR 0x527U

◆ DIV_SEL4_AFE_ADC_LIMIT4_3_MASK

#define DIV_SEL4_AFE_ADC_LIMIT4_3_MASK 0x30U

◆ DIV_SEL4_AFE_ADC_LIMIT4_3_POS

#define DIV_SEL4_AFE_ADC_LIMIT4_3_POS 4U

◆ DIV_SEL5_AFE_ADC_LIMIT5_3_ADDR

#define DIV_SEL5_AFE_ADC_LIMIT5_3_ADDR 0x52BU

◆ DIV_SEL5_AFE_ADC_LIMIT5_3_MASK

#define DIV_SEL5_AFE_ADC_LIMIT5_3_MASK 0x30U

◆ DIV_SEL5_AFE_ADC_LIMIT5_3_POS

#define DIV_SEL5_AFE_ADC_LIMIT5_3_POS 4U

◆ DIV_SEL6_AFE_ADC_LIMIT6_3_ADDR

#define DIV_SEL6_AFE_ADC_LIMIT6_3_ADDR 0x52FU

◆ DIV_SEL6_AFE_ADC_LIMIT6_3_MASK

#define DIV_SEL6_AFE_ADC_LIMIT6_3_MASK 0x30U

◆ DIV_SEL6_AFE_ADC_LIMIT6_3_POS

#define DIV_SEL6_AFE_ADC_LIMIT6_3_POS 4U

◆ DIV_SEL7_AFE_ADC_LIMIT7_3_ADDR

#define DIV_SEL7_AFE_ADC_LIMIT7_3_ADDR 0x533U

◆ DIV_SEL7_AFE_ADC_LIMIT7_3_MASK

#define DIV_SEL7_AFE_ADC_LIMIT7_3_MASK 0x30U

◆ DIV_SEL7_AFE_ADC_LIMIT7_3_POS

#define DIV_SEL7_AFE_ADC_LIMIT7_3_POS 4U

◆ DPLL_REF_DPLL_0_ADDR

#define DPLL_REF_DPLL_0_ADDR 0x1A00U

◆ DPLL_REF_DPLL_0_DEFAULT

#define DPLL_REF_DPLL_0_DEFAULT 0xF5U

◆ DPLL_REF_DPLL_10_ADDR

#define DPLL_REF_DPLL_10_ADDR 0x1A0AU

◆ DPLL_REF_DPLL_10_DEFAULT

#define DPLL_REF_DPLL_10_DEFAULT 0x81U

◆ DPLL_REF_DPLL_3_ADDR

#define DPLL_REF_DPLL_3_ADDR 0x1A03U

◆ DPLL_REF_DPLL_3_DEFAULT

#define DPLL_REF_DPLL_3_DEFAULT 0x82U

◆ DPLL_REF_DPLL_7_ADDR

#define DPLL_REF_DPLL_7_ADDR 0x1A07U

◆ DPLL_REF_DPLL_7_DEFAULT

#define DPLL_REF_DPLL_7_DEFAULT 0x04U

◆ DPLL_REF_DPLL_8_ADDR

#define DPLL_REF_DPLL_8_ADDR 0x1A08U

◆ DPLL_REF_DPLL_8_DEFAULT

#define DPLL_REF_DPLL_8_DEFAULT 0x14U

◆ DPLL_REF_DPLL_9_ADDR

#define DPLL_REF_DPLL_9_ADDR 0x1A09U

◆ DPLL_REF_DPLL_9_DEFAULT

#define DPLL_REF_DPLL_9_DEFAULT 0x40U

◆ DRIFT_ERR_VID_TX_Z_VIDEO_TX2_ADDR

#define DRIFT_ERR_VID_TX_Z_VIDEO_TX2_ADDR 0x112U

◆ DRIFT_ERR_VID_TX_Z_VIDEO_TX2_MASK

#define DRIFT_ERR_VID_TX_Z_VIDEO_TX2_MASK 0x40U

◆ DRIFT_ERR_VID_TX_Z_VIDEO_TX2_POS

#define DRIFT_ERR_VID_TX_Z_VIDEO_TX2_POS 6U

◆ DST_A_1_MISC_I2C_PT_5_ADDR

#define DST_A_1_MISC_I2C_PT_5_ADDR 0x551U

◆ DST_A_1_MISC_I2C_PT_5_MASK

#define DST_A_1_MISC_I2C_PT_5_MASK 0xFEU

◆ DST_A_1_MISC_I2C_PT_5_POS

#define DST_A_1_MISC_I2C_PT_5_POS 1U

◆ DST_A_2_MISC_I2C_PT_9_ADDR

#define DST_A_2_MISC_I2C_PT_9_ADDR 0x555U

◆ DST_A_2_MISC_I2C_PT_9_MASK

#define DST_A_2_MISC_I2C_PT_9_MASK 0xFEU

◆ DST_A_2_MISC_I2C_PT_9_POS

#define DST_A_2_MISC_I2C_PT_9_POS 1U

◆ DST_A_CC_I2C_3_ADDR

#define DST_A_CC_I2C_3_ADDR 0x43U

◆ DST_A_CC_I2C_3_MASK

#define DST_A_CC_I2C_3_MASK 0xFEU

◆ DST_A_CC_I2C_3_POS

#define DST_A_CC_I2C_3_POS 1U

◆ DST_B_1_MISC_I2C_PT_7_ADDR

#define DST_B_1_MISC_I2C_PT_7_ADDR 0x553U

◆ DST_B_1_MISC_I2C_PT_7_MASK

#define DST_B_1_MISC_I2C_PT_7_MASK 0xFEU

◆ DST_B_1_MISC_I2C_PT_7_POS

#define DST_B_1_MISC_I2C_PT_7_POS 1U

◆ DST_B_2_MISC_I2C_PT_11_ADDR

#define DST_B_2_MISC_I2C_PT_11_ADDR 0x557U

◆ DST_B_2_MISC_I2C_PT_11_MASK

#define DST_B_2_MISC_I2C_PT_11_MASK 0xFEU

◆ DST_B_2_MISC_I2C_PT_11_POS

#define DST_B_2_MISC_I2C_PT_11_POS 1U

◆ DST_B_CC_I2C_5_ADDR

#define DST_B_CC_I2C_5_ADDR 0x45U

◆ DST_B_CC_I2C_5_MASK

#define DST_B_CC_I2C_5_MASK 0xFEU

◆ DST_B_CC_I2C_5_POS

#define DST_B_CC_I2C_5_POS 1U

◆ EFUSE_CRC_ERR_OEN_TCTRL_INTR6_ADDR

#define EFUSE_CRC_ERR_OEN_TCTRL_INTR6_ADDR 0x1EU

◆ EFUSE_CRC_ERR_OEN_TCTRL_INTR6_MASK

#define EFUSE_CRC_ERR_OEN_TCTRL_INTR6_MASK 0x10U

◆ EFUSE_CRC_ERR_OEN_TCTRL_INTR6_POS

#define EFUSE_CRC_ERR_OEN_TCTRL_INTR6_POS 4U

◆ EFUSE_CRC_ERR_TCTRL_INTR7_ADDR

#define EFUSE_CRC_ERR_TCTRL_INTR7_ADDR 0x1FU

◆ EFUSE_CRC_ERR_TCTRL_INTR7_MASK

#define EFUSE_CRC_ERR_TCTRL_INTR7_MASK 0x10U

◆ EFUSE_CRC_ERR_TCTRL_INTR7_POS

#define EFUSE_CRC_ERR_TCTRL_INTR7_POS 4U

◆ EFUSE_EFUSE100_ADDR

#define EFUSE_EFUSE100_ADDR 0x1C64U

◆ EFUSE_EFUSE100_DEFAULT

#define EFUSE_EFUSE100_DEFAULT 0x00U

◆ EFUSE_EFUSE101_ADDR

#define EFUSE_EFUSE101_ADDR 0x1C65U

◆ EFUSE_EFUSE101_DEFAULT

#define EFUSE_EFUSE101_DEFAULT 0x00U

◆ EFUSE_EFUSE102_ADDR

#define EFUSE_EFUSE102_ADDR 0x1C66U

◆ EFUSE_EFUSE102_DEFAULT

#define EFUSE_EFUSE102_DEFAULT 0x00U

◆ EFUSE_EFUSE103_ADDR

#define EFUSE_EFUSE103_ADDR 0x1C67U

◆ EFUSE_EFUSE103_DEFAULT

#define EFUSE_EFUSE103_DEFAULT 0x00U

◆ EFUSE_EFUSE80_ADDR

#define EFUSE_EFUSE80_ADDR 0x1C50U

◆ EFUSE_EFUSE80_DEFAULT

#define EFUSE_EFUSE80_DEFAULT 0x00U

◆ EFUSE_EFUSE81_ADDR

#define EFUSE_EFUSE81_ADDR 0x1C51U

◆ EFUSE_EFUSE81_DEFAULT

#define EFUSE_EFUSE81_DEFAULT 0x00U

◆ EFUSE_EFUSE82_ADDR

#define EFUSE_EFUSE82_ADDR 0x1C52U

◆ EFUSE_EFUSE82_DEFAULT

#define EFUSE_EFUSE82_DEFAULT 0x00U

◆ EFUSE_EFUSE83_ADDR

#define EFUSE_EFUSE83_ADDR 0x1C53U

◆ EFUSE_EFUSE83_DEFAULT

#define EFUSE_EFUSE83_DEFAULT 0x00U

◆ EFUSE_EFUSE84_ADDR

#define EFUSE_EFUSE84_ADDR 0x1C54U

◆ EFUSE_EFUSE84_DEFAULT

#define EFUSE_EFUSE84_DEFAULT 0x00U

◆ EFUSE_EFUSE85_ADDR

#define EFUSE_EFUSE85_ADDR 0x1C55U

◆ EFUSE_EFUSE85_DEFAULT

#define EFUSE_EFUSE85_DEFAULT 0x00U

◆ EFUSE_EFUSE86_ADDR

#define EFUSE_EFUSE86_ADDR 0x1C56U

◆ EFUSE_EFUSE86_DEFAULT

#define EFUSE_EFUSE86_DEFAULT 0x00U

◆ EFUSE_EFUSE87_ADDR

#define EFUSE_EFUSE87_ADDR 0x1C57U

◆ EFUSE_EFUSE87_DEFAULT

#define EFUSE_EFUSE87_DEFAULT 0x00U

◆ EFUSE_EFUSE88_ADDR

#define EFUSE_EFUSE88_ADDR 0x1C58U

◆ EFUSE_EFUSE88_DEFAULT

#define EFUSE_EFUSE88_DEFAULT 0x00U

◆ EFUSE_EFUSE89_ADDR

#define EFUSE_EFUSE89_ADDR 0x1C59U

◆ EFUSE_EFUSE89_DEFAULT

#define EFUSE_EFUSE89_DEFAULT 0x00U

◆ EFUSE_EFUSE90_ADDR

#define EFUSE_EFUSE90_ADDR 0x1C5AU

◆ EFUSE_EFUSE90_DEFAULT

#define EFUSE_EFUSE90_DEFAULT 0x00U

◆ EFUSE_EFUSE91_ADDR

#define EFUSE_EFUSE91_ADDR 0x1C5BU

◆ EFUSE_EFUSE91_DEFAULT

#define EFUSE_EFUSE91_DEFAULT 0x00U

◆ EFUSE_EFUSE92_ADDR

#define EFUSE_EFUSE92_ADDR 0x1C5CU

◆ EFUSE_EFUSE92_DEFAULT

#define EFUSE_EFUSE92_DEFAULT 0x00U

◆ EFUSE_EFUSE93_ADDR

#define EFUSE_EFUSE93_ADDR 0x1C5DU

◆ EFUSE_EFUSE93_DEFAULT

#define EFUSE_EFUSE93_DEFAULT 0x00U

◆ EFUSE_EFUSE94_ADDR

#define EFUSE_EFUSE94_ADDR 0x1C5EU

◆ EFUSE_EFUSE94_DEFAULT

#define EFUSE_EFUSE94_DEFAULT 0x00U

◆ EFUSE_EFUSE95_ADDR

#define EFUSE_EFUSE95_ADDR 0x1C5FU

◆ EFUSE_EFUSE95_DEFAULT

#define EFUSE_EFUSE95_DEFAULT 0x00U

◆ EFUSE_EFUSE96_ADDR

#define EFUSE_EFUSE96_ADDR 0x1C60U

◆ EFUSE_EFUSE96_DEFAULT

#define EFUSE_EFUSE96_DEFAULT 0x00U

◆ EFUSE_EFUSE97_ADDR

#define EFUSE_EFUSE97_ADDR 0x1C61U

◆ EFUSE_EFUSE97_DEFAULT

#define EFUSE_EFUSE97_DEFAULT 0x00U

◆ EFUSE_EFUSE98_ADDR

#define EFUSE_EFUSE98_ADDR 0x1C62U

◆ EFUSE_EFUSE98_DEFAULT

#define EFUSE_EFUSE98_DEFAULT 0x00U

◆ EFUSE_EFUSE99_ADDR

#define EFUSE_EFUSE99_ADDR 0x1C63U

◆ EFUSE_EFUSE99_DEFAULT

#define EFUSE_EFUSE99_DEFAULT 0x00U

◆ ENABLE_LINE_INFO_FRONTTOP_FRONTTOP_0_ADDR

#define ENABLE_LINE_INFO_FRONTTOP_FRONTTOP_0_ADDR 0x308U

◆ ENABLE_LINE_INFO_FRONTTOP_FRONTTOP_0_MASK

#define ENABLE_LINE_INFO_FRONTTOP_FRONTTOP_0_MASK 0x40U

◆ ENABLE_LINE_INFO_FRONTTOP_FRONTTOP_0_POS

#define ENABLE_LINE_INFO_FRONTTOP_FRONTTOP_0_POS 6U

◆ ENC_MODE_VID_TX_Z_VIDEO_TX0_ADDR

#define ENC_MODE_VID_TX_Z_VIDEO_TX0_ADDR 0x110U

◆ ENC_MODE_VID_TX_Z_VIDEO_TX0_MASK

#define ENC_MODE_VID_TX_Z_VIDEO_TX0_MASK 0x30U

◆ ENC_MODE_VID_TX_Z_VIDEO_TX0_POS

#define ENC_MODE_VID_TX_Z_VIDEO_TX0_POS 4U

◆ ENFFE_RLMS_A_RLMSCE_ADDR

#define ENFFE_RLMS_A_RLMSCE_ADDR 0x14CEU

◆ ENFFE_RLMS_A_RLMSCE_MASK

#define ENFFE_RLMS_A_RLMSCE_MASK 0x01U

◆ ENFFE_RLMS_A_RLMSCE_POS

#define ENFFE_RLMS_A_RLMSCE_POS 0U

◆ ENMINUS_MAN_RLMS_A_RLMSCE_ADDR

#define ENMINUS_MAN_RLMS_A_RLMSCE_ADDR 0x14CEU

◆ ENMINUS_MAN_RLMS_A_RLMSCE_MASK

#define ENMINUS_MAN_RLMS_A_RLMSCE_MASK 0x08U

◆ ENMINUS_MAN_RLMS_A_RLMSCE_POS

#define ENMINUS_MAN_RLMS_A_RLMSCE_POS 3U

◆ ENMINUS_REG_RLMS_A_RLMSCE_ADDR

#define ENMINUS_REG_RLMS_A_RLMSCE_ADDR 0x14CEU

◆ ENMINUS_REG_RLMS_A_RLMSCE_MASK

#define ENMINUS_REG_RLMS_A_RLMSCE_MASK 0x10U

◆ ENMINUS_REG_RLMS_A_RLMSCE_POS

#define ENMINUS_REG_RLMS_A_RLMSCE_POS 4U

◆ EOM_CHK_AMOUNT_RLMS_A_RLMS4_ADDR

#define EOM_CHK_AMOUNT_RLMS_A_RLMS4_ADDR 0x1404U

◆ EOM_CHK_AMOUNT_RLMS_A_RLMS4_MASK

#define EOM_CHK_AMOUNT_RLMS_A_RLMS4_MASK 0xF0U

◆ EOM_CHK_AMOUNT_RLMS_A_RLMS4_POS

#define EOM_CHK_AMOUNT_RLMS_A_RLMS4_POS 4U

◆ EOM_CHK_THR_RLMS_A_RLMS4_ADDR

#define EOM_CHK_THR_RLMS_A_RLMS4_ADDR 0x1404U

◆ EOM_CHK_THR_RLMS_A_RLMS4_MASK

#define EOM_CHK_THR_RLMS_A_RLMS4_MASK 0x0CU

◆ EOM_CHK_THR_RLMS_A_RLMS4_POS

#define EOM_CHK_THR_RLMS_A_RLMS4_POS 2U

◆ EOM_DONE_RLMS_A_RLMS7_ADDR

#define EOM_DONE_RLMS_A_RLMS7_ADDR 0x1407U

◆ EOM_DONE_RLMS_A_RLMS7_MASK

#define EOM_DONE_RLMS_A_RLMS7_MASK 0x80U

◆ EOM_DONE_RLMS_A_RLMS7_POS

#define EOM_DONE_RLMS_A_RLMS7_POS 7U

◆ EOM_EN_RLMS_A_RLMS4_ADDR

#define EOM_EN_RLMS_A_RLMS4_ADDR 0x1404U

◆ EOM_EN_RLMS_A_RLMS4_MASK

#define EOM_EN_RLMS_A_RLMS4_MASK 0x01U

◆ EOM_EN_RLMS_A_RLMS4_POS

#define EOM_EN_RLMS_A_RLMS4_POS 0U

◆ EOM_ERR_FLAG_A_TCTRL_INTR5_ADDR

#define EOM_ERR_FLAG_A_TCTRL_INTR5_ADDR 0x1DU

◆ EOM_ERR_FLAG_A_TCTRL_INTR5_MASK

#define EOM_ERR_FLAG_A_TCTRL_INTR5_MASK 0x40U

◆ EOM_ERR_FLAG_A_TCTRL_INTR5_POS

#define EOM_ERR_FLAG_A_TCTRL_INTR5_POS 6U

◆ EOM_ERR_OEN_A_TCTRL_INTR4_ADDR

#define EOM_ERR_OEN_A_TCTRL_INTR4_ADDR 0x1CU

◆ EOM_ERR_OEN_A_TCTRL_INTR4_MASK

#define EOM_ERR_OEN_A_TCTRL_INTR4_MASK 0x40U

◆ EOM_ERR_OEN_A_TCTRL_INTR4_POS

#define EOM_ERR_OEN_A_TCTRL_INTR4_POS 6U

◆ EOM_MAN_TRG_REQ_RLMS_A_RLMS5_ADDR

#define EOM_MAN_TRG_REQ_RLMS_A_RLMS5_ADDR 0x1405U

◆ EOM_MAN_TRG_REQ_RLMS_A_RLMS5_MASK

#define EOM_MAN_TRG_REQ_RLMS_A_RLMS5_MASK 0x80U

◆ EOM_MAN_TRG_REQ_RLMS_A_RLMS5_POS

#define EOM_MAN_TRG_REQ_RLMS_A_RLMS5_POS 7U

◆ EOM_MIN_THR_RLMS_A_RLMS5_ADDR

#define EOM_MIN_THR_RLMS_A_RLMS5_ADDR 0x1405U

◆ EOM_MIN_THR_RLMS_A_RLMS5_MASK

#define EOM_MIN_THR_RLMS_A_RLMS5_MASK 0x7FU

◆ EOM_MIN_THR_RLMS_A_RLMS5_POS

#define EOM_MIN_THR_RLMS_A_RLMS5_POS 0U

◆ EOM_PER_MODE_RLMS_A_RLMS4_ADDR

#define EOM_PER_MODE_RLMS_A_RLMS4_ADDR 0x1404U

◆ EOM_PER_MODE_RLMS_A_RLMS4_MASK

#define EOM_PER_MODE_RLMS_A_RLMS4_MASK 0x02U

◆ EOM_PER_MODE_RLMS_A_RLMS4_POS

#define EOM_PER_MODE_RLMS_A_RLMS4_POS 1U

◆ EOM_PV_MODE_RLMS_A_RLMS6_ADDR

#define EOM_PV_MODE_RLMS_A_RLMS6_ADDR 0x1406U

◆ EOM_PV_MODE_RLMS_A_RLMS6_MASK

#define EOM_PV_MODE_RLMS_A_RLMS6_MASK 0x80U

◆ EOM_PV_MODE_RLMS_A_RLMS6_POS

#define EOM_PV_MODE_RLMS_A_RLMS6_POS 7U

◆ EOM_RLMS_A_RLMS7_ADDR

#define EOM_RLMS_A_RLMS7_ADDR 0x1407U

◆ EOM_RLMS_A_RLMS7_MASK

#define EOM_RLMS_A_RLMS7_MASK 0x7FU

◆ EOM_RLMS_A_RLMS7_POS

#define EOM_RLMS_A_RLMS7_POS 0U

◆ ERR_RX_EN_TCTRL_INTR9_ADDR

#define ERR_RX_EN_TCTRL_INTR9_ADDR 0x21U

◆ ERR_RX_EN_TCTRL_INTR9_MASK

#define ERR_RX_EN_TCTRL_INTR9_MASK 0x80U

◆ ERR_RX_EN_TCTRL_INTR9_POS

#define ERR_RX_EN_TCTRL_INTR9_POS 7U

◆ ERR_RX_ID_TCTRL_INTR9_ADDR

#define ERR_RX_ID_TCTRL_INTR9_ADDR 0x21U

◆ ERR_RX_ID_TCTRL_INTR9_MASK

#define ERR_RX_ID_TCTRL_INTR9_MASK 0x1FU

◆ ERR_RX_ID_TCTRL_INTR9_POS

#define ERR_RX_ID_TCTRL_INTR9_POS 0U

◆ ERR_TX_EN_TCTRL_INTR8_ADDR

#define ERR_TX_EN_TCTRL_INTR8_ADDR 0x20U

◆ ERR_TX_EN_TCTRL_INTR8_MASK

#define ERR_TX_EN_TCTRL_INTR8_MASK 0x80U

◆ ERR_TX_EN_TCTRL_INTR8_POS

#define ERR_TX_EN_TCTRL_INTR8_POS 7U

◆ ERR_TX_ID_TCTRL_INTR8_ADDR

#define ERR_TX_ID_TCTRL_INTR8_ADDR 0x20U

◆ ERR_TX_ID_TCTRL_INTR8_MASK

#define ERR_TX_ID_TCTRL_INTR8_MASK 0x1FU

◆ ERR_TX_ID_TCTRL_INTR8_POS

#define ERR_TX_ID_TCTRL_INTR8_POS 0U

◆ ERRB_EN_DEV_REG5_ADDR

#define ERRB_EN_DEV_REG5_ADDR 0x05U

◆ ERRB_EN_DEV_REG5_MASK

#define ERRB_EN_DEV_REG5_MASK 0x40U

◆ ERRB_EN_DEV_REG5_POS

#define ERRB_EN_DEV_REG5_POS 6U

◆ ERRG_BURST_GMSL_TX2_ADDR

#define ERRG_BURST_GMSL_TX2_ADDR 0x2AU

◆ ERRG_BURST_GMSL_TX2_MASK

#define ERRG_BURST_GMSL_TX2_MASK 0x0EU

◆ ERRG_BURST_GMSL_TX2_POS

#define ERRG_BURST_GMSL_TX2_POS 1U

◆ ERRG_CNT_GMSL_TX2_ADDR

#define ERRG_CNT_GMSL_TX2_ADDR 0x2AU

◆ ERRG_CNT_GMSL_TX2_MASK

#define ERRG_CNT_GMSL_TX2_MASK 0xC0U

◆ ERRG_CNT_GMSL_TX2_POS

#define ERRG_CNT_GMSL_TX2_POS 6U

◆ ERRG_EN_A_GMSL_TX1_ADDR

#define ERRG_EN_A_GMSL_TX1_ADDR 0x29U

◆ ERRG_EN_A_GMSL_TX1_MASK

#define ERRG_EN_A_GMSL_TX1_MASK 0x10U

◆ ERRG_EN_A_GMSL_TX1_POS

#define ERRG_EN_A_GMSL_TX1_POS 4U

◆ ERRG_PER_GMSL_TX2_ADDR

#define ERRG_PER_GMSL_TX2_ADDR 0x2AU

◆ ERRG_PER_GMSL_TX2_MASK

#define ERRG_PER_GMSL_TX2_MASK 0x01U

◆ ERRG_PER_GMSL_TX2_POS

#define ERRG_PER_GMSL_TX2_POS 0U

◆ ERRG_RATE_GMSL_TX2_ADDR

#define ERRG_RATE_GMSL_TX2_ADDR 0x2AU

◆ ERRG_RATE_GMSL_TX2_MASK

#define ERRG_RATE_GMSL_TX2_MASK 0x30U

◆ ERRG_RATE_GMSL_TX2_POS

#define ERRG_RATE_GMSL_TX2_POS 4U

◆ ERROR_TCTRL_CTRL3_ADDR

#define ERROR_TCTRL_CTRL3_ADDR 0x13U

◆ ERROR_TCTRL_CTRL3_MASK

#define ERROR_TCTRL_CTRL3_MASK 0x04U

◆ ERROR_TCTRL_CTRL3_POS

#define ERROR_TCTRL_CTRL3_POS 2U

◆ EYEMONVALCNTH_RLMS_A_RLMS3B_ADDR

#define EYEMONVALCNTH_RLMS_A_RLMS3B_ADDR 0x143BU

◆ EYEMONVALCNTH_RLMS_A_RLMS3B_MASK

#define EYEMONVALCNTH_RLMS_A_RLMS3B_MASK 0xFFU

◆ EYEMONVALCNTH_RLMS_A_RLMS3B_POS

#define EYEMONVALCNTH_RLMS_A_RLMS3B_POS 0U

◆ EYEMONVALCNTL_RLMS_A_RLMS3A_ADDR

#define EYEMONVALCNTL_RLMS_A_RLMS3A_ADDR 0x143AU

◆ EYEMONVALCNTL_RLMS_A_RLMS3A_MASK

#define EYEMONVALCNTL_RLMS_A_RLMS3A_MASK 0xFFU

◆ EYEMONVALCNTL_RLMS_A_RLMS3A_POS

#define EYEMONVALCNTL_RLMS_A_RLMS3A_POS 0U

◆ FIFO_WARN_VID_TX_Z_VIDEO_TX2_ADDR

#define FIFO_WARN_VID_TX_Z_VIDEO_TX2_ADDR 0x112U

◆ FIFO_WARN_VID_TX_Z_VIDEO_TX2_MASK

#define FIFO_WARN_VID_TX_Z_VIDEO_TX2_MASK 0x10U

◆ FIFO_WARN_VID_TX_Z_VIDEO_TX2_POS

#define FIFO_WARN_VID_TX_Z_VIDEO_TX2_POS 4U

◆ FORCE_START_MIPI_FRONTTOP_FRONTTOP_FRONTTOP_29_ADDR

#define FORCE_START_MIPI_FRONTTOP_FRONTTOP_FRONTTOP_29_ADDR 0x325U

◆ FORCE_START_MIPI_FRONTTOP_FRONTTOP_FRONTTOP_29_MASK

#define FORCE_START_MIPI_FRONTTOP_FRONTTOP_FRONTTOP_29_MASK 0x80U

◆ FORCE_START_MIPI_FRONTTOP_FRONTTOP_FRONTTOP_29_POS

#define FORCE_START_MIPI_FRONTTOP_FRONTTOP_FRONTTOP_29_POS 7U

◆ FRONTTOP_EXT12_ADDR

#define FRONTTOP_EXT12_ADDR (0x3CAU)

◆ FRONTTOP_EXT12_MASK

#define FRONTTOP_EXT12_MASK (0xFFU)

◆ FRONTTOP_EXT13_ADDR

#define FRONTTOP_EXT13_ADDR (0x3CBU)

◆ FRONTTOP_EXT13_MASK

#define FRONTTOP_EXT13_MASK (0xFFU)

◆ FRONTTOP_EXT_FRONTTOP_EXT10_ADDR

#define FRONTTOP_EXT_FRONTTOP_EXT10_ADDR 0x3CAU

◆ FRONTTOP_EXT_FRONTTOP_EXT10_DEFAULT

#define FRONTTOP_EXT_FRONTTOP_EXT10_DEFAULT 0x00U

◆ FRONTTOP_EXT_FRONTTOP_EXT11_ADDR

#define FRONTTOP_EXT_FRONTTOP_EXT11_ADDR 0x3CBU

◆ FRONTTOP_EXT_FRONTTOP_EXT11_DEFAULT

#define FRONTTOP_EXT_FRONTTOP_EXT11_DEFAULT 0x00U

◆ FRONTTOP_EXT_FRONTTOP_EXT17_ADDR

#define FRONTTOP_EXT_FRONTTOP_EXT17_ADDR 0x3D1U

◆ FRONTTOP_EXT_FRONTTOP_EXT17_DEFAULT

#define FRONTTOP_EXT_FRONTTOP_EXT17_DEFAULT 0x00U

◆ FRONTTOP_EXT_FRONTTOP_EXT8_ADDR

#define FRONTTOP_EXT_FRONTTOP_EXT8_ADDR 0x3C8U

◆ FRONTTOP_EXT_FRONTTOP_EXT8_DEFAULT

#define FRONTTOP_EXT_FRONTTOP_EXT8_DEFAULT 0x00U

◆ FRONTTOP_EXT_FRONTTOP_EXT9_ADDR

#define FRONTTOP_EXT_FRONTTOP_EXT9_ADDR 0x3C9U

◆ FRONTTOP_EXT_FRONTTOP_EXT9_DEFAULT

#define FRONTTOP_EXT_FRONTTOP_EXT9_DEFAULT 0x00U

◆ FRONTTOP_FRONTTOP_0_ADDR

#define FRONTTOP_FRONTTOP_0_ADDR 0x308U

◆ FRONTTOP_FRONTTOP_0_ALL_MASK

#define FRONTTOP_FRONTTOP_0_ALL_MASK (0xFFU)

◆ FRONTTOP_FRONTTOP_0_DEFAULT

#define FRONTTOP_FRONTTOP_0_DEFAULT 0x64U

◆ FRONTTOP_FRONTTOP_10_ADDR

#define FRONTTOP_FRONTTOP_10_ADDR 0x312U

◆ FRONTTOP_FRONTTOP_10_DEFAULT

#define FRONTTOP_FRONTTOP_10_DEFAULT 0x00U

◆ FRONTTOP_FRONTTOP_11_ADDR

#define FRONTTOP_FRONTTOP_11_ADDR 0x313U

◆ FRONTTOP_FRONTTOP_11_DEFAULT

#define FRONTTOP_FRONTTOP_11_DEFAULT 0x00U

◆ FRONTTOP_FRONTTOP_16_ADDR

#define FRONTTOP_FRONTTOP_16_ADDR 0x318U

◆ FRONTTOP_FRONTTOP_16_DEFAULT

#define FRONTTOP_FRONTTOP_16_DEFAULT 0x00U

◆ FRONTTOP_FRONTTOP_17_ADDR

#define FRONTTOP_FRONTTOP_17_ADDR 0x319U

◆ FRONTTOP_FRONTTOP_17_DEFAULT

#define FRONTTOP_FRONTTOP_17_DEFAULT 0x00U

◆ FRONTTOP_FRONTTOP_22_ADDR

#define FRONTTOP_FRONTTOP_22_ADDR 0x31EU

◆ FRONTTOP_FRONTTOP_22_DEFAULT

#define FRONTTOP_FRONTTOP_22_DEFAULT 0x18U

◆ FRONTTOP_FRONTTOP_24_ADDR

#define FRONTTOP_FRONTTOP_24_ADDR 0x320U

◆ FRONTTOP_FRONTTOP_24_DEFAULT

#define FRONTTOP_FRONTTOP_24_DEFAULT 0x00U

◆ FRONTTOP_FRONTTOP_27_ADDR

#define FRONTTOP_FRONTTOP_27_ADDR 0x323U

◆ FRONTTOP_FRONTTOP_27_DEFAULT

#define FRONTTOP_FRONTTOP_27_DEFAULT 0x30U

◆ FRONTTOP_FRONTTOP_29_ADDR

#define FRONTTOP_FRONTTOP_29_ADDR 0x325U

◆ FRONTTOP_FRONTTOP_29_DEFAULT

#define FRONTTOP_FRONTTOP_29_DEFAULT 0x00U

◆ FRONTTOP_FRONTTOP_5_ADDR

#define FRONTTOP_FRONTTOP_5_ADDR 0x30DU

◆ FRONTTOP_FRONTTOP_5_DEFAULT

#define FRONTTOP_FRONTTOP_5_DEFAULT 0xFFU

◆ FRONTTOP_FRONTTOP_6_ADDR

#define FRONTTOP_FRONTTOP_6_ADDR 0x30EU

◆ FRONTTOP_FRONTTOP_6_DEFAULT

#define FRONTTOP_FRONTTOP_6_DEFAULT 0xFFU

◆ FRONTTOP_FRONTTOP_9_ADDR

#define FRONTTOP_FRONTTOP_9_ADDR 0x311U

◆ FRONTTOP_FRONTTOP_9_DEFAULT

#define FRONTTOP_FRONTTOP_9_DEFAULT 0x40U

◆ FULL_SCK_SETUP_SPI_SPI_2_ADDR

#define FULL_SCK_SETUP_SPI_SPI_2_ADDR 0x172U

◆ FULL_SCK_SETUP_SPI_SPI_2_MASK

#define FULL_SCK_SETUP_SPI_SPI_2_MASK 0x10U

◆ FULL_SCK_SETUP_SPI_SPI_2_POS

#define FULL_SCK_SETUP_SPI_SPI_2_POS 4U

◆ FUNC_SAFE_CC_RTTN_ERR_ADDR

#define FUNC_SAFE_CC_RTTN_ERR_ADDR 0x1D5FU

◆ FUNC_SAFE_CC_RTTN_ERR_DEFAULT

#define FUNC_SAFE_CC_RTTN_ERR_DEFAULT 0x00U

◆ FUNC_SAFE_FS_INTR0_ADDR

#define FUNC_SAFE_FS_INTR0_ADDR 0x1D12U

◆ FUNC_SAFE_FS_INTR0_DEFAULT

#define FUNC_SAFE_FS_INTR0_DEFAULT 0xE0U

◆ FUNC_SAFE_FS_INTR1_ADDR

#define FUNC_SAFE_FS_INTR1_ADDR 0x1D13U

◆ FUNC_SAFE_FS_INTR1_DEFAULT

#define FUNC_SAFE_FS_INTR1_DEFAULT 0x00U

◆ FUNC_SAFE_I2C_UART_CRC0_ADDR

#define FUNC_SAFE_I2C_UART_CRC0_ADDR 0x1D08U

◆ FUNC_SAFE_I2C_UART_CRC0_DEFAULT

#define FUNC_SAFE_I2C_UART_CRC0_DEFAULT 0x00U

◆ FUNC_SAFE_I2C_UART_CRC1_ADDR

#define FUNC_SAFE_I2C_UART_CRC1_ADDR 0x1D09U

◆ FUNC_SAFE_I2C_UART_CRC1_DEFAULT

#define FUNC_SAFE_I2C_UART_CRC1_DEFAULT 0x00U

◆ FUNC_SAFE_I2C_UART_CRC2_ADDR

#define FUNC_SAFE_I2C_UART_CRC2_ADDR 0x1D0AU

◆ FUNC_SAFE_I2C_UART_CRC2_DEFAULT

#define FUNC_SAFE_I2C_UART_CRC2_DEFAULT 0x00U

◆ FUNC_SAFE_I2C_UART_CRC3_ADDR

#define FUNC_SAFE_I2C_UART_CRC3_ADDR 0x1D0BU

◆ FUNC_SAFE_I2C_UART_CRC3_DEFAULT

#define FUNC_SAFE_I2C_UART_CRC3_DEFAULT 0x00U

◆ FUNC_SAFE_I2C_UART_CRC4_ADDR

#define FUNC_SAFE_I2C_UART_CRC4_ADDR 0x1D0CU

◆ FUNC_SAFE_I2C_UART_CRC4_DEFAULT

#define FUNC_SAFE_I2C_UART_CRC4_DEFAULT 0x00U

◆ FUNC_SAFE_MEM_ECC0_ADDR

#define FUNC_SAFE_MEM_ECC0_ADDR 0x1D14U

◆ FUNC_SAFE_MEM_ECC0_DEFAULT

#define FUNC_SAFE_MEM_ECC0_DEFAULT 0x00U

◆ FUNC_SAFE_REG_POST0_ADDR

#define FUNC_SAFE_REG_POST0_ADDR 0x1D20U

◆ FUNC_SAFE_REG_POST0_DEFAULT

#define FUNC_SAFE_REG_POST0_DEFAULT 0x00U

◆ FUNC_SAFE_REGADCBIST0_ADDR

#define FUNC_SAFE_REGADCBIST0_ADDR 0x1D28U

◆ FUNC_SAFE_REGADCBIST0_DEFAULT

#define FUNC_SAFE_REGADCBIST0_DEFAULT 0x00U

◆ FUNC_SAFE_REGADCBIST12_ADDR

#define FUNC_SAFE_REGADCBIST12_ADDR 0x1D3AU

◆ FUNC_SAFE_REGADCBIST12_DEFAULT

#define FUNC_SAFE_REGADCBIST12_DEFAULT 0xFFU

◆ FUNC_SAFE_REGADCBIST13_ADDR

#define FUNC_SAFE_REGADCBIST13_ADDR 0x1D3BU

◆ FUNC_SAFE_REGADCBIST13_DEFAULT

#define FUNC_SAFE_REGADCBIST13_DEFAULT 0xFFU

◆ FUNC_SAFE_REGADCBIST14_ADDR

#define FUNC_SAFE_REGADCBIST14_ADDR 0x1D3CU

◆ FUNC_SAFE_REGADCBIST14_DEFAULT

#define FUNC_SAFE_REGADCBIST14_DEFAULT 0xC3U

◆ FUNC_SAFE_REGADCBIST15_ADDR

#define FUNC_SAFE_REGADCBIST15_ADDR 0x1D3DU

◆ FUNC_SAFE_REGADCBIST15_DEFAULT

#define FUNC_SAFE_REGADCBIST15_DEFAULT 0xFFU

◆ FUNC_SAFE_REGADCBIST3_ADDR

#define FUNC_SAFE_REGADCBIST3_ADDR 0x1D31U

◆ FUNC_SAFE_REGADCBIST3_DEFAULT

#define FUNC_SAFE_REGADCBIST3_DEFAULT 0x0FU

◆ FUNC_SAFE_REGADCBIST4_ADDR

#define FUNC_SAFE_REGADCBIST4_ADDR 0x1D32U

◆ FUNC_SAFE_REGADCBIST4_DEFAULT

#define FUNC_SAFE_REGADCBIST4_DEFAULT 0x0FU

◆ FUNC_SAFE_REGADCBIST5_ADDR

#define FUNC_SAFE_REGADCBIST5_ADDR 0x1D33U

◆ FUNC_SAFE_REGADCBIST5_DEFAULT

#define FUNC_SAFE_REGADCBIST5_DEFAULT 0x07U

◆ FUNC_SAFE_REGADCBIST6_ADDR

#define FUNC_SAFE_REGADCBIST6_ADDR 0x1D34U

◆ FUNC_SAFE_REGADCBIST6_DEFAULT

#define FUNC_SAFE_REGADCBIST6_DEFAULT 0x07U

◆ FUNC_SAFE_REGADCBIST7_ADDR

#define FUNC_SAFE_REGADCBIST7_ADDR 0x1D35U

◆ FUNC_SAFE_REGADCBIST7_DEFAULT

#define FUNC_SAFE_REGADCBIST7_DEFAULT 0x03U

◆ FUNC_SAFE_REGADCBIST9_ADDR

#define FUNC_SAFE_REGADCBIST9_ADDR 0x1D37U

◆ FUNC_SAFE_REGADCBIST9_DEFAULT

#define FUNC_SAFE_REGADCBIST9_DEFAULT 0x00U

◆ FUNC_SAFE_REGCRC0_ADDR

#define FUNC_SAFE_REGCRC0_ADDR 0x1D00U

◆ FUNC_SAFE_REGCRC0_DEFAULT

#define FUNC_SAFE_REGCRC0_DEFAULT 0x00U

◆ FUNC_SAFE_REGCRC1_ADDR

#define FUNC_SAFE_REGCRC1_ADDR 0x1D01U

◆ FUNC_SAFE_REGCRC1_DEFAULT

#define FUNC_SAFE_REGCRC1_DEFAULT 0x00U

◆ FUNC_SAFE_REGCRC2_ADDR

#define FUNC_SAFE_REGCRC2_ADDR 0x1D02U

◆ FUNC_SAFE_REGCRC2_DEFAULT

#define FUNC_SAFE_REGCRC2_DEFAULT 0x00U

◆ FUNC_SAFE_REGCRC3_ADDR

#define FUNC_SAFE_REGCRC3_ADDR 0x1D03U

◆ FUNC_SAFE_REGCRC3_DEFAULT

#define FUNC_SAFE_REGCRC3_DEFAULT 0x00U

◆ FW_PHY_CTRL_RLMS_A_RLMSA8_ADDR

#define FW_PHY_CTRL_RLMS_A_RLMSA8_ADDR 0x14A8U

◆ FW_PHY_CTRL_RLMS_A_RLMSA8_MASK

#define FW_PHY_CTRL_RLMS_A_RLMSA8_MASK 0x80U

◆ FW_PHY_CTRL_RLMS_A_RLMSA8_POS

#define FW_PHY_CTRL_RLMS_A_RLMSA8_POS 7U

◆ FW_PHY_PU_TX_RLMS_A_RLMSA8_ADDR

#define FW_PHY_PU_TX_RLMS_A_RLMSA8_ADDR 0x14A8U

◆ FW_PHY_PU_TX_RLMS_A_RLMSA8_MASK

#define FW_PHY_PU_TX_RLMS_A_RLMSA8_MASK 0x40U

◆ FW_PHY_PU_TX_RLMS_A_RLMSA8_POS

#define FW_PHY_PU_TX_RLMS_A_RLMSA8_POS 6U

◆ FW_PHY_RSTB_RLMS_A_RLMSA8_ADDR

#define FW_PHY_RSTB_RLMS_A_RLMSA8_ADDR 0x14A8U

◆ FW_PHY_RSTB_RLMS_A_RLMSA8_MASK

#define FW_PHY_RSTB_RLMS_A_RLMSA8_MASK 0x20U

◆ FW_PHY_RSTB_RLMS_A_RLMSA8_POS

#define FW_PHY_RSTB_RLMS_A_RLMSA8_POS 5U

◆ FW_REPCAL_RSTB_RLMS_A_RLMSA9_ADDR

#define FW_REPCAL_RSTB_RLMS_A_RLMSA9_ADDR 0x14A9U

◆ FW_REPCAL_RSTB_RLMS_A_RLMSA9_MASK

#define FW_REPCAL_RSTB_RLMS_A_RLMSA9_MASK 0x80U

◆ FW_REPCAL_RSTB_RLMS_A_RLMSA9_POS

#define FW_REPCAL_RSTB_RLMS_A_RLMSA9_POS 7U

◆ FW_RXD_EN_RLMS_A_RLMSA9_ADDR

#define FW_RXD_EN_RLMS_A_RLMSA9_ADDR 0x14A9U

◆ FW_RXD_EN_RLMS_A_RLMSA9_MASK

#define FW_RXD_EN_RLMS_A_RLMSA9_MASK 0x08U

◆ FW_RXD_EN_RLMS_A_RLMSA9_POS

#define FW_RXD_EN_RLMS_A_RLMSA9_POS 3U

◆ FW_TXD_EN_RLMS_A_RLMSA9_ADDR

#define FW_TXD_EN_RLMS_A_RLMSA9_ADDR 0x14A9U

◆ FW_TXD_EN_RLMS_A_RLMSA9_MASK

#define FW_TXD_EN_RLMS_A_RLMSA9_MASK 0x10U

◆ FW_TXD_EN_RLMS_A_RLMSA9_POS

#define FW_TXD_EN_RLMS_A_RLMSA9_POS 4U

◆ FW_TXD_SQUELCH_RLMS_A_RLMSA9_ADDR

#define FW_TXD_SQUELCH_RLMS_A_RLMSA9_ADDR 0x14A9U

◆ FW_TXD_SQUELCH_RLMS_A_RLMSA9_MASK

#define FW_TXD_SQUELCH_RLMS_A_RLMSA9_MASK 0x20U

◆ FW_TXD_SQUELCH_RLMS_A_RLMSA9_POS

#define FW_TXD_SQUELCH_RLMS_A_RLMSA9_POS 5U

◆ GEN_DE_VTX_Z_VTX0_ADDR

#define GEN_DE_VTX_Z_VTX0_ADDR 0x24EU

◆ GEN_DE_VTX_Z_VTX0_MASK

#define GEN_DE_VTX_Z_VTX0_MASK 0x20U

◆ GEN_DE_VTX_Z_VTX0_POS

#define GEN_DE_VTX_Z_VTX0_POS 5U

◆ GEN_HS_REF_VTG_VTX0_ADDR

#define GEN_HS_REF_VTG_VTX0_ADDR 0x3E0U

◆ GEN_HS_REF_VTG_VTX0_MASK

#define GEN_HS_REF_VTG_VTX0_MASK 0x04U

◆ GEN_HS_REF_VTG_VTX0_POS

#define GEN_HS_REF_VTG_VTX0_POS 2U

◆ GEN_HS_VTX_Z_VTX0_ADDR

#define GEN_HS_VTX_Z_VTX0_ADDR 0x24EU

◆ GEN_HS_VTX_Z_VTX0_MASK

#define GEN_HS_VTX_Z_VTX0_MASK 0x40U

◆ GEN_HS_VTX_Z_VTX0_POS

#define GEN_HS_VTX_Z_VTX0_POS 6U

◆ GEN_ROLLING_CRC_FUNC_SAFE_REGCRC0_ADDR

#define GEN_ROLLING_CRC_FUNC_SAFE_REGCRC0_ADDR 0x1D00U

◆ GEN_ROLLING_CRC_FUNC_SAFE_REGCRC0_MASK

#define GEN_ROLLING_CRC_FUNC_SAFE_REGCRC0_MASK 0x10U

◆ GEN_ROLLING_CRC_FUNC_SAFE_REGCRC0_POS

#define GEN_ROLLING_CRC_FUNC_SAFE_REGCRC0_POS 4U

◆ GEN_VS_REF_VTG_VTX0_ADDR

#define GEN_VS_REF_VTG_VTX0_ADDR 0x3E0U

◆ GEN_VS_REF_VTG_VTX0_MASK

#define GEN_VS_REF_VTG_VTX0_MASK 0x01U

◆ GEN_VS_REF_VTG_VTX0_POS

#define GEN_VS_REF_VTG_VTX0_POS 0U

◆ GEN_VS_VTX_Z_VTX0_ADDR

#define GEN_VS_VTX_Z_VTX0_ADDR 0x24EU

◆ GEN_VS_VTX_Z_VTX0_MASK

#define GEN_VS_VTX_Z_VTX0_MASK 0x80U

◆ GEN_VS_VTX_Z_VTX0_POS

#define GEN_VS_VTX_Z_VTX0_POS 7U

◆ GMSL_GPIOA_ADDR

#define GMSL_GPIOA_ADDR 0x30U

◆ GMSL_GPIOA_DEFAULT

#define GMSL_GPIOA_DEFAULT 0x41U

◆ GMSL_GPIOB_ADDR

#define GMSL_GPIOB_ADDR 0x31U

◆ GMSL_GPIOB_DEFAULT

#define GMSL_GPIOB_DEFAULT 0x88U

◆ GMSL_RX0_ADDR

#define GMSL_RX0_ADDR 0x2CU

◆ GMSL_RX0_DEFAULT

#define GMSL_RX0_DEFAULT 0x00U

◆ GMSL_RX1_ADDR

#define GMSL_RX1_ADDR 0x2DU

◆ GMSL_RX1_DEFAULT

#define GMSL_RX1_DEFAULT 0x28U

◆ GMSL_TX0_ADDR

#define GMSL_TX0_ADDR 0x28U

◆ GMSL_TX0_DEFAULT

#define GMSL_TX0_DEFAULT 0x60U

◆ GMSL_TX1_ADDR

#define GMSL_TX1_ADDR 0x29U

◆ GMSL_TX1_DEFAULT

#define GMSL_TX1_DEFAULT 0x08U

◆ GMSL_TX2_ADDR

#define GMSL_TX2_ADDR 0x2AU

◆ GMSL_TX2_DEFAULT

#define GMSL_TX2_DEFAULT 0x20U

◆ GMSL_TX3_ADDR

#define GMSL_TX3_ADDR 0x2BU

◆ GMSL_TX3_DEFAULT

#define GMSL_TX3_DEFAULT 0x44U

◆ GPIO0_0_GPIO_A_ADDR

#define GPIO0_0_GPIO_A_ADDR 0x2BEU

◆ GPIO0_0_GPIO_A_DEFAULT

#define GPIO0_0_GPIO_A_DEFAULT 0x99U

◆ GPIO0_0_GPIO_B_ADDR

#define GPIO0_0_GPIO_B_ADDR 0x2BFU

◆ GPIO0_0_GPIO_B_DEFAULT

#define GPIO0_0_GPIO_B_DEFAULT 0xA0U

◆ GPIO0_0_GPIO_C_ADDR

#define GPIO0_0_GPIO_C_ADDR 0x2C0U

◆ GPIO0_0_GPIO_C_DEFAULT

#define GPIO0_0_GPIO_C_DEFAULT 0x40U

◆ GPIO10_10_GPIO_A_ADDR

#define GPIO10_10_GPIO_A_ADDR 0x2DCU

◆ GPIO10_10_GPIO_A_DEFAULT

#define GPIO10_10_GPIO_A_DEFAULT 0x99U

◆ GPIO10_10_GPIO_B_ADDR

#define GPIO10_10_GPIO_B_ADDR 0x2DDU

◆ GPIO10_10_GPIO_B_DEFAULT

#define GPIO10_10_GPIO_B_DEFAULT 0x2AU

◆ GPIO10_10_GPIO_C_ADDR

#define GPIO10_10_GPIO_C_ADDR 0x2DEU

◆ GPIO10_10_GPIO_C_DEFAULT

#define GPIO10_10_GPIO_C_DEFAULT 0x4AU

◆ GPIO1_1_GPIO_A_ADDR

#define GPIO1_1_GPIO_A_ADDR 0x2C1U

◆ GPIO1_1_GPIO_A_DEFAULT

#define GPIO1_1_GPIO_A_DEFAULT 0x81U

◆ GPIO1_1_GPIO_B_ADDR

#define GPIO1_1_GPIO_B_ADDR 0x2C2U

◆ GPIO1_1_GPIO_B_DEFAULT

#define GPIO1_1_GPIO_B_DEFAULT 0x21U

◆ GPIO1_1_GPIO_C_ADDR

#define GPIO1_1_GPIO_C_ADDR 0x2C3U

◆ GPIO1_1_GPIO_C_DEFAULT

#define GPIO1_1_GPIO_C_DEFAULT 0x41U

◆ GPIO2_2_GPIO_A_ADDR

#define GPIO2_2_GPIO_A_ADDR 0x2C4U

◆ GPIO2_2_GPIO_A_DEFAULT

#define GPIO2_2_GPIO_A_DEFAULT 0x99U

◆ GPIO2_2_GPIO_B_ADDR

#define GPIO2_2_GPIO_B_ADDR 0x2C5U

◆ GPIO2_2_GPIO_B_DEFAULT

#define GPIO2_2_GPIO_B_DEFAULT 0x22U

◆ GPIO2_2_GPIO_C_ADDR

#define GPIO2_2_GPIO_C_ADDR 0x2C6U

◆ GPIO2_2_GPIO_C_DEFAULT

#define GPIO2_2_GPIO_C_DEFAULT 0x42U

◆ GPIO3_3_GPIO_A_ADDR

#define GPIO3_3_GPIO_A_ADDR 0x2C7U

◆ GPIO3_3_GPIO_A_DEFAULT

#define GPIO3_3_GPIO_A_DEFAULT 0x81U

◆ GPIO3_3_GPIO_B_ADDR

#define GPIO3_3_GPIO_B_ADDR 0x2C8U

◆ GPIO3_3_GPIO_B_DEFAULT

#define GPIO3_3_GPIO_B_DEFAULT 0xA3U

◆ GPIO3_3_GPIO_C_ADDR

#define GPIO3_3_GPIO_C_ADDR 0x2C9U

◆ GPIO3_3_GPIO_C_DEFAULT

#define GPIO3_3_GPIO_C_DEFAULT 0x43U

◆ GPIO4_4_GPIO_A_ADDR

#define GPIO4_4_GPIO_A_ADDR 0x2CAU

◆ GPIO4_4_GPIO_A_DEFAULT

#define GPIO4_4_GPIO_A_DEFAULT 0x99U

◆ GPIO4_4_GPIO_B_ADDR

#define GPIO4_4_GPIO_B_ADDR 0x2CBU

◆ GPIO4_4_GPIO_B_DEFAULT

#define GPIO4_4_GPIO_B_DEFAULT 0xA4U

◆ GPIO4_4_GPIO_C_ADDR

#define GPIO4_4_GPIO_C_ADDR 0x2CCU

◆ GPIO4_4_GPIO_C_DEFAULT

#define GPIO4_4_GPIO_C_DEFAULT 0x44U

◆ GPIO5_5_GPIO_A_ADDR

#define GPIO5_5_GPIO_A_ADDR 0x2CDU

◆ GPIO5_5_GPIO_A_DEFAULT

#define GPIO5_5_GPIO_A_DEFAULT 0x81U

◆ GPIO5_5_GPIO_B_ADDR

#define GPIO5_5_GPIO_B_ADDR 0x2CEU

◆ GPIO5_5_GPIO_B_DEFAULT

#define GPIO5_5_GPIO_B_DEFAULT 0xA5U

◆ GPIO5_5_GPIO_C_ADDR

#define GPIO5_5_GPIO_C_ADDR 0x2CFU

◆ GPIO5_5_GPIO_C_DEFAULT

#define GPIO5_5_GPIO_C_DEFAULT 0x45U

◆ GPIO6_6_GPIO_A_ADDR

#define GPIO6_6_GPIO_A_ADDR 0x2D0U

◆ GPIO6_6_GPIO_A_DEFAULT

#define GPIO6_6_GPIO_A_DEFAULT 0x99U

◆ GPIO6_6_GPIO_B_ADDR

#define GPIO6_6_GPIO_B_ADDR 0x2D1U

◆ GPIO6_6_GPIO_B_DEFAULT

#define GPIO6_6_GPIO_B_DEFAULT 0xA6U

◆ GPIO6_6_GPIO_C_ADDR

#define GPIO6_6_GPIO_C_ADDR 0x2D2U

◆ GPIO6_6_GPIO_C_DEFAULT

#define GPIO6_6_GPIO_C_DEFAULT 0x46U

◆ GPIO7_7_GPIO_A_ADDR

#define GPIO7_7_GPIO_A_ADDR 0x2D3U

◆ GPIO7_7_GPIO_A_DEFAULT

#define GPIO7_7_GPIO_A_DEFAULT 0x83U

◆ GPIO7_7_GPIO_B_ADDR

#define GPIO7_7_GPIO_B_ADDR 0x2D4U

◆ GPIO7_7_GPIO_B_DEFAULT

#define GPIO7_7_GPIO_B_DEFAULT 0xA7U

◆ GPIO7_7_GPIO_C_ADDR

#define GPIO7_7_GPIO_C_ADDR 0x2D5U

◆ GPIO7_7_GPIO_C_DEFAULT

#define GPIO7_7_GPIO_C_DEFAULT 0x47U

◆ GPIO8_8_GPIO_A_ADDR

#define GPIO8_8_GPIO_A_ADDR 0x2D6U

◆ GPIO8_8_GPIO_A_DEFAULT

#define GPIO8_8_GPIO_A_DEFAULT 0x9CU

◆ GPIO8_8_GPIO_B_ADDR

#define GPIO8_8_GPIO_B_ADDR 0x2D7U

◆ GPIO8_8_GPIO_B_DEFAULT

#define GPIO8_8_GPIO_B_DEFAULT 0x28U

◆ GPIO8_8_GPIO_C_ADDR

#define GPIO8_8_GPIO_C_ADDR 0x2D8U

◆ GPIO8_8_GPIO_C_DEFAULT

#define GPIO8_8_GPIO_C_DEFAULT 0x48U

◆ GPIO9_9_GPIO_A_ADDR

#define GPIO9_9_GPIO_A_ADDR 0x2D9U

◆ GPIO9_9_GPIO_A_DEFAULT

#define GPIO9_9_GPIO_A_DEFAULT 0x81U

◆ GPIO9_9_GPIO_B_ADDR

#define GPIO9_9_GPIO_B_ADDR 0x2DAU

◆ GPIO9_9_GPIO_B_DEFAULT

#define GPIO9_9_GPIO_B_DEFAULT 0xA9U

◆ GPIO9_9_GPIO_C_ADDR

#define GPIO9_9_GPIO_C_ADDR 0x2DBU

◆ GPIO9_9_GPIO_C_DEFAULT

#define GPIO9_9_GPIO_C_DEFAULT 0x49U

◆ GPIO_FWD_CDLY_GMSL_GPIOA_ADDR

#define GPIO_FWD_CDLY_GMSL_GPIOA_ADDR 0x30U

◆ GPIO_FWD_CDLY_GMSL_GPIOA_MASK

#define GPIO_FWD_CDLY_GMSL_GPIOA_MASK 0x3FU

◆ GPIO_FWD_CDLY_GMSL_GPIOA_POS

#define GPIO_FWD_CDLY_GMSL_GPIOA_POS 0U

◆ GPIO_IN_GPIO0_0_GPIO_A_ADDR

#define GPIO_IN_GPIO0_0_GPIO_A_ADDR 0x2BEU

◆ GPIO_IN_GPIO0_0_GPIO_A_MASK

#define GPIO_IN_GPIO0_0_GPIO_A_MASK 0x08U

◆ GPIO_IN_GPIO0_0_GPIO_A_POS

#define GPIO_IN_GPIO0_0_GPIO_A_POS 3U

◆ GPIO_IN_GPIO10_10_GPIO_A_ADDR

#define GPIO_IN_GPIO10_10_GPIO_A_ADDR 0x2DCU

◆ GPIO_IN_GPIO10_10_GPIO_A_MASK

#define GPIO_IN_GPIO10_10_GPIO_A_MASK 0x08U

◆ GPIO_IN_GPIO10_10_GPIO_A_POS

#define GPIO_IN_GPIO10_10_GPIO_A_POS 3U

◆ GPIO_IN_GPIO1_1_GPIO_A_ADDR

#define GPIO_IN_GPIO1_1_GPIO_A_ADDR 0x2C1U

◆ GPIO_IN_GPIO1_1_GPIO_A_MASK

#define GPIO_IN_GPIO1_1_GPIO_A_MASK 0x08U

◆ GPIO_IN_GPIO1_1_GPIO_A_POS

#define GPIO_IN_GPIO1_1_GPIO_A_POS 3U

◆ GPIO_IN_GPIO2_2_GPIO_A_ADDR

#define GPIO_IN_GPIO2_2_GPIO_A_ADDR 0x2C4U

◆ GPIO_IN_GPIO2_2_GPIO_A_MASK

#define GPIO_IN_GPIO2_2_GPIO_A_MASK 0x08U

◆ GPIO_IN_GPIO2_2_GPIO_A_POS

#define GPIO_IN_GPIO2_2_GPIO_A_POS 3U

◆ GPIO_IN_GPIO3_3_GPIO_A_ADDR

#define GPIO_IN_GPIO3_3_GPIO_A_ADDR 0x2C7U

◆ GPIO_IN_GPIO3_3_GPIO_A_MASK

#define GPIO_IN_GPIO3_3_GPIO_A_MASK 0x08U

◆ GPIO_IN_GPIO3_3_GPIO_A_POS

#define GPIO_IN_GPIO3_3_GPIO_A_POS 3U

◆ GPIO_IN_GPIO4_4_GPIO_A_ADDR

#define GPIO_IN_GPIO4_4_GPIO_A_ADDR 0x2CAU

◆ GPIO_IN_GPIO4_4_GPIO_A_MASK

#define GPIO_IN_GPIO4_4_GPIO_A_MASK 0x08U

◆ GPIO_IN_GPIO4_4_GPIO_A_POS

#define GPIO_IN_GPIO4_4_GPIO_A_POS 3U

◆ GPIO_IN_GPIO5_5_GPIO_A_ADDR

#define GPIO_IN_GPIO5_5_GPIO_A_ADDR 0x2CDU

◆ GPIO_IN_GPIO5_5_GPIO_A_MASK

#define GPIO_IN_GPIO5_5_GPIO_A_MASK 0x08U

◆ GPIO_IN_GPIO5_5_GPIO_A_POS

#define GPIO_IN_GPIO5_5_GPIO_A_POS 3U

◆ GPIO_IN_GPIO6_6_GPIO_A_ADDR

#define GPIO_IN_GPIO6_6_GPIO_A_ADDR 0x2D0U

◆ GPIO_IN_GPIO6_6_GPIO_A_MASK

#define GPIO_IN_GPIO6_6_GPIO_A_MASK 0x08U

◆ GPIO_IN_GPIO6_6_GPIO_A_POS

#define GPIO_IN_GPIO6_6_GPIO_A_POS 3U

◆ GPIO_IN_GPIO7_7_GPIO_A_ADDR

#define GPIO_IN_GPIO7_7_GPIO_A_ADDR 0x2D3U

◆ GPIO_IN_GPIO7_7_GPIO_A_MASK

#define GPIO_IN_GPIO7_7_GPIO_A_MASK 0x08U

◆ GPIO_IN_GPIO7_7_GPIO_A_POS

#define GPIO_IN_GPIO7_7_GPIO_A_POS 3U

◆ GPIO_IN_GPIO8_8_GPIO_A_ADDR

#define GPIO_IN_GPIO8_8_GPIO_A_ADDR 0x2D6U

◆ GPIO_IN_GPIO8_8_GPIO_A_MASK

#define GPIO_IN_GPIO8_8_GPIO_A_MASK 0x08U

◆ GPIO_IN_GPIO8_8_GPIO_A_POS

#define GPIO_IN_GPIO8_8_GPIO_A_POS 3U

◆ GPIO_IN_GPIO9_9_GPIO_A_ADDR

#define GPIO_IN_GPIO9_9_GPIO_A_ADDR 0x2D9U

◆ GPIO_IN_GPIO9_9_GPIO_A_MASK

#define GPIO_IN_GPIO9_9_GPIO_A_MASK 0x08U

◆ GPIO_IN_GPIO9_9_GPIO_A_POS

#define GPIO_IN_GPIO9_9_GPIO_A_POS 3U

◆ GPIO_OUT_DIS_GPIO0_0_GPIO_A_ADDR

#define GPIO_OUT_DIS_GPIO0_0_GPIO_A_ADDR 0x2BEU

◆ GPIO_OUT_DIS_GPIO0_0_GPIO_A_MASK

#define GPIO_OUT_DIS_GPIO0_0_GPIO_A_MASK 0x01U

◆ GPIO_OUT_DIS_GPIO0_0_GPIO_A_POS

#define GPIO_OUT_DIS_GPIO0_0_GPIO_A_POS 0U

◆ GPIO_OUT_DIS_GPIO10_10_GPIO_A_ADDR

#define GPIO_OUT_DIS_GPIO10_10_GPIO_A_ADDR 0x2DCU

◆ GPIO_OUT_DIS_GPIO10_10_GPIO_A_MASK

#define GPIO_OUT_DIS_GPIO10_10_GPIO_A_MASK 0x01U

◆ GPIO_OUT_DIS_GPIO10_10_GPIO_A_POS

#define GPIO_OUT_DIS_GPIO10_10_GPIO_A_POS 0U

◆ GPIO_OUT_DIS_GPIO1_1_GPIO_A_ADDR

#define GPIO_OUT_DIS_GPIO1_1_GPIO_A_ADDR 0x2C1U

◆ GPIO_OUT_DIS_GPIO1_1_GPIO_A_MASK

#define GPIO_OUT_DIS_GPIO1_1_GPIO_A_MASK 0x01U

◆ GPIO_OUT_DIS_GPIO1_1_GPIO_A_POS

#define GPIO_OUT_DIS_GPIO1_1_GPIO_A_POS 0U

◆ GPIO_OUT_DIS_GPIO2_2_GPIO_A_ADDR

#define GPIO_OUT_DIS_GPIO2_2_GPIO_A_ADDR 0x2C4U

◆ GPIO_OUT_DIS_GPIO2_2_GPIO_A_MASK

#define GPIO_OUT_DIS_GPIO2_2_GPIO_A_MASK 0x01U

◆ GPIO_OUT_DIS_GPIO2_2_GPIO_A_POS

#define GPIO_OUT_DIS_GPIO2_2_GPIO_A_POS 0U

◆ GPIO_OUT_DIS_GPIO3_3_GPIO_A_ADDR

#define GPIO_OUT_DIS_GPIO3_3_GPIO_A_ADDR 0x2C7U

◆ GPIO_OUT_DIS_GPIO3_3_GPIO_A_MASK

#define GPIO_OUT_DIS_GPIO3_3_GPIO_A_MASK 0x01U

◆ GPIO_OUT_DIS_GPIO3_3_GPIO_A_POS

#define GPIO_OUT_DIS_GPIO3_3_GPIO_A_POS 0U

◆ GPIO_OUT_DIS_GPIO4_4_GPIO_A_ADDR

#define GPIO_OUT_DIS_GPIO4_4_GPIO_A_ADDR 0x2CAU

◆ GPIO_OUT_DIS_GPIO4_4_GPIO_A_MASK

#define GPIO_OUT_DIS_GPIO4_4_GPIO_A_MASK 0x01U

◆ GPIO_OUT_DIS_GPIO4_4_GPIO_A_POS

#define GPIO_OUT_DIS_GPIO4_4_GPIO_A_POS 0U

◆ GPIO_OUT_DIS_GPIO5_5_GPIO_A_ADDR

#define GPIO_OUT_DIS_GPIO5_5_GPIO_A_ADDR 0x2CDU

◆ GPIO_OUT_DIS_GPIO5_5_GPIO_A_MASK

#define GPIO_OUT_DIS_GPIO5_5_GPIO_A_MASK 0x01U

◆ GPIO_OUT_DIS_GPIO5_5_GPIO_A_POS

#define GPIO_OUT_DIS_GPIO5_5_GPIO_A_POS 0U

◆ GPIO_OUT_DIS_GPIO6_6_GPIO_A_ADDR

#define GPIO_OUT_DIS_GPIO6_6_GPIO_A_ADDR 0x2D0U

◆ GPIO_OUT_DIS_GPIO6_6_GPIO_A_MASK

#define GPIO_OUT_DIS_GPIO6_6_GPIO_A_MASK 0x01U

◆ GPIO_OUT_DIS_GPIO6_6_GPIO_A_POS

#define GPIO_OUT_DIS_GPIO6_6_GPIO_A_POS 0U

◆ GPIO_OUT_DIS_GPIO7_7_GPIO_A_ADDR

#define GPIO_OUT_DIS_GPIO7_7_GPIO_A_ADDR 0x2D3U

◆ GPIO_OUT_DIS_GPIO7_7_GPIO_A_MASK

#define GPIO_OUT_DIS_GPIO7_7_GPIO_A_MASK 0x01U

◆ GPIO_OUT_DIS_GPIO7_7_GPIO_A_POS

#define GPIO_OUT_DIS_GPIO7_7_GPIO_A_POS 0U

◆ GPIO_OUT_DIS_GPIO8_8_GPIO_A_ADDR

#define GPIO_OUT_DIS_GPIO8_8_GPIO_A_ADDR 0x2D6U

◆ GPIO_OUT_DIS_GPIO8_8_GPIO_A_MASK

#define GPIO_OUT_DIS_GPIO8_8_GPIO_A_MASK 0x01U

◆ GPIO_OUT_DIS_GPIO8_8_GPIO_A_POS

#define GPIO_OUT_DIS_GPIO8_8_GPIO_A_POS 0U

◆ GPIO_OUT_DIS_GPIO9_9_GPIO_A_ADDR

#define GPIO_OUT_DIS_GPIO9_9_GPIO_A_ADDR 0x2D9U

◆ GPIO_OUT_DIS_GPIO9_9_GPIO_A_MASK

#define GPIO_OUT_DIS_GPIO9_9_GPIO_A_MASK 0x01U

◆ GPIO_OUT_DIS_GPIO9_9_GPIO_A_POS

#define GPIO_OUT_DIS_GPIO9_9_GPIO_A_POS 0U

◆ GPIO_OUT_GPIO0_0_GPIO_A_ADDR

#define GPIO_OUT_GPIO0_0_GPIO_A_ADDR 0x2BEU

◆ GPIO_OUT_GPIO0_0_GPIO_A_MASK

#define GPIO_OUT_GPIO0_0_GPIO_A_MASK 0x10U

◆ GPIO_OUT_GPIO0_0_GPIO_A_POS

#define GPIO_OUT_GPIO0_0_GPIO_A_POS 4U

◆ GPIO_OUT_GPIO10_10_GPIO_A_ADDR

#define GPIO_OUT_GPIO10_10_GPIO_A_ADDR 0x2DCU

◆ GPIO_OUT_GPIO10_10_GPIO_A_MASK

#define GPIO_OUT_GPIO10_10_GPIO_A_MASK 0x10U

◆ GPIO_OUT_GPIO10_10_GPIO_A_POS

#define GPIO_OUT_GPIO10_10_GPIO_A_POS 4U

◆ GPIO_OUT_GPIO1_1_GPIO_A_ADDR

#define GPIO_OUT_GPIO1_1_GPIO_A_ADDR 0x2C1U

◆ GPIO_OUT_GPIO1_1_GPIO_A_MASK

#define GPIO_OUT_GPIO1_1_GPIO_A_MASK 0x10U

◆ GPIO_OUT_GPIO1_1_GPIO_A_POS

#define GPIO_OUT_GPIO1_1_GPIO_A_POS 4U

◆ GPIO_OUT_GPIO2_2_GPIO_A_ADDR

#define GPIO_OUT_GPIO2_2_GPIO_A_ADDR 0x2C4U

◆ GPIO_OUT_GPIO2_2_GPIO_A_MASK

#define GPIO_OUT_GPIO2_2_GPIO_A_MASK 0x10U

◆ GPIO_OUT_GPIO2_2_GPIO_A_POS

#define GPIO_OUT_GPIO2_2_GPIO_A_POS 4U

◆ GPIO_OUT_GPIO3_3_GPIO_A_ADDR

#define GPIO_OUT_GPIO3_3_GPIO_A_ADDR 0x2C7U

◆ GPIO_OUT_GPIO3_3_GPIO_A_MASK

#define GPIO_OUT_GPIO3_3_GPIO_A_MASK 0x10U

◆ GPIO_OUT_GPIO3_3_GPIO_A_POS

#define GPIO_OUT_GPIO3_3_GPIO_A_POS 4U

◆ GPIO_OUT_GPIO4_4_GPIO_A_ADDR

#define GPIO_OUT_GPIO4_4_GPIO_A_ADDR 0x2CAU

◆ GPIO_OUT_GPIO4_4_GPIO_A_MASK

#define GPIO_OUT_GPIO4_4_GPIO_A_MASK 0x10U

◆ GPIO_OUT_GPIO4_4_GPIO_A_POS

#define GPIO_OUT_GPIO4_4_GPIO_A_POS 4U

◆ GPIO_OUT_GPIO5_5_GPIO_A_ADDR

#define GPIO_OUT_GPIO5_5_GPIO_A_ADDR 0x2CDU

◆ GPIO_OUT_GPIO5_5_GPIO_A_MASK

#define GPIO_OUT_GPIO5_5_GPIO_A_MASK 0x10U

◆ GPIO_OUT_GPIO5_5_GPIO_A_POS

#define GPIO_OUT_GPIO5_5_GPIO_A_POS 4U

◆ GPIO_OUT_GPIO6_6_GPIO_A_ADDR

#define GPIO_OUT_GPIO6_6_GPIO_A_ADDR 0x2D0U

◆ GPIO_OUT_GPIO6_6_GPIO_A_MASK

#define GPIO_OUT_GPIO6_6_GPIO_A_MASK 0x10U

◆ GPIO_OUT_GPIO6_6_GPIO_A_POS

#define GPIO_OUT_GPIO6_6_GPIO_A_POS 4U

◆ GPIO_OUT_GPIO7_7_GPIO_A_ADDR

#define GPIO_OUT_GPIO7_7_GPIO_A_ADDR 0x2D3U

◆ GPIO_OUT_GPIO7_7_GPIO_A_MASK

#define GPIO_OUT_GPIO7_7_GPIO_A_MASK 0x10U

◆ GPIO_OUT_GPIO7_7_GPIO_A_POS

#define GPIO_OUT_GPIO7_7_GPIO_A_POS 4U

◆ GPIO_OUT_GPIO8_8_GPIO_A_ADDR

#define GPIO_OUT_GPIO8_8_GPIO_A_ADDR 0x2D6U

◆ GPIO_OUT_GPIO8_8_GPIO_A_MASK

#define GPIO_OUT_GPIO8_8_GPIO_A_MASK 0x10U

◆ GPIO_OUT_GPIO8_8_GPIO_A_POS

#define GPIO_OUT_GPIO8_8_GPIO_A_POS 4U

◆ GPIO_OUT_GPIO9_9_GPIO_A_ADDR

#define GPIO_OUT_GPIO9_9_GPIO_A_ADDR 0x2D9U

◆ GPIO_OUT_GPIO9_9_GPIO_A_MASK

#define GPIO_OUT_GPIO9_9_GPIO_A_MASK 0x10U

◆ GPIO_OUT_GPIO9_9_GPIO_A_POS

#define GPIO_OUT_GPIO9_9_GPIO_A_POS 4U

◆ GPIO_REV_CDLY_GMSL_GPIOB_ADDR

#define GPIO_REV_CDLY_GMSL_GPIOB_ADDR 0x31U

◆ GPIO_REV_CDLY_GMSL_GPIOB_MASK

#define GPIO_REV_CDLY_GMSL_GPIOB_MASK 0x3FU

◆ GPIO_REV_CDLY_GMSL_GPIOB_POS

#define GPIO_REV_CDLY_GMSL_GPIOB_POS 0U

◆ GPIO_RX_EN_GPIO0_0_GPIO_A_ADDR

#define GPIO_RX_EN_GPIO0_0_GPIO_A_ADDR 0x2BEU

◆ GPIO_RX_EN_GPIO0_0_GPIO_A_MASK

#define GPIO_RX_EN_GPIO0_0_GPIO_A_MASK 0x04U

◆ GPIO_RX_EN_GPIO0_0_GPIO_A_POS

#define GPIO_RX_EN_GPIO0_0_GPIO_A_POS 2U

◆ GPIO_RX_EN_GPIO10_10_GPIO_A_ADDR

#define GPIO_RX_EN_GPIO10_10_GPIO_A_ADDR 0x2DCU

◆ GPIO_RX_EN_GPIO10_10_GPIO_A_MASK

#define GPIO_RX_EN_GPIO10_10_GPIO_A_MASK 0x04U

◆ GPIO_RX_EN_GPIO10_10_GPIO_A_POS

#define GPIO_RX_EN_GPIO10_10_GPIO_A_POS 2U

◆ GPIO_RX_EN_GPIO1_1_GPIO_A_ADDR

#define GPIO_RX_EN_GPIO1_1_GPIO_A_ADDR 0x2C1U

◆ GPIO_RX_EN_GPIO1_1_GPIO_A_MASK

#define GPIO_RX_EN_GPIO1_1_GPIO_A_MASK 0x04U

◆ GPIO_RX_EN_GPIO1_1_GPIO_A_POS

#define GPIO_RX_EN_GPIO1_1_GPIO_A_POS 2U

◆ GPIO_RX_EN_GPIO2_2_GPIO_A_ADDR

#define GPIO_RX_EN_GPIO2_2_GPIO_A_ADDR 0x2C4U

◆ GPIO_RX_EN_GPIO2_2_GPIO_A_MASK

#define GPIO_RX_EN_GPIO2_2_GPIO_A_MASK 0x04U

◆ GPIO_RX_EN_GPIO2_2_GPIO_A_POS

#define GPIO_RX_EN_GPIO2_2_GPIO_A_POS 2U

◆ GPIO_RX_EN_GPIO3_3_GPIO_A_ADDR

#define GPIO_RX_EN_GPIO3_3_GPIO_A_ADDR 0x2C7U

◆ GPIO_RX_EN_GPIO3_3_GPIO_A_MASK

#define GPIO_RX_EN_GPIO3_3_GPIO_A_MASK 0x04U

◆ GPIO_RX_EN_GPIO3_3_GPIO_A_POS

#define GPIO_RX_EN_GPIO3_3_GPIO_A_POS 2U

◆ GPIO_RX_EN_GPIO4_4_GPIO_A_ADDR

#define GPIO_RX_EN_GPIO4_4_GPIO_A_ADDR 0x2CAU

◆ GPIO_RX_EN_GPIO4_4_GPIO_A_MASK

#define GPIO_RX_EN_GPIO4_4_GPIO_A_MASK 0x04U

◆ GPIO_RX_EN_GPIO4_4_GPIO_A_POS

#define GPIO_RX_EN_GPIO4_4_GPIO_A_POS 2U

◆ GPIO_RX_EN_GPIO5_5_GPIO_A_ADDR

#define GPIO_RX_EN_GPIO5_5_GPIO_A_ADDR 0x2CDU

◆ GPIO_RX_EN_GPIO5_5_GPIO_A_MASK

#define GPIO_RX_EN_GPIO5_5_GPIO_A_MASK 0x04U

◆ GPIO_RX_EN_GPIO5_5_GPIO_A_POS

#define GPIO_RX_EN_GPIO5_5_GPIO_A_POS 2U

◆ GPIO_RX_EN_GPIO6_6_GPIO_A_ADDR

#define GPIO_RX_EN_GPIO6_6_GPIO_A_ADDR 0x2D0U

◆ GPIO_RX_EN_GPIO6_6_GPIO_A_MASK

#define GPIO_RX_EN_GPIO6_6_GPIO_A_MASK 0x04U

◆ GPIO_RX_EN_GPIO6_6_GPIO_A_POS

#define GPIO_RX_EN_GPIO6_6_GPIO_A_POS 2U

◆ GPIO_RX_EN_GPIO7_7_GPIO_A_ADDR

#define GPIO_RX_EN_GPIO7_7_GPIO_A_ADDR 0x2D3U

◆ GPIO_RX_EN_GPIO7_7_GPIO_A_MASK

#define GPIO_RX_EN_GPIO7_7_GPIO_A_MASK 0x04U

◆ GPIO_RX_EN_GPIO7_7_GPIO_A_POS

#define GPIO_RX_EN_GPIO7_7_GPIO_A_POS 2U

◆ GPIO_RX_EN_GPIO8_8_GPIO_A_ADDR

#define GPIO_RX_EN_GPIO8_8_GPIO_A_ADDR 0x2D6U

◆ GPIO_RX_EN_GPIO8_8_GPIO_A_MASK

#define GPIO_RX_EN_GPIO8_8_GPIO_A_MASK 0x04U

◆ GPIO_RX_EN_GPIO8_8_GPIO_A_POS

#define GPIO_RX_EN_GPIO8_8_GPIO_A_POS 2U

◆ GPIO_RX_EN_GPIO9_9_GPIO_A_ADDR

#define GPIO_RX_EN_GPIO9_9_GPIO_A_ADDR 0x2D9U

◆ GPIO_RX_EN_GPIO9_9_GPIO_A_MASK

#define GPIO_RX_EN_GPIO9_9_GPIO_A_MASK 0x04U

◆ GPIO_RX_EN_GPIO9_9_GPIO_A_POS

#define GPIO_RX_EN_GPIO9_9_GPIO_A_POS 2U

◆ GPIO_RX_ID_GPIO0_0_GPIO_C_ADDR

#define GPIO_RX_ID_GPIO0_0_GPIO_C_ADDR 0x2C0U

◆ GPIO_RX_ID_GPIO0_0_GPIO_C_MASK

#define GPIO_RX_ID_GPIO0_0_GPIO_C_MASK 0x1FU

◆ GPIO_RX_ID_GPIO0_0_GPIO_C_POS

#define GPIO_RX_ID_GPIO0_0_GPIO_C_POS 0U

◆ GPIO_RX_ID_GPIO10_10_GPIO_C_ADDR

#define GPIO_RX_ID_GPIO10_10_GPIO_C_ADDR 0x2DEU

◆ GPIO_RX_ID_GPIO10_10_GPIO_C_MASK

#define GPIO_RX_ID_GPIO10_10_GPIO_C_MASK 0x1FU

◆ GPIO_RX_ID_GPIO10_10_GPIO_C_POS

#define GPIO_RX_ID_GPIO10_10_GPIO_C_POS 0U

◆ GPIO_RX_ID_GPIO1_1_GPIO_C_ADDR

#define GPIO_RX_ID_GPIO1_1_GPIO_C_ADDR 0x2C3U

◆ GPIO_RX_ID_GPIO1_1_GPIO_C_MASK

#define GPIO_RX_ID_GPIO1_1_GPIO_C_MASK 0x1FU

◆ GPIO_RX_ID_GPIO1_1_GPIO_C_POS

#define GPIO_RX_ID_GPIO1_1_GPIO_C_POS 0U

◆ GPIO_RX_ID_GPIO2_2_GPIO_C_ADDR

#define GPIO_RX_ID_GPIO2_2_GPIO_C_ADDR 0x2C6U

◆ GPIO_RX_ID_GPIO2_2_GPIO_C_MASK

#define GPIO_RX_ID_GPIO2_2_GPIO_C_MASK 0x1FU

◆ GPIO_RX_ID_GPIO2_2_GPIO_C_POS

#define GPIO_RX_ID_GPIO2_2_GPIO_C_POS 0U

◆ GPIO_RX_ID_GPIO3_3_GPIO_C_ADDR

#define GPIO_RX_ID_GPIO3_3_GPIO_C_ADDR 0x2C9U

◆ GPIO_RX_ID_GPIO3_3_GPIO_C_MASK

#define GPIO_RX_ID_GPIO3_3_GPIO_C_MASK 0x1FU

◆ GPIO_RX_ID_GPIO3_3_GPIO_C_POS

#define GPIO_RX_ID_GPIO3_3_GPIO_C_POS 0U

◆ GPIO_RX_ID_GPIO4_4_GPIO_C_ADDR

#define GPIO_RX_ID_GPIO4_4_GPIO_C_ADDR 0x2CCU

◆ GPIO_RX_ID_GPIO4_4_GPIO_C_MASK

#define GPIO_RX_ID_GPIO4_4_GPIO_C_MASK 0x1FU

◆ GPIO_RX_ID_GPIO4_4_GPIO_C_POS

#define GPIO_RX_ID_GPIO4_4_GPIO_C_POS 0U

◆ GPIO_RX_ID_GPIO5_5_GPIO_C_ADDR

#define GPIO_RX_ID_GPIO5_5_GPIO_C_ADDR 0x2CFU

◆ GPIO_RX_ID_GPIO5_5_GPIO_C_MASK

#define GPIO_RX_ID_GPIO5_5_GPIO_C_MASK 0x1FU

◆ GPIO_RX_ID_GPIO5_5_GPIO_C_POS

#define GPIO_RX_ID_GPIO5_5_GPIO_C_POS 0U

◆ GPIO_RX_ID_GPIO6_6_GPIO_C_ADDR

#define GPIO_RX_ID_GPIO6_6_GPIO_C_ADDR 0x2D2U

◆ GPIO_RX_ID_GPIO6_6_GPIO_C_MASK

#define GPIO_RX_ID_GPIO6_6_GPIO_C_MASK 0x1FU

◆ GPIO_RX_ID_GPIO6_6_GPIO_C_POS

#define GPIO_RX_ID_GPIO6_6_GPIO_C_POS 0U

◆ GPIO_RX_ID_GPIO7_7_GPIO_C_ADDR

#define GPIO_RX_ID_GPIO7_7_GPIO_C_ADDR 0x2D5U

◆ GPIO_RX_ID_GPIO7_7_GPIO_C_MASK

#define GPIO_RX_ID_GPIO7_7_GPIO_C_MASK 0x1FU

◆ GPIO_RX_ID_GPIO7_7_GPIO_C_POS

#define GPIO_RX_ID_GPIO7_7_GPIO_C_POS 0U

◆ GPIO_RX_ID_GPIO8_8_GPIO_C_ADDR

#define GPIO_RX_ID_GPIO8_8_GPIO_C_ADDR 0x2D8U

◆ GPIO_RX_ID_GPIO8_8_GPIO_C_MASK

#define GPIO_RX_ID_GPIO8_8_GPIO_C_MASK 0x1FU

◆ GPIO_RX_ID_GPIO8_8_GPIO_C_POS

#define GPIO_RX_ID_GPIO8_8_GPIO_C_POS 0U

◆ GPIO_RX_ID_GPIO9_9_GPIO_C_ADDR

#define GPIO_RX_ID_GPIO9_9_GPIO_C_ADDR 0x2DBU

◆ GPIO_RX_ID_GPIO9_9_GPIO_C_MASK

#define GPIO_RX_ID_GPIO9_9_GPIO_C_MASK 0x1FU

◆ GPIO_RX_ID_GPIO9_9_GPIO_C_POS

#define GPIO_RX_ID_GPIO9_9_GPIO_C_POS 0U

◆ GPIO_TX_EN_GPIO0_0_GPIO_A_ADDR

#define GPIO_TX_EN_GPIO0_0_GPIO_A_ADDR 0x2BEU

◆ GPIO_TX_EN_GPIO0_0_GPIO_A_MASK

#define GPIO_TX_EN_GPIO0_0_GPIO_A_MASK 0x02U

◆ GPIO_TX_EN_GPIO0_0_GPIO_A_POS

#define GPIO_TX_EN_GPIO0_0_GPIO_A_POS 1U

◆ GPIO_TX_EN_GPIO10_10_GPIO_A_ADDR

#define GPIO_TX_EN_GPIO10_10_GPIO_A_ADDR 0x2DCU

◆ GPIO_TX_EN_GPIO10_10_GPIO_A_MASK

#define GPIO_TX_EN_GPIO10_10_GPIO_A_MASK 0x02U

◆ GPIO_TX_EN_GPIO10_10_GPIO_A_POS

#define GPIO_TX_EN_GPIO10_10_GPIO_A_POS 1U

◆ GPIO_TX_EN_GPIO1_1_GPIO_A_ADDR

#define GPIO_TX_EN_GPIO1_1_GPIO_A_ADDR 0x2C1U

◆ GPIO_TX_EN_GPIO1_1_GPIO_A_MASK

#define GPIO_TX_EN_GPIO1_1_GPIO_A_MASK 0x02U

◆ GPIO_TX_EN_GPIO1_1_GPIO_A_POS

#define GPIO_TX_EN_GPIO1_1_GPIO_A_POS 1U

◆ GPIO_TX_EN_GPIO2_2_GPIO_A_ADDR

#define GPIO_TX_EN_GPIO2_2_GPIO_A_ADDR 0x2C4U

◆ GPIO_TX_EN_GPIO2_2_GPIO_A_MASK

#define GPIO_TX_EN_GPIO2_2_GPIO_A_MASK 0x02U

◆ GPIO_TX_EN_GPIO2_2_GPIO_A_POS

#define GPIO_TX_EN_GPIO2_2_GPIO_A_POS 1U

◆ GPIO_TX_EN_GPIO3_3_GPIO_A_ADDR

#define GPIO_TX_EN_GPIO3_3_GPIO_A_ADDR 0x2C7U

◆ GPIO_TX_EN_GPIO3_3_GPIO_A_MASK

#define GPIO_TX_EN_GPIO3_3_GPIO_A_MASK 0x02U

◆ GPIO_TX_EN_GPIO3_3_GPIO_A_POS

#define GPIO_TX_EN_GPIO3_3_GPIO_A_POS 1U

◆ GPIO_TX_EN_GPIO4_4_GPIO_A_ADDR

#define GPIO_TX_EN_GPIO4_4_GPIO_A_ADDR 0x2CAU

◆ GPIO_TX_EN_GPIO4_4_GPIO_A_MASK

#define GPIO_TX_EN_GPIO4_4_GPIO_A_MASK 0x02U

◆ GPIO_TX_EN_GPIO4_4_GPIO_A_POS

#define GPIO_TX_EN_GPIO4_4_GPIO_A_POS 1U

◆ GPIO_TX_EN_GPIO5_5_GPIO_A_ADDR

#define GPIO_TX_EN_GPIO5_5_GPIO_A_ADDR 0x2CDU

◆ GPIO_TX_EN_GPIO5_5_GPIO_A_MASK

#define GPIO_TX_EN_GPIO5_5_GPIO_A_MASK 0x02U

◆ GPIO_TX_EN_GPIO5_5_GPIO_A_POS

#define GPIO_TX_EN_GPIO5_5_GPIO_A_POS 1U

◆ GPIO_TX_EN_GPIO6_6_GPIO_A_ADDR

#define GPIO_TX_EN_GPIO6_6_GPIO_A_ADDR 0x2D0U

◆ GPIO_TX_EN_GPIO6_6_GPIO_A_MASK

#define GPIO_TX_EN_GPIO6_6_GPIO_A_MASK 0x02U

◆ GPIO_TX_EN_GPIO6_6_GPIO_A_POS

#define GPIO_TX_EN_GPIO6_6_GPIO_A_POS 1U

◆ GPIO_TX_EN_GPIO7_7_GPIO_A_ADDR

#define GPIO_TX_EN_GPIO7_7_GPIO_A_ADDR 0x2D3U

◆ GPIO_TX_EN_GPIO7_7_GPIO_A_MASK

#define GPIO_TX_EN_GPIO7_7_GPIO_A_MASK 0x02U

◆ GPIO_TX_EN_GPIO7_7_GPIO_A_POS

#define GPIO_TX_EN_GPIO7_7_GPIO_A_POS 1U

◆ GPIO_TX_EN_GPIO8_8_GPIO_A_ADDR

#define GPIO_TX_EN_GPIO8_8_GPIO_A_ADDR 0x2D6U

◆ GPIO_TX_EN_GPIO8_8_GPIO_A_MASK

#define GPIO_TX_EN_GPIO8_8_GPIO_A_MASK 0x02U

◆ GPIO_TX_EN_GPIO8_8_GPIO_A_POS

#define GPIO_TX_EN_GPIO8_8_GPIO_A_POS 1U

◆ GPIO_TX_EN_GPIO9_9_GPIO_A_ADDR

#define GPIO_TX_EN_GPIO9_9_GPIO_A_ADDR 0x2D9U

◆ GPIO_TX_EN_GPIO9_9_GPIO_A_MASK

#define GPIO_TX_EN_GPIO9_9_GPIO_A_MASK 0x02U

◆ GPIO_TX_EN_GPIO9_9_GPIO_A_POS

#define GPIO_TX_EN_GPIO9_9_GPIO_A_POS 1U

◆ GPIO_TX_ID_GPIO0_0_GPIO_B_ADDR

#define GPIO_TX_ID_GPIO0_0_GPIO_B_ADDR 0x2BFU

◆ GPIO_TX_ID_GPIO0_0_GPIO_B_MASK

#define GPIO_TX_ID_GPIO0_0_GPIO_B_MASK 0x1FU

◆ GPIO_TX_ID_GPIO0_0_GPIO_B_POS

#define GPIO_TX_ID_GPIO0_0_GPIO_B_POS 0U

◆ GPIO_TX_ID_GPIO10_10_GPIO_B_ADDR

#define GPIO_TX_ID_GPIO10_10_GPIO_B_ADDR 0x2DDU

◆ GPIO_TX_ID_GPIO10_10_GPIO_B_MASK

#define GPIO_TX_ID_GPIO10_10_GPIO_B_MASK 0x1FU

◆ GPIO_TX_ID_GPIO10_10_GPIO_B_POS

#define GPIO_TX_ID_GPIO10_10_GPIO_B_POS 0U

◆ GPIO_TX_ID_GPIO1_1_GPIO_B_ADDR

#define GPIO_TX_ID_GPIO1_1_GPIO_B_ADDR 0x2C2U

◆ GPIO_TX_ID_GPIO1_1_GPIO_B_MASK

#define GPIO_TX_ID_GPIO1_1_GPIO_B_MASK 0x1FU

◆ GPIO_TX_ID_GPIO1_1_GPIO_B_POS

#define GPIO_TX_ID_GPIO1_1_GPIO_B_POS 0U

◆ GPIO_TX_ID_GPIO2_2_GPIO_B_ADDR

#define GPIO_TX_ID_GPIO2_2_GPIO_B_ADDR 0x2C5U

◆ GPIO_TX_ID_GPIO2_2_GPIO_B_MASK

#define GPIO_TX_ID_GPIO2_2_GPIO_B_MASK 0x1FU

◆ GPIO_TX_ID_GPIO2_2_GPIO_B_POS

#define GPIO_TX_ID_GPIO2_2_GPIO_B_POS 0U

◆ GPIO_TX_ID_GPIO3_3_GPIO_B_ADDR

#define GPIO_TX_ID_GPIO3_3_GPIO_B_ADDR 0x2C8U

◆ GPIO_TX_ID_GPIO3_3_GPIO_B_MASK

#define GPIO_TX_ID_GPIO3_3_GPIO_B_MASK 0x1FU

◆ GPIO_TX_ID_GPIO3_3_GPIO_B_POS

#define GPIO_TX_ID_GPIO3_3_GPIO_B_POS 0U

◆ GPIO_TX_ID_GPIO4_4_GPIO_B_ADDR

#define GPIO_TX_ID_GPIO4_4_GPIO_B_ADDR 0x2CBU

◆ GPIO_TX_ID_GPIO4_4_GPIO_B_MASK

#define GPIO_TX_ID_GPIO4_4_GPIO_B_MASK 0x1FU

◆ GPIO_TX_ID_GPIO4_4_GPIO_B_POS

#define GPIO_TX_ID_GPIO4_4_GPIO_B_POS 0U

◆ GPIO_TX_ID_GPIO5_5_GPIO_B_ADDR

#define GPIO_TX_ID_GPIO5_5_GPIO_B_ADDR 0x2CEU

◆ GPIO_TX_ID_GPIO5_5_GPIO_B_MASK

#define GPIO_TX_ID_GPIO5_5_GPIO_B_MASK 0x1FU

◆ GPIO_TX_ID_GPIO5_5_GPIO_B_POS

#define GPIO_TX_ID_GPIO5_5_GPIO_B_POS 0U

◆ GPIO_TX_ID_GPIO6_6_GPIO_B_ADDR

#define GPIO_TX_ID_GPIO6_6_GPIO_B_ADDR 0x2D1U

◆ GPIO_TX_ID_GPIO6_6_GPIO_B_MASK

#define GPIO_TX_ID_GPIO6_6_GPIO_B_MASK 0x1FU

◆ GPIO_TX_ID_GPIO6_6_GPIO_B_POS

#define GPIO_TX_ID_GPIO6_6_GPIO_B_POS 0U

◆ GPIO_TX_ID_GPIO7_7_GPIO_B_ADDR

#define GPIO_TX_ID_GPIO7_7_GPIO_B_ADDR 0x2D4U

◆ GPIO_TX_ID_GPIO7_7_GPIO_B_MASK

#define GPIO_TX_ID_GPIO7_7_GPIO_B_MASK 0x1FU

◆ GPIO_TX_ID_GPIO7_7_GPIO_B_POS

#define GPIO_TX_ID_GPIO7_7_GPIO_B_POS 0U

◆ GPIO_TX_ID_GPIO8_8_GPIO_B_ADDR

#define GPIO_TX_ID_GPIO8_8_GPIO_B_ADDR 0x2D7U

◆ GPIO_TX_ID_GPIO8_8_GPIO_B_MASK

#define GPIO_TX_ID_GPIO8_8_GPIO_B_MASK 0x1FU

◆ GPIO_TX_ID_GPIO8_8_GPIO_B_POS

#define GPIO_TX_ID_GPIO8_8_GPIO_B_POS 0U

◆ GPIO_TX_ID_GPIO9_9_GPIO_B_ADDR

#define GPIO_TX_ID_GPIO9_9_GPIO_B_ADDR 0x2DAU

◆ GPIO_TX_ID_GPIO9_9_GPIO_B_MASK

#define GPIO_TX_ID_GPIO9_9_GPIO_B_MASK 0x1FU

◆ GPIO_TX_ID_GPIO9_9_GPIO_B_POS

#define GPIO_TX_ID_GPIO9_9_GPIO_B_POS 0U

◆ GRAD_INC_VTX_Z_VTX30_ADDR

#define GRAD_INC_VTX_Z_VTX30_ADDR 0x26CU

◆ GRAD_INC_VTX_Z_VTX30_MASK

#define GRAD_INC_VTX_Z_VTX30_MASK 0xFFU

◆ GRAD_INC_VTX_Z_VTX30_POS

#define GRAD_INC_VTX_Z_VTX30_POS 0U

◆ GRAD_MODE_VTX_Z_VTX29_ADDR

#define GRAD_MODE_VTX_Z_VTX29_ADDR 0x26BU

◆ GRAD_MODE_VTX_Z_VTX29_MASK

#define GRAD_MODE_VTX_Z_VTX29_MASK 0x04U

◆ GRAD_MODE_VTX_Z_VTX29_POS

#define GRAD_MODE_VTX_Z_VTX29_POS 2U

◆ HS_CNT_0_REF_VTG_VTX19_ADDR

#define HS_CNT_0_REF_VTG_VTX19_ADDR 0x3EFU

◆ HS_CNT_0_REF_VTG_VTX19_MASK

#define HS_CNT_0_REF_VTG_VTX19_MASK 0xFFU

◆ HS_CNT_0_REF_VTG_VTX19_POS

#define HS_CNT_0_REF_VTG_VTX19_POS 0U

◆ HS_CNT_0_VTX_Z_VTX19_ADDR

#define HS_CNT_0_VTX_Z_VTX19_ADDR 0x261U

◆ HS_CNT_0_VTX_Z_VTX19_MASK

#define HS_CNT_0_VTX_Z_VTX19_MASK 0xFFU

◆ HS_CNT_0_VTX_Z_VTX19_POS

#define HS_CNT_0_VTX_Z_VTX19_POS 0U

◆ HS_CNT_1_REF_VTG_VTX18_ADDR

#define HS_CNT_1_REF_VTG_VTX18_ADDR 0x3EEU

◆ HS_CNT_1_REF_VTG_VTX18_MASK

#define HS_CNT_1_REF_VTG_VTX18_MASK 0xFFU

◆ HS_CNT_1_REF_VTG_VTX18_POS

#define HS_CNT_1_REF_VTG_VTX18_POS 0U

◆ HS_CNT_1_VTX_Z_VTX18_ADDR

#define HS_CNT_1_VTX_Z_VTX18_ADDR 0x260U

◆ HS_CNT_1_VTX_Z_VTX18_MASK

#define HS_CNT_1_VTX_Z_VTX18_MASK 0xFFU

◆ HS_CNT_1_VTX_Z_VTX18_POS

#define HS_CNT_1_VTX_Z_VTX18_POS 0U

◆ HS_DET_Z_MISC_HS_VS_Z_ADDR

#define HS_DET_Z_MISC_HS_VS_Z_ADDR 0x55FU

◆ HS_DET_Z_MISC_HS_VS_Z_MASK

#define HS_DET_Z_MISC_HS_VS_Z_MASK 0x10U

◆ HS_DET_Z_MISC_HS_VS_Z_POS

#define HS_DET_Z_MISC_HS_VS_Z_POS 4U

◆ HS_GPIO_REF_VTG_REF_VTG2_ADDR

#define HS_GPIO_REF_VTG_REF_VTG2_ADDR 0x3F2U

◆ HS_GPIO_REF_VTG_REF_VTG2_MASK

#define HS_GPIO_REF_VTG_REF_VTG2_MASK 0x3EU

◆ HS_GPIO_REF_VTG_REF_VTG2_POS

#define HS_GPIO_REF_VTG_REF_VTG2_POS 1U

◆ HS_HIGH_0_REF_VTG_VTX15_ADDR

#define HS_HIGH_0_REF_VTG_VTX15_ADDR 0x3EBU

◆ HS_HIGH_0_REF_VTG_VTX15_MASK

#define HS_HIGH_0_REF_VTG_VTX15_MASK 0xFFU

◆ HS_HIGH_0_REF_VTG_VTX15_POS

#define HS_HIGH_0_REF_VTG_VTX15_POS 0U

◆ HS_HIGH_0_VTX_Z_VTX15_ADDR

#define HS_HIGH_0_VTX_Z_VTX15_ADDR 0x25DU

◆ HS_HIGH_0_VTX_Z_VTX15_MASK

#define HS_HIGH_0_VTX_Z_VTX15_MASK 0xFFU

◆ HS_HIGH_0_VTX_Z_VTX15_POS

#define HS_HIGH_0_VTX_Z_VTX15_POS 0U

◆ HS_HIGH_1_REF_VTG_VTX14_ADDR

#define HS_HIGH_1_REF_VTG_VTX14_ADDR 0x3EAU

◆ HS_HIGH_1_REF_VTG_VTX14_MASK

#define HS_HIGH_1_REF_VTG_VTX14_MASK 0xFFU

◆ HS_HIGH_1_REF_VTG_VTX14_POS

#define HS_HIGH_1_REF_VTG_VTX14_POS 0U

◆ HS_HIGH_1_VTX_Z_VTX14_ADDR

#define HS_HIGH_1_VTX_Z_VTX14_ADDR 0x25CU

◆ HS_HIGH_1_VTX_Z_VTX14_MASK

#define HS_HIGH_1_VTX_Z_VTX14_MASK 0xFFU

◆ HS_HIGH_1_VTX_Z_VTX14_POS

#define HS_HIGH_1_VTX_Z_VTX14_POS 0U

◆ HS_INV_REF_VTG_VTX0_ADDR

#define HS_INV_REF_VTG_VTX0_ADDR 0x3E0U

◆ HS_INV_REF_VTG_VTX0_MASK

#define HS_INV_REF_VTG_VTX0_MASK 0x08U

◆ HS_INV_REF_VTG_VTX0_POS

#define HS_INV_REF_VTG_VTX0_POS 3U

◆ HS_INV_VTX_Z_VTX0_ADDR

#define HS_INV_VTX_Z_VTX0_ADDR 0x24EU

◆ HS_INV_VTX_Z_VTX0_MASK

#define HS_INV_VTX_Z_VTX0_MASK 0x08U

◆ HS_INV_VTX_Z_VTX0_POS

#define HS_INV_VTX_Z_VTX0_POS 3U

◆ HS_LOW_0_REF_VTG_VTX17_ADDR

#define HS_LOW_0_REF_VTG_VTX17_ADDR 0x3EDU

◆ HS_LOW_0_REF_VTG_VTX17_MASK

#define HS_LOW_0_REF_VTG_VTX17_MASK 0xFFU

◆ HS_LOW_0_REF_VTG_VTX17_POS

#define HS_LOW_0_REF_VTG_VTX17_POS 0U

◆ HS_LOW_0_VTX_Z_VTX17_ADDR

#define HS_LOW_0_VTX_Z_VTX17_ADDR 0x25FU

◆ HS_LOW_0_VTX_Z_VTX17_MASK

#define HS_LOW_0_VTX_Z_VTX17_MASK 0xFFU

◆ HS_LOW_0_VTX_Z_VTX17_POS

#define HS_LOW_0_VTX_Z_VTX17_POS 0U

◆ HS_LOW_1_REF_VTG_VTX16_ADDR

#define HS_LOW_1_REF_VTG_VTX16_ADDR 0x3ECU

◆ HS_LOW_1_REF_VTG_VTX16_MASK

#define HS_LOW_1_REF_VTG_VTX16_MASK 0xFFU

◆ HS_LOW_1_REF_VTG_VTX16_POS

#define HS_LOW_1_REF_VTG_VTX16_POS 0U

◆ HS_LOW_1_VTX_Z_VTX16_ADDR

#define HS_LOW_1_VTX_Z_VTX16_ADDR 0x25EU

◆ HS_LOW_1_VTX_Z_VTX16_MASK

#define HS_LOW_1_VTX_Z_VTX16_MASK 0xFFU

◆ HS_LOW_1_VTX_Z_VTX16_POS

#define HS_LOW_1_VTX_Z_VTX16_POS 0U

◆ HS_POL_Z_MISC_HS_VS_Z_ADDR

#define HS_POL_Z_MISC_HS_VS_Z_ADDR 0x55FU

◆ HS_POL_Z_MISC_HS_VS_Z_MASK

#define HS_POL_Z_MISC_HS_VS_Z_MASK 0x01U

◆ HS_POL_Z_MISC_HS_VS_Z_POS

#define HS_POL_Z_MISC_HS_VS_Z_POS 0U

◆ HSEN_REF_VTG_REF_VTG2_ADDR

#define HSEN_REF_VTG_REF_VTG2_ADDR 0x3F2U

◆ HSEN_REF_VTG_REF_VTG2_MASK

#define HSEN_REF_VTG_REF_VTG2_MASK 0x01U

◆ HSEN_REF_VTG_REF_VTG2_POS

#define HSEN_REF_VTG_REF_VTG2_POS 0U

◆ I2C_UART_CRC_ERR_INT_FUNC_SAFE_FS_INTR1_ADDR

#define I2C_UART_CRC_ERR_INT_FUNC_SAFE_FS_INTR1_ADDR 0x1D13U

◆ I2C_UART_CRC_ERR_INT_FUNC_SAFE_FS_INTR1_MASK

#define I2C_UART_CRC_ERR_INT_FUNC_SAFE_FS_INTR1_MASK 0x40U

◆ I2C_UART_CRC_ERR_INT_FUNC_SAFE_FS_INTR1_POS

#define I2C_UART_CRC_ERR_INT_FUNC_SAFE_FS_INTR1_POS 6U

◆ I2C_UART_CRC_ERR_OEN_FUNC_SAFE_FS_INTR0_ADDR

#define I2C_UART_CRC_ERR_OEN_FUNC_SAFE_FS_INTR0_ADDR 0x1D12U

◆ I2C_UART_CRC_ERR_OEN_FUNC_SAFE_FS_INTR0_MASK

#define I2C_UART_CRC_ERR_OEN_FUNC_SAFE_FS_INTR0_MASK 0x40U

◆ I2C_UART_CRC_ERR_OEN_FUNC_SAFE_FS_INTR0_POS

#define I2C_UART_CRC_ERR_OEN_FUNC_SAFE_FS_INTR0_POS 6U

◆ I2C_UART_MSGCNTR_ERR_INT_FUNC_SAFE_FS_INTR1_ADDR

#define I2C_UART_MSGCNTR_ERR_INT_FUNC_SAFE_FS_INTR1_ADDR 0x1D13U

◆ I2C_UART_MSGCNTR_ERR_INT_FUNC_SAFE_FS_INTR1_MASK

#define I2C_UART_MSGCNTR_ERR_INT_FUNC_SAFE_FS_INTR1_MASK 0x80U

◆ I2C_UART_MSGCNTR_ERR_INT_FUNC_SAFE_FS_INTR1_POS

#define I2C_UART_MSGCNTR_ERR_INT_FUNC_SAFE_FS_INTR1_POS 7U

◆ I2C_UART_MSGCNTR_ERR_OEN_FUNC_SAFE_FS_INTR0_ADDR

#define I2C_UART_MSGCNTR_ERR_OEN_FUNC_SAFE_FS_INTR0_ADDR 0x1D12U

◆ I2C_UART_MSGCNTR_ERR_OEN_FUNC_SAFE_FS_INTR0_MASK

#define I2C_UART_MSGCNTR_ERR_OEN_FUNC_SAFE_FS_INTR0_MASK 0x80U

◆ I2C_UART_MSGCNTR_ERR_OEN_FUNC_SAFE_FS_INTR0_POS

#define I2C_UART_MSGCNTR_ERR_OEN_FUNC_SAFE_FS_INTR0_POS 7U

◆ I2C_WR_COMPUTE_FUNC_SAFE_REGCRC0_ADDR

#define I2C_WR_COMPUTE_FUNC_SAFE_REGCRC0_ADDR 0x1D00U

◆ I2C_WR_COMPUTE_FUNC_SAFE_REGCRC0_MASK

#define I2C_WR_COMPUTE_FUNC_SAFE_REGCRC0_MASK 0x08U

◆ I2C_WR_COMPUTE_FUNC_SAFE_REGCRC0_POS

#define I2C_WR_COMPUTE_FUNC_SAFE_REGCRC0_POS 3U

◆ I2CSEL_DEV_REG6_ADDR

#define I2CSEL_DEV_REG6_ADDR 0x06U

◆ I2CSEL_DEV_REG6_MASK

#define I2CSEL_DEV_REG6_MASK 0x10U

◆ I2CSEL_DEV_REG6_POS

#define I2CSEL_DEV_REG6_POS 4U

◆ IDLE_ERR_FLAG_TCTRL_INTR3_ADDR

#define IDLE_ERR_FLAG_TCTRL_INTR3_ADDR 0x1BU

◆ IDLE_ERR_FLAG_TCTRL_INTR3_MASK

#define IDLE_ERR_FLAG_TCTRL_INTR3_MASK 0x04U

◆ IDLE_ERR_FLAG_TCTRL_INTR3_POS

#define IDLE_ERR_FLAG_TCTRL_INTR3_POS 2U

◆ IDLE_ERR_OEN_TCTRL_INTR2_ADDR

#define IDLE_ERR_OEN_TCTRL_INTR2_ADDR 0x1AU

◆ IDLE_ERR_OEN_TCTRL_INTR2_MASK

#define IDLE_ERR_OEN_TCTRL_INTR2_MASK 0x04U

◆ IDLE_ERR_OEN_TCTRL_INTR2_POS

#define IDLE_ERR_OEN_TCTRL_INTR2_POS 2U

◆ IDLE_ERR_TCTRL_CNT2_ADDR

#define IDLE_ERR_TCTRL_CNT2_ADDR 0x24U

◆ IDLE_ERR_TCTRL_CNT2_MASK

#define IDLE_ERR_TCTRL_CNT2_MASK 0xFFU

◆ IDLE_ERR_TCTRL_CNT2_POS

#define IDLE_ERR_TCTRL_CNT2_POS 0U

◆ IIC_1_EN_DEV_REG1_ADDR

#define IIC_1_EN_DEV_REG1_ADDR 0x01U

◆ IIC_1_EN_DEV_REG1_MASK

#define IIC_1_EN_DEV_REG1_MASK 0x40U

◆ IIC_1_EN_DEV_REG1_POS

#define IIC_1_EN_DEV_REG1_POS 6U

◆ IIC_2_EN_DEV_REG1_ADDR

#define IIC_2_EN_DEV_REG1_ADDR 0x01U

◆ IIC_2_EN_DEV_REG1_MASK

#define IIC_2_EN_DEV_REG1_MASK 0x80U

◆ IIC_2_EN_DEV_REG1_POS

#define IIC_2_EN_DEV_REG1_POS 7U

◆ INDEPENDENT_VS_FRONTTOP_13_ADDR

#define INDEPENDENT_VS_FRONTTOP_13_ADDR (0x315U)

◆ INDEPENDENT_VS_FRONTTOP_13_MASK

#define INDEPENDENT_VS_FRONTTOP_13_MASK (0x80U)

◆ INJECT_EFUSE_CRC_ERR_FUNC_SAFE_CC_RTTN_ERR_ADDR

#define INJECT_EFUSE_CRC_ERR_FUNC_SAFE_CC_RTTN_ERR_ADDR 0x1D5FU

◆ INJECT_EFUSE_CRC_ERR_FUNC_SAFE_CC_RTTN_ERR_MASK

#define INJECT_EFUSE_CRC_ERR_FUNC_SAFE_CC_RTTN_ERR_MASK 0x02U

◆ INJECT_EFUSE_CRC_ERR_FUNC_SAFE_CC_RTTN_ERR_POS

#define INJECT_EFUSE_CRC_ERR_FUNC_SAFE_CC_RTTN_ERR_POS 1U

◆ INJECT_RTTN_CRC_ERR_FUNC_SAFE_CC_RTTN_ERR_ADDR

#define INJECT_RTTN_CRC_ERR_FUNC_SAFE_CC_RTTN_ERR_ADDR 0x1D5FU

◆ INJECT_RTTN_CRC_ERR_FUNC_SAFE_CC_RTTN_ERR_MASK

#define INJECT_RTTN_CRC_ERR_FUNC_SAFE_CC_RTTN_ERR_MASK 0x01U

◆ INJECT_RTTN_CRC_ERR_FUNC_SAFE_CC_RTTN_ERR_POS

#define INJECT_RTTN_CRC_ERR_FUNC_SAFE_CC_RTTN_ERR_POS 0U

◆ INMUX_EN_AFE_ADC_CTRL_2_ADDR

#define INMUX_EN_AFE_ADC_CTRL_2_ADDR 0x502U

◆ INMUX_EN_AFE_ADC_CTRL_2_MASK

#define INMUX_EN_AFE_ADC_CTRL_2_MASK 0x01U

◆ INMUX_EN_AFE_ADC_CTRL_2_POS

#define INMUX_EN_AFE_ADC_CTRL_2_POS 0U

◆ INVCODE_LN0_MIPI_RX_EXT_EXT8_ADDR

#define INVCODE_LN0_MIPI_RX_EXT_EXT8_ADDR 0x380U

◆ INVCODE_LN0_MIPI_RX_EXT_EXT8_MASK

#define INVCODE_LN0_MIPI_RX_EXT_EXT8_MASK 0x02U

◆ INVCODE_LN0_MIPI_RX_EXT_EXT8_POS

#define INVCODE_LN0_MIPI_RX_EXT_EXT8_POS 1U

◆ INVCODE_LN1_MIPI_RX_EXT_EXT8_ADDR

#define INVCODE_LN1_MIPI_RX_EXT_EXT8_ADDR 0x380U

◆ INVCODE_LN1_MIPI_RX_EXT_EXT8_MASK

#define INVCODE_LN1_MIPI_RX_EXT_EXT8_MASK 0x04U

◆ INVCODE_LN1_MIPI_RX_EXT_EXT8_POS

#define INVCODE_LN1_MIPI_RX_EXT_EXT8_POS 2U

◆ LDO_BYPASS_TCTRL_CTRL2_ADDR

#define LDO_BYPASS_TCTRL_CTRL2_ADDR 0x12U

◆ LDO_BYPASS_TCTRL_CTRL2_MASK

#define LDO_BYPASS_TCTRL_CTRL2_MASK 0x10U

◆ LDO_BYPASS_TCTRL_CTRL2_POS

#define LDO_BYPASS_TCTRL_CTRL2_POS 4U

◆ LF_0_DEV_REG26_ADDR

#define LF_0_DEV_REG26_ADDR 0x26U

◆ LF_0_DEV_REG26_MASK

#define LF_0_DEV_REG26_MASK 0x07U

◆ LF_0_DEV_REG26_POS

#define LF_0_DEV_REG26_POS 0U

◆ LF_1_DEV_REG26_ADDR

#define LF_1_DEV_REG26_ADDR 0x26U

◆ LF_1_DEV_REG26_MASK

#define LF_1_DEV_REG26_MASK 0x70U

◆ LF_1_DEV_REG26_POS

#define LF_1_DEV_REG26_POS 4U

◆ LFLT_INT_OEN_TCTRL_INTR2_ADDR

#define LFLT_INT_OEN_TCTRL_INTR2_ADDR 0x1AU

◆ LFLT_INT_OEN_TCTRL_INTR2_MASK

#define LFLT_INT_OEN_TCTRL_INTR2_MASK 0x08U

◆ LFLT_INT_OEN_TCTRL_INTR2_POS

#define LFLT_INT_OEN_TCTRL_INTR2_POS 3U

◆ LFLT_INT_TCTRL_INTR3_ADDR

#define LFLT_INT_TCTRL_INTR3_ADDR 0x1BU

◆ LFLT_INT_TCTRL_INTR3_MASK

#define LFLT_INT_TCTRL_INTR3_MASK 0x08U

◆ LFLT_INT_TCTRL_INTR3_POS

#define LFLT_INT_TCTRL_INTR3_POS 3U

◆ LIM_HEART_VID_TX_Z_VIDEO_TX2_ADDR

#define LIM_HEART_VID_TX_Z_VIDEO_TX2_ADDR 0x112U

◆ LIM_HEART_VID_TX_Z_VIDEO_TX2_MASK

#define LIM_HEART_VID_TX_Z_VIDEO_TX2_MASK 0x04U

◆ LIM_HEART_VID_TX_Z_VIDEO_TX2_POS

#define LIM_HEART_VID_TX_Z_VIDEO_TX2_POS 2U

◆ LINE_CRC_EN_VID_TX_Z_VIDEO_TX0_ADDR

#define LINE_CRC_EN_VID_TX_Z_VIDEO_TX0_ADDR 0x110U

◆ LINE_CRC_EN_VID_TX_Z_VIDEO_TX0_MASK

#define LINE_CRC_EN_VID_TX_Z_VIDEO_TX0_MASK 0x40U

◆ LINE_CRC_EN_VID_TX_Z_VIDEO_TX0_POS

#define LINE_CRC_EN_VID_TX_Z_VIDEO_TX0_POS 6U

◆ LINE_CRC_SEL_VID_TX_Z_VIDEO_TX0_ADDR

#define LINE_CRC_SEL_VID_TX_Z_VIDEO_TX0_ADDR 0x110U

◆ LINE_CRC_SEL_VID_TX_Z_VIDEO_TX0_MASK

#define LINE_CRC_SEL_VID_TX_Z_VIDEO_TX0_MASK 0x80U

◆ LINE_CRC_SEL_VID_TX_Z_VIDEO_TX0_POS

#define LINE_CRC_SEL_VID_TX_Z_VIDEO_TX0_POS 7U

◆ LINK_PRBS_CHK_GMSL_RX1_ADDR

#define LINK_PRBS_CHK_GMSL_RX1_ADDR 0x2DU

◆ LINK_PRBS_CHK_GMSL_RX1_MASK

#define LINK_PRBS_CHK_GMSL_RX1_MASK 0x80U

◆ LINK_PRBS_CHK_GMSL_RX1_POS

#define LINK_PRBS_CHK_GMSL_RX1_POS 7U

◆ LINK_PRBS_GEN_GMSL_TX1_ADDR

#define LINK_PRBS_GEN_GMSL_TX1_ADDR 0x29U

◆ LINK_PRBS_GEN_GMSL_TX1_MASK

#define LINK_PRBS_GEN_GMSL_TX1_MASK 0x80U

◆ LINK_PRBS_GEN_GMSL_TX1_POS

#define LINK_PRBS_GEN_GMSL_TX1_POS 7U

◆ LOC_MS_EN_CC_UART_0_ADDR

#define LOC_MS_EN_CC_UART_0_ADDR 0x48U

◆ LOC_MS_EN_CC_UART_0_MASK

#define LOC_MS_EN_CC_UART_0_MASK 0x10U

◆ LOC_MS_EN_CC_UART_0_POS

#define LOC_MS_EN_CC_UART_0_POS 4U

◆ LOCK_EN_DEV_REG5_ADDR

#define LOCK_EN_DEV_REG5_ADDR 0x05U

◆ LOCK_EN_DEV_REG5_MASK

#define LOCK_EN_DEV_REG5_MASK 0x80U

◆ LOCK_EN_DEV_REG5_POS

#define LOCK_EN_DEV_REG5_POS 7U

◆ LOCKED_TCTRL_CTRL3_ADDR

#define LOCKED_TCTRL_CTRL3_ADDR 0x13U

◆ LOCKED_TCTRL_CTRL3_MASK

#define LOCKED_TCTRL_CTRL3_MASK 0x08U

◆ LOCKED_TCTRL_CTRL3_POS

#define LOCKED_TCTRL_CTRL3_POS 3U

◆ MAX_RT_ERR_CFGL_GPIO_ARQ2_ADDR

#define MAX_RT_ERR_CFGL_GPIO_ARQ2_ADDR 0x97U

◆ MAX_RT_ERR_CFGL_GPIO_ARQ2_MASK

#define MAX_RT_ERR_CFGL_GPIO_ARQ2_MASK 0x80U

◆ MAX_RT_ERR_CFGL_GPIO_ARQ2_POS

#define MAX_RT_ERR_CFGL_GPIO_ARQ2_POS 7U

◆ MAX_RT_ERR_CFGL_IIC_X_ARQ2_ADDR

#define MAX_RT_ERR_CFGL_IIC_X_ARQ2_ADDR 0xA7U

◆ MAX_RT_ERR_CFGL_IIC_X_ARQ2_MASK

#define MAX_RT_ERR_CFGL_IIC_X_ARQ2_MASK 0x80U

◆ MAX_RT_ERR_CFGL_IIC_X_ARQ2_POS

#define MAX_RT_ERR_CFGL_IIC_X_ARQ2_POS 7U

◆ MAX_RT_ERR_CFGL_IIC_Y_ARQ2_ADDR

#define MAX_RT_ERR_CFGL_IIC_Y_ARQ2_ADDR 0xAFU

◆ MAX_RT_ERR_CFGL_IIC_Y_ARQ2_MASK

#define MAX_RT_ERR_CFGL_IIC_Y_ARQ2_MASK 0x80U

◆ MAX_RT_ERR_CFGL_IIC_Y_ARQ2_POS

#define MAX_RT_ERR_CFGL_IIC_Y_ARQ2_POS 7U

◆ MAX_RT_ERR_CFGL_SPI_ARQ2_ADDR

#define MAX_RT_ERR_CFGL_SPI_ARQ2_ADDR 0x87U

◆ MAX_RT_ERR_CFGL_SPI_ARQ2_MASK

#define MAX_RT_ERR_CFGL_SPI_ARQ2_MASK 0x80U

◆ MAX_RT_ERR_CFGL_SPI_ARQ2_POS

#define MAX_RT_ERR_CFGL_SPI_ARQ2_POS 7U

◆ MAX_RT_ERR_OEN_CFGL_GPIO_ARQ1_ADDR

#define MAX_RT_ERR_OEN_CFGL_GPIO_ARQ1_ADDR 0x96U

◆ MAX_RT_ERR_OEN_CFGL_GPIO_ARQ1_MASK

#define MAX_RT_ERR_OEN_CFGL_GPIO_ARQ1_MASK 0x02U

◆ MAX_RT_ERR_OEN_CFGL_GPIO_ARQ1_POS

#define MAX_RT_ERR_OEN_CFGL_GPIO_ARQ1_POS 1U

◆ MAX_RT_ERR_OEN_CFGL_IIC_X_ARQ1_ADDR

#define MAX_RT_ERR_OEN_CFGL_IIC_X_ARQ1_ADDR 0xA6U

◆ MAX_RT_ERR_OEN_CFGL_IIC_X_ARQ1_MASK

#define MAX_RT_ERR_OEN_CFGL_IIC_X_ARQ1_MASK 0x02U

◆ MAX_RT_ERR_OEN_CFGL_IIC_X_ARQ1_POS

#define MAX_RT_ERR_OEN_CFGL_IIC_X_ARQ1_POS 1U

◆ MAX_RT_ERR_OEN_CFGL_IIC_Y_ARQ1_ADDR

#define MAX_RT_ERR_OEN_CFGL_IIC_Y_ARQ1_ADDR 0xAEU

◆ MAX_RT_ERR_OEN_CFGL_IIC_Y_ARQ1_MASK

#define MAX_RT_ERR_OEN_CFGL_IIC_Y_ARQ1_MASK 0x02U

◆ MAX_RT_ERR_OEN_CFGL_IIC_Y_ARQ1_POS

#define MAX_RT_ERR_OEN_CFGL_IIC_Y_ARQ1_POS 1U

◆ MAX_RT_ERR_OEN_CFGL_SPI_ARQ1_ADDR

#define MAX_RT_ERR_OEN_CFGL_SPI_ARQ1_ADDR 0x86U

◆ MAX_RT_ERR_OEN_CFGL_SPI_ARQ1_MASK

#define MAX_RT_ERR_OEN_CFGL_SPI_ARQ1_MASK 0x02U

◆ MAX_RT_ERR_OEN_CFGL_SPI_ARQ1_POS

#define MAX_RT_ERR_OEN_CFGL_SPI_ARQ1_POS 1U

◆ MAX_RT_FLAG_TCTRL_INTR5_ADDR

#define MAX_RT_FLAG_TCTRL_INTR5_ADDR 0x1DU

◆ MAX_RT_FLAG_TCTRL_INTR5_MASK

#define MAX_RT_FLAG_TCTRL_INTR5_MASK 0x08U

◆ MAX_RT_FLAG_TCTRL_INTR5_POS

#define MAX_RT_FLAG_TCTRL_INTR5_POS 3U

◆ MAX_RT_OEN_TCTRL_INTR4_ADDR

#define MAX_RT_OEN_TCTRL_INTR4_ADDR 0x1CU

◆ MAX_RT_OEN_TCTRL_INTR4_MASK

#define MAX_RT_OEN_TCTRL_INTR4_MASK 0x08U

◆ MAX_RT_OEN_TCTRL_INTR4_POS

#define MAX_RT_OEN_TCTRL_INTR4_POS 3U

◆ MEM_DT1_SELZ_FRONTTOP_FRONTTOP_16_ADDR

#define MEM_DT1_SELZ_FRONTTOP_FRONTTOP_16_ADDR 0x318U

◆ MEM_DT1_SELZ_FRONTTOP_FRONTTOP_16_MASK

#define MEM_DT1_SELZ_FRONTTOP_FRONTTOP_16_MASK 0x7FU

◆ MEM_DT1_SELZ_FRONTTOP_FRONTTOP_16_POS

#define MEM_DT1_SELZ_FRONTTOP_FRONTTOP_16_POS 0U

◆ MEM_DT2_SELZ_FRONTTOP_FRONTTOP_17_ADDR

#define MEM_DT2_SELZ_FRONTTOP_FRONTTOP_17_ADDR 0x319U

◆ MEM_DT2_SELZ_FRONTTOP_FRONTTOP_17_MASK

#define MEM_DT2_SELZ_FRONTTOP_FRONTTOP_17_MASK 0x7FU

◆ MEM_DT2_SELZ_FRONTTOP_FRONTTOP_17_POS

#define MEM_DT2_SELZ_FRONTTOP_FRONTTOP_17_POS 0U

◆ MEM_DT3_SELZ_EN_FRONTTOP_EXT_FRONTTOP_EXT17_ADDR

#define MEM_DT3_SELZ_EN_FRONTTOP_EXT_FRONTTOP_EXT17_ADDR 0x3D1U

◆ MEM_DT3_SELZ_EN_FRONTTOP_EXT_FRONTTOP_EXT17_MASK

#define MEM_DT3_SELZ_EN_FRONTTOP_EXT_FRONTTOP_EXT17_MASK 0x01U

◆ MEM_DT3_SELZ_EN_FRONTTOP_EXT_FRONTTOP_EXT17_POS

#define MEM_DT3_SELZ_EN_FRONTTOP_EXT_FRONTTOP_EXT17_POS 0U

◆ MEM_DT3_SELZ_FRONTTOP_EXT_FRONTTOP_EXT8_ADDR

#define MEM_DT3_SELZ_FRONTTOP_EXT_FRONTTOP_EXT8_ADDR 0x3C8U

◆ MEM_DT3_SELZ_FRONTTOP_EXT_FRONTTOP_EXT8_MASK

#define MEM_DT3_SELZ_FRONTTOP_EXT_FRONTTOP_EXT8_MASK 0xFFU

◆ MEM_DT3_SELZ_FRONTTOP_EXT_FRONTTOP_EXT8_POS

#define MEM_DT3_SELZ_FRONTTOP_EXT_FRONTTOP_EXT8_POS 0U

◆ MEM_DT4_SELZ_EN_FRONTTOP_EXT_FRONTTOP_EXT17_ADDR

#define MEM_DT4_SELZ_EN_FRONTTOP_EXT_FRONTTOP_EXT17_ADDR 0x3D1U

◆ MEM_DT4_SELZ_EN_FRONTTOP_EXT_FRONTTOP_EXT17_MASK

#define MEM_DT4_SELZ_EN_FRONTTOP_EXT_FRONTTOP_EXT17_MASK 0x02U

◆ MEM_DT4_SELZ_EN_FRONTTOP_EXT_FRONTTOP_EXT17_POS

#define MEM_DT4_SELZ_EN_FRONTTOP_EXT_FRONTTOP_EXT17_POS 1U

◆ MEM_DT4_SELZ_FRONTTOP_EXT_FRONTTOP_EXT9_ADDR

#define MEM_DT4_SELZ_FRONTTOP_EXT_FRONTTOP_EXT9_ADDR 0x3C9U

◆ MEM_DT4_SELZ_FRONTTOP_EXT_FRONTTOP_EXT9_MASK

#define MEM_DT4_SELZ_FRONTTOP_EXT_FRONTTOP_EXT9_MASK 0xFFU

◆ MEM_DT4_SELZ_FRONTTOP_EXT_FRONTTOP_EXT9_POS

#define MEM_DT4_SELZ_FRONTTOP_EXT_FRONTTOP_EXT9_POS 0U

◆ MEM_DT5_SELZ_EN_FRONTTOP_EXT_FRONTTOP_EXT17_ADDR

#define MEM_DT5_SELZ_EN_FRONTTOP_EXT_FRONTTOP_EXT17_ADDR 0x3D1U

◆ MEM_DT5_SELZ_EN_FRONTTOP_EXT_FRONTTOP_EXT17_MASK

#define MEM_DT5_SELZ_EN_FRONTTOP_EXT_FRONTTOP_EXT17_MASK 0x04U

◆ MEM_DT5_SELZ_EN_FRONTTOP_EXT_FRONTTOP_EXT17_POS

#define MEM_DT5_SELZ_EN_FRONTTOP_EXT_FRONTTOP_EXT17_POS 2U

◆ MEM_DT5_SELZ_FRONTTOP_EXT_FRONTTOP_EXT10_ADDR

#define MEM_DT5_SELZ_FRONTTOP_EXT_FRONTTOP_EXT10_ADDR 0x3CAU

◆ MEM_DT5_SELZ_FRONTTOP_EXT_FRONTTOP_EXT10_MASK

#define MEM_DT5_SELZ_FRONTTOP_EXT_FRONTTOP_EXT10_MASK 0xFFU

◆ MEM_DT5_SELZ_FRONTTOP_EXT_FRONTTOP_EXT10_POS

#define MEM_DT5_SELZ_FRONTTOP_EXT_FRONTTOP_EXT10_POS 0U

◆ MEM_DT6_SELZ_EN_FRONTTOP_EXT_FRONTTOP_EXT17_ADDR

#define MEM_DT6_SELZ_EN_FRONTTOP_EXT_FRONTTOP_EXT17_ADDR 0x3D1U

◆ MEM_DT6_SELZ_EN_FRONTTOP_EXT_FRONTTOP_EXT17_MASK

#define MEM_DT6_SELZ_EN_FRONTTOP_EXT_FRONTTOP_EXT17_MASK 0x08U

◆ MEM_DT6_SELZ_EN_FRONTTOP_EXT_FRONTTOP_EXT17_POS

#define MEM_DT6_SELZ_EN_FRONTTOP_EXT_FRONTTOP_EXT17_POS 3U

◆ MEM_DT6_SELZ_FRONTTOP_EXT_FRONTTOP_EXT11_ADDR

#define MEM_DT6_SELZ_FRONTTOP_EXT_FRONTTOP_EXT11_ADDR 0x3CBU

◆ MEM_DT6_SELZ_FRONTTOP_EXT_FRONTTOP_EXT11_MASK

#define MEM_DT6_SELZ_FRONTTOP_EXT_FRONTTOP_EXT11_MASK 0xFFU

◆ MEM_DT6_SELZ_FRONTTOP_EXT_FRONTTOP_EXT11_POS

#define MEM_DT6_SELZ_FRONTTOP_EXT_FRONTTOP_EXT11_POS 0U

◆ MEM_DT7_SELZ_MIPI_RX_EXT2_EXTA_ADDR

#define MEM_DT7_SELZ_MIPI_RX_EXT2_EXTA_ADDR 0x3DCU

◆ MEM_DT7_SELZ_MIPI_RX_EXT2_EXTA_MASK

#define MEM_DT7_SELZ_MIPI_RX_EXT2_EXTA_MASK 0x7FU

◆ MEM_DT7_SELZ_MIPI_RX_EXT2_EXTA_POS

#define MEM_DT7_SELZ_MIPI_RX_EXT2_EXTA_POS 0U

◆ MEM_DT8_SELZ_MIPI_RX_EXT2_EXTB_ADDR

#define MEM_DT8_SELZ_MIPI_RX_EXT2_EXTB_ADDR 0x3DDU

◆ MEM_DT8_SELZ_MIPI_RX_EXT2_EXTB_MASK

#define MEM_DT8_SELZ_MIPI_RX_EXT2_EXTB_MASK 0x7FU

◆ MEM_DT8_SELZ_MIPI_RX_EXT2_EXTB_POS

#define MEM_DT8_SELZ_MIPI_RX_EXT2_EXTB_POS 0U

◆ MEM_ECC_ERR1_INT_FUNC_SAFE_FS_INTR1_ADDR

#define MEM_ECC_ERR1_INT_FUNC_SAFE_FS_INTR1_ADDR 0x1D13U

◆ MEM_ECC_ERR1_INT_FUNC_SAFE_FS_INTR1_MASK

#define MEM_ECC_ERR1_INT_FUNC_SAFE_FS_INTR1_MASK 0x10U

◆ MEM_ECC_ERR1_INT_FUNC_SAFE_FS_INTR1_POS

#define MEM_ECC_ERR1_INT_FUNC_SAFE_FS_INTR1_POS 4U

◆ MEM_ECC_ERR1_OEN_FUNC_SAFE_FS_INTR0_ADDR

#define MEM_ECC_ERR1_OEN_FUNC_SAFE_FS_INTR0_ADDR 0x1D12U

◆ MEM_ECC_ERR1_OEN_FUNC_SAFE_FS_INTR0_MASK

#define MEM_ECC_ERR1_OEN_FUNC_SAFE_FS_INTR0_MASK 0x10U

◆ MEM_ECC_ERR1_OEN_FUNC_SAFE_FS_INTR0_POS

#define MEM_ECC_ERR1_OEN_FUNC_SAFE_FS_INTR0_POS 4U

◆ MEM_ECC_ERR2_INT_FUNC_SAFE_FS_INTR1_ADDR

#define MEM_ECC_ERR2_INT_FUNC_SAFE_FS_INTR1_ADDR 0x1D13U

◆ MEM_ECC_ERR2_INT_FUNC_SAFE_FS_INTR1_MASK

#define MEM_ECC_ERR2_INT_FUNC_SAFE_FS_INTR1_MASK 0x20U

◆ MEM_ECC_ERR2_INT_FUNC_SAFE_FS_INTR1_POS

#define MEM_ECC_ERR2_INT_FUNC_SAFE_FS_INTR1_POS 5U

◆ MEM_ECC_ERR2_OEN_FUNC_SAFE_FS_INTR0_ADDR

#define MEM_ECC_ERR2_OEN_FUNC_SAFE_FS_INTR0_ADDR 0x1D12U

◆ MEM_ECC_ERR2_OEN_FUNC_SAFE_FS_INTR0_MASK

#define MEM_ECC_ERR2_OEN_FUNC_SAFE_FS_INTR0_MASK 0x20U

◆ MEM_ECC_ERR2_OEN_FUNC_SAFE_FS_INTR0_POS

#define MEM_ECC_ERR2_OEN_FUNC_SAFE_FS_INTR0_POS 5U

◆ MIPI_ERR_FLAG_TCTRL_INTR7_ADDR

#define MIPI_ERR_FLAG_TCTRL_INTR7_ADDR 0x1FU

◆ MIPI_ERR_FLAG_TCTRL_INTR7_MASK

#define MIPI_ERR_FLAG_TCTRL_INTR7_MASK 0x01U

◆ MIPI_ERR_FLAG_TCTRL_INTR7_POS

#define MIPI_ERR_FLAG_TCTRL_INTR7_POS 0U

◆ MIPI_ERR_OEN_TCTRL_INTR6_ADDR

#define MIPI_ERR_OEN_TCTRL_INTR6_ADDR 0x1EU

◆ MIPI_ERR_OEN_TCTRL_INTR6_MASK

#define MIPI_ERR_OEN_TCTRL_INTR6_MASK 0x01U

◆ MIPI_ERR_OEN_TCTRL_INTR6_POS

#define MIPI_ERR_OEN_TCTRL_INTR6_POS 0U

◆ MIPI_NONCONTCLK_EN_MIPI_RX_MIPI_RX0_ADDR

#define MIPI_NONCONTCLK_EN_MIPI_RX_MIPI_RX0_ADDR 0x330U

◆ MIPI_NONCONTCLK_EN_MIPI_RX_MIPI_RX0_MASK

#define MIPI_NONCONTCLK_EN_MIPI_RX_MIPI_RX0_MASK 0x40U

◆ MIPI_NONCONTCLK_EN_MIPI_RX_MIPI_RX0_POS

#define MIPI_NONCONTCLK_EN_MIPI_RX_MIPI_RX0_POS 6U

◆ MIPI_RX_EXT2_EXTA_ADDR

#define MIPI_RX_EXT2_EXTA_ADDR 0x3DCU

◆ MIPI_RX_EXT2_EXTA_DEFAULT

#define MIPI_RX_EXT2_EXTA_DEFAULT 0x00U

◆ MIPI_RX_EXT2_EXTB_ADDR

#define MIPI_RX_EXT2_EXTB_ADDR 0x3DDU

◆ MIPI_RX_EXT2_EXTB_DEFAULT

#define MIPI_RX_EXT2_EXTB_DEFAULT 0x00U

◆ MIPI_RX_EXT3_EXT4_ADDR

#define MIPI_RX_EXT3_EXT4_ADDR 0x584U

◆ MIPI_RX_EXT3_EXT4_DEFAULT

#define MIPI_RX_EXT3_EXT4_DEFAULT 0x00U

◆ MIPI_RX_EXT3_EXT5_ADDR

#define MIPI_RX_EXT3_EXT5_ADDR 0x585U

◆ MIPI_RX_EXT3_EXT5_DEFAULT

#define MIPI_RX_EXT3_EXT5_DEFAULT 0x00U

◆ MIPI_RX_EXT3_EXT6_ADDR

#define MIPI_RX_EXT3_EXT6_ADDR 0x586U

◆ MIPI_RX_EXT3_EXT6_DEFAULT

#define MIPI_RX_EXT3_EXT6_DEFAULT 0x00U

◆ MIPI_RX_EXT3_EXT7_ADDR

#define MIPI_RX_EXT3_EXT7_ADDR 0x587U

◆ MIPI_RX_EXT3_EXT7_DEFAULT

#define MIPI_RX_EXT3_EXT7_DEFAULT 0x00U

◆ MIPI_RX_EXT3_EXT8_ADDR

#define MIPI_RX_EXT3_EXT8_ADDR 0x588U

◆ MIPI_RX_EXT3_EXT8_DEFAULT

#define MIPI_RX_EXT3_EXT8_DEFAULT 0x00U

◆ MIPI_RX_EXT_EXT00_ADDR

#define MIPI_RX_EXT_EXT00_ADDR 0x377U

◆ MIPI_RX_EXT_EXT00_DEFAULT

#define MIPI_RX_EXT_EXT00_DEFAULT 0x00U

◆ MIPI_RX_EXT_EXT0_ADDR

#define MIPI_RX_EXT_EXT0_ADDR 0x378U

◆ MIPI_RX_EXT_EXT0_DEFAULT

#define MIPI_RX_EXT_EXT0_DEFAULT 0x00U

◆ MIPI_RX_EXT_EXT11_ADDR

#define MIPI_RX_EXT_EXT11_ADDR 0x383U

◆ MIPI_RX_EXT_EXT11_DEFAULT

#define MIPI_RX_EXT_EXT11_DEFAULT 0x80U

◆ MIPI_RX_EXT_EXT1_ADDR

#define MIPI_RX_EXT_EXT1_ADDR 0x379U

◆ MIPI_RX_EXT_EXT1_DEFAULT

#define MIPI_RX_EXT_EXT1_DEFAULT 0x00U

◆ MIPI_RX_EXT_EXT21_ADDR

#define MIPI_RX_EXT_EXT21_ADDR 0x38DU

◆ MIPI_RX_EXT_EXT21_DEFAULT

#define MIPI_RX_EXT_EXT21_DEFAULT 0x00U

◆ MIPI_RX_EXT_EXT22_ADDR

#define MIPI_RX_EXT_EXT22_ADDR 0x38EU

◆ MIPI_RX_EXT_EXT22_DEFAULT

#define MIPI_RX_EXT_EXT22_DEFAULT 0x00U

◆ MIPI_RX_EXT_EXT23_ADDR

#define MIPI_RX_EXT_EXT23_ADDR 0x38FU

◆ MIPI_RX_EXT_EXT23_DEFAULT

#define MIPI_RX_EXT_EXT23_DEFAULT 0x00U

◆ MIPI_RX_EXT_EXT24_ADDR

#define MIPI_RX_EXT_EXT24_ADDR 0x390U

◆ MIPI_RX_EXT_EXT24_DEFAULT

#define MIPI_RX_EXT_EXT24_DEFAULT 0x00U

◆ MIPI_RX_EXT_EXT2_ADDR

#define MIPI_RX_EXT_EXT2_ADDR 0x37AU

◆ MIPI_RX_EXT_EXT2_DEFAULT

#define MIPI_RX_EXT_EXT2_DEFAULT 0x00U

◆ MIPI_RX_EXT_EXT3_ADDR

#define MIPI_RX_EXT_EXT3_ADDR 0x37BU

◆ MIPI_RX_EXT_EXT3_DEFAULT

#define MIPI_RX_EXT_EXT3_DEFAULT 0x00U

◆ MIPI_RX_EXT_EXT4_ADDR

#define MIPI_RX_EXT_EXT4_ADDR 0x37CU

◆ MIPI_RX_EXT_EXT4_DEFAULT

#define MIPI_RX_EXT_EXT4_DEFAULT 0x00U

◆ MIPI_RX_EXT_EXT5_ADDR

#define MIPI_RX_EXT_EXT5_ADDR 0x37DU

◆ MIPI_RX_EXT_EXT5_DEFAULT

#define MIPI_RX_EXT_EXT5_DEFAULT 0x00U

◆ MIPI_RX_EXT_EXT6_ADDR

#define MIPI_RX_EXT_EXT6_ADDR 0x37EU

◆ MIPI_RX_EXT_EXT6_DEFAULT

#define MIPI_RX_EXT_EXT6_DEFAULT 0x00U

◆ MIPI_RX_EXT_EXT7_ADDR

#define MIPI_RX_EXT_EXT7_ADDR 0x37FU

◆ MIPI_RX_EXT_EXT7_DEFAULT

#define MIPI_RX_EXT_EXT7_DEFAULT 0x00U

◆ MIPI_RX_EXT_EXT8_ADDR

#define MIPI_RX_EXT_EXT8_ADDR 0x380U

◆ MIPI_RX_EXT_EXT8_DEFAULT

#define MIPI_RX_EXT_EXT8_DEFAULT 0x00U

◆ MIPI_RX_EXT_EXT9_ADDR

#define MIPI_RX_EXT_EXT9_ADDR 0x381U

◆ MIPI_RX_EXT_EXT9_DEFAULT

#define MIPI_RX_EXT_EXT9_DEFAULT 0x00U

◆ MIPI_RX_MIPI_RX0_ADDR

#define MIPI_RX_MIPI_RX0_ADDR 0x330U

◆ MIPI_RX_MIPI_RX0_DEFAULT

#define MIPI_RX_MIPI_RX0_DEFAULT 0x00U

◆ MIPI_RX_MIPI_RX11_ADDR

#define MIPI_RX_MIPI_RX11_ADDR 0x33BU

◆ MIPI_RX_MIPI_RX11_DEFAULT

#define MIPI_RX_MIPI_RX11_DEFAULT 0x00U

◆ MIPI_RX_MIPI_RX12_ADDR

#define MIPI_RX_MIPI_RX12_ADDR 0x33CU

◆ MIPI_RX_MIPI_RX12_DEFAULT

#define MIPI_RX_MIPI_RX12_DEFAULT 0x00U

◆ MIPI_RX_MIPI_RX13_ADDR

#define MIPI_RX_MIPI_RX13_ADDR 0x33DU

◆ MIPI_RX_MIPI_RX13_DEFAULT

#define MIPI_RX_MIPI_RX13_DEFAULT 0x00U

◆ MIPI_RX_MIPI_RX14_ADDR

#define MIPI_RX_MIPI_RX14_ADDR 0x33EU

◆ MIPI_RX_MIPI_RX14_DEFAULT

#define MIPI_RX_MIPI_RX14_DEFAULT 0x00U

◆ MIPI_RX_MIPI_RX19_ADDR

#define MIPI_RX_MIPI_RX19_ADDR 0x343U

◆ MIPI_RX_MIPI_RX19_DEFAULT

#define MIPI_RX_MIPI_RX19_DEFAULT 0x00U

◆ MIPI_RX_MIPI_RX1_ADDR

#define MIPI_RX_MIPI_RX1_ADDR 0x331U

◆ MIPI_RX_MIPI_RX1_DEFAULT

#define MIPI_RX_MIPI_RX1_DEFAULT 0x30U

◆ MIPI_RX_MIPI_RX20_ADDR

#define MIPI_RX_MIPI_RX20_ADDR 0x344U

◆ MIPI_RX_MIPI_RX20_DEFAULT

#define MIPI_RX_MIPI_RX20_DEFAULT 0x00U

◆ MIPI_RX_MIPI_RX21_ADDR

#define MIPI_RX_MIPI_RX21_ADDR 0x345U

◆ MIPI_RX_MIPI_RX21_DEFAULT

#define MIPI_RX_MIPI_RX21_DEFAULT 0x00U

◆ MIPI_RX_MIPI_RX22_ADDR

#define MIPI_RX_MIPI_RX22_ADDR 0x346U

◆ MIPI_RX_MIPI_RX22_DEFAULT

#define MIPI_RX_MIPI_RX22_DEFAULT 0x00U

◆ MIPI_RX_MIPI_RX23_ADDR

#define MIPI_RX_MIPI_RX23_ADDR 0x347U

◆ MIPI_RX_MIPI_RX23_DEFAULT

#define MIPI_RX_MIPI_RX23_DEFAULT 0x00U

◆ MIPI_RX_MIPI_RX2_ADDR

#define MIPI_RX_MIPI_RX2_ADDR 0x332U

◆ MIPI_RX_MIPI_RX2_DEFAULT

#define MIPI_RX_MIPI_RX2_DEFAULT 0xE0U

◆ MIPI_RX_MIPI_RX3_ADDR

#define MIPI_RX_MIPI_RX3_ADDR 0x333U

◆ MIPI_RX_MIPI_RX3_DEFAULT

#define MIPI_RX_MIPI_RX3_DEFAULT 0x04U

◆ MIPI_RX_MIPI_RX4_ADDR

#define MIPI_RX_MIPI_RX4_ADDR 0x334U

◆ MIPI_RX_MIPI_RX4_DEFAULT

#define MIPI_RX_MIPI_RX4_DEFAULT 0x00U

◆ MIPI_RX_MIPI_RX5_ADDR

#define MIPI_RX_MIPI_RX5_ADDR 0x335U

◆ MIPI_RX_MIPI_RX5_DEFAULT

#define MIPI_RX_MIPI_RX5_DEFAULT 0x00U

◆ MIPI_RX_MIPI_RX60_ADDR

#define MIPI_RX_MIPI_RX60_ADDR 0x36CU

◆ MIPI_RX_MIPI_RX60_DEFAULT

#define MIPI_RX_MIPI_RX60_DEFAULT 0x00U

◆ MIPI_RX_MIPI_RX61_ADDR

#define MIPI_RX_MIPI_RX61_ADDR 0x36DU

◆ MIPI_RX_MIPI_RX61_DEFAULT

#define MIPI_RX_MIPI_RX61_DEFAULT 0x00U

◆ MIPI_RX_MIPI_RX62_ADDR

#define MIPI_RX_MIPI_RX62_ADDR 0x36EU

◆ MIPI_RX_MIPI_RX62_DEFAULT

#define MIPI_RX_MIPI_RX62_DEFAULT 0x00U

◆ MIPI_RX_MIPI_RX63_ADDR

#define MIPI_RX_MIPI_RX63_ADDR 0x36FU

◆ MIPI_RX_MIPI_RX63_DEFAULT

#define MIPI_RX_MIPI_RX63_DEFAULT 0x00U

◆ MIPI_RX_MIPI_RX7_ADDR

#define MIPI_RX_MIPI_RX7_ADDR 0x337U

◆ MIPI_RX_MIPI_RX7_DEFAULT

#define MIPI_RX_MIPI_RX7_DEFAULT 0x00U

◆ MIPI_RX_MIPI_RX8_ADDR

#define MIPI_RX_MIPI_RX8_ADDR 0x338U

◆ MIPI_RX_MIPI_RX8_DEFAULT

#define MIPI_RX_MIPI_RX8_DEFAULT 0x55U

◆ MIPI_RX_RESET_MIPI_RX_MIPI_RX0_ADDR

#define MIPI_RX_RESET_MIPI_RX_MIPI_RX0_ADDR 0x330U

◆ MIPI_RX_RESET_MIPI_RX_MIPI_RX0_MASK

#define MIPI_RX_RESET_MIPI_RX_MIPI_RX0_MASK 0x08U

◆ MIPI_RX_RESET_MIPI_RX_MIPI_RX0_POS

#define MIPI_RX_RESET_MIPI_RX_MIPI_RX0_POS 3U

◆ MISC_HS_VS_Z_ADDR

#define MISC_HS_VS_Z_ADDR 0x55FU

◆ MISC_HS_VS_Z_DEFAULT

#define MISC_HS_VS_Z_DEFAULT 0x00U

◆ MISC_I2C_PT_10_ADDR

#define MISC_I2C_PT_10_ADDR 0x556U

◆ MISC_I2C_PT_10_DEFAULT

#define MISC_I2C_PT_10_DEFAULT 0x00U

◆ MISC_I2C_PT_11_ADDR

#define MISC_I2C_PT_11_ADDR 0x557U

◆ MISC_I2C_PT_11_DEFAULT

#define MISC_I2C_PT_11_DEFAULT 0x00U

◆ MISC_I2C_PT_4_ADDR

#define MISC_I2C_PT_4_ADDR 0x550U

◆ MISC_I2C_PT_4_DEFAULT

#define MISC_I2C_PT_4_DEFAULT 0x00U

◆ MISC_I2C_PT_5_ADDR

#define MISC_I2C_PT_5_ADDR 0x551U

◆ MISC_I2C_PT_5_DEFAULT

#define MISC_I2C_PT_5_DEFAULT 0x00U

◆ MISC_I2C_PT_6_ADDR

#define MISC_I2C_PT_6_ADDR 0x552U

◆ MISC_I2C_PT_6_DEFAULT

#define MISC_I2C_PT_6_DEFAULT 0x00U

◆ MISC_I2C_PT_7_ADDR

#define MISC_I2C_PT_7_ADDR 0x553U

◆ MISC_I2C_PT_7_DEFAULT

#define MISC_I2C_PT_7_DEFAULT 0x00U

◆ MISC_I2C_PT_8_ADDR

#define MISC_I2C_PT_8_ADDR 0x554U

◆ MISC_I2C_PT_8_DEFAULT

#define MISC_I2C_PT_8_DEFAULT 0x00U

◆ MISC_I2C_PT_9_ADDR

#define MISC_I2C_PT_9_ADDR 0x555U

◆ MISC_I2C_PT_9_DEFAULT

#define MISC_I2C_PT_9_DEFAULT 0x00U

◆ MISC_PIO_SLEW_0_ADDR

#define MISC_PIO_SLEW_0_ADDR 0x56FU

◆ MISC_PIO_SLEW_0_DEFAULT

#define MISC_PIO_SLEW_0_DEFAULT 0x3EU

◆ MISC_PIO_SLEW_1_ADDR

#define MISC_PIO_SLEW_1_ADDR 0x570U

◆ MISC_PIO_SLEW_1_DEFAULT

#define MISC_PIO_SLEW_1_DEFAULT 0x3CU

◆ MISC_PIO_SLEW_2_ADDR

#define MISC_PIO_SLEW_2_ADDR 0x571U

◆ MISC_PIO_SLEW_2_DEFAULT

#define MISC_PIO_SLEW_2_DEFAULT 0xFCU

◆ MISC_UART_PT_0_ADDR

#define MISC_UART_PT_0_ADDR 0x548U

◆ MISC_UART_PT_0_DEFAULT

#define MISC_UART_PT_0_DEFAULT 0xDCU

◆ MISC_UART_PT_1_ADDR

#define MISC_UART_PT_1_ADDR 0x549U

◆ MISC_UART_PT_1_DEFAULT

#define MISC_UART_PT_1_DEFAULT 0x05U

◆ MISC_UART_PT_2_ADDR

#define MISC_UART_PT_2_ADDR 0x54AU

◆ MISC_UART_PT_2_DEFAULT

#define MISC_UART_PT_2_DEFAULT 0xDCU

◆ MISC_UART_PT_3_ADDR

#define MISC_UART_PT_3_ADDR 0x54BU

◆ MISC_UART_PT_3_DEFAULT

#define MISC_UART_PT_3_DEFAULT 0x05U

◆ MISC_UNLOCK_KEY_ADDR

#define MISC_UNLOCK_KEY_ADDR 0x56EU

◆ MISC_UNLOCK_KEY_DEFAULT

#define MISC_UNLOCK_KEY_DEFAULT 0xBBU

◆ MSGCNTR_LSB_FUNC_SAFE_I2C_UART_CRC3_ADDR

#define MSGCNTR_LSB_FUNC_SAFE_I2C_UART_CRC3_ADDR 0x1D0BU

◆ MSGCNTR_LSB_FUNC_SAFE_I2C_UART_CRC3_MASK

#define MSGCNTR_LSB_FUNC_SAFE_I2C_UART_CRC3_MASK 0xFFU

◆ MSGCNTR_LSB_FUNC_SAFE_I2C_UART_CRC3_POS

#define MSGCNTR_LSB_FUNC_SAFE_I2C_UART_CRC3_POS 0U

◆ MSGCNTR_MSB_FUNC_SAFE_I2C_UART_CRC4_ADDR

#define MSGCNTR_MSB_FUNC_SAFE_I2C_UART_CRC4_ADDR 0x1D0CU

◆ MSGCNTR_MSB_FUNC_SAFE_I2C_UART_CRC4_MASK

#define MSGCNTR_MSB_FUNC_SAFE_I2C_UART_CRC4_MASK 0xFFU

◆ MSGCNTR_MSB_FUNC_SAFE_I2C_UART_CRC4_POS

#define MSGCNTR_MSB_FUNC_SAFE_I2C_UART_CRC4_POS 0U

◆ MST_BT_CC_I2C_1_ADDR

#define MST_BT_CC_I2C_1_ADDR 0x41U

◆ MST_BT_CC_I2C_1_MASK

#define MST_BT_CC_I2C_1_MASK 0x70U

◆ MST_BT_CC_I2C_1_POS

#define MST_BT_CC_I2C_1_POS 4U

◆ MST_BT_PT_CC_I2C_PT_1_ADDR

#define MST_BT_PT_CC_I2C_PT_1_ADDR 0x4DU

◆ MST_BT_PT_CC_I2C_PT_1_MASK

#define MST_BT_PT_CC_I2C_PT_1_MASK 0x70U

◆ MST_BT_PT_CC_I2C_PT_1_POS

#define MST_BT_PT_CC_I2C_PT_1_POS 4U

◆ MST_SLVN_SPI_SPI_0_ADDR

#define MST_SLVN_SPI_SPI_0_ADDR 0x170U

◆ MST_SLVN_SPI_SPI_0_MASK

#define MST_SLVN_SPI_SPI_0_MASK 0x02U

◆ MST_SLVN_SPI_SPI_0_POS

#define MST_SLVN_SPI_SPI_0_POS 1U

◆ MST_TO_CC_I2C_1_ADDR

#define MST_TO_CC_I2C_1_ADDR 0x41U

◆ MST_TO_CC_I2C_1_MASK

#define MST_TO_CC_I2C_1_MASK 0x07U

◆ MST_TO_CC_I2C_1_POS

#define MST_TO_CC_I2C_1_POS 0U

◆ MST_TO_PT_CC_I2C_PT_1_ADDR

#define MST_TO_PT_CC_I2C_PT_1_ADDR 0x4DU

◆ MST_TO_PT_CC_I2C_PT_1_MASK

#define MST_TO_PT_CC_I2C_PT_1_MASK 0x07U

◆ MST_TO_PT_CC_I2C_PT_1_POS

#define MST_TO_PT_CC_I2C_PT_1_POS 0U

◆ MUXV_CTRL_FUNC_SAFE_REGADCBIST9_ADDR

#define MUXV_CTRL_FUNC_SAFE_REGADCBIST9_ADDR 0x1D37U

◆ MUXV_CTRL_FUNC_SAFE_REGADCBIST9_MASK

#define MUXV_CTRL_FUNC_SAFE_REGADCBIST9_MASK 0xFFU

◆ MUXV_CTRL_FUNC_SAFE_REGADCBIST9_POS

#define MUXV_CTRL_FUNC_SAFE_REGADCBIST9_POS 0U

◆ MUXVER_EN_FUNC_SAFE_REGADCBIST0_ADDR

#define MUXVER_EN_FUNC_SAFE_REGADCBIST0_ADDR 0x1D28U

◆ MUXVER_EN_FUNC_SAFE_REGADCBIST0_MASK

#define MUXVER_EN_FUNC_SAFE_REGADCBIST0_MASK 0x10U

◆ MUXVER_EN_FUNC_SAFE_REGADCBIST0_POS

#define MUXVER_EN_FUNC_SAFE_REGADCBIST0_POS 4U

◆ OSNMODE_RLMS_A_RLMS32_ADDR

#define OSNMODE_RLMS_A_RLMS32_ADDR 0x1432U

◆ OSNMODE_RLMS_A_RLMS32_MASK

#define OSNMODE_RLMS_A_RLMS32_MASK 0x80U

◆ OSNMODE_RLMS_A_RLMS32_POS

#define OSNMODE_RLMS_A_RLMS32_POS 7U

◆ OUT_TYPE_GPIO0_0_GPIO_B_ADDR

#define OUT_TYPE_GPIO0_0_GPIO_B_ADDR 0x2BFU

◆ OUT_TYPE_GPIO0_0_GPIO_B_MASK

#define OUT_TYPE_GPIO0_0_GPIO_B_MASK 0x20U

◆ OUT_TYPE_GPIO0_0_GPIO_B_POS

#define OUT_TYPE_GPIO0_0_GPIO_B_POS 5U

◆ OUT_TYPE_GPIO10_10_GPIO_B_ADDR

#define OUT_TYPE_GPIO10_10_GPIO_B_ADDR 0x2DDU

◆ OUT_TYPE_GPIO10_10_GPIO_B_MASK

#define OUT_TYPE_GPIO10_10_GPIO_B_MASK 0x20U

◆ OUT_TYPE_GPIO10_10_GPIO_B_POS

#define OUT_TYPE_GPIO10_10_GPIO_B_POS 5U

◆ OUT_TYPE_GPIO1_1_GPIO_B_ADDR

#define OUT_TYPE_GPIO1_1_GPIO_B_ADDR 0x2C2U

◆ OUT_TYPE_GPIO1_1_GPIO_B_MASK

#define OUT_TYPE_GPIO1_1_GPIO_B_MASK 0x20U

◆ OUT_TYPE_GPIO1_1_GPIO_B_POS

#define OUT_TYPE_GPIO1_1_GPIO_B_POS 5U

◆ OUT_TYPE_GPIO2_2_GPIO_B_ADDR

#define OUT_TYPE_GPIO2_2_GPIO_B_ADDR 0x2C5U

◆ OUT_TYPE_GPIO2_2_GPIO_B_MASK

#define OUT_TYPE_GPIO2_2_GPIO_B_MASK 0x20U

◆ OUT_TYPE_GPIO2_2_GPIO_B_POS

#define OUT_TYPE_GPIO2_2_GPIO_B_POS 5U

◆ OUT_TYPE_GPIO3_3_GPIO_B_ADDR

#define OUT_TYPE_GPIO3_3_GPIO_B_ADDR 0x2C8U

◆ OUT_TYPE_GPIO3_3_GPIO_B_MASK

#define OUT_TYPE_GPIO3_3_GPIO_B_MASK 0x20U

◆ OUT_TYPE_GPIO3_3_GPIO_B_POS

#define OUT_TYPE_GPIO3_3_GPIO_B_POS 5U

◆ OUT_TYPE_GPIO4_4_GPIO_B_ADDR

#define OUT_TYPE_GPIO4_4_GPIO_B_ADDR 0x2CBU

◆ OUT_TYPE_GPIO4_4_GPIO_B_MASK

#define OUT_TYPE_GPIO4_4_GPIO_B_MASK 0x20U

◆ OUT_TYPE_GPIO4_4_GPIO_B_POS

#define OUT_TYPE_GPIO4_4_GPIO_B_POS 5U

◆ OUT_TYPE_GPIO5_5_GPIO_B_ADDR

#define OUT_TYPE_GPIO5_5_GPIO_B_ADDR 0x2CEU

◆ OUT_TYPE_GPIO5_5_GPIO_B_MASK

#define OUT_TYPE_GPIO5_5_GPIO_B_MASK 0x20U

◆ OUT_TYPE_GPIO5_5_GPIO_B_POS

#define OUT_TYPE_GPIO5_5_GPIO_B_POS 5U

◆ OUT_TYPE_GPIO6_6_GPIO_B_ADDR

#define OUT_TYPE_GPIO6_6_GPIO_B_ADDR 0x2D1U

◆ OUT_TYPE_GPIO6_6_GPIO_B_MASK

#define OUT_TYPE_GPIO6_6_GPIO_B_MASK 0x20U

◆ OUT_TYPE_GPIO6_6_GPIO_B_POS

#define OUT_TYPE_GPIO6_6_GPIO_B_POS 5U

◆ OUT_TYPE_GPIO7_7_GPIO_B_ADDR

#define OUT_TYPE_GPIO7_7_GPIO_B_ADDR 0x2D4U

◆ OUT_TYPE_GPIO7_7_GPIO_B_MASK

#define OUT_TYPE_GPIO7_7_GPIO_B_MASK 0x20U

◆ OUT_TYPE_GPIO7_7_GPIO_B_POS

#define OUT_TYPE_GPIO7_7_GPIO_B_POS 5U

◆ OUT_TYPE_GPIO8_8_GPIO_B_ADDR

#define OUT_TYPE_GPIO8_8_GPIO_B_ADDR 0x2D7U

◆ OUT_TYPE_GPIO8_8_GPIO_B_MASK

#define OUT_TYPE_GPIO8_8_GPIO_B_MASK 0x20U

◆ OUT_TYPE_GPIO8_8_GPIO_B_POS

#define OUT_TYPE_GPIO8_8_GPIO_B_POS 5U

◆ OUT_TYPE_GPIO9_9_GPIO_B_ADDR

#define OUT_TYPE_GPIO9_9_GPIO_B_ADDR 0x2DAU

◆ OUT_TYPE_GPIO9_9_GPIO_B_MASK

#define OUT_TYPE_GPIO9_9_GPIO_B_MASK 0x20U

◆ OUT_TYPE_GPIO9_9_GPIO_B_POS

#define OUT_TYPE_GPIO9_9_GPIO_B_POS 5U

◆ OVERFLOW_VID_TX_Z_VIDEO_TX2_ADDR

#define OVERFLOW_VID_TX_Z_VIDEO_TX2_ADDR 0x112U

◆ OVERFLOW_VID_TX_Z_VIDEO_TX2_MASK

#define OVERFLOW_VID_TX_Z_VIDEO_TX2_MASK 0x20U

◆ OVERFLOW_VID_TX_Z_VIDEO_TX2_POS

#define OVERFLOW_VID_TX_Z_VIDEO_TX2_POS 5U

◆ OVR_RES_CFG_GPIO0_0_GPIO_C_ADDR

#define OVR_RES_CFG_GPIO0_0_GPIO_C_ADDR 0x2C0U

◆ OVR_RES_CFG_GPIO0_0_GPIO_C_MASK

#define OVR_RES_CFG_GPIO0_0_GPIO_C_MASK 0x80U

◆ OVR_RES_CFG_GPIO0_0_GPIO_C_POS

#define OVR_RES_CFG_GPIO0_0_GPIO_C_POS 7U

◆ OVR_RES_CFG_GPIO10_10_GPIO_C_ADDR

#define OVR_RES_CFG_GPIO10_10_GPIO_C_ADDR 0x2DEU

◆ OVR_RES_CFG_GPIO10_10_GPIO_C_MASK

#define OVR_RES_CFG_GPIO10_10_GPIO_C_MASK 0x80U

◆ OVR_RES_CFG_GPIO10_10_GPIO_C_POS

#define OVR_RES_CFG_GPIO10_10_GPIO_C_POS 7U

◆ OVR_RES_CFG_GPIO1_1_GPIO_C_ADDR

#define OVR_RES_CFG_GPIO1_1_GPIO_C_ADDR 0x2C3U

◆ OVR_RES_CFG_GPIO1_1_GPIO_C_MASK

#define OVR_RES_CFG_GPIO1_1_GPIO_C_MASK 0x80U

◆ OVR_RES_CFG_GPIO1_1_GPIO_C_POS

#define OVR_RES_CFG_GPIO1_1_GPIO_C_POS 7U

◆ OVR_RES_CFG_GPIO2_2_GPIO_C_ADDR

#define OVR_RES_CFG_GPIO2_2_GPIO_C_ADDR 0x2C6U

◆ OVR_RES_CFG_GPIO2_2_GPIO_C_MASK

#define OVR_RES_CFG_GPIO2_2_GPIO_C_MASK 0x80U

◆ OVR_RES_CFG_GPIO2_2_GPIO_C_POS

#define OVR_RES_CFG_GPIO2_2_GPIO_C_POS 7U

◆ OVR_RES_CFG_GPIO3_3_GPIO_C_ADDR

#define OVR_RES_CFG_GPIO3_3_GPIO_C_ADDR 0x2C9U

◆ OVR_RES_CFG_GPIO3_3_GPIO_C_MASK

#define OVR_RES_CFG_GPIO3_3_GPIO_C_MASK 0x80U

◆ OVR_RES_CFG_GPIO3_3_GPIO_C_POS

#define OVR_RES_CFG_GPIO3_3_GPIO_C_POS 7U

◆ OVR_RES_CFG_GPIO4_4_GPIO_C_ADDR

#define OVR_RES_CFG_GPIO4_4_GPIO_C_ADDR 0x2CCU

◆ OVR_RES_CFG_GPIO4_4_GPIO_C_MASK

#define OVR_RES_CFG_GPIO4_4_GPIO_C_MASK 0x80U

◆ OVR_RES_CFG_GPIO4_4_GPIO_C_POS

#define OVR_RES_CFG_GPIO4_4_GPIO_C_POS 7U

◆ OVR_RES_CFG_GPIO5_5_GPIO_C_ADDR

#define OVR_RES_CFG_GPIO5_5_GPIO_C_ADDR 0x2CFU

◆ OVR_RES_CFG_GPIO5_5_GPIO_C_MASK

#define OVR_RES_CFG_GPIO5_5_GPIO_C_MASK 0x80U

◆ OVR_RES_CFG_GPIO5_5_GPIO_C_POS

#define OVR_RES_CFG_GPIO5_5_GPIO_C_POS 7U

◆ OVR_RES_CFG_GPIO6_6_GPIO_C_ADDR

#define OVR_RES_CFG_GPIO6_6_GPIO_C_ADDR 0x2D2U

◆ OVR_RES_CFG_GPIO6_6_GPIO_C_MASK

#define OVR_RES_CFG_GPIO6_6_GPIO_C_MASK 0x80U

◆ OVR_RES_CFG_GPIO6_6_GPIO_C_POS

#define OVR_RES_CFG_GPIO6_6_GPIO_C_POS 7U

◆ OVR_RES_CFG_GPIO7_7_GPIO_C_ADDR

#define OVR_RES_CFG_GPIO7_7_GPIO_C_ADDR 0x2D5U

◆ OVR_RES_CFG_GPIO7_7_GPIO_C_MASK

#define OVR_RES_CFG_GPIO7_7_GPIO_C_MASK 0x80U

◆ OVR_RES_CFG_GPIO7_7_GPIO_C_POS

#define OVR_RES_CFG_GPIO7_7_GPIO_C_POS 7U

◆ OVR_RES_CFG_GPIO8_8_GPIO_C_ADDR

#define OVR_RES_CFG_GPIO8_8_GPIO_C_ADDR 0x2D8U

◆ OVR_RES_CFG_GPIO8_8_GPIO_C_MASK

#define OVR_RES_CFG_GPIO8_8_GPIO_C_MASK 0x80U

◆ OVR_RES_CFG_GPIO8_8_GPIO_C_POS

#define OVR_RES_CFG_GPIO8_8_GPIO_C_POS 7U

◆ OVR_RES_CFG_GPIO9_9_GPIO_C_ADDR

#define OVR_RES_CFG_GPIO9_9_GPIO_C_ADDR 0x2DBU

◆ OVR_RES_CFG_GPIO9_9_GPIO_C_MASK

#define OVR_RES_CFG_GPIO9_9_GPIO_C_MASK 0x80U

◆ OVR_RES_CFG_GPIO9_9_GPIO_C_POS

#define OVR_RES_CFG_GPIO9_9_GPIO_C_POS 7U

◆ PATGEN_CLK_SRC_VTX_Z_VTX1_ADDR

#define PATGEN_CLK_SRC_VTX_Z_VTX1_ADDR 0x24FU

◆ PATGEN_CLK_SRC_VTX_Z_VTX1_MASK

#define PATGEN_CLK_SRC_VTX_Z_VTX1_MASK 0x0EU

◆ PATGEN_CLK_SRC_VTX_Z_VTX1_POS

#define PATGEN_CLK_SRC_VTX_Z_VTX1_POS 1U

◆ PATGEN_MODE_VTX_Z_VTX29_ADDR

#define PATGEN_MODE_VTX_Z_VTX29_ADDR 0x26BU

◆ PATGEN_MODE_VTX_Z_VTX29_MASK

#define PATGEN_MODE_VTX_Z_VTX29_MASK 0x03U

◆ PATGEN_MODE_VTX_Z_VTX29_POS

#define PATGEN_MODE_VTX_Z_VTX29_POS 0U

◆ PCLK_GPIO_REF_VTG_REF_VTG1_ADDR

#define PCLK_GPIO_REF_VTG_REF_VTG1_ADDR 0x3F1U

◆ PCLK_GPIO_REF_VTG_REF_VTG1_MASK

#define PCLK_GPIO_REF_VTG_REF_VTG1_MASK 0x3EU

◆ PCLK_GPIO_REF_VTG_REF_VTG1_POS

#define PCLK_GPIO_REF_VTG_REF_VTG1_POS 1U

◆ PCLKDET_VID_TX_Z_VIDEO_TX2_ADDR

#define PCLKDET_VID_TX_Z_VIDEO_TX2_ADDR 0x112U

◆ PCLKDET_VID_TX_Z_VIDEO_TX2_MASK

#define PCLKDET_VID_TX_Z_VIDEO_TX2_MASK 0x80U

◆ PCLKDET_VID_TX_Z_VIDEO_TX2_POS

#define PCLKDET_VID_TX_Z_VIDEO_TX2_POS 7U

◆ PCLKDET_VTX_VTX_Z_VTX1_ADDR

#define PCLKDET_VTX_VTX_Z_VTX1_ADDR 0x24FU

◆ PCLKDET_VTX_VTX_Z_VTX1_MASK

#define PCLKDET_VTX_VTX_Z_VTX1_MASK 0x20U

◆ PCLKDET_VTX_VTX_Z_VTX1_POS

#define PCLKDET_VTX_VTX_Z_VTX1_POS 5U

◆ PCLKEN_REF_VTG_REF_VTG1_ADDR

#define PCLKEN_REF_VTG_REF_VTG1_ADDR 0x3F1U

◆ PCLKEN_REF_VTG_REF_VTG1_MASK

#define PCLKEN_REF_VTG_REF_VTG1_MASK 0x01U

◆ PCLKEN_REF_VTG_REF_VTG1_POS

#define PCLKEN_REF_VTG_REF_VTG1_POS 0U

◆ PERIODIC_COMPUTE_FUNC_SAFE_REGCRC0_ADDR

#define PERIODIC_COMPUTE_FUNC_SAFE_REGCRC0_ADDR 0x1D00U

◆ PERIODIC_COMPUTE_FUNC_SAFE_REGCRC0_MASK

#define PERIODIC_COMPUTE_FUNC_SAFE_REGCRC0_MASK 0x04U

◆ PERIODIC_COMPUTE_FUNC_SAFE_REGCRC0_POS

#define PERIODIC_COMPUTE_FUNC_SAFE_REGCRC0_POS 2U

◆ PFDDIV_RSHORT_CMU_CMU2_ADDR

#define PFDDIV_RSHORT_CMU_CMU2_ADDR 0x302U

◆ PFDDIV_RSHORT_CMU_CMU2_MASK

#define PFDDIV_RSHORT_CMU_CMU2_MASK 0x70U

◆ PFDDIV_RSHORT_CMU_CMU2_POS

#define PFDDIV_RSHORT_CMU_CMU2_POS 4U

◆ PHY1_CPHYCDRMASK_MIPI_RX_EXT_EXT11_ADDR

#define PHY1_CPHYCDRMASK_MIPI_RX_EXT_EXT11_ADDR 0x383U

◆ PHY1_CPHYCDRMASK_MIPI_RX_EXT_EXT11_MASK

#define PHY1_CPHYCDRMASK_MIPI_RX_EXT_EXT11_MASK 0x03U

◆ PHY1_CPHYCDRMASK_MIPI_RX_EXT_EXT11_POS

#define PHY1_CPHYCDRMASK_MIPI_RX_EXT_EXT11_POS 0U

◆ PHY1_HS_ERR_MIPI_RX_MIPI_RX12_ADDR

#define PHY1_HS_ERR_MIPI_RX_MIPI_RX12_ADDR 0x33CU

◆ PHY1_HS_ERR_MIPI_RX_MIPI_RX12_LANE0_1B_ERR_MASK

#define PHY1_HS_ERR_MIPI_RX_MIPI_RX12_LANE0_1B_ERR_MASK (0x01U)

◆ PHY1_HS_ERR_MIPI_RX_MIPI_RX12_LANE0_1B_ERR_POS

#define PHY1_HS_ERR_MIPI_RX_MIPI_RX12_LANE0_1B_ERR_POS (0U)

◆ PHY1_HS_ERR_MIPI_RX_MIPI_RX12_LANE0_2B_ERR_MASK

#define PHY1_HS_ERR_MIPI_RX_MIPI_RX12_LANE0_2B_ERR_MASK (0x04U)

◆ PHY1_HS_ERR_MIPI_RX_MIPI_RX12_LANE0_2B_ERR_POS

#define PHY1_HS_ERR_MIPI_RX_MIPI_RX12_LANE0_2B_ERR_POS (2U)

◆ PHY1_HS_ERR_MIPI_RX_MIPI_RX12_LANE1_1B_ERR_MASK

#define PHY1_HS_ERR_MIPI_RX_MIPI_RX12_LANE1_1B_ERR_MASK (0x02U)

◆ PHY1_HS_ERR_MIPI_RX_MIPI_RX12_LANE1_1B_ERR_POS

#define PHY1_HS_ERR_MIPI_RX_MIPI_RX12_LANE1_1B_ERR_POS (1U)

◆ PHY1_HS_ERR_MIPI_RX_MIPI_RX12_LANE1_2B_ERR_MASK

#define PHY1_HS_ERR_MIPI_RX_MIPI_RX12_LANE1_2B_ERR_MASK (0x08U)

◆ PHY1_HS_ERR_MIPI_RX_MIPI_RX12_LANE1_2B_ERR_POS

#define PHY1_HS_ERR_MIPI_RX_MIPI_RX12_LANE1_2B_ERR_POS (3U)

◆ PHY1_HS_ERR_MIPI_RX_MIPI_RX12_MASK

#define PHY1_HS_ERR_MIPI_RX_MIPI_RX12_MASK 0xFFU

◆ PHY1_HS_ERR_MIPI_RX_MIPI_RX12_POS

#define PHY1_HS_ERR_MIPI_RX_MIPI_RX12_POS 0U

◆ PHY1_HS_ERR_MIPI_RX_MIPI_RX12_SKEW_CALIB_LANE0_ERR_MASK

#define PHY1_HS_ERR_MIPI_RX_MIPI_RX12_SKEW_CALIB_LANE0_ERR_MASK (0x20U)

◆ PHY1_HS_ERR_MIPI_RX_MIPI_RX12_SKEW_CALIB_LANE0_ERR_POS

#define PHY1_HS_ERR_MIPI_RX_MIPI_RX12_SKEW_CALIB_LANE0_ERR_POS (5U)

◆ PHY1_HS_ERR_MIPI_RX_MIPI_RX12_SKEW_CALIB_LANE1_ERR_MASK

#define PHY1_HS_ERR_MIPI_RX_MIPI_RX12_SKEW_CALIB_LANE1_ERR_MASK (0x10U)

◆ PHY1_HS_ERR_MIPI_RX_MIPI_RX12_SKEW_CALIB_LANE1_ERR_POS

#define PHY1_HS_ERR_MIPI_RX_MIPI_RX12_SKEW_CALIB_LANE1_ERR_POS (4U)

◆ PHY1_LANE_MAP_MIPI_RX_MIPI_RX2_ADDR

#define PHY1_LANE_MAP_MIPI_RX_MIPI_RX2_ADDR 0x332U

◆ PHY1_LANE_MAP_MIPI_RX_MIPI_RX2_ALL_MASK

#define PHY1_LANE_MAP_MIPI_RX_MIPI_RX2_ALL_MASK (0xFFU)

◆ PHY1_LANE_MAP_MIPI_RX_MIPI_RX2_MASK

#define PHY1_LANE_MAP_MIPI_RX_MIPI_RX2_MASK 0xF0U

◆ PHY1_LANE_MAP_MIPI_RX_MIPI_RX2_POS

#define PHY1_LANE_MAP_MIPI_RX_MIPI_RX2_POS 4U

◆ PHY1_LANE_MAP_SER_LANE_2_MIPI_RX_MIPI_RX2_MASK

#define PHY1_LANE_MAP_SER_LANE_2_MIPI_RX_MIPI_RX2_MASK (0x30U)

◆ PHY1_LANE_MAP_SER_LANE_2_MIPI_RX_MIPI_RX2_POS

#define PHY1_LANE_MAP_SER_LANE_2_MIPI_RX_MIPI_RX2_POS (4U)

◆ PHY1_LANE_MAP_SER_LANE_3_MIPI_RX_MIPI_RX2_MASK

#define PHY1_LANE_MAP_SER_LANE_3_MIPI_RX_MIPI_RX2_MASK (0xC0U)

◆ PHY1_LANE_MAP_SER_LANE_3_MIPI_RX_MIPI_RX2_POS

#define PHY1_LANE_MAP_SER_LANE_3_MIPI_RX_MIPI_RX2_POS (6U)

◆ PHY1_LP_ERR_MIPI_RX_MIPI_RX11_ADDR

#define PHY1_LP_ERR_MIPI_RX_MIPI_RX11_ADDR 0x33BU

◆ PHY1_LP_ERR_MIPI_RX_MIPI_RX11_INVALID_LINE_SEQ_ON_CLK_MASK

#define PHY1_LP_ERR_MIPI_RX_MIPI_RX11_INVALID_LINE_SEQ_ON_CLK_MASK (0x10U)

◆ PHY1_LP_ERR_MIPI_RX_MIPI_RX11_INVALID_LINE_SEQ_ON_CLK_POS

#define PHY1_LP_ERR_MIPI_RX_MIPI_RX11_INVALID_LINE_SEQ_ON_CLK_POS (4U)

◆ PHY1_LP_ERR_MIPI_RX_MIPI_RX11_INVALID_LINE_SEQ_ON_D0_MASK

#define PHY1_LP_ERR_MIPI_RX_MIPI_RX11_INVALID_LINE_SEQ_ON_D0_MASK (0x04U)

◆ PHY1_LP_ERR_MIPI_RX_MIPI_RX11_INVALID_LINE_SEQ_ON_D0_POS

#define PHY1_LP_ERR_MIPI_RX_MIPI_RX11_INVALID_LINE_SEQ_ON_D0_POS (2U)

◆ PHY1_LP_ERR_MIPI_RX_MIPI_RX11_INVALID_LINE_SEQ_ON_D1_MASK

#define PHY1_LP_ERR_MIPI_RX_MIPI_RX11_INVALID_LINE_SEQ_ON_D1_MASK (0x08U)

◆ PHY1_LP_ERR_MIPI_RX_MIPI_RX11_INVALID_LINE_SEQ_ON_D1_POS

#define PHY1_LP_ERR_MIPI_RX_MIPI_RX11_INVALID_LINE_SEQ_ON_D1_POS (3U)

◆ PHY1_LP_ERR_MIPI_RX_MIPI_RX11_MASK

#define PHY1_LP_ERR_MIPI_RX_MIPI_RX11_MASK 0x1FU

◆ PHY1_LP_ERR_MIPI_RX_MIPI_RX11_POS

#define PHY1_LP_ERR_MIPI_RX_MIPI_RX11_POS 0U

◆ PHY1_LP_ERR_MIPI_RX_MIPI_RX11_UNRECOGNIZED_ESC_CMD_RCVD_ON_CLK_MASK

#define PHY1_LP_ERR_MIPI_RX_MIPI_RX11_UNRECOGNIZED_ESC_CMD_RCVD_ON_CLK_MASK (0x02U)

◆ PHY1_LP_ERR_MIPI_RX_MIPI_RX11_UNRECOGNIZED_ESC_CMD_RCVD_ON_CLK_POS

#define PHY1_LP_ERR_MIPI_RX_MIPI_RX11_UNRECOGNIZED_ESC_CMD_RCVD_ON_CLK_POS (1U)

◆ PHY1_LP_ERR_MIPI_RX_MIPI_RX11_UNRECOGNIZED_ESC_CMD_RCVD_ON_D0_MASK

#define PHY1_LP_ERR_MIPI_RX_MIPI_RX11_UNRECOGNIZED_ESC_CMD_RCVD_ON_D0_MASK (0x01U)

◆ PHY1_LP_ERR_MIPI_RX_MIPI_RX11_UNRECOGNIZED_ESC_CMD_RCVD_ON_D0_POS

#define PHY1_LP_ERR_MIPI_RX_MIPI_RX11_UNRECOGNIZED_ESC_CMD_RCVD_ON_D0_POS (0U)

◆ PHY1_PKT_CNT_MIPI_RX_EXT_EXT21_ADDR

#define PHY1_PKT_CNT_MIPI_RX_EXT_EXT21_ADDR 0x38DU

◆ PHY1_PKT_CNT_MIPI_RX_EXT_EXT21_MASK

#define PHY1_PKT_CNT_MIPI_RX_EXT_EXT21_MASK 0xFFU

◆ PHY1_PKT_CNT_MIPI_RX_EXT_EXT21_POS

#define PHY1_PKT_CNT_MIPI_RX_EXT_EXT21_POS 0U

◆ PHY1_POL_MAP_DATA_LANE_2_MIPI_RX_MIPI_RX5_MASK

#define PHY1_POL_MAP_DATA_LANE_2_MIPI_RX_MIPI_RX5_MASK (0x01U)

◆ PHY1_POL_MAP_DATA_LANE_2_MIPI_RX_MIPI_RX5_POS

#define PHY1_POL_MAP_DATA_LANE_2_MIPI_RX_MIPI_RX5_POS (0U)

◆ PHY1_POL_MAP_DATA_LANE_3_MIPI_RX_MIPI_RX5_MASK

#define PHY1_POL_MAP_DATA_LANE_3_MIPI_RX_MIPI_RX5_MASK (0x02U)

◆ PHY1_POL_MAP_DATA_LANE_3_MIPI_RX_MIPI_RX5_POS

#define PHY1_POL_MAP_DATA_LANE_3_MIPI_RX_MIPI_RX5_POS (1U)

◆ PHY1_POL_MAP_MIPI_RX_MIPI_RX4_ADDR

#define PHY1_POL_MAP_MIPI_RX_MIPI_RX4_ADDR 0x334U

◆ PHY1_POL_MAP_MIPI_RX_MIPI_RX4_ALL_MASK

#define PHY1_POL_MAP_MIPI_RX_MIPI_RX4_ALL_MASK (0xFFU)

◆ PHY1_POL_MAP_MIPI_RX_MIPI_RX4_MASK

#define PHY1_POL_MAP_MIPI_RX_MIPI_RX4_MASK 0x70U

◆ PHY1_POL_MAP_MIPI_RX_MIPI_RX4_POS

#define PHY1_POL_MAP_MIPI_RX_MIPI_RX4_POS 4U

◆ PHY2_HS_ERR_MIPI_RX_MIPI_RX14_ADDR

#define PHY2_HS_ERR_MIPI_RX_MIPI_RX14_ADDR 0x33EU

◆ PHY2_HS_ERR_MIPI_RX_MIPI_RX14_LANE0_1B_ERR_MASK

#define PHY2_HS_ERR_MIPI_RX_MIPI_RX14_LANE0_1B_ERR_MASK (0x04U)

◆ PHY2_HS_ERR_MIPI_RX_MIPI_RX14_LANE0_1B_ERR_POS

#define PHY2_HS_ERR_MIPI_RX_MIPI_RX14_LANE0_1B_ERR_POS (2U)

◆ PHY2_HS_ERR_MIPI_RX_MIPI_RX14_LANE0_2B_ERR_MASK

#define PHY2_HS_ERR_MIPI_RX_MIPI_RX14_LANE0_2B_ERR_MASK (0x01U)

◆ PHY2_HS_ERR_MIPI_RX_MIPI_RX14_LANE0_2B_ERR_POS

#define PHY2_HS_ERR_MIPI_RX_MIPI_RX14_LANE0_2B_ERR_POS (0U)

◆ PHY2_HS_ERR_MIPI_RX_MIPI_RX14_LANE1_1B_ERR_MASK

#define PHY2_HS_ERR_MIPI_RX_MIPI_RX14_LANE1_1B_ERR_MASK (0x08U)

◆ PHY2_HS_ERR_MIPI_RX_MIPI_RX14_LANE1_1B_ERR_POS

#define PHY2_HS_ERR_MIPI_RX_MIPI_RX14_LANE1_1B_ERR_POS (3U)

◆ PHY2_HS_ERR_MIPI_RX_MIPI_RX14_LANE1_2B_ERR_MASK

#define PHY2_HS_ERR_MIPI_RX_MIPI_RX14_LANE1_2B_ERR_MASK (0x02U)

◆ PHY2_HS_ERR_MIPI_RX_MIPI_RX14_LANE1_2B_ERR_POS

#define PHY2_HS_ERR_MIPI_RX_MIPI_RX14_LANE1_2B_ERR_POS (1U)

◆ PHY2_HS_ERR_MIPI_RX_MIPI_RX14_MASK

#define PHY2_HS_ERR_MIPI_RX_MIPI_RX14_MASK 0xFFU

◆ PHY2_HS_ERR_MIPI_RX_MIPI_RX14_POS

#define PHY2_HS_ERR_MIPI_RX_MIPI_RX14_POS 0U

◆ PHY2_HS_ERR_MIPI_RX_MIPI_RX14_SKEW_CALIB_LANE0_ERR_MASK

#define PHY2_HS_ERR_MIPI_RX_MIPI_RX14_SKEW_CALIB_LANE0_ERR_MASK (0x20U)

◆ PHY2_HS_ERR_MIPI_RX_MIPI_RX14_SKEW_CALIB_LANE0_ERR_POS

#define PHY2_HS_ERR_MIPI_RX_MIPI_RX14_SKEW_CALIB_LANE0_ERR_POS (5U)

◆ PHY2_HS_ERR_MIPI_RX_MIPI_RX14_SKEW_CALIB_LANE1_ERR_MASK

#define PHY2_HS_ERR_MIPI_RX_MIPI_RX14_SKEW_CALIB_LANE1_ERR_MASK (0x10U)

◆ PHY2_HS_ERR_MIPI_RX_MIPI_RX14_SKEW_CALIB_LANE1_ERR_POS

#define PHY2_HS_ERR_MIPI_RX_MIPI_RX14_SKEW_CALIB_LANE1_ERR_POS (4U)

◆ PHY2_LANE_MAP_MIPI_RX_MIPI_RX3_ADDR

#define PHY2_LANE_MAP_MIPI_RX_MIPI_RX3_ADDR 0x333U

◆ PHY2_LANE_MAP_MIPI_RX_MIPI_RX3_MASK

#define PHY2_LANE_MAP_MIPI_RX_MIPI_RX3_MASK 0x0FU

◆ PHY2_LANE_MAP_MIPI_RX_MIPI_RX3_POS

#define PHY2_LANE_MAP_MIPI_RX_MIPI_RX3_POS 0U

◆ PHY2_LANE_MAP_SER_LANE_0_MIPI_RX_MIPI_RX3_MASK

#define PHY2_LANE_MAP_SER_LANE_0_MIPI_RX_MIPI_RX3_MASK (0x03U)

◆ PHY2_LANE_MAP_SER_LANE_0_MIPI_RX_MIPI_RX3_POS

#define PHY2_LANE_MAP_SER_LANE_0_MIPI_RX_MIPI_RX3_POS (0U)

◆ PHY2_LANE_MAP_SER_LANE_1_MIPI_RX_MIPI_RX3_MASK

#define PHY2_LANE_MAP_SER_LANE_1_MIPI_RX_MIPI_RX3_MASK (0x0CU)

◆ PHY2_LANE_MAP_SER_LANE_1_MIPI_RX_MIPI_RX3_POS

#define PHY2_LANE_MAP_SER_LANE_1_MIPI_RX_MIPI_RX3_POS (2U)

◆ PHY2_LP_ERR_MIPI_RX_MIPI_RX13_ADDR

#define PHY2_LP_ERR_MIPI_RX_MIPI_RX13_ADDR 0x33DU

◆ PHY2_LP_ERR_MIPI_RX_MIPI_RX13_INVALID_LINE_SEQ_ON_CLK_MASK

#define PHY2_LP_ERR_MIPI_RX_MIPI_RX13_INVALID_LINE_SEQ_ON_CLK_MASK (0x10U)

◆ PHY2_LP_ERR_MIPI_RX_MIPI_RX13_INVALID_LINE_SEQ_ON_CLK_POS

#define PHY2_LP_ERR_MIPI_RX_MIPI_RX13_INVALID_LINE_SEQ_ON_CLK_POS (4U)

◆ PHY2_LP_ERR_MIPI_RX_MIPI_RX13_INVALID_LINE_SEQ_ON_D0_MASK

#define PHY2_LP_ERR_MIPI_RX_MIPI_RX13_INVALID_LINE_SEQ_ON_D0_MASK (0x04U)

◆ PHY2_LP_ERR_MIPI_RX_MIPI_RX13_INVALID_LINE_SEQ_ON_D0_POS

#define PHY2_LP_ERR_MIPI_RX_MIPI_RX13_INVALID_LINE_SEQ_ON_D0_POS (2U)

◆ PHY2_LP_ERR_MIPI_RX_MIPI_RX13_INVALID_LINE_SEQ_ON_D1_MASK

#define PHY2_LP_ERR_MIPI_RX_MIPI_RX13_INVALID_LINE_SEQ_ON_D1_MASK (0x08U)

◆ PHY2_LP_ERR_MIPI_RX_MIPI_RX13_INVALID_LINE_SEQ_ON_D1_POS

#define PHY2_LP_ERR_MIPI_RX_MIPI_RX13_INVALID_LINE_SEQ_ON_D1_POS (3U)

◆ PHY2_LP_ERR_MIPI_RX_MIPI_RX13_MASK

#define PHY2_LP_ERR_MIPI_RX_MIPI_RX13_MASK 0x1FU

◆ PHY2_LP_ERR_MIPI_RX_MIPI_RX13_POS

#define PHY2_LP_ERR_MIPI_RX_MIPI_RX13_POS 0U

◆ PHY2_LP_ERR_MIPI_RX_MIPI_RX13_UNRECOGNIZED_ESC_CMD_RCVD_ON_CLK_MASK

#define PHY2_LP_ERR_MIPI_RX_MIPI_RX13_UNRECOGNIZED_ESC_CMD_RCVD_ON_CLK_MASK (0x02U)

◆ PHY2_LP_ERR_MIPI_RX_MIPI_RX13_UNRECOGNIZED_ESC_CMD_RCVD_ON_CLK_POS

#define PHY2_LP_ERR_MIPI_RX_MIPI_RX13_UNRECOGNIZED_ESC_CMD_RCVD_ON_CLK_POS (1U)

◆ PHY2_LP_ERR_MIPI_RX_MIPI_RX13_UNRECOGNIZED_ESC_CMD_RCVD_ON_D0_MASK

#define PHY2_LP_ERR_MIPI_RX_MIPI_RX13_UNRECOGNIZED_ESC_CMD_RCVD_ON_D0_MASK (0x01U)

◆ PHY2_LP_ERR_MIPI_RX_MIPI_RX13_UNRECOGNIZED_ESC_CMD_RCVD_ON_D0_POS

#define PHY2_LP_ERR_MIPI_RX_MIPI_RX13_UNRECOGNIZED_ESC_CMD_RCVD_ON_D0_POS (0U)

◆ PHY2_POL_MAP_CLK_LANE_MIPI_RX_MIPI_RX5_MASK

#define PHY2_POL_MAP_CLK_LANE_MIPI_RX_MIPI_RX5_MASK (0x04U)

◆ PHY2_POL_MAP_CLK_LANE_MIPI_RX_MIPI_RX5_POS

#define PHY2_POL_MAP_CLK_LANE_MIPI_RX_MIPI_RX5_POS (2U)

◆ PHY2_POL_MAP_DATA_LANE_0_MIPI_RX_MIPI_RX5_MASK

#define PHY2_POL_MAP_DATA_LANE_0_MIPI_RX_MIPI_RX5_MASK (0x01U)

◆ PHY2_POL_MAP_DATA_LANE_0_MIPI_RX_MIPI_RX5_POS

#define PHY2_POL_MAP_DATA_LANE_0_MIPI_RX_MIPI_RX5_POS (0U)

◆ PHY2_POL_MAP_DATA_LANE_1_MIPI_RX_MIPI_RX5_MASK

#define PHY2_POL_MAP_DATA_LANE_1_MIPI_RX_MIPI_RX5_MASK (0x02U)

◆ PHY2_POL_MAP_DATA_LANE_1_MIPI_RX_MIPI_RX5_POS

#define PHY2_POL_MAP_DATA_LANE_1_MIPI_RX_MIPI_RX5_POS (1U)

◆ PHY2_POL_MAP_MIPI_RX_MIPI_RX5_ADDR

#define PHY2_POL_MAP_MIPI_RX_MIPI_RX5_ADDR 0x335U

◆ PHY2_POL_MAP_MIPI_RX_MIPI_RX5_MASK

#define PHY2_POL_MAP_MIPI_RX_MIPI_RX5_MASK 0x07U

◆ PHY2_POL_MAP_MIPI_RX_MIPI_RX5_POS

#define PHY2_POL_MAP_MIPI_RX_MIPI_RX5_POS 0U

◆ PHY_CLK_CNT_MIPI_RX_EXT_EXT24_ADDR

#define PHY_CLK_CNT_MIPI_RX_EXT_EXT24_ADDR 0x390U

◆ PHY_CLK_CNT_MIPI_RX_EXT_EXT24_MASK

#define PHY_CLK_CNT_MIPI_RX_EXT_EXT24_MASK 0xFFU

◆ PHY_CLK_CNT_MIPI_RX_EXT_EXT24_POS

#define PHY_CLK_CNT_MIPI_RX_EXT_EXT24_POS 0U

◆ PHY_CONFIG_MIPI_RX_MIPI_RX0_ADDR

#define PHY_CONFIG_MIPI_RX_MIPI_RX0_ADDR (0x330U)

◆ PHY_CONFIG_MIPI_RX_MIPI_RX0_MASK

#define PHY_CONFIG_MIPI_RX_MIPI_RX0_MASK (0x07U)

◆ PHY_CONFIG_MIPI_RX_MIPI_RX0_POS

#define PHY_CONFIG_MIPI_RX_MIPI_RX0_POS (0U)

◆ PIO00_SLEW_MISC_PIO_SLEW_0_ADDR

#define PIO00_SLEW_MISC_PIO_SLEW_0_ADDR 0x56FU

◆ PIO00_SLEW_MISC_PIO_SLEW_0_MASK

#define PIO00_SLEW_MISC_PIO_SLEW_0_MASK 0x03U

◆ PIO00_SLEW_MISC_PIO_SLEW_0_POS

#define PIO00_SLEW_MISC_PIO_SLEW_0_POS 0U

◆ PIO010_SLEW_MISC_PIO_SLEW_2_ADDR

#define PIO010_SLEW_MISC_PIO_SLEW_2_ADDR 0x571U

◆ PIO010_SLEW_MISC_PIO_SLEW_2_MASK

#define PIO010_SLEW_MISC_PIO_SLEW_2_MASK 0x30U

◆ PIO010_SLEW_MISC_PIO_SLEW_2_POS

#define PIO010_SLEW_MISC_PIO_SLEW_2_POS 4U

◆ PIO011_SLEW_MISC_PIO_SLEW_2_ADDR

#define PIO011_SLEW_MISC_PIO_SLEW_2_ADDR 0x571U

◆ PIO011_SLEW_MISC_PIO_SLEW_2_MASK

#define PIO011_SLEW_MISC_PIO_SLEW_2_MASK 0xC0U

◆ PIO011_SLEW_MISC_PIO_SLEW_2_POS

#define PIO011_SLEW_MISC_PIO_SLEW_2_POS 6U

◆ PIO01_SLEW_MISC_PIO_SLEW_0_ADDR

#define PIO01_SLEW_MISC_PIO_SLEW_0_ADDR 0x56FU

◆ PIO01_SLEW_MISC_PIO_SLEW_0_MASK

#define PIO01_SLEW_MISC_PIO_SLEW_0_MASK 0x0CU

◆ PIO01_SLEW_MISC_PIO_SLEW_0_POS

#define PIO01_SLEW_MISC_PIO_SLEW_0_POS 2U

◆ PIO02_SLEW_MISC_PIO_SLEW_0_ADDR

#define PIO02_SLEW_MISC_PIO_SLEW_0_ADDR 0x56FU

◆ PIO02_SLEW_MISC_PIO_SLEW_0_MASK

#define PIO02_SLEW_MISC_PIO_SLEW_0_MASK 0x30U

◆ PIO02_SLEW_MISC_PIO_SLEW_0_POS

#define PIO02_SLEW_MISC_PIO_SLEW_0_POS 4U

◆ PIO05_SLEW_MISC_PIO_SLEW_1_ADDR

#define PIO05_SLEW_MISC_PIO_SLEW_1_ADDR 0x570U

◆ PIO05_SLEW_MISC_PIO_SLEW_1_MASK

#define PIO05_SLEW_MISC_PIO_SLEW_1_MASK 0x0CU

◆ PIO05_SLEW_MISC_PIO_SLEW_1_POS

#define PIO05_SLEW_MISC_PIO_SLEW_1_POS 2U

◆ PIO06_SLEW_MISC_PIO_SLEW_1_ADDR

#define PIO06_SLEW_MISC_PIO_SLEW_1_ADDR 0x570U

◆ PIO06_SLEW_MISC_PIO_SLEW_1_MASK

#define PIO06_SLEW_MISC_PIO_SLEW_1_MASK 0x30U

◆ PIO06_SLEW_MISC_PIO_SLEW_1_POS

#define PIO06_SLEW_MISC_PIO_SLEW_1_POS 4U

◆ PKT_CNT_EXP_TCTRL_INTR1_ADDR

#define PKT_CNT_EXP_TCTRL_INTR1_ADDR 0x19U

◆ PKT_CNT_EXP_TCTRL_INTR1_MASK

#define PKT_CNT_EXP_TCTRL_INTR1_MASK 0xF0U

◆ PKT_CNT_EXP_TCTRL_INTR1_POS

#define PKT_CNT_EXP_TCTRL_INTR1_POS 4U

◆ PKT_CNT_FLAG_TCTRL_INTR5_ADDR

#define PKT_CNT_FLAG_TCTRL_INTR5_ADDR 0x1DU

◆ PKT_CNT_FLAG_TCTRL_INTR5_MASK

#define PKT_CNT_FLAG_TCTRL_INTR5_MASK 0x02U

◆ PKT_CNT_FLAG_TCTRL_INTR5_POS

#define PKT_CNT_FLAG_TCTRL_INTR5_POS 1U

◆ PKT_CNT_LBW_GMSL_RX0_ADDR

#define PKT_CNT_LBW_GMSL_RX0_ADDR 0x2CU

◆ PKT_CNT_LBW_GMSL_RX0_MASK

#define PKT_CNT_LBW_GMSL_RX0_MASK 0xC0U

◆ PKT_CNT_LBW_GMSL_RX0_POS

#define PKT_CNT_LBW_GMSL_RX0_POS 6U

◆ PKT_CNT_OEN_TCTRL_INTR4_ADDR

#define PKT_CNT_OEN_TCTRL_INTR4_ADDR 0x1CU

◆ PKT_CNT_OEN_TCTRL_INTR4_MASK

#define PKT_CNT_OEN_TCTRL_INTR4_MASK 0x02U

◆ PKT_CNT_OEN_TCTRL_INTR4_POS

#define PKT_CNT_OEN_TCTRL_INTR4_POS 1U

◆ PKT_CNT_SEL_GMSL_RX0_ADDR

#define PKT_CNT_SEL_GMSL_RX0_ADDR 0x2CU

◆ PKT_CNT_SEL_GMSL_RX0_MASK

#define PKT_CNT_SEL_GMSL_RX0_MASK 0x0FU

◆ PKT_CNT_SEL_GMSL_RX0_POS

#define PKT_CNT_SEL_GMSL_RX0_POS 0U

◆ PKT_CNT_TCTRL_CNT3_ADDR

#define PKT_CNT_TCTRL_CNT3_ADDR 0x25U

◆ PKT_CNT_TCTRL_CNT3_MASK

#define PKT_CNT_TCTRL_CNT3_MASK 0xFFU

◆ PKT_CNT_TCTRL_CNT3_POS

#define PKT_CNT_TCTRL_CNT3_POS 0U

◆ PORZ_INT_FLAG_TCTRL_INTR7_ADDR

#define PORZ_INT_FLAG_TCTRL_INTR7_ADDR 0x1FU

◆ PORZ_INT_FLAG_TCTRL_INTR7_MASK

#define PORZ_INT_FLAG_TCTRL_INTR7_MASK 0x40U

◆ PORZ_INT_FLAG_TCTRL_INTR7_POS

#define PORZ_INT_FLAG_TCTRL_INTR7_POS 6U

◆ PORZ_INT_OEN_TCTRL_INTR6_ADDR

#define PORZ_INT_OEN_TCTRL_INTR6_ADDR 0x1EU

◆ PORZ_INT_OEN_TCTRL_INTR6_MASK

#define PORZ_INT_OEN_TCTRL_INTR6_MASK 0x40U

◆ PORZ_INT_OEN_TCTRL_INTR6_POS

#define PORZ_INT_OEN_TCTRL_INTR6_POS 6U

◆ POST_DONE_FUNC_SAFE_REG_POST0_ADDR

#define POST_DONE_FUNC_SAFE_REG_POST0_ADDR 0x1D20U

◆ POST_DONE_FUNC_SAFE_REG_POST0_MASK

#define POST_DONE_FUNC_SAFE_REG_POST0_MASK 0x80U

◆ POST_DONE_FUNC_SAFE_REG_POST0_POS

#define POST_DONE_FUNC_SAFE_REG_POST0_POS 7U

◆ POST_LBIST_PASSED_FUNC_SAFE_REG_POST0_ADDR

#define POST_LBIST_PASSED_FUNC_SAFE_REG_POST0_ADDR 0x1D20U

◆ POST_LBIST_PASSED_FUNC_SAFE_REG_POST0_MASK

#define POST_LBIST_PASSED_FUNC_SAFE_REG_POST0_MASK 0x20U

◆ POST_LBIST_PASSED_FUNC_SAFE_REG_POST0_POS

#define POST_LBIST_PASSED_FUNC_SAFE_REG_POST0_POS 5U

◆ POST_MBIST_PASSED_FUNC_SAFE_REG_POST0_ADDR

#define POST_MBIST_PASSED_FUNC_SAFE_REG_POST0_ADDR 0x1D20U

◆ POST_MBIST_PASSED_FUNC_SAFE_REG_POST0_MASK

#define POST_MBIST_PASSED_FUNC_SAFE_REG_POST0_MASK 0x40U

◆ POST_MBIST_PASSED_FUNC_SAFE_REG_POST0_POS

#define POST_MBIST_PASSED_FUNC_SAFE_REG_POST0_POS 6U

◆ PU_LF0_DEV_REG5_ADDR

#define PU_LF0_DEV_REG5_ADDR 0x05U

◆ PU_LF0_DEV_REG5_MASK

#define PU_LF0_DEV_REG5_MASK 0x01U

◆ PU_LF0_DEV_REG5_POS

#define PU_LF0_DEV_REG5_POS 0U

◆ PU_LF1_DEV_REG5_ADDR

#define PU_LF1_DEV_REG5_ADDR 0x05U

◆ PU_LF1_DEV_REG5_MASK

#define PU_LF1_DEV_REG5_MASK 0x02U

◆ PU_LF1_DEV_REG5_POS

#define PU_LF1_DEV_REG5_POS 1U

◆ PULL_UPDN_SEL_GPIO0_0_GPIO_B_ADDR

#define PULL_UPDN_SEL_GPIO0_0_GPIO_B_ADDR 0x2BFU

◆ PULL_UPDN_SEL_GPIO0_0_GPIO_B_MASK

#define PULL_UPDN_SEL_GPIO0_0_GPIO_B_MASK 0xC0U

◆ PULL_UPDN_SEL_GPIO0_0_GPIO_B_POS

#define PULL_UPDN_SEL_GPIO0_0_GPIO_B_POS 6U

◆ PULL_UPDN_SEL_GPIO10_10_GPIO_B_ADDR

#define PULL_UPDN_SEL_GPIO10_10_GPIO_B_ADDR 0x2DDU

◆ PULL_UPDN_SEL_GPIO10_10_GPIO_B_MASK

#define PULL_UPDN_SEL_GPIO10_10_GPIO_B_MASK 0xC0U

◆ PULL_UPDN_SEL_GPIO10_10_GPIO_B_POS

#define PULL_UPDN_SEL_GPIO10_10_GPIO_B_POS 6U

◆ PULL_UPDN_SEL_GPIO1_1_GPIO_B_ADDR

#define PULL_UPDN_SEL_GPIO1_1_GPIO_B_ADDR 0x2C2U

◆ PULL_UPDN_SEL_GPIO1_1_GPIO_B_MASK

#define PULL_UPDN_SEL_GPIO1_1_GPIO_B_MASK 0xC0U

◆ PULL_UPDN_SEL_GPIO1_1_GPIO_B_POS

#define PULL_UPDN_SEL_GPIO1_1_GPIO_B_POS 6U

◆ PULL_UPDN_SEL_GPIO2_2_GPIO_B_ADDR

#define PULL_UPDN_SEL_GPIO2_2_GPIO_B_ADDR 0x2C5U

◆ PULL_UPDN_SEL_GPIO2_2_GPIO_B_MASK

#define PULL_UPDN_SEL_GPIO2_2_GPIO_B_MASK 0xC0U

◆ PULL_UPDN_SEL_GPIO2_2_GPIO_B_POS

#define PULL_UPDN_SEL_GPIO2_2_GPIO_B_POS 6U

◆ PULL_UPDN_SEL_GPIO3_3_GPIO_B_ADDR

#define PULL_UPDN_SEL_GPIO3_3_GPIO_B_ADDR 0x2C8U

◆ PULL_UPDN_SEL_GPIO3_3_GPIO_B_MASK

#define PULL_UPDN_SEL_GPIO3_3_GPIO_B_MASK 0xC0U

◆ PULL_UPDN_SEL_GPIO3_3_GPIO_B_POS

#define PULL_UPDN_SEL_GPIO3_3_GPIO_B_POS 6U

◆ PULL_UPDN_SEL_GPIO4_4_GPIO_B_ADDR

#define PULL_UPDN_SEL_GPIO4_4_GPIO_B_ADDR 0x2CBU

◆ PULL_UPDN_SEL_GPIO4_4_GPIO_B_MASK

#define PULL_UPDN_SEL_GPIO4_4_GPIO_B_MASK 0xC0U

◆ PULL_UPDN_SEL_GPIO4_4_GPIO_B_POS

#define PULL_UPDN_SEL_GPIO4_4_GPIO_B_POS 6U

◆ PULL_UPDN_SEL_GPIO5_5_GPIO_B_ADDR

#define PULL_UPDN_SEL_GPIO5_5_GPIO_B_ADDR 0x2CEU

◆ PULL_UPDN_SEL_GPIO5_5_GPIO_B_MASK

#define PULL_UPDN_SEL_GPIO5_5_GPIO_B_MASK 0xC0U

◆ PULL_UPDN_SEL_GPIO5_5_GPIO_B_POS

#define PULL_UPDN_SEL_GPIO5_5_GPIO_B_POS 6U

◆ PULL_UPDN_SEL_GPIO6_6_GPIO_B_ADDR

#define PULL_UPDN_SEL_GPIO6_6_GPIO_B_ADDR 0x2D1U

◆ PULL_UPDN_SEL_GPIO6_6_GPIO_B_MASK

#define PULL_UPDN_SEL_GPIO6_6_GPIO_B_MASK 0xC0U

◆ PULL_UPDN_SEL_GPIO6_6_GPIO_B_POS

#define PULL_UPDN_SEL_GPIO6_6_GPIO_B_POS 6U

◆ PULL_UPDN_SEL_GPIO7_7_GPIO_B_ADDR

#define PULL_UPDN_SEL_GPIO7_7_GPIO_B_ADDR 0x2D4U

◆ PULL_UPDN_SEL_GPIO7_7_GPIO_B_MASK

#define PULL_UPDN_SEL_GPIO7_7_GPIO_B_MASK 0xC0U

◆ PULL_UPDN_SEL_GPIO7_7_GPIO_B_POS

#define PULL_UPDN_SEL_GPIO7_7_GPIO_B_POS 6U

◆ PULL_UPDN_SEL_GPIO8_8_GPIO_B_ADDR

#define PULL_UPDN_SEL_GPIO8_8_GPIO_B_ADDR 0x2D7U

◆ PULL_UPDN_SEL_GPIO8_8_GPIO_B_MASK

#define PULL_UPDN_SEL_GPIO8_8_GPIO_B_MASK 0xC0U

◆ PULL_UPDN_SEL_GPIO8_8_GPIO_B_POS

#define PULL_UPDN_SEL_GPIO8_8_GPIO_B_POS 6U

◆ PULL_UPDN_SEL_GPIO9_9_GPIO_B_ADDR

#define PULL_UPDN_SEL_GPIO9_9_GPIO_B_ADDR 0x2DAU

◆ PULL_UPDN_SEL_GPIO9_9_GPIO_B_MASK

#define PULL_UPDN_SEL_GPIO9_9_GPIO_B_MASK 0xC0U

◆ PULL_UPDN_SEL_GPIO9_9_GPIO_B_POS

#define PULL_UPDN_SEL_GPIO9_9_GPIO_B_POS 6U

◆ RCLK_ALT_DEV_REG3_ADDR

#define RCLK_ALT_DEV_REG3_ADDR 0x03U

◆ RCLK_ALT_DEV_REG3_MASK

#define RCLK_ALT_DEV_REG3_MASK 0x04U

◆ RCLK_ALT_DEV_REG3_POS

#define RCLK_ALT_DEV_REG3_POS 2U

◆ RCLKEN_DEV_REG6_ADDR

#define RCLKEN_DEV_REG6_ADDR 0x06U

◆ RCLKEN_DEV_REG6_MASK

#define RCLKEN_DEV_REG6_MASK 0x20U

◆ RCLKEN_DEV_REG6_POS

#define RCLKEN_DEV_REG6_POS 5U

◆ RCLKEN_Y_REF_VTG_REF_VTG1_ADDR

#define RCLKEN_Y_REF_VTG_REF_VTG1_ADDR 0x3F1U

◆ RCLKEN_Y_REF_VTG_REF_VTG1_MASK

#define RCLKEN_Y_REF_VTG_REF_VTG1_MASK 0x80U

◆ RCLKEN_Y_REF_VTG_REF_VTG1_POS

#define RCLKEN_Y_REF_VTG_REF_VTG1_POS 7U

◆ RCLKSEL_DEV_REG3_ADDR

#define RCLKSEL_DEV_REG3_ADDR 0x03U

◆ RCLKSEL_DEV_REG3_MASK

#define RCLKSEL_DEV_REG3_MASK 0x03U

◆ RCLKSEL_DEV_REG3_POS

#define RCLKSEL_DEV_REG3_POS 0U

◆ REF_VTG_MODE_REF_VTG_VTX0_ADDR

#define REF_VTG_MODE_REF_VTG_VTX0_ADDR 0x3E0U

◆ REF_VTG_MODE_REF_VTG_VTX0_MASK

#define REF_VTG_MODE_REF_VTG_VTX0_MASK 0x30U

◆ REF_VTG_MODE_REF_VTG_VTX0_POS

#define REF_VTG_MODE_REF_VTG_VTX0_POS 4U

◆ REF_VTG_REF_VTG0_ADDR

#define REF_VTG_REF_VTG0_ADDR 0x3F0U

◆ REF_VTG_REF_VTG0_DEFAULT

#define REF_VTG_REF_VTG0_DEFAULT 0x50U

◆ REF_VTG_REF_VTG1_ADDR

#define REF_VTG_REF_VTG1_ADDR 0x3F1U

◆ REF_VTG_REF_VTG1_DEFAULT

#define REF_VTG_REF_VTG1_DEFAULT 0x00U

◆ REF_VTG_REF_VTG2_ADDR

#define REF_VTG_REF_VTG2_ADDR 0x3F2U

◆ REF_VTG_REF_VTG2_DEFAULT

#define REF_VTG_REF_VTG2_DEFAULT 0x00U

◆ REF_VTG_REF_VTG3_ADDR

#define REF_VTG_REF_VTG3_ADDR 0x3F3U

◆ REF_VTG_REF_VTG3_DEFAULT

#define REF_VTG_REF_VTG3_DEFAULT 0x00U

◆ REF_VTG_REF_VTG4_ADDR

#define REF_VTG_REF_VTG4_ADDR 0x3F4U

◆ REF_VTG_REF_VTG4_DEFAULT

#define REF_VTG_REF_VTG4_DEFAULT 0x00U

◆ REF_VTG_REF_VTG5_ADDR

#define REF_VTG_REF_VTG5_ADDR 0x3F5U

◆ REF_VTG_REF_VTG5_DEFAULT

#define REF_VTG_REF_VTG5_DEFAULT 0x00U

◆ REF_VTG_REF_VTG6_ADDR

#define REF_VTG_REF_VTG6_ADDR 0x3F6U

◆ REF_VTG_REF_VTG6_DEFAULT

#define REF_VTG_REF_VTG6_DEFAULT 0x00U

◆ REF_VTG_REF_VTG7_ADDR

#define REF_VTG_REF_VTG7_ADDR 0x3F7U

◆ REF_VTG_REF_VTG7_DEFAULT

#define REF_VTG_REF_VTG7_DEFAULT 0x00U

◆ REF_VTG_REF_VTG8_ADDR

#define REF_VTG_REF_VTG8_ADDR 0x3F8U

◆ REF_VTG_REF_VTG8_DEFAULT

#define REF_VTG_REF_VTG8_DEFAULT 0x00U

◆ REF_VTG_REF_VTG9_ADDR

#define REF_VTG_REF_VTG9_ADDR 0x3F9U

◆ REF_VTG_REF_VTG9_DEFAULT

#define REF_VTG_REF_VTG9_DEFAULT 0x1EU

◆ REF_VTG_TRIG_EN_REF_VTG_REF_VTG9_ADDR

#define REF_VTG_TRIG_EN_REF_VTG_REF_VTG9_ADDR 0x3F9U

◆ REF_VTG_TRIG_EN_REF_VTG_REF_VTG9_MASK

#define REF_VTG_TRIG_EN_REF_VTG_REF_VTG9_MASK 0x80U

◆ REF_VTG_TRIG_EN_REF_VTG_REF_VTG9_POS

#define REF_VTG_TRIG_EN_REF_VTG_REF_VTG9_POS 7U

◆ REF_VTG_TRIG_ID_REF_VTG_REF_VTG9_ADDR

#define REF_VTG_TRIG_ID_REF_VTG_REF_VTG9_ADDR 0x3F9U

◆ REF_VTG_TRIG_ID_REF_VTG_REF_VTG9_MASK

#define REF_VTG_TRIG_ID_REF_VTG_REF_VTG9_MASK 0x1FU

◆ REF_VTG_TRIG_ID_REF_VTG_REF_VTG9_POS

#define REF_VTG_TRIG_ID_REF_VTG_REF_VTG9_POS 0U

◆ REF_VTG_VTX0_ADDR

#define REF_VTG_VTX0_ADDR 0x3E0U

◆ REF_VTG_VTX0_DEFAULT

#define REF_VTG_VTX0_DEFAULT 0x70U

◆ REF_VTG_VTX10_ADDR

#define REF_VTG_VTX10_ADDR 0x3E6U

◆ REF_VTG_VTX10_DEFAULT

#define REF_VTG_VTX10_DEFAULT 0x00U

◆ REF_VTG_VTX11_ADDR

#define REF_VTG_VTX11_ADDR 0x3E7U

◆ REF_VTG_VTX11_DEFAULT

#define REF_VTG_VTX11_DEFAULT 0x00U

◆ REF_VTG_VTX12_ADDR

#define REF_VTG_VTX12_ADDR 0x3E8U

◆ REF_VTG_VTX12_DEFAULT

#define REF_VTG_VTX12_DEFAULT 0x00U

◆ REF_VTG_VTX13_ADDR

#define REF_VTG_VTX13_ADDR 0x3E9U

◆ REF_VTG_VTX13_DEFAULT

#define REF_VTG_VTX13_DEFAULT 0x00U

◆ REF_VTG_VTX14_ADDR

#define REF_VTG_VTX14_ADDR 0x3EAU

◆ REF_VTG_VTX14_DEFAULT

#define REF_VTG_VTX14_DEFAULT 0x00U

◆ REF_VTG_VTX15_ADDR

#define REF_VTG_VTX15_ADDR 0x3EBU

◆ REF_VTG_VTX15_DEFAULT

#define REF_VTG_VTX15_DEFAULT 0x00U

◆ REF_VTG_VTX16_ADDR

#define REF_VTG_VTX16_ADDR 0x3ECU

◆ REF_VTG_VTX16_DEFAULT

#define REF_VTG_VTX16_DEFAULT 0x00U

◆ REF_VTG_VTX17_ADDR

#define REF_VTG_VTX17_ADDR 0x3EDU

◆ REF_VTG_VTX17_DEFAULT

#define REF_VTG_VTX17_DEFAULT 0x00U

◆ REF_VTG_VTX18_ADDR

#define REF_VTG_VTX18_ADDR 0x3EEU

◆ REF_VTG_VTX18_DEFAULT

#define REF_VTG_VTX18_DEFAULT 0x00U

◆ REF_VTG_VTX19_ADDR

#define REF_VTG_VTX19_ADDR 0x3EFU

◆ REF_VTG_VTX19_DEFAULT

#define REF_VTG_VTX19_DEFAULT 0x00U

◆ REF_VTG_VTX5_ADDR

#define REF_VTG_VTX5_ADDR 0x3E1U

◆ REF_VTG_VTX5_DEFAULT

#define REF_VTG_VTX5_DEFAULT 0x00U

◆ REF_VTG_VTX6_ADDR

#define REF_VTG_VTX6_ADDR 0x3E2U

◆ REF_VTG_VTX6_DEFAULT

#define REF_VTG_VTX6_DEFAULT 0x00U

◆ REF_VTG_VTX7_ADDR

#define REF_VTG_VTX7_ADDR 0x3E3U

◆ REF_VTG_VTX7_DEFAULT

#define REF_VTG_VTX7_DEFAULT 0x00U

◆ REF_VTG_VTX8_ADDR

#define REF_VTG_VTX8_ADDR 0x3E4U

◆ REF_VTG_VTX8_DEFAULT

#define REF_VTG_VTX8_DEFAULT 0x00U

◆ REF_VTG_VTX9_ADDR

#define REF_VTG_VTX9_ADDR 0x3E5U

◆ REF_VTG_VTX9_DEFAULT

#define REF_VTG_VTX9_DEFAULT 0x00U

◆ REFGEN_EN_REF_VTG_REF_VTG0_ADDR

#define REFGEN_EN_REF_VTG_REF_VTG0_ADDR 0x3F0U

◆ REFGEN_EN_REF_VTG_REF_VTG0_MASK

#define REFGEN_EN_REF_VTG_REF_VTG0_MASK 0x01U

◆ REFGEN_EN_REF_VTG_REF_VTG0_POS

#define REFGEN_EN_REF_VTG_REF_VTG0_POS 0U

◆ REFGEN_FB_FRACT_H_REF_VTG_REF_VTG5_ADDR

#define REFGEN_FB_FRACT_H_REF_VTG_REF_VTG5_ADDR 0x3F5U

◆ REFGEN_FB_FRACT_H_REF_VTG_REF_VTG5_MASK

#define REFGEN_FB_FRACT_H_REF_VTG_REF_VTG5_MASK 0x0FU

◆ REFGEN_FB_FRACT_H_REF_VTG_REF_VTG5_POS

#define REFGEN_FB_FRACT_H_REF_VTG_REF_VTG5_POS 0U

◆ REFGEN_FB_FRACT_L_REF_VTG_REF_VTG4_ADDR

#define REFGEN_FB_FRACT_L_REF_VTG_REF_VTG4_ADDR 0x3F4U

◆ REFGEN_FB_FRACT_L_REF_VTG_REF_VTG4_MASK

#define REFGEN_FB_FRACT_L_REF_VTG_REF_VTG4_MASK 0xFFU

◆ REFGEN_FB_FRACT_L_REF_VTG_REF_VTG4_POS

#define REFGEN_FB_FRACT_L_REF_VTG_REF_VTG4_POS 0U

◆ REFGEN_LOCKED_REF_VTG_REF_VTG0_ADDR

#define REFGEN_LOCKED_REF_VTG_REF_VTG0_ADDR 0x3F0U

◆ REFGEN_LOCKED_REF_VTG_REF_VTG0_MASK

#define REFGEN_LOCKED_REF_VTG_REF_VTG0_MASK 0x80U

◆ REFGEN_LOCKED_REF_VTG_REF_VTG0_POS

#define REFGEN_LOCKED_REF_VTG_REF_VTG0_POS 7U

◆ REFGEN_PREDEF_EN_REF_VTG_REF_VTG0_ADDR

#define REFGEN_PREDEF_EN_REF_VTG_REF_VTG0_ADDR 0x3F0U

◆ REFGEN_PREDEF_EN_REF_VTG_REF_VTG0_MASK

#define REFGEN_PREDEF_EN_REF_VTG_REF_VTG0_MASK 0x40U

◆ REFGEN_PREDEF_EN_REF_VTG_REF_VTG0_POS

#define REFGEN_PREDEF_EN_REF_VTG_REF_VTG0_POS 6U

◆ REFGEN_PREDEF_FREQ_ALT_REF_VTG_REF_VTG0_ADDR

#define REFGEN_PREDEF_FREQ_ALT_REF_VTG_REF_VTG0_ADDR 0x3F0U

◆ REFGEN_PREDEF_FREQ_ALT_REF_VTG_REF_VTG0_MASK

#define REFGEN_PREDEF_FREQ_ALT_REF_VTG_REF_VTG0_MASK 0x08U

◆ REFGEN_PREDEF_FREQ_ALT_REF_VTG_REF_VTG0_POS

#define REFGEN_PREDEF_FREQ_ALT_REF_VTG_REF_VTG0_POS 3U

◆ REFGEN_PREDEF_FREQ_REF_VTG_REF_VTG0_ADDR

#define REFGEN_PREDEF_FREQ_REF_VTG_REF_VTG0_ADDR 0x3F0U

◆ REFGEN_PREDEF_FREQ_REF_VTG_REF_VTG0_MASK

#define REFGEN_PREDEF_FREQ_REF_VTG_REF_VTG0_MASK 0x30U

◆ REFGEN_PREDEF_FREQ_REF_VTG_REF_VTG0_POS

#define REFGEN_PREDEF_FREQ_REF_VTG_REF_VTG0_POS 4U

◆ REFGEN_RST_REF_VTG_REF_VTG0_ADDR

#define REFGEN_RST_REF_VTG_REF_VTG0_ADDR 0x3F0U

◆ REFGEN_RST_REF_VTG_REF_VTG0_MASK

#define REFGEN_RST_REF_VTG_REF_VTG0_MASK 0x02U

◆ REFGEN_RST_REF_VTG_REF_VTG0_POS

#define REFGEN_RST_REF_VTG_REF_VTG0_POS 1U

◆ REFGEN_UNLOCKED_OEN_TCTRL_INTR2_ADDR

#define REFGEN_UNLOCKED_OEN_TCTRL_INTR2_ADDR 0x1AU

◆ REFGEN_UNLOCKED_OEN_TCTRL_INTR2_MASK

#define REFGEN_UNLOCKED_OEN_TCTRL_INTR2_MASK 0x80U

◆ REFGEN_UNLOCKED_OEN_TCTRL_INTR2_POS

#define REFGEN_UNLOCKED_OEN_TCTRL_INTR2_POS 7U

◆ REFGEN_UNLOCKED_TCTRL_INTR3_ADDR

#define REFGEN_UNLOCKED_TCTRL_INTR3_ADDR 0x1BU

◆ REFGEN_UNLOCKED_TCTRL_INTR3_MASK

#define REFGEN_UNLOCKED_TCTRL_INTR3_MASK 0x80U

◆ REFGEN_UNLOCKED_TCTRL_INTR3_POS

#define REFGEN_UNLOCKED_TCTRL_INTR3_POS 7U

◆ REFLIM_FUNC_SAFE_REGADCBIST3_ADDR

#define REFLIM_FUNC_SAFE_REGADCBIST3_ADDR 0x1D31U

◆ REFLIM_FUNC_SAFE_REGADCBIST3_MASK

#define REFLIM_FUNC_SAFE_REGADCBIST3_MASK 0xFFU

◆ REFLIM_FUNC_SAFE_REGADCBIST3_POS

#define REFLIM_FUNC_SAFE_REGADCBIST3_POS 0U

◆ REFLIM_IE_AFE_ADC_INTRIE3_ADDR

#define REFLIM_IE_AFE_ADC_INTRIE3_ADDR 0x50FU

◆ REFLIM_IE_AFE_ADC_INTRIE3_MASK

#define REFLIM_IE_AFE_ADC_INTRIE3_MASK 0x40U

◆ REFLIM_IE_AFE_ADC_INTRIE3_POS

#define REFLIM_IE_AFE_ADC_INTRIE3_POS 6U

◆ REFLIM_IF_AFE_ADC_INTR3_ADDR

#define REFLIM_IF_AFE_ADC_INTR3_ADDR 0x513U

◆ REFLIM_IF_AFE_ADC_INTR3_MASK

#define REFLIM_IF_AFE_ADC_INTR3_MASK 0x40U

◆ REFLIM_IF_AFE_ADC_INTR3_POS

#define REFLIM_IF_AFE_ADC_INTR3_POS 6U

◆ REFLIMSCL1_FUNC_SAFE_REGADCBIST4_ADDR

#define REFLIMSCL1_FUNC_SAFE_REGADCBIST4_ADDR 0x1D32U

◆ REFLIMSCL1_FUNC_SAFE_REGADCBIST4_MASK

#define REFLIMSCL1_FUNC_SAFE_REGADCBIST4_MASK 0xFFU

◆ REFLIMSCL1_FUNC_SAFE_REGADCBIST4_POS

#define REFLIMSCL1_FUNC_SAFE_REGADCBIST4_POS 0U

◆ REFLIMSCL1_IE_AFE_ADC_INTRIE3_ADDR

#define REFLIMSCL1_IE_AFE_ADC_INTRIE3_ADDR 0x50FU

◆ REFLIMSCL1_IE_AFE_ADC_INTRIE3_MASK

#define REFLIMSCL1_IE_AFE_ADC_INTRIE3_MASK 0x20U

◆ REFLIMSCL1_IE_AFE_ADC_INTRIE3_POS

#define REFLIMSCL1_IE_AFE_ADC_INTRIE3_POS 5U

◆ REFLIMSCL1_IF_AFE_ADC_INTR3_ADDR

#define REFLIMSCL1_IF_AFE_ADC_INTR3_ADDR 0x513U

◆ REFLIMSCL1_IF_AFE_ADC_INTR3_MASK

#define REFLIMSCL1_IF_AFE_ADC_INTR3_MASK 0x20U

◆ REFLIMSCL1_IF_AFE_ADC_INTR3_POS

#define REFLIMSCL1_IF_AFE_ADC_INTR3_POS 5U

◆ REFLIMSCL2_FUNC_SAFE_REGADCBIST5_ADDR

#define REFLIMSCL2_FUNC_SAFE_REGADCBIST5_ADDR 0x1D33U

◆ REFLIMSCL2_FUNC_SAFE_REGADCBIST5_MASK

#define REFLIMSCL2_FUNC_SAFE_REGADCBIST5_MASK 0xFFU

◆ REFLIMSCL2_FUNC_SAFE_REGADCBIST5_POS

#define REFLIMSCL2_FUNC_SAFE_REGADCBIST5_POS 0U

◆ REFLIMSCL2_IE_AFE_ADC_INTRIE3_ADDR

#define REFLIMSCL2_IE_AFE_ADC_INTRIE3_ADDR 0x50FU

◆ REFLIMSCL2_IE_AFE_ADC_INTRIE3_MASK

#define REFLIMSCL2_IE_AFE_ADC_INTRIE3_MASK 0x10U

◆ REFLIMSCL2_IE_AFE_ADC_INTRIE3_POS

#define REFLIMSCL2_IE_AFE_ADC_INTRIE3_POS 4U

◆ REFLIMSCL2_IF_AFE_ADC_INTR3_ADDR

#define REFLIMSCL2_IF_AFE_ADC_INTR3_ADDR 0x513U

◆ REFLIMSCL2_IF_AFE_ADC_INTR3_MASK

#define REFLIMSCL2_IF_AFE_ADC_INTR3_MASK 0x10U

◆ REFLIMSCL2_IF_AFE_ADC_INTR3_POS

#define REFLIMSCL2_IF_AFE_ADC_INTR3_POS 4U

◆ REFLIMSCL3_FUNC_SAFE_REGADCBIST6_ADDR

#define REFLIMSCL3_FUNC_SAFE_REGADCBIST6_ADDR 0x1D34U

◆ REFLIMSCL3_FUNC_SAFE_REGADCBIST6_MASK

#define REFLIMSCL3_FUNC_SAFE_REGADCBIST6_MASK 0xFFU

◆ REFLIMSCL3_FUNC_SAFE_REGADCBIST6_POS

#define REFLIMSCL3_FUNC_SAFE_REGADCBIST6_POS 0U

◆ REFLIMSCL3_IE_AFE_ADC_INTRIE3_ADDR

#define REFLIMSCL3_IE_AFE_ADC_INTRIE3_ADDR 0x50FU

◆ REFLIMSCL3_IE_AFE_ADC_INTRIE3_MASK

#define REFLIMSCL3_IE_AFE_ADC_INTRIE3_MASK 0x08U

◆ REFLIMSCL3_IE_AFE_ADC_INTRIE3_POS

#define REFLIMSCL3_IE_AFE_ADC_INTRIE3_POS 3U

◆ REFLIMSCL3_IF_AFE_ADC_INTR3_ADDR

#define REFLIMSCL3_IF_AFE_ADC_INTR3_ADDR 0x513U

◆ REFLIMSCL3_IF_AFE_ADC_INTR3_MASK

#define REFLIMSCL3_IF_AFE_ADC_INTR3_MASK 0x08U

◆ REFLIMSCL3_IF_AFE_ADC_INTR3_POS

#define REFLIMSCL3_IF_AFE_ADC_INTR3_POS 3U

◆ REG_CRC_ERR_FLAG_FUNC_SAFE_FS_INTR1_ADDR

#define REG_CRC_ERR_FLAG_FUNC_SAFE_FS_INTR1_ADDR 0x1D13U

◆ REG_CRC_ERR_FLAG_FUNC_SAFE_FS_INTR1_MASK

#define REG_CRC_ERR_FLAG_FUNC_SAFE_FS_INTR1_MASK 0x01U

◆ REG_CRC_ERR_FLAG_FUNC_SAFE_FS_INTR1_POS

#define REG_CRC_ERR_FLAG_FUNC_SAFE_FS_INTR1_POS 0U

◆ REG_CRC_ERR_OEN_FUNC_SAFE_FS_INTR0_ADDR

#define REG_CRC_ERR_OEN_FUNC_SAFE_FS_INTR0_ADDR 0x1D12U

◆ REG_CRC_ERR_OEN_FUNC_SAFE_FS_INTR0_MASK

#define REG_CRC_ERR_OEN_FUNC_SAFE_FS_INTR0_MASK 0x01U

◆ REG_CRC_ERR_OEN_FUNC_SAFE_FS_INTR0_POS

#define REG_CRC_ERR_OEN_FUNC_SAFE_FS_INTR0_POS 0U

◆ REGCRC_LSB_FUNC_SAFE_REGCRC2_ADDR

#define REGCRC_LSB_FUNC_SAFE_REGCRC2_ADDR 0x1D02U

◆ REGCRC_LSB_FUNC_SAFE_REGCRC2_MASK

#define REGCRC_LSB_FUNC_SAFE_REGCRC2_MASK 0xFFU

◆ REGCRC_LSB_FUNC_SAFE_REGCRC2_POS

#define REGCRC_LSB_FUNC_SAFE_REGCRC2_POS 0U

◆ REGCRC_MSB_FUNC_SAFE_REGCRC3_ADDR

#define REGCRC_MSB_FUNC_SAFE_REGCRC3_ADDR 0x1D03U

◆ REGCRC_MSB_FUNC_SAFE_REGCRC3_MASK

#define REGCRC_MSB_FUNC_SAFE_REGCRC3_MASK 0xFFU

◆ REGCRC_MSB_FUNC_SAFE_REGCRC3_POS

#define REGCRC_MSB_FUNC_SAFE_REGCRC3_POS 0U

◆ REM_ERR_FLAG_TCTRL_INTR3_ADDR

#define REM_ERR_FLAG_TCTRL_INTR3_ADDR 0x1BU

◆ REM_ERR_FLAG_TCTRL_INTR3_MASK

#define REM_ERR_FLAG_TCTRL_INTR3_MASK 0x20U

◆ REM_ERR_FLAG_TCTRL_INTR3_POS

#define REM_ERR_FLAG_TCTRL_INTR3_POS 5U

◆ REM_ERR_OEN_TCTRL_INTR2_ADDR

#define REM_ERR_OEN_TCTRL_INTR2_ADDR 0x1AU

◆ REM_ERR_OEN_TCTRL_INTR2_MASK

#define REM_ERR_OEN_TCTRL_INTR2_MASK 0x20U

◆ REM_ERR_OEN_TCTRL_INTR2_POS

#define REM_ERR_OEN_TCTRL_INTR2_POS 5U

◆ REM_MS_EN_CC_UART_0_ADDR

#define REM_MS_EN_CC_UART_0_ADDR 0x48U

◆ REM_MS_EN_CC_UART_0_MASK

#define REM_MS_EN_CC_UART_0_MASK 0x20U

◆ REM_MS_EN_CC_UART_0_POS

#define REM_MS_EN_CC_UART_0_POS 5U

◆ REQ_HOLD_OFF_SPI_SPI_2_ADDR

#define REQ_HOLD_OFF_SPI_SPI_2_ADDR 0x172U

◆ REQ_HOLD_OFF_SPI_SPI_2_MASK

#define REQ_HOLD_OFF_SPI_SPI_2_MASK 0xE0U

◆ REQ_HOLD_OFF_SPI_SPI_2_POS

#define REQ_HOLD_OFF_SPI_SPI_2_POS 5U

◆ REQ_HOLD_OFF_TO_SPI_SPI_8_ADDR

#define REQ_HOLD_OFF_TO_SPI_SPI_8_ADDR 0x178U

◆ REQ_HOLD_OFF_TO_SPI_SPI_8_MASK

#define REQ_HOLD_OFF_TO_SPI_SPI_8_MASK 0xFFU

◆ REQ_HOLD_OFF_TO_SPI_SPI_8_POS

#define REQ_HOLD_OFF_TO_SPI_SPI_8_POS 0U

◆ RES_CFG_GPIO0_0_GPIO_A_ADDR

#define RES_CFG_GPIO0_0_GPIO_A_ADDR 0x2BEU

◆ RES_CFG_GPIO0_0_GPIO_A_MASK

#define RES_CFG_GPIO0_0_GPIO_A_MASK 0x80U

◆ RES_CFG_GPIO0_0_GPIO_A_POS

#define RES_CFG_GPIO0_0_GPIO_A_POS 7U

◆ RES_CFG_GPIO10_10_GPIO_A_ADDR

#define RES_CFG_GPIO10_10_GPIO_A_ADDR 0x2DCU

◆ RES_CFG_GPIO10_10_GPIO_A_MASK

#define RES_CFG_GPIO10_10_GPIO_A_MASK 0x80U

◆ RES_CFG_GPIO10_10_GPIO_A_POS

#define RES_CFG_GPIO10_10_GPIO_A_POS 7U

◆ RES_CFG_GPIO1_1_GPIO_A_ADDR

#define RES_CFG_GPIO1_1_GPIO_A_ADDR 0x2C1U

◆ RES_CFG_GPIO1_1_GPIO_A_MASK

#define RES_CFG_GPIO1_1_GPIO_A_MASK 0x80U

◆ RES_CFG_GPIO1_1_GPIO_A_POS

#define RES_CFG_GPIO1_1_GPIO_A_POS 7U

◆ RES_CFG_GPIO2_2_GPIO_A_ADDR

#define RES_CFG_GPIO2_2_GPIO_A_ADDR 0x2C4U

◆ RES_CFG_GPIO2_2_GPIO_A_MASK

#define RES_CFG_GPIO2_2_GPIO_A_MASK 0x80U

◆ RES_CFG_GPIO2_2_GPIO_A_POS

#define RES_CFG_GPIO2_2_GPIO_A_POS 7U

◆ RES_CFG_GPIO3_3_GPIO_A_ADDR

#define RES_CFG_GPIO3_3_GPIO_A_ADDR 0x2C7U

◆ RES_CFG_GPIO3_3_GPIO_A_MASK

#define RES_CFG_GPIO3_3_GPIO_A_MASK 0x80U

◆ RES_CFG_GPIO3_3_GPIO_A_POS

#define RES_CFG_GPIO3_3_GPIO_A_POS 7U

◆ RES_CFG_GPIO4_4_GPIO_A_ADDR

#define RES_CFG_GPIO4_4_GPIO_A_ADDR 0x2CAU

◆ RES_CFG_GPIO4_4_GPIO_A_MASK

#define RES_CFG_GPIO4_4_GPIO_A_MASK 0x80U

◆ RES_CFG_GPIO4_4_GPIO_A_POS

#define RES_CFG_GPIO4_4_GPIO_A_POS 7U

◆ RES_CFG_GPIO5_5_GPIO_A_ADDR

#define RES_CFG_GPIO5_5_GPIO_A_ADDR 0x2CDU

◆ RES_CFG_GPIO5_5_GPIO_A_MASK

#define RES_CFG_GPIO5_5_GPIO_A_MASK 0x80U

◆ RES_CFG_GPIO5_5_GPIO_A_POS

#define RES_CFG_GPIO5_5_GPIO_A_POS 7U

◆ RES_CFG_GPIO6_6_GPIO_A_ADDR

#define RES_CFG_GPIO6_6_GPIO_A_ADDR 0x2D0U

◆ RES_CFG_GPIO6_6_GPIO_A_MASK

#define RES_CFG_GPIO6_6_GPIO_A_MASK 0x80U

◆ RES_CFG_GPIO6_6_GPIO_A_POS

#define RES_CFG_GPIO6_6_GPIO_A_POS 7U

◆ RES_CFG_GPIO7_7_GPIO_A_ADDR

#define RES_CFG_GPIO7_7_GPIO_A_ADDR 0x2D3U

◆ RES_CFG_GPIO7_7_GPIO_A_MASK

#define RES_CFG_GPIO7_7_GPIO_A_MASK 0x80U

◆ RES_CFG_GPIO7_7_GPIO_A_POS

#define RES_CFG_GPIO7_7_GPIO_A_POS 7U

◆ RES_CFG_GPIO8_8_GPIO_A_ADDR

#define RES_CFG_GPIO8_8_GPIO_A_ADDR 0x2D6U

◆ RES_CFG_GPIO8_8_GPIO_A_MASK

#define RES_CFG_GPIO8_8_GPIO_A_MASK 0x80U

◆ RES_CFG_GPIO8_8_GPIO_A_POS

#define RES_CFG_GPIO8_8_GPIO_A_POS 7U

◆ RES_CFG_GPIO9_9_GPIO_A_ADDR

#define RES_CFG_GPIO9_9_GPIO_A_ADDR 0x2D9U

◆ RES_CFG_GPIO9_9_GPIO_A_MASK

#define RES_CFG_GPIO9_9_GPIO_A_MASK 0x80U

◆ RES_CFG_GPIO9_9_GPIO_A_POS

#define RES_CFG_GPIO9_9_GPIO_A_POS 7U

◆ RESET_ALL_TCTRL_CTRL0_ADDR

#define RESET_ALL_TCTRL_CTRL0_ADDR 0x10U

◆ RESET_ALL_TCTRL_CTRL0_MASK

#define RESET_ALL_TCTRL_CTRL0_MASK 0x80U

◆ RESET_ALL_TCTRL_CTRL0_POS

#define RESET_ALL_TCTRL_CTRL0_POS 7U

◆ RESET_CRC_ERR_CNT_FUNC_SAFE_I2C_UART_CRC1_ADDR

#define RESET_CRC_ERR_CNT_FUNC_SAFE_I2C_UART_CRC1_ADDR 0x1D09U

◆ RESET_CRC_ERR_CNT_FUNC_SAFE_I2C_UART_CRC1_MASK

#define RESET_CRC_ERR_CNT_FUNC_SAFE_I2C_UART_CRC1_MASK 0x01U

◆ RESET_CRC_ERR_CNT_FUNC_SAFE_I2C_UART_CRC1_POS

#define RESET_CRC_ERR_CNT_FUNC_SAFE_I2C_UART_CRC1_POS 0U

◆ RESET_CRC_FUNC_SAFE_REGCRC0_ADDR

#define RESET_CRC_FUNC_SAFE_REGCRC0_ADDR 0x1D00U

◆ RESET_CRC_FUNC_SAFE_REGCRC0_MASK

#define RESET_CRC_FUNC_SAFE_REGCRC0_MASK 0x01U

◆ RESET_CRC_FUNC_SAFE_REGCRC0_POS

#define RESET_CRC_FUNC_SAFE_REGCRC0_POS 0U

◆ RESET_EFUSE_CRC_ERR_FUNC_SAFE_CC_RTTN_ERR_ADDR

#define RESET_EFUSE_CRC_ERR_FUNC_SAFE_CC_RTTN_ERR_ADDR 0x1D5FU

◆ RESET_EFUSE_CRC_ERR_FUNC_SAFE_CC_RTTN_ERR_MASK

#define RESET_EFUSE_CRC_ERR_FUNC_SAFE_CC_RTTN_ERR_MASK 0x04U

◆ RESET_EFUSE_CRC_ERR_FUNC_SAFE_CC_RTTN_ERR_POS

#define RESET_EFUSE_CRC_ERR_FUNC_SAFE_CC_RTTN_ERR_POS 2U

◆ RESET_LINK_TCTRL_CTRL0_ADDR

#define RESET_LINK_TCTRL_CTRL0_ADDR 0x10U

◆ RESET_LINK_TCTRL_CTRL0_MASK

#define RESET_LINK_TCTRL_CTRL0_MASK 0x40U

◆ RESET_LINK_TCTRL_CTRL0_POS

#define RESET_LINK_TCTRL_CTRL0_POS 6U

◆ RESET_MEM_ECC_ERR1_CNT_FUNC_SAFE_MEM_ECC0_ADDR

#define RESET_MEM_ECC_ERR1_CNT_FUNC_SAFE_MEM_ECC0_ADDR 0x1D14U

◆ RESET_MEM_ECC_ERR1_CNT_FUNC_SAFE_MEM_ECC0_MASK

#define RESET_MEM_ECC_ERR1_CNT_FUNC_SAFE_MEM_ECC0_MASK 0x01U

◆ RESET_MEM_ECC_ERR1_CNT_FUNC_SAFE_MEM_ECC0_POS

#define RESET_MEM_ECC_ERR1_CNT_FUNC_SAFE_MEM_ECC0_POS 0U

◆ RESET_MEM_ECC_ERR2_CNT_FUNC_SAFE_MEM_ECC0_ADDR

#define RESET_MEM_ECC_ERR2_CNT_FUNC_SAFE_MEM_ECC0_ADDR 0x1D14U

◆ RESET_MEM_ECC_ERR2_CNT_FUNC_SAFE_MEM_ECC0_MASK

#define RESET_MEM_ECC_ERR2_CNT_FUNC_SAFE_MEM_ECC0_MASK 0x02U

◆ RESET_MEM_ECC_ERR2_CNT_FUNC_SAFE_MEM_ECC0_POS

#define RESET_MEM_ECC_ERR2_CNT_FUNC_SAFE_MEM_ECC0_POS 1U

◆ RESET_MSGCNTR_ERR_CNT_FUNC_SAFE_I2C_UART_CRC1_ADDR

#define RESET_MSGCNTR_ERR_CNT_FUNC_SAFE_I2C_UART_CRC1_ADDR 0x1D09U

◆ RESET_MSGCNTR_ERR_CNT_FUNC_SAFE_I2C_UART_CRC1_MASK

#define RESET_MSGCNTR_ERR_CNT_FUNC_SAFE_I2C_UART_CRC1_MASK 0x02U

◆ RESET_MSGCNTR_ERR_CNT_FUNC_SAFE_I2C_UART_CRC1_POS

#define RESET_MSGCNTR_ERR_CNT_FUNC_SAFE_I2C_UART_CRC1_POS 1U

◆ RESET_MSGCNTR_FUNC_SAFE_I2C_UART_CRC0_ADDR

#define RESET_MSGCNTR_FUNC_SAFE_I2C_UART_CRC0_ADDR 0x1D08U

◆ RESET_MSGCNTR_FUNC_SAFE_I2C_UART_CRC0_MASK

#define RESET_MSGCNTR_FUNC_SAFE_I2C_UART_CRC0_MASK 0x01U

◆ RESET_MSGCNTR_FUNC_SAFE_I2C_UART_CRC0_POS

#define RESET_MSGCNTR_FUNC_SAFE_I2C_UART_CRC0_POS 0U

◆ RESET_ONESHOT_TCTRL_CTRL0_ADDR

#define RESET_ONESHOT_TCTRL_CTRL0_ADDR 0x10U

◆ RESET_ONESHOT_TCTRL_CTRL0_MASK

#define RESET_ONESHOT_TCTRL_CTRL0_MASK 0x20U

◆ RESET_ONESHOT_TCTRL_CTRL0_POS

#define RESET_ONESHOT_TCTRL_CTRL0_POS 5U

◆ RLMS_A_RLMS17_ADDR

#define RLMS_A_RLMS17_ADDR 0x1417U

◆ RLMS_A_RLMS17_DEFAULT

#define RLMS_A_RLMS17_DEFAULT 0x00U

◆ RLMS_A_RLMS1C_ADDR

#define RLMS_A_RLMS1C_ADDR 0x141CU

◆ RLMS_A_RLMS1C_DEFAULT

#define RLMS_A_RLMS1C_DEFAULT 0x00U

◆ RLMS_A_RLMS1D_ADDR

#define RLMS_A_RLMS1D_ADDR 0x141DU

◆ RLMS_A_RLMS1D_DEFAULT

#define RLMS_A_RLMS1D_DEFAULT 0x02U

◆ RLMS_A_RLMS1F_ADDR

#define RLMS_A_RLMS1F_ADDR 0x141FU

◆ RLMS_A_RLMS1F_DEFAULT

#define RLMS_A_RLMS1F_DEFAULT 0x00U

◆ RLMS_A_RLMS32_ADDR

#define RLMS_A_RLMS32_ADDR 0x1432U

◆ RLMS_A_RLMS32_DEFAULT

#define RLMS_A_RLMS32_DEFAULT 0x7FU

◆ RLMS_A_RLMS3A_ADDR

#define RLMS_A_RLMS3A_ADDR 0x143AU

◆ RLMS_A_RLMS3A_DEFAULT

#define RLMS_A_RLMS3A_DEFAULT 0x00U

◆ RLMS_A_RLMS3B_ADDR

#define RLMS_A_RLMS3B_ADDR 0x143BU

◆ RLMS_A_RLMS3B_DEFAULT

#define RLMS_A_RLMS3B_DEFAULT 0x00U

◆ RLMS_A_RLMS4_ADDR

#define RLMS_A_RLMS4_ADDR 0x1404U

◆ RLMS_A_RLMS4_DEFAULT

#define RLMS_A_RLMS4_DEFAULT 0x4BU

◆ RLMS_A_RLMS5_ADDR

#define RLMS_A_RLMS5_ADDR 0x1405U

◆ RLMS_A_RLMS5_DEFAULT

#define RLMS_A_RLMS5_DEFAULT 0x10U

◆ RLMS_A_RLMS64_ADDR

#define RLMS_A_RLMS64_ADDR 0x1464U

◆ RLMS_A_RLMS64_DEFAULT

#define RLMS_A_RLMS64_DEFAULT 0x90U

◆ RLMS_A_RLMS6_ADDR

#define RLMS_A_RLMS6_ADDR 0x1406U

◆ RLMS_A_RLMS6_DEFAULT

#define RLMS_A_RLMS6_DEFAULT 0x80U

◆ RLMS_A_RLMS70_ADDR

#define RLMS_A_RLMS70_ADDR 0x1470U

◆ RLMS_A_RLMS70_DEFAULT

#define RLMS_A_RLMS70_DEFAULT 0x01U

◆ RLMS_A_RLMS71_ADDR

#define RLMS_A_RLMS71_ADDR 0x1471U

◆ RLMS_A_RLMS71_DEFAULT

#define RLMS_A_RLMS71_DEFAULT 0x02U

◆ RLMS_A_RLMS72_ADDR

#define RLMS_A_RLMS72_ADDR 0x1472U

◆ RLMS_A_RLMS72_DEFAULT

#define RLMS_A_RLMS72_DEFAULT 0xCFU

◆ RLMS_A_RLMS73_ADDR

#define RLMS_A_RLMS73_ADDR 0x1473U

◆ RLMS_A_RLMS73_DEFAULT

#define RLMS_A_RLMS73_DEFAULT 0x00U

◆ RLMS_A_RLMS74_ADDR

#define RLMS_A_RLMS74_ADDR 0x1474U

◆ RLMS_A_RLMS74_DEFAULT

#define RLMS_A_RLMS74_DEFAULT 0x00U

◆ RLMS_A_RLMS75_ADDR

#define RLMS_A_RLMS75_ADDR 0x1475U

◆ RLMS_A_RLMS75_DEFAULT

#define RLMS_A_RLMS75_DEFAULT 0x00U

◆ RLMS_A_RLMS76_ADDR

#define RLMS_A_RLMS76_ADDR 0x1476U

◆ RLMS_A_RLMS76_DEFAULT

#define RLMS_A_RLMS76_DEFAULT 0x00U

◆ RLMS_A_RLMS7_ADDR

#define RLMS_A_RLMS7_ADDR 0x1407U

◆ RLMS_A_RLMS7_DEFAULT

#define RLMS_A_RLMS7_DEFAULT 0x00U

◆ RLMS_A_RLMSA8_ADDR

#define RLMS_A_RLMSA8_ADDR 0x14A8U

◆ RLMS_A_RLMSA8_DEFAULT

#define RLMS_A_RLMSA8_DEFAULT 0x00U

◆ RLMS_A_RLMSA9_ADDR

#define RLMS_A_RLMSA9_ADDR 0x14A9U

◆ RLMS_A_RLMSA9_DEFAULT

#define RLMS_A_RLMSA9_DEFAULT 0x00U

◆ RLMS_A_RLMSAA_ADDR

#define RLMS_A_RLMSAA_ADDR 0x14AAU

◆ RLMS_A_RLMSAA_DEFAULT

#define RLMS_A_RLMSAA_DEFAULT 0x90U

◆ RLMS_A_RLMSCE_ADDR

#define RLMS_A_RLMSCE_ADDR 0x14CEU

◆ RLMS_A_RLMSCE_DEFAULT

#define RLMS_A_RLMSCE_DEFAULT 0x01U

◆ ROR_CLK_DET_RLMS_A_RLMSAA_ADDR

#define ROR_CLK_DET_RLMS_A_RLMSAA_ADDR 0x14AAU

◆ ROR_CLK_DET_RLMS_A_RLMSAA_MASK

#define ROR_CLK_DET_RLMS_A_RLMSAA_MASK 0x20U

◆ ROR_CLK_DET_RLMS_A_RLMSAA_POS

#define ROR_CLK_DET_RLMS_A_RLMSAA_POS 5U

◆ RR_ACCURACY_FUNC_SAFE_REGADCBIST0_ADDR

#define RR_ACCURACY_FUNC_SAFE_REGADCBIST0_ADDR 0x1D28U

◆ RR_ACCURACY_FUNC_SAFE_REGADCBIST0_MASK

#define RR_ACCURACY_FUNC_SAFE_REGADCBIST0_MASK 0x80U

◆ RR_ACCURACY_FUNC_SAFE_REGADCBIST0_POS

#define RR_ACCURACY_FUNC_SAFE_REGADCBIST0_POS 7U

◆ RT_CNT_CFGL_GPIO_ARQ2_ADDR

#define RT_CNT_CFGL_GPIO_ARQ2_ADDR 0x97U

◆ RT_CNT_CFGL_GPIO_ARQ2_MASK

#define RT_CNT_CFGL_GPIO_ARQ2_MASK 0x7FU

◆ RT_CNT_CFGL_GPIO_ARQ2_POS

#define RT_CNT_CFGL_GPIO_ARQ2_POS 0U

◆ RT_CNT_CFGL_IIC_X_ARQ2_ADDR

#define RT_CNT_CFGL_IIC_X_ARQ2_ADDR 0xA7U

◆ RT_CNT_CFGL_IIC_X_ARQ2_MASK

#define RT_CNT_CFGL_IIC_X_ARQ2_MASK 0x7FU

◆ RT_CNT_CFGL_IIC_X_ARQ2_POS

#define RT_CNT_CFGL_IIC_X_ARQ2_POS 0U

◆ RT_CNT_CFGL_IIC_Y_ARQ2_ADDR

#define RT_CNT_CFGL_IIC_Y_ARQ2_ADDR 0xAFU

◆ RT_CNT_CFGL_IIC_Y_ARQ2_MASK

#define RT_CNT_CFGL_IIC_Y_ARQ2_MASK 0x7FU

◆ RT_CNT_CFGL_IIC_Y_ARQ2_POS

#define RT_CNT_CFGL_IIC_Y_ARQ2_POS 0U

◆ RT_CNT_CFGL_SPI_ARQ2_ADDR

#define RT_CNT_CFGL_SPI_ARQ2_ADDR 0x87U

◆ RT_CNT_CFGL_SPI_ARQ2_MASK

#define RT_CNT_CFGL_SPI_ARQ2_MASK 0x7FU

◆ RT_CNT_CFGL_SPI_ARQ2_POS

#define RT_CNT_CFGL_SPI_ARQ2_POS 0U

◆ RT_CNT_FLAG_TCTRL_INTR5_ADDR

#define RT_CNT_FLAG_TCTRL_INTR5_ADDR 0x1DU

◆ RT_CNT_FLAG_TCTRL_INTR5_MASK

#define RT_CNT_FLAG_TCTRL_INTR5_MASK 0x04U

◆ RT_CNT_FLAG_TCTRL_INTR5_POS

#define RT_CNT_FLAG_TCTRL_INTR5_POS 2U

◆ RT_CNT_OEN_CFGL_GPIO_ARQ1_ADDR

#define RT_CNT_OEN_CFGL_GPIO_ARQ1_ADDR 0x96U

◆ RT_CNT_OEN_CFGL_GPIO_ARQ1_MASK

#define RT_CNT_OEN_CFGL_GPIO_ARQ1_MASK 0x01U

◆ RT_CNT_OEN_CFGL_GPIO_ARQ1_POS

#define RT_CNT_OEN_CFGL_GPIO_ARQ1_POS 0U

◆ RT_CNT_OEN_CFGL_IIC_X_ARQ1_ADDR

#define RT_CNT_OEN_CFGL_IIC_X_ARQ1_ADDR 0xA6U

◆ RT_CNT_OEN_CFGL_IIC_X_ARQ1_MASK

#define RT_CNT_OEN_CFGL_IIC_X_ARQ1_MASK 0x01U

◆ RT_CNT_OEN_CFGL_IIC_X_ARQ1_POS

#define RT_CNT_OEN_CFGL_IIC_X_ARQ1_POS 0U

◆ RT_CNT_OEN_CFGL_IIC_Y_ARQ1_ADDR

#define RT_CNT_OEN_CFGL_IIC_Y_ARQ1_ADDR 0xAEU

◆ RT_CNT_OEN_CFGL_IIC_Y_ARQ1_MASK

#define RT_CNT_OEN_CFGL_IIC_Y_ARQ1_MASK 0x01U

◆ RT_CNT_OEN_CFGL_IIC_Y_ARQ1_POS

#define RT_CNT_OEN_CFGL_IIC_Y_ARQ1_POS 0U

◆ RT_CNT_OEN_CFGL_SPI_ARQ1_ADDR

#define RT_CNT_OEN_CFGL_SPI_ARQ1_ADDR 0x86U

◆ RT_CNT_OEN_CFGL_SPI_ARQ1_MASK

#define RT_CNT_OEN_CFGL_SPI_ARQ1_MASK 0x01U

◆ RT_CNT_OEN_CFGL_SPI_ARQ1_POS

#define RT_CNT_OEN_CFGL_SPI_ARQ1_POS 0U

◆ RT_CNT_OEN_TCTRL_INTR4_ADDR

#define RT_CNT_OEN_TCTRL_INTR4_ADDR 0x1CU

◆ RT_CNT_OEN_TCTRL_INTR4_MASK

#define RT_CNT_OEN_TCTRL_INTR4_MASK 0x04U

◆ RT_CNT_OEN_TCTRL_INTR4_POS

#define RT_CNT_OEN_TCTRL_INTR4_POS 2U

◆ RTTN_CRC_ERR_OEN_TCTRL_INTR6_ADDR

#define RTTN_CRC_ERR_OEN_TCTRL_INTR6_ADDR 0x1EU

◆ RTTN_CRC_ERR_OEN_TCTRL_INTR6_MASK

#define RTTN_CRC_ERR_OEN_TCTRL_INTR6_MASK 0x08U

◆ RTTN_CRC_ERR_OEN_TCTRL_INTR6_POS

#define RTTN_CRC_ERR_OEN_TCTRL_INTR6_POS 3U

◆ RTTN_CRC_INT_TCTRL_INTR7_ADDR

#define RTTN_CRC_INT_TCTRL_INTR7_ADDR 0x1FU

◆ RTTN_CRC_INT_TCTRL_INTR7_MASK

#define RTTN_CRC_INT_TCTRL_INTR7_MASK 0x08U

◆ RTTN_CRC_INT_TCTRL_INTR7_POS

#define RTTN_CRC_INT_TCTRL_INTR7_POS 3U

◆ RUN_ACCURACY_FUNC_SAFE_REGADCBIST0_ADDR

#define RUN_ACCURACY_FUNC_SAFE_REGADCBIST0_ADDR 0x1D28U

◆ RUN_ACCURACY_FUNC_SAFE_REGADCBIST0_MASK

#define RUN_ACCURACY_FUNC_SAFE_REGADCBIST0_MASK 0x04U

◆ RUN_ACCURACY_FUNC_SAFE_REGADCBIST0_POS

#define RUN_ACCURACY_FUNC_SAFE_REGADCBIST0_POS 2U

◆ RUN_TMON_CAL_FUNC_SAFE_REGADCBIST0_ADDR

#define RUN_TMON_CAL_FUNC_SAFE_REGADCBIST0_ADDR 0x1D28U

◆ RUN_TMON_CAL_FUNC_SAFE_REGADCBIST0_MASK

#define RUN_TMON_CAL_FUNC_SAFE_REGADCBIST0_MASK 0x01U

◆ RUN_TMON_CAL_FUNC_SAFE_REGADCBIST0_POS

#define RUN_TMON_CAL_FUNC_SAFE_REGADCBIST0_POS 0U

◆ RWN_IO_EN_SPI_SPI_6_ADDR

#define RWN_IO_EN_SPI_SPI_6_ADDR 0x176U

◆ RWN_IO_EN_SPI_SPI_6_MASK

#define RWN_IO_EN_SPI_SPI_6_MASK 0x01U

◆ RWN_IO_EN_SPI_SPI_6_POS

#define RWN_IO_EN_SPI_SPI_6_POS 0U

◆ RX_CRC_EN_CFGI_INFOFR_TR0_ADDR

#define RX_CRC_EN_CFGI_INFOFR_TR0_ADDR 0x78U

◆ RX_CRC_EN_CFGI_INFOFR_TR0_MASK

#define RX_CRC_EN_CFGI_INFOFR_TR0_MASK 0x40U

◆ RX_CRC_EN_CFGI_INFOFR_TR0_POS

#define RX_CRC_EN_CFGI_INFOFR_TR0_POS 6U

◆ RX_CRC_EN_CFGL_GPIO_TR0_ADDR

#define RX_CRC_EN_CFGL_GPIO_TR0_ADDR 0x90U

◆ RX_CRC_EN_CFGL_GPIO_TR0_MASK

#define RX_CRC_EN_CFGL_GPIO_TR0_MASK 0x40U

◆ RX_CRC_EN_CFGL_GPIO_TR0_POS

#define RX_CRC_EN_CFGL_GPIO_TR0_POS 6U

◆ RX_CRC_EN_CFGL_IIC_X_TR0_ADDR

#define RX_CRC_EN_CFGL_IIC_X_TR0_ADDR 0xA0U

◆ RX_CRC_EN_CFGL_IIC_X_TR0_MASK

#define RX_CRC_EN_CFGL_IIC_X_TR0_MASK 0x40U

◆ RX_CRC_EN_CFGL_IIC_X_TR0_POS

#define RX_CRC_EN_CFGL_IIC_X_TR0_POS 6U

◆ RX_CRC_EN_CFGL_IIC_Y_TR0_ADDR

#define RX_CRC_EN_CFGL_IIC_Y_TR0_ADDR 0xA8U

◆ RX_CRC_EN_CFGL_IIC_Y_TR0_MASK

#define RX_CRC_EN_CFGL_IIC_Y_TR0_MASK 0x40U

◆ RX_CRC_EN_CFGL_IIC_Y_TR0_POS

#define RX_CRC_EN_CFGL_IIC_Y_TR0_POS 6U

◆ RX_CRC_EN_CFGL_SPI_TR0_ADDR

#define RX_CRC_EN_CFGL_SPI_TR0_ADDR 0x80U

◆ RX_CRC_EN_CFGL_SPI_TR0_MASK

#define RX_CRC_EN_CFGL_SPI_TR0_MASK 0x40U

◆ RX_CRC_EN_CFGL_SPI_TR0_POS

#define RX_CRC_EN_CFGL_SPI_TR0_POS 6U

◆ RX_FEC_EN_GMSL_TX0_ADDR

#define RX_FEC_EN_GMSL_TX0_ADDR (0x28U)

◆ RX_FEC_EN_GMSL_TX0_MASK

#define RX_FEC_EN_GMSL_TX0_MASK (0x01U)

◆ RX_FEC_EN_GMSL_TX0_POS

#define RX_FEC_EN_GMSL_TX0_POS (0U)

◆ RX_RATE_DEV_REG1_ADDR

#define RX_RATE_DEV_REG1_ADDR 0x01U

◆ RX_RATE_DEV_REG1_MASK

#define RX_RATE_DEV_REG1_MASK 0x03U

◆ RX_RATE_DEV_REG1_POS

#define RX_RATE_DEV_REG1_POS 0U

◆ RX_SRC_SEL_CFGI_INFOFR_TR4_ADDR

#define RX_SRC_SEL_CFGI_INFOFR_TR4_ADDR 0x7CU

◆ RX_SRC_SEL_CFGI_INFOFR_TR4_MASK

#define RX_SRC_SEL_CFGI_INFOFR_TR4_MASK 0xFFU

◆ RX_SRC_SEL_CFGI_INFOFR_TR4_POS

#define RX_SRC_SEL_CFGI_INFOFR_TR4_POS 0U

◆ RX_SRC_SEL_CFGL_GPIO_TR4_ADDR

#define RX_SRC_SEL_CFGL_GPIO_TR4_ADDR 0x94U

◆ RX_SRC_SEL_CFGL_GPIO_TR4_MASK

#define RX_SRC_SEL_CFGL_GPIO_TR4_MASK 0xFFU

◆ RX_SRC_SEL_CFGL_GPIO_TR4_POS

#define RX_SRC_SEL_CFGL_GPIO_TR4_POS 0U

◆ RX_SRC_SEL_CFGL_IIC_X_TR4_ADDR

#define RX_SRC_SEL_CFGL_IIC_X_TR4_ADDR 0xA4U

◆ RX_SRC_SEL_CFGL_IIC_X_TR4_MASK

#define RX_SRC_SEL_CFGL_IIC_X_TR4_MASK 0xFFU

◆ RX_SRC_SEL_CFGL_IIC_X_TR4_POS

#define RX_SRC_SEL_CFGL_IIC_X_TR4_POS 0U

◆ RX_SRC_SEL_CFGL_IIC_Y_TR4_ADDR

#define RX_SRC_SEL_CFGL_IIC_Y_TR4_ADDR 0xACU

◆ RX_SRC_SEL_CFGL_IIC_Y_TR4_MASK

#define RX_SRC_SEL_CFGL_IIC_Y_TR4_MASK 0xFFU

◆ RX_SRC_SEL_CFGL_IIC_Y_TR4_POS

#define RX_SRC_SEL_CFGL_IIC_Y_TR4_POS 0U

◆ RX_SRC_SEL_CFGL_SPI_TR4_ADDR

#define RX_SRC_SEL_CFGL_SPI_TR4_ADDR 0x84U

◆ RX_SRC_SEL_CFGL_SPI_TR4_MASK

#define RX_SRC_SEL_CFGL_SPI_TR4_MASK 0xFFU

◆ RX_SRC_SEL_CFGL_SPI_TR4_POS

#define RX_SRC_SEL_CFGL_SPI_TR4_POS 0U

◆ SERIAL_NUMBER_0_EFUSE_EFUSE80_ADDR

#define SERIAL_NUMBER_0_EFUSE_EFUSE80_ADDR 0x1C50U

◆ SERIAL_NUMBER_0_EFUSE_EFUSE80_MASK

#define SERIAL_NUMBER_0_EFUSE_EFUSE80_MASK 0xFFU

◆ SERIAL_NUMBER_0_EFUSE_EFUSE80_POS

#define SERIAL_NUMBER_0_EFUSE_EFUSE80_POS 0U

◆ SERIAL_NUMBER_10_EFUSE_EFUSE90_ADDR

#define SERIAL_NUMBER_10_EFUSE_EFUSE90_ADDR 0x1C5AU

◆ SERIAL_NUMBER_10_EFUSE_EFUSE90_MASK

#define SERIAL_NUMBER_10_EFUSE_EFUSE90_MASK 0xFFU

◆ SERIAL_NUMBER_10_EFUSE_EFUSE90_POS

#define SERIAL_NUMBER_10_EFUSE_EFUSE90_POS 0U

◆ SERIAL_NUMBER_11_EFUSE_EFUSE91_ADDR

#define SERIAL_NUMBER_11_EFUSE_EFUSE91_ADDR 0x1C5BU

◆ SERIAL_NUMBER_11_EFUSE_EFUSE91_MASK

#define SERIAL_NUMBER_11_EFUSE_EFUSE91_MASK 0xFFU

◆ SERIAL_NUMBER_11_EFUSE_EFUSE91_POS

#define SERIAL_NUMBER_11_EFUSE_EFUSE91_POS 0U

◆ SERIAL_NUMBER_12_EFUSE_EFUSE92_ADDR

#define SERIAL_NUMBER_12_EFUSE_EFUSE92_ADDR 0x1C5CU

◆ SERIAL_NUMBER_12_EFUSE_EFUSE92_MASK

#define SERIAL_NUMBER_12_EFUSE_EFUSE92_MASK 0xFFU

◆ SERIAL_NUMBER_12_EFUSE_EFUSE92_POS

#define SERIAL_NUMBER_12_EFUSE_EFUSE92_POS 0U

◆ SERIAL_NUMBER_13_EFUSE_EFUSE93_ADDR

#define SERIAL_NUMBER_13_EFUSE_EFUSE93_ADDR 0x1C5DU

◆ SERIAL_NUMBER_13_EFUSE_EFUSE93_MASK

#define SERIAL_NUMBER_13_EFUSE_EFUSE93_MASK 0xFFU

◆ SERIAL_NUMBER_13_EFUSE_EFUSE93_POS

#define SERIAL_NUMBER_13_EFUSE_EFUSE93_POS 0U

◆ SERIAL_NUMBER_14_EFUSE_EFUSE94_ADDR

#define SERIAL_NUMBER_14_EFUSE_EFUSE94_ADDR 0x1C5EU

◆ SERIAL_NUMBER_14_EFUSE_EFUSE94_MASK

#define SERIAL_NUMBER_14_EFUSE_EFUSE94_MASK 0xFFU

◆ SERIAL_NUMBER_14_EFUSE_EFUSE94_POS

#define SERIAL_NUMBER_14_EFUSE_EFUSE94_POS 0U

◆ SERIAL_NUMBER_15_EFUSE_EFUSE95_ADDR

#define SERIAL_NUMBER_15_EFUSE_EFUSE95_ADDR 0x1C5FU

◆ SERIAL_NUMBER_15_EFUSE_EFUSE95_MASK

#define SERIAL_NUMBER_15_EFUSE_EFUSE95_MASK 0xFFU

◆ SERIAL_NUMBER_15_EFUSE_EFUSE95_POS

#define SERIAL_NUMBER_15_EFUSE_EFUSE95_POS 0U

◆ SERIAL_NUMBER_16_EFUSE_EFUSE96_ADDR

#define SERIAL_NUMBER_16_EFUSE_EFUSE96_ADDR 0x1C60U

◆ SERIAL_NUMBER_16_EFUSE_EFUSE96_MASK

#define SERIAL_NUMBER_16_EFUSE_EFUSE96_MASK 0xFFU

◆ SERIAL_NUMBER_16_EFUSE_EFUSE96_POS

#define SERIAL_NUMBER_16_EFUSE_EFUSE96_POS 0U

◆ SERIAL_NUMBER_17_EFUSE_EFUSE97_ADDR

#define SERIAL_NUMBER_17_EFUSE_EFUSE97_ADDR 0x1C61U

◆ SERIAL_NUMBER_17_EFUSE_EFUSE97_MASK

#define SERIAL_NUMBER_17_EFUSE_EFUSE97_MASK 0xFFU

◆ SERIAL_NUMBER_17_EFUSE_EFUSE97_POS

#define SERIAL_NUMBER_17_EFUSE_EFUSE97_POS 0U

◆ SERIAL_NUMBER_18_EFUSE_EFUSE98_ADDR

#define SERIAL_NUMBER_18_EFUSE_EFUSE98_ADDR 0x1C62U

◆ SERIAL_NUMBER_18_EFUSE_EFUSE98_MASK

#define SERIAL_NUMBER_18_EFUSE_EFUSE98_MASK 0xFFU

◆ SERIAL_NUMBER_18_EFUSE_EFUSE98_POS

#define SERIAL_NUMBER_18_EFUSE_EFUSE98_POS 0U

◆ SERIAL_NUMBER_19_EFUSE_EFUSE99_ADDR

#define SERIAL_NUMBER_19_EFUSE_EFUSE99_ADDR 0x1C63U

◆ SERIAL_NUMBER_19_EFUSE_EFUSE99_MASK

#define SERIAL_NUMBER_19_EFUSE_EFUSE99_MASK 0xFFU

◆ SERIAL_NUMBER_19_EFUSE_EFUSE99_POS

#define SERIAL_NUMBER_19_EFUSE_EFUSE99_POS 0U

◆ SERIAL_NUMBER_1_EFUSE_EFUSE81_ADDR

#define SERIAL_NUMBER_1_EFUSE_EFUSE81_ADDR 0x1C51U

◆ SERIAL_NUMBER_1_EFUSE_EFUSE81_MASK

#define SERIAL_NUMBER_1_EFUSE_EFUSE81_MASK 0xFFU

◆ SERIAL_NUMBER_1_EFUSE_EFUSE81_POS

#define SERIAL_NUMBER_1_EFUSE_EFUSE81_POS 0U

◆ SERIAL_NUMBER_20_EFUSE_EFUSE100_ADDR

#define SERIAL_NUMBER_20_EFUSE_EFUSE100_ADDR 0x1C64U

◆ SERIAL_NUMBER_20_EFUSE_EFUSE100_MASK

#define SERIAL_NUMBER_20_EFUSE_EFUSE100_MASK 0xFFU

◆ SERIAL_NUMBER_20_EFUSE_EFUSE100_POS

#define SERIAL_NUMBER_20_EFUSE_EFUSE100_POS 0U

◆ SERIAL_NUMBER_21_EFUSE_EFUSE101_ADDR

#define SERIAL_NUMBER_21_EFUSE_EFUSE101_ADDR 0x1C65U

◆ SERIAL_NUMBER_21_EFUSE_EFUSE101_MASK

#define SERIAL_NUMBER_21_EFUSE_EFUSE101_MASK 0xFFU

◆ SERIAL_NUMBER_21_EFUSE_EFUSE101_POS

#define SERIAL_NUMBER_21_EFUSE_EFUSE101_POS 0U

◆ SERIAL_NUMBER_22_EFUSE_EFUSE102_ADDR

#define SERIAL_NUMBER_22_EFUSE_EFUSE102_ADDR 0x1C66U

◆ SERIAL_NUMBER_22_EFUSE_EFUSE102_MASK

#define SERIAL_NUMBER_22_EFUSE_EFUSE102_MASK 0xFFU

◆ SERIAL_NUMBER_22_EFUSE_EFUSE102_POS

#define SERIAL_NUMBER_22_EFUSE_EFUSE102_POS 0U

◆ SERIAL_NUMBER_23_EFUSE_EFUSE103_ADDR

#define SERIAL_NUMBER_23_EFUSE_EFUSE103_ADDR 0x1C67U

◆ SERIAL_NUMBER_23_EFUSE_EFUSE103_MASK

#define SERIAL_NUMBER_23_EFUSE_EFUSE103_MASK 0xFFU

◆ SERIAL_NUMBER_23_EFUSE_EFUSE103_POS

#define SERIAL_NUMBER_23_EFUSE_EFUSE103_POS 0U

◆ SERIAL_NUMBER_2_EFUSE_EFUSE82_ADDR

#define SERIAL_NUMBER_2_EFUSE_EFUSE82_ADDR 0x1C52U

◆ SERIAL_NUMBER_2_EFUSE_EFUSE82_MASK

#define SERIAL_NUMBER_2_EFUSE_EFUSE82_MASK 0xFFU

◆ SERIAL_NUMBER_2_EFUSE_EFUSE82_POS

#define SERIAL_NUMBER_2_EFUSE_EFUSE82_POS 0U

◆ SERIAL_NUMBER_3_EFUSE_EFUSE83_ADDR

#define SERIAL_NUMBER_3_EFUSE_EFUSE83_ADDR 0x1C53U

◆ SERIAL_NUMBER_3_EFUSE_EFUSE83_MASK

#define SERIAL_NUMBER_3_EFUSE_EFUSE83_MASK 0xFFU

◆ SERIAL_NUMBER_3_EFUSE_EFUSE83_POS

#define SERIAL_NUMBER_3_EFUSE_EFUSE83_POS 0U

◆ SERIAL_NUMBER_4_EFUSE_EFUSE84_ADDR

#define SERIAL_NUMBER_4_EFUSE_EFUSE84_ADDR 0x1C54U

◆ SERIAL_NUMBER_4_EFUSE_EFUSE84_MASK

#define SERIAL_NUMBER_4_EFUSE_EFUSE84_MASK 0xFFU

◆ SERIAL_NUMBER_4_EFUSE_EFUSE84_POS

#define SERIAL_NUMBER_4_EFUSE_EFUSE84_POS 0U

◆ SERIAL_NUMBER_5_EFUSE_EFUSE85_ADDR

#define SERIAL_NUMBER_5_EFUSE_EFUSE85_ADDR 0x1C55U

◆ SERIAL_NUMBER_5_EFUSE_EFUSE85_MASK

#define SERIAL_NUMBER_5_EFUSE_EFUSE85_MASK 0xFFU

◆ SERIAL_NUMBER_5_EFUSE_EFUSE85_POS

#define SERIAL_NUMBER_5_EFUSE_EFUSE85_POS 0U

◆ SERIAL_NUMBER_6_EFUSE_EFUSE86_ADDR

#define SERIAL_NUMBER_6_EFUSE_EFUSE86_ADDR 0x1C56U

◆ SERIAL_NUMBER_6_EFUSE_EFUSE86_MASK

#define SERIAL_NUMBER_6_EFUSE_EFUSE86_MASK 0xFFU

◆ SERIAL_NUMBER_6_EFUSE_EFUSE86_POS

#define SERIAL_NUMBER_6_EFUSE_EFUSE86_POS 0U

◆ SERIAL_NUMBER_7_EFUSE_EFUSE87_ADDR

#define SERIAL_NUMBER_7_EFUSE_EFUSE87_ADDR 0x1C57U

◆ SERIAL_NUMBER_7_EFUSE_EFUSE87_MASK

#define SERIAL_NUMBER_7_EFUSE_EFUSE87_MASK 0xFFU

◆ SERIAL_NUMBER_7_EFUSE_EFUSE87_POS

#define SERIAL_NUMBER_7_EFUSE_EFUSE87_POS 0U

◆ SERIAL_NUMBER_8_EFUSE_EFUSE88_ADDR

#define SERIAL_NUMBER_8_EFUSE_EFUSE88_ADDR 0x1C58U

◆ SERIAL_NUMBER_8_EFUSE_EFUSE88_MASK

#define SERIAL_NUMBER_8_EFUSE_EFUSE88_MASK 0xFFU

◆ SERIAL_NUMBER_8_EFUSE_EFUSE88_POS

#define SERIAL_NUMBER_8_EFUSE_EFUSE88_POS 0U

◆ SERIAL_NUMBER_9_EFUSE_EFUSE89_ADDR

#define SERIAL_NUMBER_9_EFUSE_EFUSE89_ADDR 0x1C59U

◆ SERIAL_NUMBER_9_EFUSE_EFUSE89_MASK

#define SERIAL_NUMBER_9_EFUSE_EFUSE89_MASK 0xFFU

◆ SERIAL_NUMBER_9_EFUSE_EFUSE89_POS

#define SERIAL_NUMBER_9_EFUSE_EFUSE89_POS 0U

◆ SLEEP_TCTRL_CTRL0_ADDR

#define SLEEP_TCTRL_CTRL0_ADDR 0x10U

◆ SLEEP_TCTRL_CTRL0_MASK

#define SLEEP_TCTRL_CTRL0_MASK 0x08U

◆ SLEEP_TCTRL_CTRL0_POS

#define SLEEP_TCTRL_CTRL0_POS 3U

◆ SLV_SH_CC_I2C_0_ADDR

#define SLV_SH_CC_I2C_0_ADDR 0x40U

◆ SLV_SH_CC_I2C_0_MASK

#define SLV_SH_CC_I2C_0_MASK 0x30U

◆ SLV_SH_CC_I2C_0_POS

#define SLV_SH_CC_I2C_0_POS 4U

◆ SLV_SH_PT_CC_I2C_PT_0_ADDR

#define SLV_SH_PT_CC_I2C_PT_0_ADDR 0x4CU

◆ SLV_SH_PT_CC_I2C_PT_0_MASK

#define SLV_SH_PT_CC_I2C_PT_0_MASK 0x30U

◆ SLV_SH_PT_CC_I2C_PT_0_POS

#define SLV_SH_PT_CC_I2C_PT_0_POS 4U

◆ SLV_TO_CC_I2C_0_ADDR

#define SLV_TO_CC_I2C_0_ADDR 0x40U

◆ SLV_TO_CC_I2C_0_MASK

#define SLV_TO_CC_I2C_0_MASK 0x07U

◆ SLV_TO_CC_I2C_0_POS

#define SLV_TO_CC_I2C_0_POS 0U

◆ SLV_TO_PT_CC_I2C_PT_0_ADDR

#define SLV_TO_PT_CC_I2C_PT_0_ADDR 0x4CU

◆ SLV_TO_PT_CC_I2C_PT_0_MASK

#define SLV_TO_PT_CC_I2C_PT_0_MASK 0x07U

◆ SLV_TO_PT_CC_I2C_PT_0_POS

#define SLV_TO_PT_CC_I2C_PT_0_POS 0U

◆ SOFT_BPPZ_EN_FRONTTOP_FRONTTOP_22_ADDR

#define SOFT_BPPZ_EN_FRONTTOP_FRONTTOP_22_ADDR 0x31EU

◆ SOFT_BPPZ_EN_FRONTTOP_FRONTTOP_22_MASK

#define SOFT_BPPZ_EN_FRONTTOP_FRONTTOP_22_MASK 0x20U

◆ SOFT_BPPZ_EN_FRONTTOP_FRONTTOP_22_POS

#define SOFT_BPPZ_EN_FRONTTOP_FRONTTOP_22_POS 5U

◆ SOFT_BPPZ_FRONTTOP_FRONTTOP_22_ADDR

#define SOFT_BPPZ_FRONTTOP_FRONTTOP_22_ADDR 0x31EU

◆ SOFT_BPPZ_FRONTTOP_FRONTTOP_22_MASK

#define SOFT_BPPZ_FRONTTOP_FRONTTOP_22_MASK 0x1FU

◆ SOFT_BPPZ_FRONTTOP_FRONTTOP_22_POS

#define SOFT_BPPZ_FRONTTOP_FRONTTOP_22_POS 0U

◆ SOFT_DTZ_EN_FRONTTOP_FRONTTOP_22_ADDR

#define SOFT_DTZ_EN_FRONTTOP_FRONTTOP_22_ADDR 0x31EU

◆ SOFT_DTZ_EN_FRONTTOP_FRONTTOP_22_MASK

#define SOFT_DTZ_EN_FRONTTOP_FRONTTOP_22_MASK 0x80U

◆ SOFT_DTZ_EN_FRONTTOP_FRONTTOP_22_POS

#define SOFT_DTZ_EN_FRONTTOP_FRONTTOP_22_POS 7U

◆ SOFT_DTZ_FRONTTOP_FRONTTOP_27_ADDR

#define SOFT_DTZ_FRONTTOP_FRONTTOP_27_ADDR 0x323U

◆ SOFT_DTZ_FRONTTOP_FRONTTOP_27_MASK

#define SOFT_DTZ_FRONTTOP_FRONTTOP_27_MASK 0x3FU

◆ SOFT_DTZ_FRONTTOP_FRONTTOP_27_POS

#define SOFT_DTZ_FRONTTOP_FRONTTOP_27_POS 0U

◆ SOFT_VCZ_EN_FRONTTOP_FRONTTOP_22_ADDR

#define SOFT_VCZ_EN_FRONTTOP_FRONTTOP_22_ADDR 0x31EU

◆ SOFT_VCZ_EN_FRONTTOP_FRONTTOP_22_MASK

#define SOFT_VCZ_EN_FRONTTOP_FRONTTOP_22_MASK 0x40U

◆ SOFT_VCZ_EN_FRONTTOP_FRONTTOP_22_POS

#define SOFT_VCZ_EN_FRONTTOP_FRONTTOP_22_POS 6U

◆ SOFT_VCZ_FRONTTOP_FRONTTOP_24_ADDR

#define SOFT_VCZ_FRONTTOP_FRONTTOP_24_ADDR 0x320U

◆ SOFT_VCZ_FRONTTOP_FRONTTOP_24_MASK

#define SOFT_VCZ_FRONTTOP_FRONTTOP_24_MASK 0x30U

◆ SOFT_VCZ_FRONTTOP_FRONTTOP_24_POS

#define SOFT_VCZ_FRONTTOP_FRONTTOP_24_POS 4U

◆ SPI_BASE_PRIO_SPI_SPI_1_ADDR

#define SPI_BASE_PRIO_SPI_SPI_1_ADDR 0x171U

◆ SPI_BASE_PRIO_SPI_SPI_1_MASK

#define SPI_BASE_PRIO_SPI_SPI_1_MASK 0x03U

◆ SPI_BASE_PRIO_SPI_SPI_1_POS

#define SPI_BASE_PRIO_SPI_SPI_1_POS 0U

◆ SPI_CC_EN_SPI_SPI_0_ADDR

#define SPI_CC_EN_SPI_SPI_0_ADDR 0x170U

◆ SPI_CC_EN_SPI_SPI_0_MASK

#define SPI_CC_EN_SPI_SPI_0_MASK 0x04U

◆ SPI_CC_EN_SPI_SPI_0_POS

#define SPI_CC_EN_SPI_SPI_0_POS 2U

◆ SPI_CC_RD_SPI_CC_RD__ADDR

#define SPI_CC_RD_SPI_CC_RD__ADDR 0x1380U

◆ SPI_CC_RD_SPI_CC_RD__DEFAULT

#define SPI_CC_RD_SPI_CC_RD__DEFAULT 0x00U

◆ SPI_CC_TRG_ID_SPI_SPI_0_ADDR

#define SPI_CC_TRG_ID_SPI_SPI_0_ADDR 0x170U

◆ SPI_CC_TRG_ID_SPI_SPI_0_MASK

#define SPI_CC_TRG_ID_SPI_SPI_0_MASK 0x30U

◆ SPI_CC_TRG_ID_SPI_SPI_0_POS

#define SPI_CC_TRG_ID_SPI_SPI_0_POS 4U

◆ SPI_CC_WR_SPI_CC_WR__ADDR

#define SPI_CC_WR_SPI_CC_WR__ADDR 0x1300U

◆ SPI_CC_WR_SPI_CC_WR__DEFAULT

#define SPI_CC_WR_SPI_CC_WR__DEFAULT 0x00U

◆ SPI_EN_SPI_SPI_0_ADDR

#define SPI_EN_SPI_SPI_0_ADDR 0x170U

◆ SPI_EN_SPI_SPI_0_MASK

#define SPI_EN_SPI_SPI_0_MASK 0x01U

◆ SPI_EN_SPI_SPI_0_POS

#define SPI_EN_SPI_SPI_0_POS 0U

◆ SPI_IGNR_ID_SPI_SPI_0_ADDR

#define SPI_IGNR_ID_SPI_SPI_0_ADDR 0x170U

◆ SPI_IGNR_ID_SPI_SPI_0_MASK

#define SPI_IGNR_ID_SPI_SPI_0_MASK 0x08U

◆ SPI_IGNR_ID_SPI_SPI_0_POS

#define SPI_IGNR_ID_SPI_SPI_0_POS 3U

◆ SPI_LOC_ID_SPI_SPI_0_ADDR

#define SPI_LOC_ID_SPI_SPI_0_ADDR 0x170U

◆ SPI_LOC_ID_SPI_SPI_0_MASK

#define SPI_LOC_ID_SPI_SPI_0_MASK 0xC0U

◆ SPI_LOC_ID_SPI_SPI_0_POS

#define SPI_LOC_ID_SPI_SPI_0_POS 6U

◆ SPI_LOC_N_SPI_SPI_1_ADDR

#define SPI_LOC_N_SPI_SPI_1_ADDR 0x171U

◆ SPI_LOC_N_SPI_SPI_1_MASK

#define SPI_LOC_N_SPI_SPI_1_MASK 0xFCU

◆ SPI_LOC_N_SPI_SPI_1_POS

#define SPI_LOC_N_SPI_SPI_1_POS 2U

◆ SPI_MOD3_F_SPI_SPI_2_ADDR

#define SPI_MOD3_F_SPI_SPI_2_ADDR 0x172U

◆ SPI_MOD3_F_SPI_SPI_2_MASK

#define SPI_MOD3_F_SPI_SPI_2_MASK 0x08U

◆ SPI_MOD3_F_SPI_SPI_2_POS

#define SPI_MOD3_F_SPI_SPI_2_POS 3U

◆ SPI_MOD3_SPI_SPI_2_ADDR

#define SPI_MOD3_SPI_SPI_2_ADDR 0x172U

◆ SPI_MOD3_SPI_SPI_2_MASK

#define SPI_MOD3_SPI_SPI_2_MASK 0x04U

◆ SPI_MOD3_SPI_SPI_2_POS

#define SPI_MOD3_SPI_SPI_2_POS 2U

◆ SPI_RX_OVRFLW_SPI_SPI_7_ADDR

#define SPI_RX_OVRFLW_SPI_SPI_7_ADDR 0x177U

◆ SPI_RX_OVRFLW_SPI_SPI_7_MASK

#define SPI_RX_OVRFLW_SPI_SPI_7_MASK 0x80U

◆ SPI_RX_OVRFLW_SPI_SPI_7_POS

#define SPI_RX_OVRFLW_SPI_SPI_7_POS 7U

◆ SPI_SPI_0_ADDR

#define SPI_SPI_0_ADDR 0x170U

◆ SPI_SPI_0_DEFAULT

#define SPI_SPI_0_DEFAULT 0x08U

◆ SPI_SPI_1_ADDR

#define SPI_SPI_1_ADDR 0x171U

◆ SPI_SPI_1_DEFAULT

#define SPI_SPI_1_DEFAULT 0x1DU

◆ SPI_SPI_2_ADDR

#define SPI_SPI_2_ADDR 0x172U

◆ SPI_SPI_2_DEFAULT

#define SPI_SPI_2_DEFAULT 0x03U

◆ SPI_SPI_3_ADDR

#define SPI_SPI_3_ADDR 0x173U

◆ SPI_SPI_3_DEFAULT

#define SPI_SPI_3_DEFAULT 0x00U

◆ SPI_SPI_4_ADDR

#define SPI_SPI_4_ADDR 0x174U

◆ SPI_SPI_4_DEFAULT

#define SPI_SPI_4_DEFAULT 0x00U

◆ SPI_SPI_5_ADDR

#define SPI_SPI_5_ADDR 0x175U

◆ SPI_SPI_5_DEFAULT

#define SPI_SPI_5_DEFAULT 0x00U

◆ SPI_SPI_6_ADDR

#define SPI_SPI_6_ADDR 0x176U

◆ SPI_SPI_6_DEFAULT

#define SPI_SPI_6_DEFAULT 0x00U

◆ SPI_SPI_7_ADDR

#define SPI_SPI_7_ADDR 0x177U

◆ SPI_SPI_7_DEFAULT

#define SPI_SPI_7_DEFAULT 0x00U

◆ SPI_SPI_8_ADDR

#define SPI_SPI_8_ADDR 0x178U

◆ SPI_SPI_8_DEFAULT

#define SPI_SPI_8_DEFAULT 0x00U

◆ SPI_TX_OVRFLW_SPI_SPI_7_ADDR

#define SPI_TX_OVRFLW_SPI_SPI_7_ADDR 0x177U

◆ SPI_TX_OVRFLW_SPI_SPI_7_MASK

#define SPI_TX_OVRFLW_SPI_SPI_7_MASK 0x40U

◆ SPI_TX_OVRFLW_SPI_SPI_7_POS

#define SPI_TX_OVRFLW_SPI_SPI_7_POS 6U

◆ SPIM_SCK_HI_CLKS_SPI_SPI_5_ADDR

#define SPIM_SCK_HI_CLKS_SPI_SPI_5_ADDR 0x175U

◆ SPIM_SCK_HI_CLKS_SPI_SPI_5_MASK

#define SPIM_SCK_HI_CLKS_SPI_SPI_5_MASK 0xFFU

◆ SPIM_SCK_HI_CLKS_SPI_SPI_5_POS

#define SPIM_SCK_HI_CLKS_SPI_SPI_5_POS 0U

◆ SPIM_SCK_LO_CLKS_SPI_SPI_4_ADDR

#define SPIM_SCK_LO_CLKS_SPI_SPI_4_ADDR 0x174U

◆ SPIM_SCK_LO_CLKS_SPI_SPI_4_MASK

#define SPIM_SCK_LO_CLKS_SPI_SPI_4_MASK 0xFFU

◆ SPIM_SCK_LO_CLKS_SPI_SPI_4_POS

#define SPIM_SCK_LO_CLKS_SPI_SPI_4_POS 0U

◆ SPIM_SS1_ACT_H_SPI_SPI_2_ADDR

#define SPIM_SS1_ACT_H_SPI_SPI_2_ADDR 0x172U

◆ SPIM_SS1_ACT_H_SPI_SPI_2_MASK

#define SPIM_SS1_ACT_H_SPI_SPI_2_MASK 0x01U

◆ SPIM_SS1_ACT_H_SPI_SPI_2_POS

#define SPIM_SS1_ACT_H_SPI_SPI_2_POS 0U

◆ SPIM_SS2_ACT_H_SPI_SPI_2_ADDR

#define SPIM_SS2_ACT_H_SPI_SPI_2_ADDR 0x172U

◆ SPIM_SS2_ACT_H_SPI_SPI_2_MASK

#define SPIM_SS2_ACT_H_SPI_SPI_2_MASK 0x02U

◆ SPIM_SS2_ACT_H_SPI_SPI_2_POS

#define SPIM_SS2_ACT_H_SPI_SPI_2_POS 1U

◆ SPIM_SS_DLY_CLKS_SPI_SPI_3_ADDR

#define SPIM_SS_DLY_CLKS_SPI_SPI_3_ADDR 0x173U

◆ SPIM_SS_DLY_CLKS_SPI_SPI_3_MASK

#define SPIM_SS_DLY_CLKS_SPI_SPI_3_MASK 0xFFU

◆ SPIM_SS_DLY_CLKS_SPI_SPI_3_POS

#define SPIM_SS_DLY_CLKS_SPI_SPI_3_POS 0U

◆ SPIS_BYTE_CNT_SPI_SPI_7_ADDR

#define SPIS_BYTE_CNT_SPI_SPI_7_ADDR 0x177U

◆ SPIS_BYTE_CNT_SPI_SPI_7_MASK

#define SPIS_BYTE_CNT_SPI_SPI_7_MASK 0x1FU

◆ SPIS_BYTE_CNT_SPI_SPI_7_POS

#define SPIS_BYTE_CNT_SPI_SPI_7_POS 0U

◆ SPIS_RWN_SPI_SPI_6_ADDR

#define SPIS_RWN_SPI_SPI_6_ADDR 0x176U

◆ SPIS_RWN_SPI_SPI_6_MASK

#define SPIS_RWN_SPI_SPI_6_MASK 0x10U

◆ SPIS_RWN_SPI_SPI_6_POS

#define SPIS_RWN_SPI_SPI_6_POS 4U

◆ SRC_A_1_MISC_I2C_PT_4_ADDR

#define SRC_A_1_MISC_I2C_PT_4_ADDR 0x550U

◆ SRC_A_1_MISC_I2C_PT_4_MASK

#define SRC_A_1_MISC_I2C_PT_4_MASK 0xFEU

◆ SRC_A_1_MISC_I2C_PT_4_POS

#define SRC_A_1_MISC_I2C_PT_4_POS 1U

◆ SRC_A_2_MISC_I2C_PT_8_ADDR

#define SRC_A_2_MISC_I2C_PT_8_ADDR 0x554U

◆ SRC_A_2_MISC_I2C_PT_8_MASK

#define SRC_A_2_MISC_I2C_PT_8_MASK 0xFEU

◆ SRC_A_2_MISC_I2C_PT_8_POS

#define SRC_A_2_MISC_I2C_PT_8_POS 1U

◆ SRC_A_CC_I2C_2_ADDR

#define SRC_A_CC_I2C_2_ADDR 0x42U

◆ SRC_A_CC_I2C_2_MASK

#define SRC_A_CC_I2C_2_MASK 0xFEU

◆ SRC_A_CC_I2C_2_POS

#define SRC_A_CC_I2C_2_POS 1U

◆ SRC_B_1_MISC_I2C_PT_6_ADDR

#define SRC_B_1_MISC_I2C_PT_6_ADDR 0x552U

◆ SRC_B_1_MISC_I2C_PT_6_MASK

#define SRC_B_1_MISC_I2C_PT_6_MASK 0xFEU

◆ SRC_B_1_MISC_I2C_PT_6_POS

#define SRC_B_1_MISC_I2C_PT_6_POS 1U

◆ SRC_B_2_MISC_I2C_PT_10_ADDR

#define SRC_B_2_MISC_I2C_PT_10_ADDR 0x556U

◆ SRC_B_2_MISC_I2C_PT_10_MASK

#define SRC_B_2_MISC_I2C_PT_10_MASK 0xFEU

◆ SRC_B_2_MISC_I2C_PT_10_POS

#define SRC_B_2_MISC_I2C_PT_10_POS 1U

◆ SRC_B_CC_I2C_4_ADDR

#define SRC_B_CC_I2C_4_ADDR 0x44U

◆ SRC_B_CC_I2C_4_MASK

#define SRC_B_CC_I2C_4_MASK 0xFEU

◆ SRC_B_CC_I2C_4_POS

#define SRC_B_CC_I2C_4_POS 1U

◆ SS_IO_EN_1_SPI_SPI_6_ADDR

#define SS_IO_EN_1_SPI_SPI_6_ADDR 0x176U

◆ SS_IO_EN_1_SPI_SPI_6_MASK

#define SS_IO_EN_1_SPI_SPI_6_MASK 0x04U

◆ SS_IO_EN_1_SPI_SPI_6_POS

#define SS_IO_EN_1_SPI_SPI_6_POS 2U

◆ SS_IO_EN_2_SPI_SPI_6_ADDR

#define SS_IO_EN_2_SPI_SPI_6_ADDR 0x176U

◆ SS_IO_EN_2_SPI_SPI_6_MASK

#define SS_IO_EN_2_SPI_SPI_6_MASK 0x08U

◆ SS_IO_EN_2_SPI_SPI_6_POS

#define SS_IO_EN_2_SPI_SPI_6_POS 3U

◆ START_PORTB_FRONTTOP_FRONTTOP_0_ADDR

#define START_PORTB_FRONTTOP_FRONTTOP_0_ADDR 0x308U

◆ START_PORTB_FRONTTOP_FRONTTOP_0_MASK

#define START_PORTB_FRONTTOP_FRONTTOP_0_MASK 0x20U

◆ START_PORTB_FRONTTOP_FRONTTOP_0_POS

#define START_PORTB_FRONTTOP_FRONTTOP_0_POS 5U

◆ START_PORTBZ_FRONTTOP_FRONTTOP_9_ADDR

#define START_PORTBZ_FRONTTOP_FRONTTOP_9_ADDR 0x311U

◆ START_PORTBZ_FRONTTOP_FRONTTOP_9_MASK

#define START_PORTBZ_FRONTTOP_FRONTTOP_9_MASK 0x40U

◆ START_PORTBZ_FRONTTOP_FRONTTOP_9_POS

#define START_PORTBZ_FRONTTOP_FRONTTOP_9_POS 6U

◆ T_CLK_SETTLE_MIPI_RX_MIPI_RX8_ADDR

#define T_CLK_SETTLE_MIPI_RX_MIPI_RX8_ADDR 0x338U

◆ T_CLK_SETTLE_MIPI_RX_MIPI_RX8_MASK

#define T_CLK_SETTLE_MIPI_RX_MIPI_RX8_MASK 0x03U

◆ T_CLK_SETTLE_MIPI_RX_MIPI_RX8_POS

#define T_CLK_SETTLE_MIPI_RX_MIPI_RX8_POS 0U

◆ T_EST_OUT_B0_FUNC_SAFE_REGADCBIST13_ADDR

#define T_EST_OUT_B0_FUNC_SAFE_REGADCBIST13_ADDR 0x1D3BU

◆ T_EST_OUT_B0_FUNC_SAFE_REGADCBIST13_MASK

#define T_EST_OUT_B0_FUNC_SAFE_REGADCBIST13_MASK 0xFFU

◆ T_EST_OUT_B0_FUNC_SAFE_REGADCBIST13_POS

#define T_EST_OUT_B0_FUNC_SAFE_REGADCBIST13_POS 0U

◆ T_EST_OUT_B1_FUNC_SAFE_REGADCBIST14_ADDR

#define T_EST_OUT_B1_FUNC_SAFE_REGADCBIST14_ADDR 0x1D3CU

◆ T_EST_OUT_B1_FUNC_SAFE_REGADCBIST14_MASK

#define T_EST_OUT_B1_FUNC_SAFE_REGADCBIST14_MASK 0xC0U

◆ T_EST_OUT_B1_FUNC_SAFE_REGADCBIST14_POS

#define T_EST_OUT_B1_FUNC_SAFE_REGADCBIST14_POS 6U

◆ T_HS_DEC_EN_MIPI_RX_MIPI_RX8_ADDR

#define T_HS_DEC_EN_MIPI_RX_MIPI_RX8_ADDR 0x338U

◆ T_HS_DEC_EN_MIPI_RX_MIPI_RX8_MASK

#define T_HS_DEC_EN_MIPI_RX_MIPI_RX8_MASK 0xC0U

◆ T_HS_DEC_EN_MIPI_RX_MIPI_RX8_POS

#define T_HS_DEC_EN_MIPI_RX_MIPI_RX8_POS 6U

◆ T_HS_SETTLE_MIPI_RX_MIPI_RX8_ADDR

#define T_HS_SETTLE_MIPI_RX_MIPI_RX8_ADDR 0x338U

◆ T_HS_SETTLE_MIPI_RX_MIPI_RX8_MASK

#define T_HS_SETTLE_MIPI_RX_MIPI_RX8_MASK 0x30U

◆ T_HS_SETTLE_MIPI_RX_MIPI_RX8_POS

#define T_HS_SETTLE_MIPI_RX_MIPI_RX8_POS 4U

◆ TCTRL_CNT0_ADDR

#define TCTRL_CNT0_ADDR 0x22U

◆ TCTRL_CNT0_DEFAULT

#define TCTRL_CNT0_DEFAULT 0x00U

◆ TCTRL_CNT2_ADDR

#define TCTRL_CNT2_ADDR 0x24U

◆ TCTRL_CNT2_DEFAULT

#define TCTRL_CNT2_DEFAULT 0x00U

◆ TCTRL_CNT3_ADDR

#define TCTRL_CNT3_ADDR 0x25U

◆ TCTRL_CNT3_DEFAULT

#define TCTRL_CNT3_DEFAULT 0x00U

◆ TCTRL_CTRL0_ADDR

#define TCTRL_CTRL0_ADDR 0x10U

◆ TCTRL_CTRL0_DEFAULT

#define TCTRL_CTRL0_DEFAULT 0x01U

◆ TCTRL_CTRL1_ADDR

#define TCTRL_CTRL1_ADDR 0x11U

◆ TCTRL_CTRL1_DEFAULT

#define TCTRL_CTRL1_DEFAULT 0x02U

◆ TCTRL_CTRL2_ADDR

#define TCTRL_CTRL2_ADDR 0x12U

◆ TCTRL_CTRL2_DEFAULT

#define TCTRL_CTRL2_DEFAULT 0x04U

◆ TCTRL_CTRL3_ADDR

#define TCTRL_CTRL3_ADDR 0x13U

◆ TCTRL_CTRL3_DEFAULT

#define TCTRL_CTRL3_DEFAULT 0x10U

◆ TCTRL_INTR0_ADDR

#define TCTRL_INTR0_ADDR 0x18U

◆ TCTRL_INTR0_DEFAULT

#define TCTRL_INTR0_DEFAULT 0xA0U

◆ TCTRL_INTR1_ADDR

#define TCTRL_INTR1_ADDR 0x19U

◆ TCTRL_INTR1_DEFAULT

#define TCTRL_INTR1_DEFAULT 0x00U

◆ TCTRL_INTR2_ADDR

#define TCTRL_INTR2_ADDR 0x1AU

◆ TCTRL_INTR2_DEFAULT

#define TCTRL_INTR2_DEFAULT 0x09U

◆ TCTRL_INTR3_ADDR

#define TCTRL_INTR3_ADDR 0x1BU

◆ TCTRL_INTR3_DEFAULT

#define TCTRL_INTR3_DEFAULT 0x00U

◆ TCTRL_INTR4_ADDR

#define TCTRL_INTR4_ADDR 0x1CU

◆ TCTRL_INTR4_DEFAULT

#define TCTRL_INTR4_DEFAULT 0x08U

◆ TCTRL_INTR5_ADDR

#define TCTRL_INTR5_ADDR 0x1DU

◆ TCTRL_INTR5_DEFAULT

#define TCTRL_INTR5_DEFAULT 0x00U

◆ TCTRL_INTR6_ADDR

#define TCTRL_INTR6_ADDR 0x1EU

◆ TCTRL_INTR6_DEFAULT

#define TCTRL_INTR6_DEFAULT 0xFBU

◆ TCTRL_INTR7_ADDR

#define TCTRL_INTR7_ADDR 0x1FU

◆ TCTRL_INTR7_DEFAULT

#define TCTRL_INTR7_DEFAULT 0x00U

◆ TCTRL_INTR8_ADDR

#define TCTRL_INTR8_ADDR 0x20U

◆ TCTRL_INTR8_DEFAULT

#define TCTRL_INTR8_DEFAULT 0x9FU

◆ TCTRL_INTR9_ADDR

#define TCTRL_INTR9_ADDR 0x21U

◆ TCTRL_INTR9_DEFAULT

#define TCTRL_INTR9_DEFAULT 0xDFU

◆ TCTRL_PWR0_ADDR

#define TCTRL_PWR0_ADDR 0x08U

◆ TCTRL_PWR0_DEFAULT

#define TCTRL_PWR0_DEFAULT 0x00U

◆ TCTRL_PWR4_ADDR

#define TCTRL_PWR4_ADDR 0x0CU

◆ TCTRL_PWR4_DEFAULT

#define TCTRL_PWR4_DEFAULT 0x15U

◆ TLIMIT_FUNC_SAFE_REGADCBIST7_ADDR

#define TLIMIT_FUNC_SAFE_REGADCBIST7_ADDR 0x1D35U

◆ TLIMIT_FUNC_SAFE_REGADCBIST7_MASK

#define TLIMIT_FUNC_SAFE_REGADCBIST7_MASK 0xFFU

◆ TLIMIT_FUNC_SAFE_REGADCBIST7_POS

#define TLIMIT_FUNC_SAFE_REGADCBIST7_POS 0U

◆ TMON_ERR_IE_AFE_ADC_INTRIE3_ADDR

#define TMON_ERR_IE_AFE_ADC_INTRIE3_ADDR 0x50FU

◆ TMON_ERR_IE_AFE_ADC_INTRIE3_MASK

#define TMON_ERR_IE_AFE_ADC_INTRIE3_MASK 0x02U

◆ TMON_ERR_IE_AFE_ADC_INTRIE3_POS

#define TMON_ERR_IE_AFE_ADC_INTRIE3_POS 1U

◆ TMON_ERR_IF_AFE_ADC_INTR3_ADDR

#define TMON_ERR_IF_AFE_ADC_INTR3_ADDR 0x513U

◆ TMON_ERR_IF_AFE_ADC_INTR3_MASK

#define TMON_ERR_IF_AFE_ADC_INTR3_MASK 0x02U

◆ TMON_ERR_IF_AFE_ADC_INTR3_POS

#define TMON_ERR_IF_AFE_ADC_INTR3_POS 1U

◆ TMONCAL_OOD_WAIT_B2_FUNC_SAFE_REGADCBIST12_ADDR

#define TMONCAL_OOD_WAIT_B2_FUNC_SAFE_REGADCBIST12_ADDR 0x1D3AU

◆ TMONCAL_OOD_WAIT_B2_FUNC_SAFE_REGADCBIST12_MASK

#define TMONCAL_OOD_WAIT_B2_FUNC_SAFE_REGADCBIST12_MASK 0xFFU

◆ TMONCAL_OOD_WAIT_B2_FUNC_SAFE_REGADCBIST12_POS

#define TMONCAL_OOD_WAIT_B2_FUNC_SAFE_REGADCBIST12_POS 0U

◆ TUN_FIFO_OVERFLOW_MIPI_RX_EXT_EXT8_ADDR

#define TUN_FIFO_OVERFLOW_MIPI_RX_EXT_EXT8_ADDR 0x380U

◆ TUN_FIFO_OVERFLOW_MIPI_RX_EXT_EXT8_MASK

#define TUN_FIFO_OVERFLOW_MIPI_RX_EXT_EXT8_MASK 0x01U

◆ TUN_FIFO_OVERFLOW_MIPI_RX_EXT_EXT8_POS

#define TUN_FIFO_OVERFLOW_MIPI_RX_EXT_EXT8_POS 0U

◆ TUN_MODE_MIPI_RX_EXT_EXT11_ADDR

#define TUN_MODE_MIPI_RX_EXT_EXT11_ADDR 0x383U

◆ TUN_MODE_MIPI_RX_EXT_EXT11_MASK

#define TUN_MODE_MIPI_RX_EXT_EXT11_MASK 0x80U

◆ TUN_MODE_MIPI_RX_EXT_EXT11_POS

#define TUN_MODE_MIPI_RX_EXT_EXT11_POS 7U

◆ TUN_PKT_CNT_MIPI_RX_EXT_EXT23_ADDR

#define TUN_PKT_CNT_MIPI_RX_EXT_EXT23_ADDR 0x38FU

◆ TUN_PKT_CNT_MIPI_RX_EXT_EXT23_MASK

#define TUN_PKT_CNT_MIPI_RX_EXT_EXT23_MASK 0xFFU

◆ TUN_PKT_CNT_MIPI_RX_EXT_EXT23_POS

#define TUN_PKT_CNT_MIPI_RX_EXT_EXT23_POS 0U

◆ TX_COMP_EN_GPIO0_0_GPIO_A_ADDR

#define TX_COMP_EN_GPIO0_0_GPIO_A_ADDR 0x2BEU

◆ TX_COMP_EN_GPIO0_0_GPIO_A_MASK

#define TX_COMP_EN_GPIO0_0_GPIO_A_MASK 0x20U

◆ TX_COMP_EN_GPIO0_0_GPIO_A_POS

#define TX_COMP_EN_GPIO0_0_GPIO_A_POS 5U

◆ TX_COMP_EN_GPIO10_10_GPIO_A_ADDR

#define TX_COMP_EN_GPIO10_10_GPIO_A_ADDR 0x2DCU

◆ TX_COMP_EN_GPIO10_10_GPIO_A_MASK

#define TX_COMP_EN_GPIO10_10_GPIO_A_MASK 0x20U

◆ TX_COMP_EN_GPIO10_10_GPIO_A_POS

#define TX_COMP_EN_GPIO10_10_GPIO_A_POS 5U

◆ TX_COMP_EN_GPIO1_1_GPIO_A_ADDR

#define TX_COMP_EN_GPIO1_1_GPIO_A_ADDR 0x2C1U

◆ TX_COMP_EN_GPIO1_1_GPIO_A_MASK

#define TX_COMP_EN_GPIO1_1_GPIO_A_MASK 0x20U

◆ TX_COMP_EN_GPIO1_1_GPIO_A_POS

#define TX_COMP_EN_GPIO1_1_GPIO_A_POS 5U

◆ TX_COMP_EN_GPIO2_2_GPIO_A_ADDR

#define TX_COMP_EN_GPIO2_2_GPIO_A_ADDR 0x2C4U

◆ TX_COMP_EN_GPIO2_2_GPIO_A_MASK

#define TX_COMP_EN_GPIO2_2_GPIO_A_MASK 0x20U

◆ TX_COMP_EN_GPIO2_2_GPIO_A_POS

#define TX_COMP_EN_GPIO2_2_GPIO_A_POS 5U

◆ TX_COMP_EN_GPIO3_3_GPIO_A_ADDR

#define TX_COMP_EN_GPIO3_3_GPIO_A_ADDR 0x2C7U

◆ TX_COMP_EN_GPIO3_3_GPIO_A_MASK

#define TX_COMP_EN_GPIO3_3_GPIO_A_MASK 0x20U

◆ TX_COMP_EN_GPIO3_3_GPIO_A_POS

#define TX_COMP_EN_GPIO3_3_GPIO_A_POS 5U

◆ TX_COMP_EN_GPIO4_4_GPIO_A_ADDR

#define TX_COMP_EN_GPIO4_4_GPIO_A_ADDR 0x2CAU

◆ TX_COMP_EN_GPIO4_4_GPIO_A_MASK

#define TX_COMP_EN_GPIO4_4_GPIO_A_MASK 0x20U

◆ TX_COMP_EN_GPIO4_4_GPIO_A_POS

#define TX_COMP_EN_GPIO4_4_GPIO_A_POS 5U

◆ TX_COMP_EN_GPIO5_5_GPIO_A_ADDR

#define TX_COMP_EN_GPIO5_5_GPIO_A_ADDR 0x2CDU

◆ TX_COMP_EN_GPIO5_5_GPIO_A_MASK

#define TX_COMP_EN_GPIO5_5_GPIO_A_MASK 0x20U

◆ TX_COMP_EN_GPIO5_5_GPIO_A_POS

#define TX_COMP_EN_GPIO5_5_GPIO_A_POS 5U

◆ TX_COMP_EN_GPIO6_6_GPIO_A_ADDR

#define TX_COMP_EN_GPIO6_6_GPIO_A_ADDR 0x2D0U

◆ TX_COMP_EN_GPIO6_6_GPIO_A_MASK

#define TX_COMP_EN_GPIO6_6_GPIO_A_MASK 0x20U

◆ TX_COMP_EN_GPIO6_6_GPIO_A_POS

#define TX_COMP_EN_GPIO6_6_GPIO_A_POS 5U

◆ TX_COMP_EN_GPIO7_7_GPIO_A_ADDR

#define TX_COMP_EN_GPIO7_7_GPIO_A_ADDR 0x2D3U

◆ TX_COMP_EN_GPIO7_7_GPIO_A_MASK

#define TX_COMP_EN_GPIO7_7_GPIO_A_MASK 0x20U

◆ TX_COMP_EN_GPIO7_7_GPIO_A_POS

#define TX_COMP_EN_GPIO7_7_GPIO_A_POS 5U

◆ TX_COMP_EN_GPIO8_8_GPIO_A_ADDR

#define TX_COMP_EN_GPIO8_8_GPIO_A_ADDR 0x2D6U

◆ TX_COMP_EN_GPIO8_8_GPIO_A_MASK

#define TX_COMP_EN_GPIO8_8_GPIO_A_MASK 0x20U

◆ TX_COMP_EN_GPIO8_8_GPIO_A_POS

#define TX_COMP_EN_GPIO8_8_GPIO_A_POS 5U

◆ TX_COMP_EN_GPIO9_9_GPIO_A_ADDR

#define TX_COMP_EN_GPIO9_9_GPIO_A_ADDR 0x2D9U

◆ TX_COMP_EN_GPIO9_9_GPIO_A_MASK

#define TX_COMP_EN_GPIO9_9_GPIO_A_MASK 0x20U

◆ TX_COMP_EN_GPIO9_9_GPIO_A_POS

#define TX_COMP_EN_GPIO9_9_GPIO_A_POS 5U

◆ TX_CRC_EN_CFGI_INFOFR_TR0_ADDR

#define TX_CRC_EN_CFGI_INFOFR_TR0_ADDR 0x78U

◆ TX_CRC_EN_CFGI_INFOFR_TR0_MASK

#define TX_CRC_EN_CFGI_INFOFR_TR0_MASK 0x80U

◆ TX_CRC_EN_CFGI_INFOFR_TR0_POS

#define TX_CRC_EN_CFGI_INFOFR_TR0_POS 7U

◆ TX_CRC_EN_CFGL_GPIO_TR0_ADDR

#define TX_CRC_EN_CFGL_GPIO_TR0_ADDR 0x90U

◆ TX_CRC_EN_CFGL_GPIO_TR0_MASK

#define TX_CRC_EN_CFGL_GPIO_TR0_MASK 0x80U

◆ TX_CRC_EN_CFGL_GPIO_TR0_POS

#define TX_CRC_EN_CFGL_GPIO_TR0_POS 7U

◆ TX_CRC_EN_CFGL_IIC_X_TR0_ADDR

#define TX_CRC_EN_CFGL_IIC_X_TR0_ADDR 0xA0U

◆ TX_CRC_EN_CFGL_IIC_X_TR0_MASK

#define TX_CRC_EN_CFGL_IIC_X_TR0_MASK 0x80U

◆ TX_CRC_EN_CFGL_IIC_X_TR0_POS

#define TX_CRC_EN_CFGL_IIC_X_TR0_POS 7U

◆ TX_CRC_EN_CFGL_IIC_Y_TR0_ADDR

#define TX_CRC_EN_CFGL_IIC_Y_TR0_ADDR 0xA8U

◆ TX_CRC_EN_CFGL_IIC_Y_TR0_MASK

#define TX_CRC_EN_CFGL_IIC_Y_TR0_MASK 0x80U

◆ TX_CRC_EN_CFGL_IIC_Y_TR0_POS

#define TX_CRC_EN_CFGL_IIC_Y_TR0_POS 7U

◆ TX_CRC_EN_CFGL_SPI_TR0_ADDR

#define TX_CRC_EN_CFGL_SPI_TR0_ADDR 0x80U

◆ TX_CRC_EN_CFGL_SPI_TR0_MASK

#define TX_CRC_EN_CFGL_SPI_TR0_MASK 0x80U

◆ TX_CRC_EN_CFGL_SPI_TR0_POS

#define TX_CRC_EN_CFGL_SPI_TR0_POS 7U

◆ TX_CRC_EN_CFGV_VIDEO_Z_TX0_ADDR

#define TX_CRC_EN_CFGV_VIDEO_Z_TX0_ADDR 0x58U

◆ TX_CRC_EN_CFGV_VIDEO_Z_TX0_MASK

#define TX_CRC_EN_CFGV_VIDEO_Z_TX0_MASK 0x80U

◆ TX_CRC_EN_CFGV_VIDEO_Z_TX0_POS

#define TX_CRC_EN_CFGV_VIDEO_Z_TX0_POS 7U

◆ TX_FEC_ACTIVE_GMSL_TX3_ADDR

#define TX_FEC_ACTIVE_GMSL_TX3_ADDR 0x2BU

◆ TX_FEC_ACTIVE_GMSL_TX3_MASK

#define TX_FEC_ACTIVE_GMSL_TX3_MASK 0x20U

◆ TX_FEC_ACTIVE_GMSL_TX3_POS

#define TX_FEC_ACTIVE_GMSL_TX3_POS 5U

◆ TX_FEC_CRC_EN_GMSL_TX1_ADDR

#define TX_FEC_CRC_EN_GMSL_TX1_ADDR 0x29U

◆ TX_FEC_CRC_EN_GMSL_TX1_MASK

#define TX_FEC_CRC_EN_GMSL_TX1_MASK 0x08U

◆ TX_FEC_CRC_EN_GMSL_TX1_POS

#define TX_FEC_CRC_EN_GMSL_TX1_POS 3U

◆ TX_FEC_EN_GMSL_TX0_ADDR

#define TX_FEC_EN_GMSL_TX0_ADDR 0x28U

◆ TX_FEC_EN_GMSL_TX0_MASK

#define TX_FEC_EN_GMSL_TX0_MASK 0x02U

◆ TX_FEC_EN_GMSL_TX0_POS

#define TX_FEC_EN_GMSL_TX0_POS 1U

◆ TX_RATE_DEV_REG1_ADDR

#define TX_RATE_DEV_REG1_ADDR 0x01U

◆ TX_RATE_DEV_REG1_MASK

#define TX_RATE_DEV_REG1_MASK 0x0CU

◆ TX_RATE_DEV_REG1_POS

#define TX_RATE_DEV_REG1_POS 2U

◆ TX_SRC_ID_CFGI_INFOFR_TR3_ADDR

#define TX_SRC_ID_CFGI_INFOFR_TR3_ADDR 0x7BU

◆ TX_SRC_ID_CFGI_INFOFR_TR3_MASK

#define TX_SRC_ID_CFGI_INFOFR_TR3_MASK 0x07U

◆ TX_SRC_ID_CFGI_INFOFR_TR3_POS

#define TX_SRC_ID_CFGI_INFOFR_TR3_POS 0U

◆ TX_SRC_ID_CFGL_GPIO_TR3_ADDR

#define TX_SRC_ID_CFGL_GPIO_TR3_ADDR 0x93U

◆ TX_SRC_ID_CFGL_GPIO_TR3_MASK

#define TX_SRC_ID_CFGL_GPIO_TR3_MASK 0x07U

◆ TX_SRC_ID_CFGL_GPIO_TR3_POS

#define TX_SRC_ID_CFGL_GPIO_TR3_POS 0U

◆ TX_SRC_ID_CFGL_IIC_X_TR3_ADDR

#define TX_SRC_ID_CFGL_IIC_X_TR3_ADDR 0xA3U

◆ TX_SRC_ID_CFGL_IIC_X_TR3_MASK

#define TX_SRC_ID_CFGL_IIC_X_TR3_MASK 0x07U

◆ TX_SRC_ID_CFGL_IIC_X_TR3_POS

#define TX_SRC_ID_CFGL_IIC_X_TR3_POS 0U

◆ TX_SRC_ID_CFGL_IIC_Y_TR3_ADDR

#define TX_SRC_ID_CFGL_IIC_Y_TR3_ADDR 0xABU

◆ TX_SRC_ID_CFGL_IIC_Y_TR3_MASK

#define TX_SRC_ID_CFGL_IIC_Y_TR3_MASK 0x07U

◆ TX_SRC_ID_CFGL_IIC_Y_TR3_POS

#define TX_SRC_ID_CFGL_IIC_Y_TR3_POS 0U

◆ TX_SRC_ID_CFGL_SPI_TR3_ADDR

#define TX_SRC_ID_CFGL_SPI_TR3_ADDR 0x83U

◆ TX_SRC_ID_CFGL_SPI_TR3_MASK

#define TX_SRC_ID_CFGL_SPI_TR3_MASK 0x07U

◆ TX_SRC_ID_CFGL_SPI_TR3_POS

#define TX_SRC_ID_CFGL_SPI_TR3_POS 0U

◆ TX_STR_SEL_CFGV_VIDEO_Z_TX3_ADDR

#define TX_STR_SEL_CFGV_VIDEO_Z_TX3_ADDR 0x5BU

◆ TX_STR_SEL_CFGV_VIDEO_Z_TX3_MASK

#define TX_STR_SEL_CFGV_VIDEO_Z_TX3_MASK 0x03U

◆ TX_STR_SEL_CFGV_VIDEO_Z_TX3_POS

#define TX_STR_SEL_CFGV_VIDEO_Z_TX3_POS 0U

◆ TXSSCCENSPRST_RLMS_A_RLMS71_ADDR

#define TXSSCCENSPRST_RLMS_A_RLMS71_ADDR 0x1471U

◆ TXSSCCENSPRST_RLMS_A_RLMS71_MASK

#define TXSSCCENSPRST_RLMS_A_RLMS71_MASK 0x7EU

◆ TXSSCCENSPRST_RLMS_A_RLMS71_POS

#define TXSSCCENSPRST_RLMS_A_RLMS71_POS 1U

◆ TXSSCEN_RLMS_A_RLMS71_ADDR

#define TXSSCEN_RLMS_A_RLMS71_ADDR 0x1471U

◆ TXSSCEN_RLMS_A_RLMS71_MASK

#define TXSSCEN_RLMS_A_RLMS71_MASK 0x01U

◆ TXSSCEN_RLMS_A_RLMS71_POS

#define TXSSCEN_RLMS_A_RLMS71_POS 0U

◆ TXSSCFRQCTRL_RLMS_A_RLMS70_ADDR

#define TXSSCFRQCTRL_RLMS_A_RLMS70_ADDR 0x1470U

◆ TXSSCFRQCTRL_RLMS_A_RLMS70_MASK

#define TXSSCFRQCTRL_RLMS_A_RLMS70_MASK 0x7FU

◆ TXSSCFRQCTRL_RLMS_A_RLMS70_POS

#define TXSSCFRQCTRL_RLMS_A_RLMS70_POS 0U

◆ TXSSCMODE_RLMS_A_RLMS64_ADDR

#define TXSSCMODE_RLMS_A_RLMS64_ADDR 0x1464U

◆ TXSSCMODE_RLMS_A_RLMS64_MASK

#define TXSSCMODE_RLMS_A_RLMS64_MASK 0x03U

◆ TXSSCMODE_RLMS_A_RLMS64_POS

#define TXSSCMODE_RLMS_A_RLMS64_POS 0U

◆ TXSSCPHH_RLMS_A_RLMS75_ADDR

#define TXSSCPHH_RLMS_A_RLMS75_ADDR 0x1475U

◆ TXSSCPHH_RLMS_A_RLMS75_MASK

#define TXSSCPHH_RLMS_A_RLMS75_MASK 0x7FU

◆ TXSSCPHH_RLMS_A_RLMS75_POS

#define TXSSCPHH_RLMS_A_RLMS75_POS 0U

◆ TXSSCPHL_RLMS_A_RLMS74_ADDR

#define TXSSCPHL_RLMS_A_RLMS74_ADDR 0x1474U

◆ TXSSCPHL_RLMS_A_RLMS74_MASK

#define TXSSCPHL_RLMS_A_RLMS74_MASK 0xFFU

◆ TXSSCPHL_RLMS_A_RLMS74_POS

#define TXSSCPHL_RLMS_A_RLMS74_POS 0U

◆ TXSSCPHQUAD_RLMS_A_RLMS76_ADDR

#define TXSSCPHQUAD_RLMS_A_RLMS76_ADDR 0x1476U

◆ TXSSCPHQUAD_RLMS_A_RLMS76_MASK

#define TXSSCPHQUAD_RLMS_A_RLMS76_MASK 0x03U

◆ TXSSCPHQUAD_RLMS_A_RLMS76_POS

#define TXSSCPHQUAD_RLMS_A_RLMS76_POS 0U

◆ TXSSCPRESCLH_RLMS_A_RLMS73_ADDR

#define TXSSCPRESCLH_RLMS_A_RLMS73_ADDR 0x1473U

◆ TXSSCPRESCLH_RLMS_A_RLMS73_MASK

#define TXSSCPRESCLH_RLMS_A_RLMS73_MASK 0x07U

◆ TXSSCPRESCLH_RLMS_A_RLMS73_POS

#define TXSSCPRESCLH_RLMS_A_RLMS73_POS 0U

◆ TXSSCPRESCLL_RLMS_A_RLMS72_ADDR

#define TXSSCPRESCLL_RLMS_A_RLMS72_ADDR 0x1472U

◆ TXSSCPRESCLL_RLMS_A_RLMS72_MASK

#define TXSSCPRESCLL_RLMS_A_RLMS72_MASK 0xFFU

◆ TXSSCPRESCLL_RLMS_A_RLMS72_POS

#define TXSSCPRESCLL_RLMS_A_RLMS72_POS 0U

◆ UART_1_EN_DEV_REG3_ADDR

#define UART_1_EN_DEV_REG3_ADDR 0x03U

◆ UART_1_EN_DEV_REG3_MASK

#define UART_1_EN_DEV_REG3_MASK 0x10U

◆ UART_1_EN_DEV_REG3_POS

#define UART_1_EN_DEV_REG3_POS 4U

◆ UART_2_EN_DEV_REG3_ADDR

#define UART_2_EN_DEV_REG3_ADDR 0x03U

◆ UART_2_EN_DEV_REG3_MASK

#define UART_2_EN_DEV_REG3_MASK 0x20U

◆ UART_2_EN_DEV_REG3_POS

#define UART_2_EN_DEV_REG3_POS 5U

◆ UNLOCK_KEY_MISC_UNLOCK_KEY_ADDR

#define UNLOCK_KEY_MISC_UNLOCK_KEY_ADDR 0x56EU

◆ UNLOCK_KEY_MISC_UNLOCK_KEY_MASK

#define UNLOCK_KEY_MISC_UNLOCK_KEY_MASK 0xFFU

◆ UNLOCK_KEY_MISC_UNLOCK_KEY_POS

#define UNLOCK_KEY_MISC_UNLOCK_KEY_POS 0U

◆ V2D_0_VTX_Z_VTX22_ADDR

#define V2D_0_VTX_Z_VTX22_ADDR 0x264U

◆ V2D_0_VTX_Z_VTX22_MASK

#define V2D_0_VTX_Z_VTX22_MASK 0xFFU

◆ V2D_0_VTX_Z_VTX22_POS

#define V2D_0_VTX_Z_VTX22_POS 0U

◆ V2D_1_VTX_Z_VTX21_ADDR

#define V2D_1_VTX_Z_VTX21_ADDR 0x263U

◆ V2D_1_VTX_Z_VTX21_MASK

#define V2D_1_VTX_Z_VTX21_MASK 0xFFU

◆ V2D_1_VTX_Z_VTX21_POS

#define V2D_1_VTX_Z_VTX21_POS 0U

◆ V2D_2_VTX_Z_VTX20_ADDR

#define V2D_2_VTX_Z_VTX20_ADDR 0x262U

◆ V2D_2_VTX_Z_VTX20_MASK

#define V2D_2_VTX_Z_VTX20_MASK 0xFFU

◆ V2D_2_VTX_Z_VTX20_POS

#define V2D_2_VTX_Z_VTX20_POS 0U

◆ V2H_0_REF_VTG_VTX13_ADDR

#define V2H_0_REF_VTG_VTX13_ADDR 0x3E9U

◆ V2H_0_REF_VTG_VTX13_MASK

#define V2H_0_REF_VTG_VTX13_MASK 0xFFU

◆ V2H_0_REF_VTG_VTX13_POS

#define V2H_0_REF_VTG_VTX13_POS 0U

◆ V2H_0_VTX_Z_VTX13_ADDR

#define V2H_0_VTX_Z_VTX13_ADDR 0x25BU

◆ V2H_0_VTX_Z_VTX13_MASK

#define V2H_0_VTX_Z_VTX13_MASK 0xFFU

◆ V2H_0_VTX_Z_VTX13_POS

#define V2H_0_VTX_Z_VTX13_POS 0U

◆ V2H_1_REF_VTG_VTX12_ADDR

#define V2H_1_REF_VTG_VTX12_ADDR 0x3E8U

◆ V2H_1_REF_VTG_VTX12_MASK

#define V2H_1_REF_VTG_VTX12_MASK 0xFFU

◆ V2H_1_REF_VTG_VTX12_POS

#define V2H_1_REF_VTG_VTX12_POS 0U

◆ V2H_1_VTX_Z_VTX12_ADDR

#define V2H_1_VTX_Z_VTX12_ADDR 0x25AU

◆ V2H_1_VTX_Z_VTX12_MASK

#define V2H_1_VTX_Z_VTX12_MASK 0xFFU

◆ V2H_1_VTX_Z_VTX12_POS

#define V2H_1_VTX_Z_VTX12_POS 0U

◆ V2H_2_REF_VTG_VTX11_ADDR

#define V2H_2_REF_VTG_VTX11_ADDR 0x3E7U

◆ V2H_2_REF_VTG_VTX11_MASK

#define V2H_2_REF_VTG_VTX11_MASK 0xFFU

◆ V2H_2_REF_VTG_VTX11_POS

#define V2H_2_REF_VTG_VTX11_POS 0U

◆ V2H_2_VTX_Z_VTX11_ADDR

#define V2H_2_VTX_Z_VTX11_ADDR 0x259U

◆ V2H_2_VTX_Z_VTX11_MASK

#define V2H_2_VTX_Z_VTX11_MASK 0xFFU

◆ V2H_2_VTX_Z_VTX11_POS

#define V2H_2_VTX_Z_VTX11_POS 0U

◆ VC_SELZ_H_FRONTTOP_FRONTTOP_6_ADDR

#define VC_SELZ_H_FRONTTOP_FRONTTOP_6_ADDR 0x30EU

◆ VC_SELZ_H_FRONTTOP_FRONTTOP_6_MASK

#define VC_SELZ_H_FRONTTOP_FRONTTOP_6_MASK 0xFFU

◆ VC_SELZ_H_FRONTTOP_FRONTTOP_6_POS

#define VC_SELZ_H_FRONTTOP_FRONTTOP_6_POS 0U

◆ VC_SELZ_L_FRONTTOP_FRONTTOP_5_ADDR

#define VC_SELZ_L_FRONTTOP_FRONTTOP_5_ADDR 0x30DU

◆ VC_SELZ_L_FRONTTOP_FRONTTOP_5_MASK

#define VC_SELZ_L_FRONTTOP_FRONTTOP_5_MASK 0xFFU

◆ VC_SELZ_L_FRONTTOP_FRONTTOP_5_POS

#define VC_SELZ_L_FRONTTOP_FRONTTOP_5_POS 0U

◆ VDD18_OV_FLAG_TCTRL_INTR5_ADDR

#define VDD18_OV_FLAG_TCTRL_INTR5_ADDR 0x1DU

◆ VDD18_OV_FLAG_TCTRL_INTR5_MASK

#define VDD18_OV_FLAG_TCTRL_INTR5_MASK 0x10U

◆ VDD18_OV_FLAG_TCTRL_INTR5_POS

#define VDD18_OV_FLAG_TCTRL_INTR5_POS 4U

◆ VDD18_OV_OEN_TCTRL_INTR4_ADDR

#define VDD18_OV_OEN_TCTRL_INTR4_ADDR 0x1CU

◆ VDD18_OV_OEN_TCTRL_INTR4_MASK

#define VDD18_OV_OEN_TCTRL_INTR4_MASK 0x10U

◆ VDD18_OV_OEN_TCTRL_INTR4_POS

#define VDD18_OV_OEN_TCTRL_INTR4_POS 4U

◆ VDD_OV_FLAG_TCTRL_INTR5_ADDR

#define VDD_OV_FLAG_TCTRL_INTR5_ADDR 0x1DU

◆ VDD_OV_FLAG_TCTRL_INTR5_MASK

#define VDD_OV_FLAG_TCTRL_INTR5_MASK 0x20U

◆ VDD_OV_FLAG_TCTRL_INTR5_POS

#define VDD_OV_FLAG_TCTRL_INTR5_POS 5U

◆ VDD_OV_OEN_TCTRL_INTR4_ADDR

#define VDD_OV_OEN_TCTRL_INTR4_ADDR 0x1CU

◆ VDD_OV_OEN_TCTRL_INTR4_MASK

#define VDD_OV_OEN_TCTRL_INTR4_MASK 0x20U

◆ VDD_OV_OEN_TCTRL_INTR4_POS

#define VDD_OV_OEN_TCTRL_INTR4_POS 5U

◆ VDDBAD_INT_FLAG_TCTRL_INTR7_ADDR

#define VDDBAD_INT_FLAG_TCTRL_INTR7_ADDR 0x1FU

◆ VDDBAD_INT_FLAG_TCTRL_INTR7_MASK

#define VDDBAD_INT_FLAG_TCTRL_INTR7_MASK 0x20U

◆ VDDBAD_INT_FLAG_TCTRL_INTR7_POS

#define VDDBAD_INT_FLAG_TCTRL_INTR7_POS 5U

◆ VDDBAD_INT_OEN_TCTRL_INTR6_ADDR

#define VDDBAD_INT_OEN_TCTRL_INTR6_ADDR 0x1EU

◆ VDDBAD_INT_OEN_TCTRL_INTR6_MASK

#define VDDBAD_INT_OEN_TCTRL_INTR6_MASK 0x20U

◆ VDDBAD_INT_OEN_TCTRL_INTR6_POS

#define VDDBAD_INT_OEN_TCTRL_INTR6_POS 5U

◆ VDDBAD_STATUS_TCTRL_PWR0_ADDR

#define VDDBAD_STATUS_TCTRL_PWR0_ADDR 0x08U

◆ VDDBAD_STATUS_TCTRL_PWR0_MASK

#define VDDBAD_STATUS_TCTRL_PWR0_MASK 0xE0U

◆ VDDBAD_STATUS_TCTRL_PWR0_POS

#define VDDBAD_STATUS_TCTRL_PWR0_POS 5U

◆ VDDCMP_INT_FLAG_TCTRL_INTR7_ADDR

#define VDDCMP_INT_FLAG_TCTRL_INTR7_ADDR 0x1FU

◆ VDDCMP_INT_FLAG_TCTRL_INTR7_MASK

#define VDDCMP_INT_FLAG_TCTRL_INTR7_MASK 0x80U

◆ VDDCMP_INT_FLAG_TCTRL_INTR7_POS

#define VDDCMP_INT_FLAG_TCTRL_INTR7_POS 7U

◆ VDDCMP_INT_OEN_TCTRL_INTR6_ADDR

#define VDDCMP_INT_OEN_TCTRL_INTR6_ADDR 0x1EU

◆ VDDCMP_INT_OEN_TCTRL_INTR6_MASK

#define VDDCMP_INT_OEN_TCTRL_INTR6_MASK 0x80U

◆ VDDCMP_INT_OEN_TCTRL_INTR6_POS

#define VDDCMP_INT_OEN_TCTRL_INTR6_POS 7U

◆ VID_PRBS_EN_VTX_Z_VTX29_ADDR

#define VID_PRBS_EN_VTX_Z_VTX29_ADDR 0x26BU

◆ VID_PRBS_EN_VTX_Z_VTX29_MASK

#define VID_PRBS_EN_VTX_Z_VTX29_MASK 0x80U

◆ VID_PRBS_EN_VTX_Z_VTX29_POS

#define VID_PRBS_EN_VTX_Z_VTX29_POS 7U

◆ VID_TX_EN_Z_DEV_REG2_ADDR

#define VID_TX_EN_Z_DEV_REG2_ADDR 0x02U

◆ VID_TX_EN_Z_DEV_REG2_MASK

#define VID_TX_EN_Z_DEV_REG2_MASK 0x40U

◆ VID_TX_EN_Z_DEV_REG2_POS

#define VID_TX_EN_Z_DEV_REG2_POS 6U

◆ VID_TX_Z_VIDEO_TX0_ADDR

#define VID_TX_Z_VIDEO_TX0_ADDR 0x110U

◆ VID_TX_Z_VIDEO_TX0_DEFAULT

#define VID_TX_Z_VIDEO_TX0_DEFAULT 0x68U

◆ VID_TX_Z_VIDEO_TX1_ADDR

#define VID_TX_Z_VIDEO_TX1_ADDR 0x111U

◆ VID_TX_Z_VIDEO_TX1_DEFAULT

#define VID_TX_Z_VIDEO_TX1_DEFAULT 0x58U

◆ VID_TX_Z_VIDEO_TX2_ADDR

#define VID_TX_Z_VIDEO_TX2_ADDR 0x112U

◆ VID_TX_Z_VIDEO_TX2_DEFAULT

#define VID_TX_Z_VIDEO_TX2_DEFAULT 0x0AU

◆ VPRBS_FAIL_VTX_Z_VTX29_ADDR

#define VPRBS_FAIL_VTX_Z_VTX29_ADDR 0x26BU

◆ VPRBS_FAIL_VTX_Z_VTX29_MASK

#define VPRBS_FAIL_VTX_Z_VTX29_MASK 0x20U

◆ VPRBS_FAIL_VTX_Z_VTX29_POS

#define VPRBS_FAIL_VTX_Z_VTX29_POS 5U

◆ VREF_CAP_EN_TCTRL_CTRL1_ADDR

#define VREF_CAP_EN_TCTRL_CTRL1_ADDR 0x11U

◆ VREF_CAP_EN_TCTRL_CTRL1_MASK

#define VREF_CAP_EN_TCTRL_CTRL1_MASK 0x40U

◆ VREF_CAP_EN_TCTRL_CTRL1_POS

#define VREF_CAP_EN_TCTRL_CTRL1_POS 6U

◆ VREG_OV_FLAG_TCTRL_INTR5_ADDR

#define VREG_OV_FLAG_TCTRL_INTR5_ADDR 0x1DU

◆ VREG_OV_FLAG_TCTRL_INTR5_MASK

#define VREG_OV_FLAG_TCTRL_INTR5_MASK 0x80U

◆ VREG_OV_FLAG_TCTRL_INTR5_POS

#define VREG_OV_FLAG_TCTRL_INTR5_POS 7U

◆ VREG_OV_OEN_TCTRL_INTR4_ADDR

#define VREG_OV_OEN_TCTRL_INTR4_ADDR 0x1CU

◆ VREG_OV_OEN_TCTRL_INTR4_MASK

#define VREG_OV_OEN_TCTRL_INTR4_MASK 0x80U

◆ VREG_OV_OEN_TCTRL_INTR4_POS

#define VREG_OV_OEN_TCTRL_INTR4_POS 7U

◆ VS_DET_Z_MISC_HS_VS_Z_ADDR

#define VS_DET_Z_MISC_HS_VS_Z_ADDR 0x55FU

◆ VS_DET_Z_MISC_HS_VS_Z_MASK

#define VS_DET_Z_MISC_HS_VS_Z_MASK 0x20U

◆ VS_DET_Z_MISC_HS_VS_Z_POS

#define VS_DET_Z_MISC_HS_VS_Z_POS 5U

◆ VS_DLY_0_REF_VTG_REF_VTG8_ADDR

#define VS_DLY_0_REF_VTG_REF_VTG8_ADDR 0x3F8U

◆ VS_DLY_0_REF_VTG_REF_VTG8_MASK

#define VS_DLY_0_REF_VTG_REF_VTG8_MASK 0xFFU

◆ VS_DLY_0_REF_VTG_REF_VTG8_POS

#define VS_DLY_0_REF_VTG_REF_VTG8_POS 0U

◆ VS_DLY_0_VTX_Z_VTX4_ADDR

#define VS_DLY_0_VTX_Z_VTX4_ADDR 0x252U

◆ VS_DLY_0_VTX_Z_VTX4_MASK

#define VS_DLY_0_VTX_Z_VTX4_MASK 0xFFU

◆ VS_DLY_0_VTX_Z_VTX4_POS

#define VS_DLY_0_VTX_Z_VTX4_POS 0U

◆ VS_DLY_1_REF_VTG_REF_VTG7_ADDR

#define VS_DLY_1_REF_VTG_REF_VTG7_ADDR 0x3F7U

◆ VS_DLY_1_REF_VTG_REF_VTG7_MASK

#define VS_DLY_1_REF_VTG_REF_VTG7_MASK 0xFFU

◆ VS_DLY_1_REF_VTG_REF_VTG7_POS

#define VS_DLY_1_REF_VTG_REF_VTG7_POS 0U

◆ VS_DLY_1_VTX_Z_VTX3_ADDR

#define VS_DLY_1_VTX_Z_VTX3_ADDR 0x251U

◆ VS_DLY_1_VTX_Z_VTX3_MASK

#define VS_DLY_1_VTX_Z_VTX3_MASK 0xFFU

◆ VS_DLY_1_VTX_Z_VTX3_POS

#define VS_DLY_1_VTX_Z_VTX3_POS 0U

◆ VS_DLY_2_REF_VTG_REF_VTG6_ADDR

#define VS_DLY_2_REF_VTG_REF_VTG6_ADDR 0x3F6U

◆ VS_DLY_2_REF_VTG_REF_VTG6_MASK

#define VS_DLY_2_REF_VTG_REF_VTG6_MASK 0xFFU

◆ VS_DLY_2_REF_VTG_REF_VTG6_POS

#define VS_DLY_2_REF_VTG_REF_VTG6_POS 0U

◆ VS_DLY_2_VTX_Z_VTX2_ADDR

#define VS_DLY_2_VTX_Z_VTX2_ADDR 0x250U

◆ VS_DLY_2_VTX_Z_VTX2_MASK

#define VS_DLY_2_VTX_Z_VTX2_MASK 0xFFU

◆ VS_DLY_2_VTX_Z_VTX2_POS

#define VS_DLY_2_VTX_Z_VTX2_POS 0U

◆ VS_GPIO_REF_VTG_REF_VTG3_ADDR

#define VS_GPIO_REF_VTG_REF_VTG3_ADDR 0x3F3U

◆ VS_GPIO_REF_VTG_REF_VTG3_MASK

#define VS_GPIO_REF_VTG_REF_VTG3_MASK 0x3EU

◆ VS_GPIO_REF_VTG_REF_VTG3_POS

#define VS_GPIO_REF_VTG_REF_VTG3_POS 1U

◆ VS_HIGH_0_REF_VTG_VTX7_ADDR

#define VS_HIGH_0_REF_VTG_VTX7_ADDR 0x3E3U

◆ VS_HIGH_0_REF_VTG_VTX7_MASK

#define VS_HIGH_0_REF_VTG_VTX7_MASK 0xFFU

◆ VS_HIGH_0_REF_VTG_VTX7_POS

#define VS_HIGH_0_REF_VTG_VTX7_POS 0U

◆ VS_HIGH_0_VTX_Z_VTX7_ADDR

#define VS_HIGH_0_VTX_Z_VTX7_ADDR 0x255U

◆ VS_HIGH_0_VTX_Z_VTX7_MASK

#define VS_HIGH_0_VTX_Z_VTX7_MASK 0xFFU

◆ VS_HIGH_0_VTX_Z_VTX7_POS

#define VS_HIGH_0_VTX_Z_VTX7_POS 0U

◆ VS_HIGH_1_REF_VTG_VTX6_ADDR

#define VS_HIGH_1_REF_VTG_VTX6_ADDR 0x3E2U

◆ VS_HIGH_1_REF_VTG_VTX6_MASK

#define VS_HIGH_1_REF_VTG_VTX6_MASK 0xFFU

◆ VS_HIGH_1_REF_VTG_VTX6_POS

#define VS_HIGH_1_REF_VTG_VTX6_POS 0U

◆ VS_HIGH_1_VTX_Z_VTX6_ADDR

#define VS_HIGH_1_VTX_Z_VTX6_ADDR 0x254U

◆ VS_HIGH_1_VTX_Z_VTX6_MASK

#define VS_HIGH_1_VTX_Z_VTX6_MASK 0xFFU

◆ VS_HIGH_1_VTX_Z_VTX6_POS

#define VS_HIGH_1_VTX_Z_VTX6_POS 0U

◆ VS_HIGH_2_REF_VTG_VTX5_ADDR

#define VS_HIGH_2_REF_VTG_VTX5_ADDR 0x3E1U

◆ VS_HIGH_2_REF_VTG_VTX5_MASK

#define VS_HIGH_2_REF_VTG_VTX5_MASK 0xFFU

◆ VS_HIGH_2_REF_VTG_VTX5_POS

#define VS_HIGH_2_REF_VTG_VTX5_POS 0U

◆ VS_HIGH_2_VTX_Z_VTX5_ADDR

#define VS_HIGH_2_VTX_Z_VTX5_ADDR 0x253U

◆ VS_HIGH_2_VTX_Z_VTX5_MASK

#define VS_HIGH_2_VTX_Z_VTX5_MASK 0xFFU

◆ VS_HIGH_2_VTX_Z_VTX5_POS

#define VS_HIGH_2_VTX_Z_VTX5_POS 0U

◆ VS_INV_REF_VTG_VTX0_ADDR

#define VS_INV_REF_VTG_VTX0_ADDR 0x3E0U

◆ VS_INV_REF_VTG_VTX0_MASK

#define VS_INV_REF_VTG_VTX0_MASK 0x02U

◆ VS_INV_REF_VTG_VTX0_POS

#define VS_INV_REF_VTG_VTX0_POS 1U

◆ VS_INV_VTX_Z_VTX0_ADDR

#define VS_INV_VTX_Z_VTX0_ADDR 0x24EU

◆ VS_INV_VTX_Z_VTX0_MASK

#define VS_INV_VTX_Z_VTX0_MASK 0x10U

◆ VS_INV_VTX_Z_VTX0_POS

#define VS_INV_VTX_Z_VTX0_POS 4U

◆ VS_LOW_0_REF_VTG_VTX10_ADDR

#define VS_LOW_0_REF_VTG_VTX10_ADDR 0x3E6U

◆ VS_LOW_0_REF_VTG_VTX10_MASK

#define VS_LOW_0_REF_VTG_VTX10_MASK 0xFFU

◆ VS_LOW_0_REF_VTG_VTX10_POS

#define VS_LOW_0_REF_VTG_VTX10_POS 0U

◆ VS_LOW_0_VTX_Z_VTX10_ADDR

#define VS_LOW_0_VTX_Z_VTX10_ADDR 0x258U

◆ VS_LOW_0_VTX_Z_VTX10_MASK

#define VS_LOW_0_VTX_Z_VTX10_MASK 0xFFU

◆ VS_LOW_0_VTX_Z_VTX10_POS

#define VS_LOW_0_VTX_Z_VTX10_POS 0U

◆ VS_LOW_1_REF_VTG_VTX9_ADDR

#define VS_LOW_1_REF_VTG_VTX9_ADDR 0x3E5U

◆ VS_LOW_1_REF_VTG_VTX9_MASK

#define VS_LOW_1_REF_VTG_VTX9_MASK 0xFFU

◆ VS_LOW_1_REF_VTG_VTX9_POS

#define VS_LOW_1_REF_VTG_VTX9_POS 0U

◆ VS_LOW_1_VTX_Z_VTX9_ADDR

#define VS_LOW_1_VTX_Z_VTX9_ADDR 0x257U

◆ VS_LOW_1_VTX_Z_VTX9_MASK

#define VS_LOW_1_VTX_Z_VTX9_MASK 0xFFU

◆ VS_LOW_1_VTX_Z_VTX9_POS

#define VS_LOW_1_VTX_Z_VTX9_POS 0U

◆ VS_LOW_2_REF_VTG_VTX8_ADDR

#define VS_LOW_2_REF_VTG_VTX8_ADDR 0x3E4U

◆ VS_LOW_2_REF_VTG_VTX8_MASK

#define VS_LOW_2_REF_VTG_VTX8_MASK 0xFFU

◆ VS_LOW_2_REF_VTG_VTX8_POS

#define VS_LOW_2_REF_VTG_VTX8_POS 0U

◆ VS_LOW_2_VTX_Z_VTX8_ADDR

#define VS_LOW_2_VTX_Z_VTX8_ADDR 0x256U

◆ VS_LOW_2_VTX_Z_VTX8_MASK

#define VS_LOW_2_VTX_Z_VTX8_MASK 0xFFU

◆ VS_LOW_2_VTX_Z_VTX8_POS

#define VS_LOW_2_VTX_Z_VTX8_POS 0U

◆ VS_POL_Z_MISC_HS_VS_Z_ADDR

#define VS_POL_Z_MISC_HS_VS_Z_ADDR 0x55FU

◆ VS_POL_Z_MISC_HS_VS_Z_MASK

#define VS_POL_Z_MISC_HS_VS_Z_MASK 0x02U

◆ VS_POL_Z_MISC_HS_VS_Z_POS

#define VS_POL_Z_MISC_HS_VS_Z_POS 1U

◆ VS_TRIG_REF_VTG_VTX0_ADDR

#define VS_TRIG_REF_VTG_VTX0_ADDR 0x3E0U

◆ VS_TRIG_REF_VTG_VTX0_MASK

#define VS_TRIG_REF_VTG_VTX0_MASK 0x40U

◆ VS_TRIG_REF_VTG_VTX0_POS

#define VS_TRIG_REF_VTG_VTX0_POS 6U

◆ VS_TRIG_VTX_Z_VTX1_ADDR

#define VS_TRIG_VTX_Z_VTX1_ADDR 0x24FU

◆ VS_TRIG_VTX_Z_VTX1_MASK

#define VS_TRIG_VTX_Z_VTX1_MASK 0x01U

◆ VS_TRIG_VTX_Z_VTX1_POS

#define VS_TRIG_VTX_Z_VTX1_POS 0U

◆ VSEN_REF_VTG_REF_VTG3_ADDR

#define VSEN_REF_VTG_REF_VTG3_ADDR 0x3F3U

◆ VSEN_REF_VTG_REF_VTG3_MASK

#define VSEN_REF_VTG_REF_VTG3_MASK 0x01U

◆ VSEN_REF_VTG_REF_VTG3_POS

#define VSEN_REF_VTG_REF_VTG3_POS 0U

◆ VTG_MODE_VTX_Z_VTX0_ADDR

#define VTG_MODE_VTX_Z_VTX0_ADDR 0x24EU

◆ VTG_MODE_VTX_Z_VTX0_MASK

#define VTG_MODE_VTX_Z_VTX0_MASK 0x03U

◆ VTG_MODE_VTX_Z_VTX0_POS

#define VTG_MODE_VTX_Z_VTX0_POS 0U

◆ VTX_Z_CROSS_0_ADDR

#define VTX_Z_CROSS_0_ADDR 0x236U

◆ VTX_Z_CROSS_0_DEFAULT

#define VTX_Z_CROSS_0_DEFAULT 0x00U

◆ VTX_Z_CROSS_10_ADDR

#define VTX_Z_CROSS_10_ADDR 0x240U

◆ VTX_Z_CROSS_10_DEFAULT

#define VTX_Z_CROSS_10_DEFAULT 0x0AU

◆ VTX_Z_CROSS_11_ADDR

#define VTX_Z_CROSS_11_ADDR 0x241U

◆ VTX_Z_CROSS_11_DEFAULT

#define VTX_Z_CROSS_11_DEFAULT 0x0BU

◆ VTX_Z_CROSS_12_ADDR

#define VTX_Z_CROSS_12_ADDR 0x242U

◆ VTX_Z_CROSS_12_DEFAULT

#define VTX_Z_CROSS_12_DEFAULT 0x0CU

◆ VTX_Z_CROSS_13_ADDR

#define VTX_Z_CROSS_13_ADDR 0x243U

◆ VTX_Z_CROSS_13_DEFAULT

#define VTX_Z_CROSS_13_DEFAULT 0x0DU

◆ VTX_Z_CROSS_14_ADDR

#define VTX_Z_CROSS_14_ADDR 0x244U

◆ VTX_Z_CROSS_14_DEFAULT

#define VTX_Z_CROSS_14_DEFAULT 0x0EU

◆ VTX_Z_CROSS_15_ADDR

#define VTX_Z_CROSS_15_ADDR 0x245U

◆ VTX_Z_CROSS_15_DEFAULT

#define VTX_Z_CROSS_15_DEFAULT 0x0FU

◆ VTX_Z_CROSS_16_ADDR

#define VTX_Z_CROSS_16_ADDR 0x246U

◆ VTX_Z_CROSS_16_DEFAULT

#define VTX_Z_CROSS_16_DEFAULT 0x10U

◆ VTX_Z_CROSS_17_ADDR

#define VTX_Z_CROSS_17_ADDR 0x247U

◆ VTX_Z_CROSS_17_DEFAULT

#define VTX_Z_CROSS_17_DEFAULT 0x11U

◆ VTX_Z_CROSS_18_ADDR

#define VTX_Z_CROSS_18_ADDR 0x248U

◆ VTX_Z_CROSS_18_DEFAULT

#define VTX_Z_CROSS_18_DEFAULT 0x12U

◆ VTX_Z_CROSS_19_ADDR

#define VTX_Z_CROSS_19_ADDR 0x249U

◆ VTX_Z_CROSS_19_DEFAULT

#define VTX_Z_CROSS_19_DEFAULT 0x13U

◆ VTX_Z_CROSS_1_ADDR

#define VTX_Z_CROSS_1_ADDR 0x237U

◆ VTX_Z_CROSS_1_DEFAULT

#define VTX_Z_CROSS_1_DEFAULT 0x01U

◆ VTX_Z_CROSS_20_ADDR

#define VTX_Z_CROSS_20_ADDR 0x24AU

◆ VTX_Z_CROSS_20_DEFAULT

#define VTX_Z_CROSS_20_DEFAULT 0x14U

◆ VTX_Z_CROSS_21_ADDR

#define VTX_Z_CROSS_21_ADDR 0x24BU

◆ VTX_Z_CROSS_21_DEFAULT

#define VTX_Z_CROSS_21_DEFAULT 0x15U

◆ VTX_Z_CROSS_22_ADDR

#define VTX_Z_CROSS_22_ADDR 0x24CU

◆ VTX_Z_CROSS_22_DEFAULT

#define VTX_Z_CROSS_22_DEFAULT 0x16U

◆ VTX_Z_CROSS_23_ADDR

#define VTX_Z_CROSS_23_ADDR 0x24DU

◆ VTX_Z_CROSS_23_DEFAULT

#define VTX_Z_CROSS_23_DEFAULT 0x17U

◆ VTX_Z_CROSS_2_ADDR

#define VTX_Z_CROSS_2_ADDR 0x238U

◆ VTX_Z_CROSS_2_DEFAULT

#define VTX_Z_CROSS_2_DEFAULT 0x02U

◆ VTX_Z_CROSS_3_ADDR

#define VTX_Z_CROSS_3_ADDR 0x239U

◆ VTX_Z_CROSS_3_DEFAULT

#define VTX_Z_CROSS_3_DEFAULT 0x03U

◆ VTX_Z_CROSS_4_ADDR

#define VTX_Z_CROSS_4_ADDR 0x23AU

◆ VTX_Z_CROSS_4_DEFAULT

#define VTX_Z_CROSS_4_DEFAULT 0x04U

◆ VTX_Z_CROSS_5_ADDR

#define VTX_Z_CROSS_5_ADDR 0x23BU

◆ VTX_Z_CROSS_5_DEFAULT

#define VTX_Z_CROSS_5_DEFAULT 0x05U

◆ VTX_Z_CROSS_6_ADDR

#define VTX_Z_CROSS_6_ADDR 0x23CU

◆ VTX_Z_CROSS_6_DEFAULT

#define VTX_Z_CROSS_6_DEFAULT 0x06U

◆ VTX_Z_CROSS_7_ADDR

#define VTX_Z_CROSS_7_ADDR 0x23DU

◆ VTX_Z_CROSS_7_DEFAULT

#define VTX_Z_CROSS_7_DEFAULT 0x07U

◆ VTX_Z_CROSS_8_ADDR

#define VTX_Z_CROSS_8_ADDR 0x23EU

◆ VTX_Z_CROSS_8_DEFAULT

#define VTX_Z_CROSS_8_DEFAULT 0x08U

◆ VTX_Z_CROSS_9_ADDR

#define VTX_Z_CROSS_9_ADDR 0x23FU

◆ VTX_Z_CROSS_9_DEFAULT

#define VTX_Z_CROSS_9_DEFAULT 0x09U

◆ VTX_Z_VTX0_ADDR

#define VTX_Z_VTX0_ADDR 0x24EU

◆ VTX_Z_VTX0_DEFAULT

#define VTX_Z_VTX0_DEFAULT 0x03U

◆ VTX_Z_VTX10_ADDR

#define VTX_Z_VTX10_ADDR 0x258U

◆ VTX_Z_VTX10_DEFAULT

#define VTX_Z_VTX10_DEFAULT 0x00U

◆ VTX_Z_VTX11_ADDR

#define VTX_Z_VTX11_ADDR 0x259U

◆ VTX_Z_VTX11_DEFAULT

#define VTX_Z_VTX11_DEFAULT 0x00U

◆ VTX_Z_VTX12_ADDR

#define VTX_Z_VTX12_ADDR 0x25AU

◆ VTX_Z_VTX12_DEFAULT

#define VTX_Z_VTX12_DEFAULT 0x00U

◆ VTX_Z_VTX13_ADDR

#define VTX_Z_VTX13_ADDR 0x25BU

◆ VTX_Z_VTX13_DEFAULT

#define VTX_Z_VTX13_DEFAULT 0x00U

◆ VTX_Z_VTX14_ADDR

#define VTX_Z_VTX14_ADDR 0x25CU

◆ VTX_Z_VTX14_DEFAULT

#define VTX_Z_VTX14_DEFAULT 0x00U

◆ VTX_Z_VTX15_ADDR

#define VTX_Z_VTX15_ADDR 0x25DU

◆ VTX_Z_VTX15_DEFAULT

#define VTX_Z_VTX15_DEFAULT 0x00U

◆ VTX_Z_VTX16_ADDR

#define VTX_Z_VTX16_ADDR 0x25EU

◆ VTX_Z_VTX16_DEFAULT

#define VTX_Z_VTX16_DEFAULT 0x00U

◆ VTX_Z_VTX17_ADDR

#define VTX_Z_VTX17_ADDR 0x25FU

◆ VTX_Z_VTX17_DEFAULT

#define VTX_Z_VTX17_DEFAULT 0x00U

◆ VTX_Z_VTX18_ADDR

#define VTX_Z_VTX18_ADDR 0x260U

◆ VTX_Z_VTX18_DEFAULT

#define VTX_Z_VTX18_DEFAULT 0x00U

◆ VTX_Z_VTX19_ADDR

#define VTX_Z_VTX19_ADDR 0x261U

◆ VTX_Z_VTX19_DEFAULT

#define VTX_Z_VTX19_DEFAULT 0x00U

◆ VTX_Z_VTX1_ADDR

#define VTX_Z_VTX1_ADDR 0x24FU

◆ VTX_Z_VTX1_DEFAULT

#define VTX_Z_VTX1_DEFAULT 0x01U

◆ VTX_Z_VTX20_ADDR

#define VTX_Z_VTX20_ADDR 0x262U

◆ VTX_Z_VTX20_DEFAULT

#define VTX_Z_VTX20_DEFAULT 0x00U

◆ VTX_Z_VTX21_ADDR

#define VTX_Z_VTX21_ADDR 0x263U

◆ VTX_Z_VTX21_DEFAULT

#define VTX_Z_VTX21_DEFAULT 0x00U

◆ VTX_Z_VTX22_ADDR

#define VTX_Z_VTX22_ADDR 0x264U

◆ VTX_Z_VTX22_DEFAULT

#define VTX_Z_VTX22_DEFAULT 0x00U

◆ VTX_Z_VTX23_ADDR

#define VTX_Z_VTX23_ADDR 0x265U

◆ VTX_Z_VTX23_DEFAULT

#define VTX_Z_VTX23_DEFAULT 0x00U

◆ VTX_Z_VTX24_ADDR

#define VTX_Z_VTX24_ADDR 0x266U

◆ VTX_Z_VTX24_DEFAULT

#define VTX_Z_VTX24_DEFAULT 0x00U

◆ VTX_Z_VTX25_ADDR

#define VTX_Z_VTX25_ADDR 0x267U

◆ VTX_Z_VTX25_DEFAULT

#define VTX_Z_VTX25_DEFAULT 0x00U

◆ VTX_Z_VTX26_ADDR

#define VTX_Z_VTX26_ADDR 0x268U

◆ VTX_Z_VTX26_DEFAULT

#define VTX_Z_VTX26_DEFAULT 0x00U

◆ VTX_Z_VTX27_ADDR

#define VTX_Z_VTX27_ADDR 0x269U

◆ VTX_Z_VTX27_DEFAULT

#define VTX_Z_VTX27_DEFAULT 0x00U

◆ VTX_Z_VTX28_ADDR

#define VTX_Z_VTX28_ADDR 0x26AU

◆ VTX_Z_VTX28_DEFAULT

#define VTX_Z_VTX28_DEFAULT 0x00U

◆ VTX_Z_VTX29_ADDR

#define VTX_Z_VTX29_ADDR 0x26BU

◆ VTX_Z_VTX29_DEFAULT

#define VTX_Z_VTX29_DEFAULT 0x00U

◆ VTX_Z_VTX2_ADDR

#define VTX_Z_VTX2_ADDR 0x250U

◆ VTX_Z_VTX2_DEFAULT

#define VTX_Z_VTX2_DEFAULT 0x00U

◆ VTX_Z_VTX30_ADDR

#define VTX_Z_VTX30_ADDR 0x26CU

◆ VTX_Z_VTX30_DEFAULT

#define VTX_Z_VTX30_DEFAULT 0x04U

◆ VTX_Z_VTX31_ADDR

#define VTX_Z_VTX31_ADDR 0x26DU

◆ VTX_Z_VTX31_DEFAULT

#define VTX_Z_VTX31_DEFAULT 0x00U

◆ VTX_Z_VTX32_ADDR

#define VTX_Z_VTX32_ADDR 0x26EU

◆ VTX_Z_VTX32_DEFAULT

#define VTX_Z_VTX32_DEFAULT 0x00U

◆ VTX_Z_VTX33_ADDR

#define VTX_Z_VTX33_ADDR 0x26FU

◆ VTX_Z_VTX33_DEFAULT

#define VTX_Z_VTX33_DEFAULT 0x00U

◆ VTX_Z_VTX34_ADDR

#define VTX_Z_VTX34_ADDR 0x270U

◆ VTX_Z_VTX34_DEFAULT

#define VTX_Z_VTX34_DEFAULT 0x00U

◆ VTX_Z_VTX35_ADDR

#define VTX_Z_VTX35_ADDR 0x271U

◆ VTX_Z_VTX35_DEFAULT

#define VTX_Z_VTX35_DEFAULT 0x00U

◆ VTX_Z_VTX36_ADDR

#define VTX_Z_VTX36_ADDR 0x272U

◆ VTX_Z_VTX36_DEFAULT

#define VTX_Z_VTX36_DEFAULT 0x00U

◆ VTX_Z_VTX37_ADDR

#define VTX_Z_VTX37_ADDR 0x273U

◆ VTX_Z_VTX37_DEFAULT

#define VTX_Z_VTX37_DEFAULT 0x00U

◆ VTX_Z_VTX38_ADDR

#define VTX_Z_VTX38_ADDR 0x274U

◆ VTX_Z_VTX38_DEFAULT

#define VTX_Z_VTX38_DEFAULT 0x00U

◆ VTX_Z_VTX39_ADDR

#define VTX_Z_VTX39_ADDR 0x275U

◆ VTX_Z_VTX39_DEFAULT

#define VTX_Z_VTX39_DEFAULT 0x00U

◆ VTX_Z_VTX3_ADDR

#define VTX_Z_VTX3_ADDR 0x251U

◆ VTX_Z_VTX3_DEFAULT

#define VTX_Z_VTX3_DEFAULT 0x00U

◆ VTX_Z_VTX40_ADDR

#define VTX_Z_VTX40_ADDR 0x276U

◆ VTX_Z_VTX40_DEFAULT

#define VTX_Z_VTX40_DEFAULT 0x18U

◆ VTX_Z_VTX41_ADDR

#define VTX_Z_VTX41_ADDR 0x277U

◆ VTX_Z_VTX41_DEFAULT

#define VTX_Z_VTX41_DEFAULT 0x19U

◆ VTX_Z_VTX42_ADDR

#define VTX_Z_VTX42_ADDR 0x278U

◆ VTX_Z_VTX42_DEFAULT

#define VTX_Z_VTX42_DEFAULT 0x1AU

◆ VTX_Z_VTX4_ADDR

#define VTX_Z_VTX4_ADDR 0x252U

◆ VTX_Z_VTX4_DEFAULT

#define VTX_Z_VTX4_DEFAULT 0x00U

◆ VTX_Z_VTX5_ADDR

#define VTX_Z_VTX5_ADDR 0x253U

◆ VTX_Z_VTX5_DEFAULT

#define VTX_Z_VTX5_DEFAULT 0x00U

◆ VTX_Z_VTX6_ADDR

#define VTX_Z_VTX6_ADDR 0x254U

◆ VTX_Z_VTX6_DEFAULT

#define VTX_Z_VTX6_DEFAULT 0x00U

◆ VTX_Z_VTX7_ADDR

#define VTX_Z_VTX7_ADDR 0x255U

◆ VTX_Z_VTX7_DEFAULT

#define VTX_Z_VTX7_DEFAULT 0x00U

◆ VTX_Z_VTX8_ADDR

#define VTX_Z_VTX8_ADDR 0x256U

◆ VTX_Z_VTX8_DEFAULT

#define VTX_Z_VTX8_DEFAULT 0x00U

◆ VTX_Z_VTX9_ADDR

#define VTX_Z_VTX9_ADDR 0x257U

◆ VTX_Z_VTX9_DEFAULT

#define VTX_Z_VTX9_DEFAULT 0x00U

◆ WAKE_EN_A_TCTRL_PWR4_ADDR

#define WAKE_EN_A_TCTRL_PWR4_ADDR 0x0CU

◆ WAKE_EN_A_TCTRL_PWR4_MASK

#define WAKE_EN_A_TCTRL_PWR4_MASK 0x10U

◆ WAKE_EN_A_TCTRL_PWR4_POS

#define WAKE_EN_A_TCTRL_PWR4_POS 4U

◆ XTAL_PU_DEV_REG4_ADDR

#define XTAL_PU_DEV_REG4_ADDR 0x04U

◆ XTAL_PU_DEV_REG4_MASK

#define XTAL_PU_DEV_REG4_MASK 0x01U

◆ XTAL_PU_DEV_REG4_POS

#define XTAL_PU_DEV_REG4_POS 0U

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