precision-converters-firmware
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app_config_stm32.h
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1/***************************************************************************/
13#ifndef APP_CONFIG_STM32_H_
14#define APP_CONFIG_STM32_H_
15
16/******************************************************************************/
17/***************************** Include Files **********************************/
18/******************************************************************************/
19#include "main.h"
20#include "stm32_spi.h"
21#include "stm32_i2c.h"
22#include "stm32_uart.h"
23#include "stm32_gpio.h"
24#include "app_config.h"
25#if (INTERFACE_MODE != SPI_DMA_MODE)
26#include "stm32_gpio_irq.h"
27#else
28#include "stm32_dma.h"
29#endif
30#include "stm32_tdm.h"
31#if (INTERFACE_MODE == SPI_DMA_MODE)
32#include "stm32_pwm.h"
33#endif
34#if defined (TARGET_SDP_K1)
35#include "stm32_usb_uart.h"
36#endif
37
38/******************************************************************************/
39/********************** Macros and Constants Definition ***********************/
40/******************************************************************************/
41
42#if defined (TARGET_SDP_K1)
43/* The below configurations are specific to STM32F469NIH6 MCU on SDP-K1 Board. */
44#define HW_CARRIER_NAME SDP_K1
45
46/* STM32 SPI Specific parameters */
47#define STM32_SPI_ID 1 // SPI1
48#define STM32_SPI_CS_PORT 0 // GPIO Port A
49#define SPI_CSB 15 // PA_15
50
51/* STM32 I2C Specific parameters */
52#define STM32_I2C_ID 1 // I2C1
53
54/* STM32 UART specific parameters */
55#define APP_UART_HANDLE &huart5
56#define UART_IRQ_ID UART5_IRQn
57
58/* STM32 GPIO specific parameters */
59#define DIG_AUX_1 7 // PG7
60#define DIG_AUX_2 10 // PG10
61#define SYNC_INB 9 // PG9
62#define LED_GPO 4
63
64#define DIG_AUX_1_PORT 6 // GPIOG
65#define DIG_AUX_2_PORT 6 // GPIOG
66#define SYNC_INB_PORT 6 // GPIOG
67#define SYNC_INB_PORT_ID GPIOG
68
69#define GPIO_TRIGGER_INT_PORT EXTI_GPIOG // PG7
70
71#define I2C_TIMING 0 // (Unused)
72
73/* SPI DMA specific parameters */
74#define AD469x_DMA_NUM_CHANNELS 2
75
76#define Rx_DMA_IRQ_ID DMA2_Stream0_IRQn
77#define AD469x_TxDMA_CHANNEL_NUM DMA_CHANNEL_7
78#define AD469x_RxDMA_CHANNEL_NUM DMA_CHANNEL_3
79
80/* Tx Trigger timer parameters */
81#define TX_TRIGGER_TIMER_ID 8 // Timer 8
82#define TX_TRIGGER_TIMER_HANDLE htim8
83/* Tx trigger period considering a MAX SPI clock of 20MHz and 32 bit transfer */
84#define TX_TRIGGER_PERIOD 700
85#define TX_TRIGGER_DUTY_RATIO 30
86#define TIMER_8_PRESCALER 0
87#define TIMER_8_CLK_DIVIDER 2
88#define TIMER_CHANNEL_1 1
89#else
90/* The below configurations are specific to STM32H563ZIT6 MCU on NUCLEO-H563ZI Board. */
91#define HW_CARRIER_NAME NUCLEO-H563ZI
92
93/* STM32 SPI Specific parameters */
94#define STM32_SPI_ID 1 // SPI1
95#define STM32_SPI_CS_PORT 3 // GPIO Port D
96#define SPI_CSB 14 // PD_14
97
98/* STM32 I2C Specific parameters */
99#define STM32_I2C_ID 1 // I2C1
100
101/* STM32 UART specific parameters */
102#define APP_UART_HANDLE &huart3
103
104/* STM32 GPIO specific parameters */
105#define DIG_AUX_1 14 // PG14
106#define DIG_AUX_2 12 // PG12
107#define SYNC_INB 14 // PE14
108#define LED_GPO LED1_GREEN_Pin
109
110#define DIG_AUX_1_PORT 6 // GPIOG
111#define DIG_AUX_2_PORT 6 // GPIOG
112#define SYNC_INB_PORT 4 // GPIOE
113
114#define GPIO_TRIGGER_INT_PORT EXTI_GPIOG // PG14
115
116/* I2C timing register value for standard mode of operation
117 * Check here for more understanding on I2C timing register
118 * configuration: https://wiki.analog.com/resources/no-os/drivers/i2c */
119#define I2C_TIMING 0x00000E14
120
121/* TDM specific Parameters */
122#define TDM_DATA_SIZE 32
123#define TDM_SLOTS_PER_FRAME 1
124#define TDM_FS_ACTIVE_LENGTH 8
125
126/* Expect DMA to read 800 samples in one cycle */
127#define TDM_N_SAMPLES_DMA_READ 800
128/* This makes sure that the processor gets into the
129 * Half complete callback function after every 400 samples */
130#define TDM_DMA_READ_SIZE TDM_N_SAMPLES_DMA_READ * TDM_SLOTS_PER_FRAME/2
131
132#define STM32_SAI_BASE SAI1_Block_A
133#endif
134
135/* Note: The below macro and the type of digital filter chosen together
136 * decides the output data rate to be configured for the device.
137 * Filter configuration can be modified by changing the macro "AD4170_FILTER_CONFIG"
138 * in the respective user configuration header file.
139 * Please refer to the datasheet for more details on the other filter configurations.
140 * It has to be noted that this is not the maximum ODR permissible by the device, but
141 * a value specific to the NUCLEO-H563ZI platform tested with a 10MHz SPI clock. The maximum
142 * ODR might vary across platforms and data continuity is not guaranteed above this ODR
143 * on the IIO Client*/
144
145/* Value corresponding to 24KSPS ODR (per channel) with Sinc5 average filter */
146#define FS_SINC5_AVG_24_KSPS 20
147
148/* Value corresponding to 512ksps ODR (per channel) with Sinc5 filter */
149#define FS_SINC5_512_KSPS 1
150
151/* Value corresponding to 62.5 ODR (per channel) with Sinc3 filter */
152#define FS_SINC3_62P5_KSPS 4
153
154#if (INTERFACE_MODE == SPI_INTERRUPT_MODE)
155#define FS_CONFIG_VALUE FS_SINC5_AVG_24_KSPS
156#define AD4170_MAX_SAMPLING_RATE 24000
157#else // TDM_MODE and SPI_DMA_MODE
158#if defined (DEV_AD4170)
159#define FS_CONFIG_VALUE FS_SINC5_512_KSPS
160#define AD4170_MAX_SAMPLING_RATE 500000
161#elif defined (DEV_AD4190)
162#define FS_CONFIG_VALUE FS_SINC3_62P5_KSPS
163#define AD4170_MAX_SAMPLING_RATE 62500
164#endif
165#endif
166
167#define TICKER_INTERRUPT_PERIOD_uSEC (0) // unused
168
169/* Max SPI Speed */
170#define AD4170_MAX_SPI_SPEED 20000000
171
172/******************************************************************************/
173/********************** Public/Extern Declarations ****************************/
174/******************************************************************************/
175
176extern struct stm32_spi_init_param stm32_spi_extra_init_params;
177extern struct stm32_uart_init_param stm32_uart_extra_init_params;
178extern struct stm32_gpio_init_param stm32_trigger_gpio_extra_init_params;
179extern struct stm32_gpio_init_param stm32_dig_aux1_gpio_extra_init_params;
180extern struct stm32_gpio_init_param stm32_dig_aux2_gpio_extra_init_params;
181extern struct stm32_gpio_init_param stm32_sync_inb_gpio_extra_init_params;
182extern struct stm32_gpio_init_param stm32_csb_gpio_extra_init_params;
183extern struct stm32_gpio_irq_init_param stm32_trigger_gpio_irq_init_params;
184extern struct stm32_tdm_init_param stm32_tdm_extra_init_params;
185extern struct stm32_i2c_init_param stm32_i2c_extra_init_params;
186#if !defined (TARGET_SDP_K1)
187extern UART_HandleTypeDef huart3;
188#else
189extern TIM_HandleTypeDef htim8;
190extern UART_HandleTypeDef huart5;
191extern DMA_HandleTypeDef hdma_spi1_rx;
192extern DMA_HandleTypeDef hdma_tim8_ch1;
193extern USBD_HandleTypeDef hUsbDeviceHS;
195#endif
196extern bool data_capture_operation;
197extern struct iio_device_data *ad4170_iio_dev_data;
198extern uint8_t num_of_active_channels;
199extern volatile bool tdm_read_started;
200extern volatile struct iio_device_data* iio_dev_data_g;
201extern uint32_t nb_of_samples_g;
202extern volatile uint32_t* buff_start_addr;
203extern int32_t data_read;
204extern uint32_t rxdma_ndtr;
205extern volatile bool ad4170_dma_buff_full;
206extern uint32_t dma_cycle_count;
207extern struct stm32_spi_desc* sdesc;
208
209#if (INTERFACE_MODE == SPI_DMA_MODE)
210extern struct stm32_pwm_init_param stm32_tx_trigger_extra_init_params;
211extern struct no_os_dma_init_param ad4170_dma_init_param;
212extern struct stm32_dma_channel rxdma_channel;
213extern struct stm32_dma_channel txdma_channel;
214#endif
215
216void tim8_config(void);
217void stm32_timer_stop(void);
218void stm32_system_init(void);
219void stm32_abort_dma_transfer(void);
220void ad4170_dma_rx_cplt(SAI_HandleTypeDef *hsai);
221void ad4170_dma_rx_half_cplt(SAI_HandleTypeDef *hsai);
222void ad4170_spi_dma_rx_cplt_callback(DMA_HandleTypeDef* hdma);
223void ad4170_spi_dma_rx_half_cplt_callback(DMA_HandleTypeDef* hdma);
224void update_buff(uint32_t* local_buf, uint32_t* buf_start_addr);
225void tim8_init(struct no_os_pwm_desc *pwm_desc);
227extern volatile uint32_t callback_count;
228#endif /* APP_CONFIG_STM32_H_ */
struct no_os_pwm_desc * pwm_desc
Definition app_config.c:106
int stm32_timer_stop(void)
Stop generating timer signals.
Definition app_config_stm32.c:281
UART_HandleTypeDef huart5
DMA_HandleTypeDef hdma_tim8_ch1
struct stm32_dma_channel rxdma_channel
Definition app_config_stm32.c:136
USBD_HandleTypeDef hUsbDeviceHS
void stm32_system_init(void)
Initialize the STM32 system peripherals.
Definition app_config_stm32.c:176
void tim8_config(void)
Configure Tx Trigger timer for slave mode operation, one-pulse mode and to generate DMA requests.
Definition app_config_stm32.c:245
struct stm32_pwm_init_param stm32_tx_trigger_extra_init_params
Definition app_config_stm32.c:99
int stm32_abort_dma_transfer(void)
Abort DMA Transfers.
Definition app_config_stm32.c:315
struct stm32_usb_uart_init_param stm32_vcom_extra_init_params
Definition app_config_stm32.c:38
DMA_HandleTypeDef hdma_spi1_rx
struct stm32_gpio_irq_init_param stm32_trigger_gpio_irq_init_params
Definition app_config_stm32.c:43
struct stm32_i2c_init_param stm32_i2c_extra_init_params
Definition app_config_stm32.c:152
volatile int dma_cycle_count
Definition app_config_stm32.c:242
uint32_t rxdma_ndtr
Definition app_config_stm32.c:245
void update_buff(uint8_t *local_buf, uint8_t *buf_start_addr)
Update buffer index.
Definition app_config_stm32.c:499
struct stm32_uart_init_param stm32_uart_extra_init_params
Definition app_config_stm32.c:102
uint8_t local_buf[MAX_LOCAL_BUF_SIZE]
Definition ad405x_support.c:42
struct stm32_spi_init_param stm32_spi_extra_init_params
Definition app_config_stm32.c:46
struct stm32_tdm_init_param stm32_tdm_extra_init_params
Definition app_config_stm32.c:52
bool data_capture_operation
Definition ad4134_iio.c:96
UART_HandleTypeDef huart3
struct stm32_gpio_init_param stm32_csb_gpio_extra_init_params
Definition app_config_stm32.c:96
struct stm32_gpio_init_param stm32_sync_inb_gpio_extra_init_params
Definition app_config_stm32.c:76
volatile struct iio_device_data * iio_dev_data_g
Definition ad405x_iio.c:281
uint32_t nb_of_samples_g
Definition ad4170_iio.c:386
struct stm32_dma_channel txdma_channel
Definition app_config_stm32.c:115
void ad4170_dma_rx_half_cplt(SAI_HandleTypeDef *hsai)
SAI DMA Receive Half Complete Callback function.
Definition app_config_stm32.c:211
volatile uint32_t callback_count
Definition app_config_stm32.c:35
struct stm32_gpio_init_param stm32_dig_aux2_gpio_extra_init_params
Definition app_config_stm32.c:70
volatile bool ad4170_dma_buff_full
Definition ad4170_iio.c:395
void ad4170_spi_dma_rx_half_cplt_callback(DMA_HandleTypeDef *hdma)
Callback function to flag the capture of Half the number of requested samples.
Definition app_config_stm32.c:307
struct iio_device_data * ad4170_iio_dev_data
Definition ad4170_iio.c:320
struct stm32_spi_desc * sdesc
Definition app_config_stm32.c:146
void tim8_init(struct no_os_pwm_desc *pwm_desc)
Initialize Tx trigger advanced PWM parameters.
Definition app_config_stm32.c:408
uint8_t num_of_active_channels
Definition ad4170_iio.c:184
void ad4170_spi_dma_rx_cplt_callback(DMA_HandleTypeDef *hdma)
Callback function to flag the capture of number of requested samples.
Definition app_config_stm32.c:270
volatile bool tdm_read_started
Definition ad4170_iio.c:331
struct stm32_gpio_init_param stm32_dig_aux1_gpio_extra_init_params
Definition app_config_stm32.c:64
volatile uint32_t * buff_start_addr
Definition ad405x_iio.c:140
int32_t data_read
Definition app_support.c:49
struct stm32_gpio_init_param stm32_trigger_gpio_extra_init_params
Definition app_config_stm32.c:58
struct no_os_dma_init_param ad4170_dma_init_param
Definition app_config.c:182
void MX_USB_DEVICE_Init(void)
void ad4170_dma_rx_cplt(SAI_HandleTypeDef *hsai)
SAI DMA Receive Complete Callback function.
Definition app_config_stm32.c:228
TIM_HandleTypeDef htim8
Configuration file of nanodac firmware example program.
VCOM driver for stm32 as a no_os_uart implementation.
Specific initialization parameters for stm32 UART over USB.
Definition stm32_usb_uart.h:27