Reference

AD9523-1 clock chip model.

ad9523_1

Bases: ad9523_1_bf

AD9523-1 clock chip model.

This model currently supports VCXO+PLL2 configurations

Source code in adijif/clocks/ad9523.py

class ad9523_1(ad9523_1_bf):
    """AD9523-1 clock chip model.

    This model currently supports VCXO+PLL2 configurations
    """

    # Ranges
    m1_available = [3, 4, 5]
    d_available = [*range(1, 1024)]
    n2_available = [12, 16, 17, 20, 21, 22, 24, 25, 26, *range(28, 255)]
    a_available = [*range(0, 4)]
    b_available = [*range(3, 64)]
    # N = (PxB) + A, P=4, A==[0,1,2,3], B=[3..63]
    # See table 46 of DS for limits
    r2_available = list(range(1, 31 + 1))

    # Defaults
    _m1: Union[List[int], int] = [3, 4, 5]
    _d: Union[List[int], int] = [*range(1, 1024)]
    _n2: Union[List[int], int] = [
        12,
        16,
        17,
        20,
        21,
        22,
        24,
        25,
        26,
        *range(28, 255),
    ]
    _r2: Union[List[int], int] = list(range(1, 31 + 1))

    # Limits
    vco_min = 2.94e9
    vco_max = 3.1e9
    pfd_max = 259e6

    # State management
    _clk_names: List[str] = []

    minimize_feedback_dividers = True

    """ Enable internal VCXO/PLL1 doubler """
    use_vcxo_double = False

    vcxo: Union[int, float, CpoIntVar] = 125e6

    @property
    def m1(self) -> Union[int, List[int]]:
        """VCO divider path 1.

        Valid dividers are 3,4,5

        Returns:
            int: Current allowable dividers
        """
        return self._m1

    @m1.setter
    def m1(self, value: Union[int, List[int]]) -> None:
        """VCO divider path 1.

        Valid dividers are 3,4,5

        Args:
            value (int, list[int]): Allowable values for divider

        """
        self._check_in_range(value, self.m1_available, "m1")
        self._m1 = value

    @property
    def d(self) -> Union[int, List[int]]:
        """Output dividers.

        Valid dividers are 1->1023

        Returns:
            int: Current allowable dividers
        """
        return self._d

    @d.setter
    def d(self, value: Union[int, List[int]]) -> None:
        """Output dividers.

        Valid dividers are 1->1023

        Args:
            value (int, list[int]): Allowable values for divider

        """
        self._check_in_range(value, self.d_available, "d")
        self._d = value

    @property
    def n2(self) -> Union[int, List[int]]:
        """n2: VCO feedback divider.

        Valid dividers are 12, 16, 17, 20, 21, 22, 24, 25, 26, 28->255

        Returns:
            int: Current allowable dividers
        """
        return self._n2

    @n2.setter
    def n2(self, value: Union[int, List[int]]) -> None:
        """VCO feedback divider.

        Valid dividers are 12, 16, 17, 20, 21, 22, 24, 25, 26, 28->255

        Args:
            value (int, list[int]): Allowable values for divider

        """
        self._check_in_range(value, self.n2_available, "n2")
        self._n2 = value

    @property
    def r2(self) -> Union[int, List[int]]:
        """VCXO input dividers.

        Valid dividers are 1->31

        Returns:
            int: Current allowable dividers
        """
        return self._r2

    @r2.setter
    def r2(self, value: Union[int, List[int]]) -> None:
        """VCXO input dividers.

        Valid dividers are 1->31

        Args:
            value (int, list[int]): Allowable values for divider

        """
        self._check_in_range(value, self.r2_available, "r2")
        self._r2 = value

    def get_config(self, solution: CpoSolveResult = None) -> Dict:
        """Extract configurations from solver results.

        Collect internal clock chip configuration and output clock definitions
        leading to connected devices (converters, FPGAs)

        Args:
            solution (CpoSolveResult): CPlex solution. Only needed for CPlex solver

        Returns:
            Dict: Dictionary of clocking rates and dividers for configuration

        Raises:
            Exception: If solver is not called first
        """
        if not self._clk_names:
            raise Exception(
                "set_requested_clocks must be called before get_config"
            )
        for k in ["out_dividers", "m1", "n2", "r2"]:
            if k not in self.config.keys():
                raise Exception("Missing key: " + str(k))

        if solution:  # type: ignore
            self.solution = solution
        config: Dict = {
            "m1": self._get_val(self.config["m1"]),
            "n2": self._get_val(self.config["n2"]),
            "r2": self._get_val(self.config["r2"]),
            "out_dividers": [
                self._get_val(x) for x in self.config["out_dividers"]
            ],
            "output_clocks": [],
        }

        config["vcxo"] = self._get_val(
            self.vcxo
        )  # pytype: disable=attribute-error
        vcxo = config["vcxo"]

        clk = vcxo / config["r2"] * config["n2"] / config["m1"]
        output_cfg = {}
        for i, div in enumerate(self.config["out_dividers"]):
            div = self._get_val(div)
            rate = clk / div
            output_cfg[self._clk_names[i]] = {"rate": rate, "divider": div}
        config["output_clocks"] = output_cfg
        config["vco"] = clk
        config["part"] = "AD9523-1"

        return config

    def _setup_solver_constraints(
        self, vcxo: Union[float, int, CpoIntVar]
    ) -> None:
        """Apply constraints to solver model.

        Args:
            vcxo (int): VCXO frequency in hertz

        Raises:
            Exception: Unknown solver
        """
        self.config = {
            "r2": self._convert_input(self._r2, "r2"),
            "m1": self._convert_input(self._m1, "m1"),
            "n2": self._convert_input(self._n2, "n2"),
        }
        if not isinstance(vcxo, (int, float)):
            self.config["vcxo_set"] = vcxo(self.model)  # type: ignore
            vcxo = self.config["vcxo_set"]["range"]
        self.vcxo = vcxo

        # PLL2 equations
        self._add_equation(
            [
                vcxo / self.config["r2"] <= self.pfd_max,
                vcxo / self.config["r2"] * self.config["n2"] <= self.vco_max,
                vcxo / self.config["r2"] * self.config["n2"] >= self.vco_min,
            ]
        )
        # Objectives
        if self.minimize_feedback_dividers:
            if self.solver == "CPLEX":
                ...
                # self.model.minimize(self.config["n2"])
                # cost = self.model
                # self.model.minimize_static_lex([self.config["n2"],])
            elif self.solver == "gekko":
                self.model.Obj(self.config["n2"])
            else:
                raise Exception("Unknown solver {}".format(self.solver))

    def _add_objective(self, sys_refs: List[CpoIntVar]) -> None:
        # Minimize feedback divider and sysref frequencies
        if self.minimize_feedback_dividers:
            self._objectives = [self.config["n2"]] + sys_refs
            # self.model.add(
            #     self.model.minimize_static_lex([self.config["n2"]] + sys_refs)
            # )
        else:
            self._objectives = [sys_refs]
            # self.model.add(self.model.minimize_static_lex(sys_refs))

    def _setup(self, vcxo: int) -> None:
        # Setup clock chip internal constraints

        # FIXME: ADD SPLIT m1 configuration support

        if self.use_vcxo_double and not isinstance(vcxo, int):
            raise Exception("VCXO doubler not supported in this mode TBD")
        if self.use_vcxo_double:
            vcxo *= 2
        self._setup_solver_constraints(vcxo)
        self.config["out_dividers"] = []

    def _get_clock_constraint(
        self, clk_name: List[str]
    ) -> Union[int, float, CpoExpr, GK_Intermediate]:
        """Get abstract clock output.

        Args:
            clk_name (str):  String of clock name

        Returns:
            (int or float or CpoExpr or GK_Intermediate): Abstract
                or concrete clock reference
        """
        od = self._convert_input(self._d, "d_" + str(clk_name))
        self.config["out_dividers"].append(od)
        return (
            self.vcxo
            / self.config["r2"]
            * self.config["n2"]
            / self.config["m1"]
            / od
        )

    def set_requested_clocks(
        self, vcxo: int, out_freqs: List, clk_names: List[str]
    ) -> None:
        """Define necessary clocks to be generated in model.

        Args:
            vcxo (int): VCXO frequency in hertz
            out_freqs (List): list of required clocks to be output
            clk_names (List[str]):  list of strings of clock names

        Raises:
            Exception: If len(out_freqs) != len(clk_names)
        """
        if len(clk_names) != len(out_freqs):
            raise Exception("clk_names is not the same size as out_freqs")
        self._clk_names = clk_names

        # Setup clock chip internal constraints
        self._setup(vcxo)

        # Add requested clocks to output constraints
        for out_freq in out_freqs:
            # od = self.model.Var(integer=True, lb=1, ub=1023, value=1)
            od = self._convert_input(self._d, "d_" + str(out_freq))
            # od = self.model.sos1([n*n for n in range(1,9)])

            self._add_equation(
                [
                    self.vcxo
                    / self.config["r2"]
                    * self.config["n2"]
                    / self.config["m1"]
                    / od
                    == out_freq
                ]
            )
            self.config["out_dividers"].append(od)

d: Union[int, List[int]] property writable

Output dividers.

Valid dividers are 1->1023

Returns:

Name	Type	Description
int	Union[int, List[int]]	Current allowable dividers

m1: Union[int, List[int]] property writable

VCO divider path 1.

Valid dividers are 3,4,5

Returns:

Name	Type	Description
int	Union[int, List[int]]	Current allowable dividers

minimize_feedback_dividers = True class-attribute instance-attribute

Enable internal VCXO/PLL1 doubler

n2: Union[int, List[int]] property writable

n2: VCO feedback divider.

Valid dividers are 12, 16, 17, 20, 21, 22, 24, 25, 26, 28->255

Returns:

Name	Type	Description
int	Union[int, List[int]]	Current allowable dividers

r2: Union[int, List[int]] property writable

VCXO input dividers.

Valid dividers are 1->31

Returns:

Name	Type	Description
int	Union[int, List[int]]	Current allowable dividers

get_config(solution=None)

Extract configurations from solver results.

Collect internal clock chip configuration and output clock definitions leading to connected devices (converters, FPGAs)

Parameters:

Name	Type	Description	Default
solution	CpoSolveResult	CPlex solution. Only needed for CPlex solver	None

Returns:

Name	Type	Description
Dict	Dict	Dictionary of clocking rates and dividers for configuration

Raises:

Type	Description
Exception	If solver is not called first

Source code in adijif/clocks/ad9523.py

def get_config(self, solution: CpoSolveResult = None) -> Dict:
    """Extract configurations from solver results.

    Collect internal clock chip configuration and output clock definitions
    leading to connected devices (converters, FPGAs)

    Args:
        solution (CpoSolveResult): CPlex solution. Only needed for CPlex solver

    Returns:
        Dict: Dictionary of clocking rates and dividers for configuration

    Raises:
        Exception: If solver is not called first
    """
    if not self._clk_names:
        raise Exception(
            "set_requested_clocks must be called before get_config"
        )
    for k in ["out_dividers", "m1", "n2", "r2"]:
        if k not in self.config.keys():
            raise Exception("Missing key: " + str(k))

    if solution:  # type: ignore
        self.solution = solution
    config: Dict = {
        "m1": self._get_val(self.config["m1"]),
        "n2": self._get_val(self.config["n2"]),
        "r2": self._get_val(self.config["r2"]),
        "out_dividers": [
            self._get_val(x) for x in self.config["out_dividers"]
        ],
        "output_clocks": [],
    }

    config["vcxo"] = self._get_val(
        self.vcxo
    )  # pytype: disable=attribute-error
    vcxo = config["vcxo"]

    clk = vcxo / config["r2"] * config["n2"] / config["m1"]
    output_cfg = {}
    for i, div in enumerate(self.config["out_dividers"]):
        div = self._get_val(div)
        rate = clk / div
        output_cfg[self._clk_names[i]] = {"rate": rate, "divider": div}
    config["output_clocks"] = output_cfg
    config["vco"] = clk
    config["part"] = "AD9523-1"

    return config

set_requested_clocks(vcxo, out_freqs, clk_names)

Define necessary clocks to be generated in model.

Parameters:

Name	Type	Description	Default
vcxo	int	VCXO frequency in hertz	required
out_freqs	List	list of required clocks to be output	required
clk_names	List[str]	list of strings of clock names	required

Raises:

Type	Description
Exception	If len(out_freqs) != len(clk_names)

Source code in adijif/clocks/ad9523.py

def set_requested_clocks(
    self, vcxo: int, out_freqs: List, clk_names: List[str]
) -> None:
    """Define necessary clocks to be generated in model.

    Args:
        vcxo (int): VCXO frequency in hertz
        out_freqs (List): list of required clocks to be output
        clk_names (List[str]):  list of strings of clock names

    Raises:
        Exception: If len(out_freqs) != len(clk_names)
    """
    if len(clk_names) != len(out_freqs):
        raise Exception("clk_names is not the same size as out_freqs")
    self._clk_names = clk_names

    # Setup clock chip internal constraints
    self._setup(vcxo)

    # Add requested clocks to output constraints
    for out_freq in out_freqs:
        # od = self.model.Var(integer=True, lb=1, ub=1023, value=1)
        od = self._convert_input(self._d, "d_" + str(out_freq))
        # od = self.model.sos1([n*n for n in range(1,9)])

        self._add_equation(
            [
                self.vcxo
                / self.config["r2"]
                * self.config["n2"]
                / self.config["m1"]
                / od
                == out_freq
            ]
        )
        self.config["out_dividers"].append(od)

AD9528 clock chip model.

ad9528

Bases: ad9528_bf

AD9528 clock chip model.

This model currently supports VCXO+PLL2 configurations

Source code in adijif/clocks/ad9528.py

class ad9528(ad9528_bf):
    """AD9528 clock chip model.

    This model currently supports VCXO+PLL2 configurations
    """

    # Ranges
    """ VCO divider """
    m1_available = [3, 4, 5]
    """ Output dividers """
    d_available = [*range(1, 1024)]
    """ sysref dividers """
    k_available = [*range(0, 65536)]
    """ VCXO multiplier """
    n2_available = [*range(1, 256)]
    """ VCO calibration dividers """
    a_available = [0, 1, 2, 3]
    b_availble = [*range(3, 64)]
    # N = (PxB) + A, P=4, A==[0,1,2,3], B=[3..63]
    # See table 46 of DS for limits
    """ VCXO dividers """
    r1_available = [*range(1, 32)]

    # State management
    _clk_names: List[str] = []

    # Defaults
    _m1: Union[List[int], int] = [3, 4, 5]
    _d: Union[List[int], int] = [*range(1, 1024)]
    _k: Union[List[int], int] = k_available
    _n2: Union[List[int], int] = n2_available
    _r1: Union[List[int], int] = [*range(1, 32)]
    _a: Union[List[int], int] = [*range(0, 4)]
    _b: Union[List[int], int] = [*range(3, 64)]

    # Limits
    vco_min = 3450e6
    vco_max = 4025e6
    pfd_max = 275e6

    minimize_feedback_dividers = True

    use_vcxo_double = False
    vcxo = 125e6

    # sysref parameters
    sysref_external = False
    _sysref = None

    @property
    def m1(self) -> Union[int, List[int]]:
        """VCO divider path 1.

        Valid dividers are 3,4,5

        Returns:
            int: Current allowable dividers
        """
        return self._m1

    @m1.setter
    def m1(self, value: Union[int, List[int]]) -> None:
        """VCO divider path 1.

        Valid dividers are 3,4,5

        Args:
            value (int, list[int]): Allowable values for divider

        """
        self._check_in_range(value, self.m1_available, "m1")
        self._m1 = value

    @property
    def d(self) -> Union[int, List[int]]:
        """Output dividers.

        Valid dividers are 1->1023

        Returns:
            int: Current allowable dividers
        """
        return self._d

    @d.setter
    def d(self, value: Union[int, List[int]]) -> None:
        """Output dividers.

        Valid dividers are 1->1023

        Args:
            value (int, list[int]): Allowable values for divider

        """
        self._check_in_range(value, self.d_available, "d")
        self._d = value

    @property
    def k(self) -> Union[int, List[int]]:
        """Sysref dividers.

        Valid dividers are 0->65535

        Returns:
            int: Current allowable dividers
        """
        return self._k

    @k.setter
    def k(self, value: Union[int, List[int]]) -> None:
        """Sysref dividers.

        Valid dividers are 0->65535

        Args:
            value (int, list[int]): Allowable values for divider

        """
        self._check_in_range(value, self.d_available, "k")
        self._k = value

    @property
    def n2(self) -> Union[int, List[int]]:
        """n2: VCO feedback divider.

        Valid dividers are 1->255

        Returns:
            int: Current allowable dividers
        """
        return self._n2

    @n2.setter
    def n2(self, value: Union[int, List[int]]) -> None:
        """VCO feedback divider.

        Valid dividers are 1->255

        Args:
            value (int, list[int]): Allowable values for divider

        """
        self._check_in_range(value, self.n2_available, "n2")
        self._n2 = value

    @property
    def r1(self) -> Union[int, List[int]]:
        """VCXO input dividers.

        Valid dividers are 1->31

        Returns:
            int: Current allowable dividers
        """
        return self._r1

    @r1.setter
    def r1(self, value: Union[int, List[int]]) -> None:
        """VCXO input dividers.

        Valid dividers are 1->31

        Args:
            value (int, list[int]): Allowable values for divider

        """
        self._check_in_range(value, self.r1_available, "r1")
        self._r1 = value

    @property
    def a(self) -> Union[int, List[int]]:
        """VCO calibration divider 1.

        Valid dividers are 0->3

        Returns:
            int: Current allowable dividers
        """
        return self._a

    @a.setter
    def a(self, value: Union[int, List[int]]) -> None:
        """VCO calibration divider 1.

        Valid dividers are 0->3

        Args:
            value (int, list[int]): Allowable values for counter

        """
        self._check_in_range(value, self.a_available, "a")
        self._a = value

    @property
    def b(self) -> Union[int, List[int]]:
        """VCO calibration divider 2.

        Valid dividers are 3->63

        Returns:
            int: Current allowable dividers
        """
        return self._b

    @b.setter
    def b(self, value: Union[int, List[int]]) -> None:
        """VCO calibration divider 2.

        Valid dividers are 3->63

        Args:
            value (int, list[int]): Allowable values for counter

        """
        self._check_in_range(value, self.b_available, "b")
        self._b = value

    @property
    def vco(self) -> float:
        """VCO Frequency in Hz.

        Returns:
            float: computed VCO frequency
        """
        r1 = self._get_val(self.config["r1"])
        m1 = self._get_val(self.config["m1"])
        n2 = self._get_val(self.config["n2"])

        return self.vcxo / r1 * m1 * n2

    @property
    def sysref(self) -> int:
        """SYSREF Frequency in Hz.

        Returns:
            int: computed sysref frequency
        """
        r1 = self._get_val(self.config["r1"])
        k = self._get_val(self.config["k"])

        if self.sysref_external:
            sysref_src = self.vcxo
        else:
            sysref_src = self.vcxo / r1

        return sysref_src / (2 * k)

    @sysref.setter
    def sysref(self, value: Union[int, float]) -> None:
        """Set sysref frequency.

        Args:
            value (int, float): Frequency
        """
        self._sysref = int(value)

    def get_config(self, solution: CpoSolveResult = None) -> Dict:
        """Extract configurations from solver results.

        Collect internal clock chip configuration and output clock definitions
        leading to connected devices (converters, FPGAs)

        Args:
            solution (CpoSolveResult): CPlex solution. Only needed for CPlex solver

        Returns:
            Dict: Dictionary of clocking rates and dividers for configuration

        Raises:
            Exception: If solver is not called first
        """
        if not self._clk_names:
            raise Exception(
                "set_requested_clocks must be called before get_config"
            )

        if solution:
            self.solution = solution

        # out_dividers = [solution.get_value(x) for x in self.config["out_dividers"]]
        out_dividers = [self._get_val(x) for x in self.config["out_dividers"]]

        config: Dict = {
            "vcxo": self.vcxo / 2 if self.use_vcxo_double else self.vcxo,
            "vco": self.vco,
            "r1": self._get_val(self.config["r1"]),
            "n2": self._get_val(self.config["n2"]),
            "m1": self._get_val(self.config["m1"]),
            "a": self._get_val(self.config["a"]),
            "b": self._get_val(self.config["b"]),
            "out_dividers": out_dividers,
            "output_clocks": [],
        }

        if self._sysref:
            config["k"] = self._get_val(self.config["k"])
            config["sysref"] = self.sysref

        clk = self.vcxo * config["n2"] / config["r1"]

        output_cfg = {}
        for i, div in enumerate(out_dividers):
            rate = clk / div
            output_cfg[self._clk_names[i]] = {
                "rate": rate,
                "divider": div,
            }

        config["output_clocks"] = output_cfg
        return config

    def _setup_solver_constraints(self, vcxo: int) -> None:
        """Apply constraints to solver model.

        Args:
            vcxo (int): VCXO frequency in hertz

        Raises:
            Exception: Unknown solver
        """
        if not isinstance(vcxo, (float, int)):
            vcxo = vcxo(self.model)
            self.vcxo = vcxo["range"]
        else:
            self.vcxo = vcxo

        self.config = {
            "r1": self._convert_input(self._r1, "r1"),
            "m1": self._convert_input(self._m1, "m1"),
            "k": self._convert_input(self._k, "k"),
            "n2": self._convert_input(self._n2, "n2"),
            "a": self._convert_input(self._a, "a"),
            "b": self._convert_input(self._b, "b"),
        }
        # self.config = {"r1": self.model.Var(integer=True, lb=1, ub=31, value=1)}
        # self.config["m1"] = self.model.Var(integer=True, lb=3, ub=5, value=3)
        # self.config["n2"] = self.model.Var(integer=True, lb=12, ub=255, value=12)

        # PLL2 equations
        self._add_equation(
            [
                self.vcxo / self.config["r1"] <= self.pfd_max,
                self.vcxo
                / self.config["r1"]
                * self.config["m1"]
                * self.config["n2"]
                <= self.vco_max,
                self.vcxo
                / self.config["r1"]
                * self.config["m1"]
                * self.config["n2"]
                >= self.vco_min,
                4 * self.config["b"] + self.config["a"] >= 16,
                4 * self.config["b"] + self.config["a"]
                == self.config["m1"] * self.config["n2"],
            ]
        )
        # Objectives
        if self.minimize_feedback_dividers:
            if self.solver == "CPLEX":
                self._add_objective(self.config["n2"])
                # self.model.minimize(self.config["n2"])
            elif self.solver == "gekko":
                self.model.Obj(self.config["n2"])
            else:
                raise Exception("Unknown solver {}".format(self.solver))
        # self.model.Obj(self.config["n2"] * self.config["m1"])

    def _setup(self, vcxo: int) -> None:
        # Setup clock chip internal constraints

        # FIXME: ADD SPLIT m1 configuration support

        # Setup clock chip internal constraints
        if self.use_vcxo_double:
            vcxo *= 2
        self._setup_solver_constraints(vcxo)

        # Add requested clocks to output constraints
        self.config["out_dividers"] = []

    def _get_clock_constraint(
        self, clk_name: str
    ) -> Union[int, float, CpoExpr, GK_Intermediate]:
        """Get abstract clock output.

        Args:
            clk_name (str):  String of clock name

        Returns:
            (int or float or CpoExpr or GK_Intermediate): Abstract
                or concrete clock reference
        """
        od = self._convert_input(self._d, "d_" + str(clk_name))
        self.config["out_dividers"].append(od)
        return self.vcxo / self.config["r1"] * self.config["n2"] / od

    def set_requested_clocks(
        self,
        vcxo: int,
        out_freqs: List,
        clk_names: List[str],
    ) -> None:
        """Define necessary clocks to be generated in model.

        Args:
            vcxo (int): VCXO frequency in hertz
            out_freqs (List): list of required clocks to be output
            clk_names (List[str]):  list of strings of clock names

        Raises:
            Exception: If len(out_freqs) != len(clk_names)
        """
        if len(clk_names) != len(out_freqs):
            raise Exception("clk_names is not the same size as out_freqs")
        self._clk_names = clk_names

        # Setup clock chip internal constraints
        self._setup(vcxo)

        if self._sysref:
            if self.sysref_external:
                sysref_src = self.vcxo
            else:
                sysref_src = self.vcxo / self.config["r1"]

            self._add_equation(
                [sysref_src / (2 * self.config["k"]) == self._sysref]
            )

        # Add requested clocks to output constraints
        for out_freq, name in zip(out_freqs, clk_names):  # noqa: B905
            # od = self.model.Var(integer=True, lb=1, ub=256, value=1)
            od = self._convert_input(self._d, f"d_{name}_{out_freq}")
            # od = self.model.sos1([n*n for n in range(1,9)])
            self._add_equation(
                [
                    self.vcxo / self.config["r1"] * self.config["n2"] / od
                    == out_freq
                ]
            )
            self.config["out_dividers"].append(od)

a: Union[int, List[int]] property writable

VCO calibration divider 1.

Valid dividers are 0->3

Returns:

Name	Type	Description
int	Union[int, List[int]]	Current allowable dividers

b: Union[int, List[int]] property writable

VCO calibration divider 2.

Valid dividers are 3->63

Returns:

Name	Type	Description
int	Union[int, List[int]]	Current allowable dividers

b_availble = [*range(3, 64)] class-attribute instance-attribute

VCXO dividers

d: Union[int, List[int]] property writable

Output dividers.

Valid dividers are 1->1023

Returns:

Name	Type	Description
int	Union[int, List[int]]	Current allowable dividers

d_available = [*range(1, 1024)] class-attribute instance-attribute

sysref dividers

k: Union[int, List[int]] property writable

Sysref dividers.

Valid dividers are 0->65535

Returns:

Name	Type	Description
int	Union[int, List[int]]	Current allowable dividers

k_available = [*range(0, 65536)] class-attribute instance-attribute

VCXO multiplier

m1: Union[int, List[int]] property writable

VCO divider path 1.

Valid dividers are 3,4,5

Returns:

Name	Type	Description
int	Union[int, List[int]]	Current allowable dividers

m1_available = [3, 4, 5] class-attribute instance-attribute

Output dividers

n2: Union[int, List[int]] property writable

n2: VCO feedback divider.

Valid dividers are 1->255

Returns:

Name	Type	Description
int	Union[int, List[int]]	Current allowable dividers

n2_available = [*range(1, 256)] class-attribute instance-attribute

VCO calibration dividers

r1: Union[int, List[int]] property writable

VCXO input dividers.

Valid dividers are 1->31

Returns:

Name	Type	Description
int	Union[int, List[int]]	Current allowable dividers

sysref: int property writable

SYSREF Frequency in Hz.

Returns:

Name	Type	Description
int	int	computed sysref frequency

vco: float property

VCO Frequency in Hz.

Returns:

Name	Type	Description
float	float	computed VCO frequency

get_config(solution=None)

Extract configurations from solver results.

Collect internal clock chip configuration and output clock definitions leading to connected devices (converters, FPGAs)

Parameters:

Name	Type	Description	Default
solution	CpoSolveResult	CPlex solution. Only needed for CPlex solver	None

Returns:

Name	Type	Description
Dict	Dict	Dictionary of clocking rates and dividers for configuration

Raises:

Type	Description
Exception	If solver is not called first

Source code in adijif/clocks/ad9528.py

def get_config(self, solution: CpoSolveResult = None) -> Dict:
    """Extract configurations from solver results.

    Collect internal clock chip configuration and output clock definitions
    leading to connected devices (converters, FPGAs)

    Args:
        solution (CpoSolveResult): CPlex solution. Only needed for CPlex solver

    Returns:
        Dict: Dictionary of clocking rates and dividers for configuration

    Raises:
        Exception: If solver is not called first
    """
    if not self._clk_names:
        raise Exception(
            "set_requested_clocks must be called before get_config"
        )

    if solution:
        self.solution = solution

    # out_dividers = [solution.get_value(x) for x in self.config["out_dividers"]]
    out_dividers = [self._get_val(x) for x in self.config["out_dividers"]]

    config: Dict = {
        "vcxo": self.vcxo / 2 if self.use_vcxo_double else self.vcxo,
        "vco": self.vco,
        "r1": self._get_val(self.config["r1"]),
        "n2": self._get_val(self.config["n2"]),
        "m1": self._get_val(self.config["m1"]),
        "a": self._get_val(self.config["a"]),
        "b": self._get_val(self.config["b"]),
        "out_dividers": out_dividers,
        "output_clocks": [],
    }

    if self._sysref:
        config["k"] = self._get_val(self.config["k"])
        config["sysref"] = self.sysref

    clk = self.vcxo * config["n2"] / config["r1"]

    output_cfg = {}
    for i, div in enumerate(out_dividers):
        rate = clk / div
        output_cfg[self._clk_names[i]] = {
            "rate": rate,
            "divider": div,
        }

    config["output_clocks"] = output_cfg
    return config

set_requested_clocks(vcxo, out_freqs, clk_names)

Define necessary clocks to be generated in model.

Parameters:

Name	Type	Description	Default
vcxo	int	VCXO frequency in hertz	required
out_freqs	List	list of required clocks to be output	required
clk_names	List[str]	list of strings of clock names	required

Raises:

Type	Description
Exception	If len(out_freqs) != len(clk_names)

Source code in adijif/clocks/ad9528.py

def set_requested_clocks(
    self,
    vcxo: int,
    out_freqs: List,
    clk_names: List[str],
) -> None:
    """Define necessary clocks to be generated in model.

    Args:
        vcxo (int): VCXO frequency in hertz
        out_freqs (List): list of required clocks to be output
        clk_names (List[str]):  list of strings of clock names

    Raises:
        Exception: If len(out_freqs) != len(clk_names)
    """
    if len(clk_names) != len(out_freqs):
        raise Exception("clk_names is not the same size as out_freqs")
    self._clk_names = clk_names

    # Setup clock chip internal constraints
    self._setup(vcxo)

    if self._sysref:
        if self.sysref_external:
            sysref_src = self.vcxo
        else:
            sysref_src = self.vcxo / self.config["r1"]

        self._add_equation(
            [sysref_src / (2 * self.config["k"]) == self._sysref]
        )

    # Add requested clocks to output constraints
    for out_freq, name in zip(out_freqs, clk_names):  # noqa: B905
        # od = self.model.Var(integer=True, lb=1, ub=256, value=1)
        od = self._convert_input(self._d, f"d_{name}_{out_freq}")
        # od = self.model.sos1([n*n for n in range(1,9)])
        self._add_equation(
            [
                self.vcxo / self.config["r1"] * self.config["n2"] / od
                == out_freq
            ]
        )
        self.config["out_dividers"].append(od)

HMC7044 clock chip model.

hmc7044

Bases: hmc7044_bf

HMC7044 clock chip model.

This model currently supports VCXO+PLL2 configurations

Source code in adijif/clocks/hmc7044.py

class hmc7044(hmc7044_bf):
    """HMC7044 clock chip model.

    This model currently supports VCXO+PLL2 configurations
    """

    # Ranges
    # r2_divider_min = 1
    # r2_divider_max = 4095
    r2_available = [*range(1, 4095 + 1)]

    """ Output dividers """
    d_available = [1, 3, 5, *range(2, 4095, 2)]
    # When pulse generation is required (like for sysref) divder range
    # is limited
    d_syspulse_available = [*range(32, 4095, 2)]

    # Defaults
    _d: Union[int, List[int]] = [1, 3, 5, *range(2, 4095, 2)]
    _r2: Union[int, List[int]] = [*range(1, 4095 + 1)]

    # Limits
    """ Internal limits """
    vco_min = 2400e6
    vco_max = 3200e6
    pfd_max = 250e6
    vcxo_min = 10e6
    vcxo_max = 500e6

    use_vcxo_double = True
    vxco_doubler_available = [1, 2]
    _vxco_doubler = [1, 2]

    minimize_feedback_dividers = True

    # State management
    _clk_names: List[str] = []

    def __init__(
        self, model: Union[GEKKO, CpoModel] = None, solver: str = "CPLEX"
    ) -> None:
        """Initialize HMC7044 clock chip model.

        Args:
            model (Model): Model to add constraints to
            solver (str): Solver to use. Should be one of "CPLEX" or "gekko"

        Raises:
            Exception: Invalid solver
        """
        super(hmc7044, self).__init__(model, solver)
        if solver == "gekko":
            self.n2_available = [*range(8, 65535 + 1)]
            self._n2 = [*range(8, 65535 + 1)]
        elif solver == "CPLEX":
            self.n2_available = [*range(8, 65535 + 1)]
            self._n2 = [*range(8, 65535 + 1)]
        else:
            raise Exception("Unknown solver {}".format(solver))

    @property
    def d(self) -> Union[int, List[int]]:
        """Output dividers.

        Valid dividers are 1,2,3,4,5,6->(even)->4094

        Returns:
            int: Current allowable dividers
        """
        return self._d

    @d.setter
    def d(self, value: Union[int, List[int]]) -> None:
        """Output dividers.

        Valid dividers are 1,2,3,4,5,6->(even)->4094

        Args:
            value (int, list[int]): Allowable values for divider
        """
        self._check_in_range(value, self.d_available, "d")
        self._d = value

    @property
    def n2(self) -> Union[int, List[int]]:
        """n2: VCO feedback divider.

        Valid dividers are 8->65536

        Returns:
            int: Current allowable dividers
        """
        return self._n2

    @n2.setter
    def n2(self, value: Union[int, List[int]]) -> None:
        """VCO feedback divider.

        Valid dividers are 8->65536

        Args:
            value (int, list[int]): Allowable values for divider
        """
        self._check_in_range(value, self.n2_available, "n2")
        self._n2 = value

    @property
    def r2(self) -> Union[int, List[int]]:
        """VCXO input dividers.

        Valid dividers are 1->4096

        Returns:
            int: Current allowable dividers
        """
        return self._r2

    @r2.setter
    def r2(self, value: Union[int, List[int]]) -> None:
        """VCXO input dividers.

        Valid dividers are 1->4096

        Args:
            value (int, list[int]): Allowable values for divider
        """
        self._check_in_range(value, self.r2_available, "r2")
        self._r2 = value

    @property
    def vxco_doubler(self) -> Union[int, List[int]]:
        """VCXO doubler.

        Valid dividers are 1,2

        Returns:
            int: Current doubler value
        """
        return self._vxco_doubler

    @vxco_doubler.setter
    def vxco_doubler(self, value: Union[int, List[int]]) -> None:
        """VCXO doubler.

        Valid dividers are 1,2

        Args:
            value (int, list[int]): Allowable values for divider

        """
        self._check_in_range(value, self.vxco_doubler_available, "vxco_doubler")
        self._vxco_doubler = value

    def _init_diagram(self) -> None:
        """Initialize diagram for HMC7044 alone."""
        self.ic_diagram_node = None
        self._diagram_output_dividers = []

        # lo = Layout("HMC7044 Example")

        self.ic_diagram_node = Node("HMC7044")
        # lo.add_node(root)

        # External
        # ref_in = Node("REF_IN", ntype="input")
        # lo.add_node(ref_in)

        vcxo_doubler = Node("VCXO Doubler", ntype="shell")
        self.ic_diagram_node.add_child(vcxo_doubler)

        # Inside the IC
        r2_div = Node("R2", ntype="divider")
        # r2_div.value = "2"
        self.ic_diagram_node.add_child(r2_div)
        pfd = Node("PFD", ntype="phase-frequency-detector")
        self.ic_diagram_node.add_child(pfd)
        lf = Node("LF", ntype="loop-filter")
        self.ic_diagram_node.add_child(lf)
        vco = Node("VCO", ntype="voltage-controlled-oscillator")
        vco.shape = "circle"
        self.ic_diagram_node.add_child(vco)
        n2 = Node("N2", ntype="divider")
        self.ic_diagram_node.add_child(n2)

        out_dividers = Node("Output Dividers", ntype="shell")
        # ds = 4
        # out_divs = []
        # for i in range(ds):
        #     div = Node(f"D{i+1}", ntype="divider")
        #     out_dividers.add_child(div)
        #     out_divs.append(div)

        self.ic_diagram_node.add_child(out_dividers)

        # Connections inside the IC
        # lo.add_connection({"from": ref_in, "to": r2_div, 'rate': 125000000})
        self.ic_diagram_node.add_connection(
            {"from": vcxo_doubler, "to": r2_div}
        )
        self.ic_diagram_node.add_connection(
            {"from": r2_div, "to": pfd, "rate": 125000000 / 2}
        )
        self.ic_diagram_node.add_connection({"from": pfd, "to": lf})
        self.ic_diagram_node.add_connection({"from": lf, "to": vco})
        self.ic_diagram_node.add_connection({"from": vco, "to": n2})
        self.ic_diagram_node.add_connection({"from": n2, "to": pfd})

        self.ic_diagram_node.add_connection(
            {"from": vco, "to": out_dividers, "rate": 4000000000}
        )
        # for div in out_divs:
        #     self.ic_diagram_node.add_connection({"from": out_dividers, "to": div})
        #     # root.add_connection({"from": vco, "to": div})

    def _update_diagram(self, config: Dict) -> None:
        """Update diagram with configuration.

        Args:
            config (Dict): Configuration dictionary

        Raises:
            Exception: If key is not D followed by a number
        """
        # Add output dividers
        keys = config.keys()
        output_dividers = self.ic_diagram_node.get_child("Output Dividers")
        for key in keys:
            if key.startswith("D"):
                div = Node(key, ntype="divider")
                output_dividers.add_child(div)
                self.ic_diagram_node.add_connection(
                    {"from": output_dividers, "to": div}
                )
            else:
                raise Exception(
                    f"Unknown key {key}. Must be of for DX where X is a number"
                )

    def draw(self) -> str:
        """Draw diagram in d2 language for IC alone with reference clock.

        Returns:
            str: Diagram in d2 language

        Raises:
            Exception: If no solution is saved
        """
        if not self._saved_solution:
            raise Exception("No solution to draw. Must call solve first.")
        lo = Layout("HMC7044 Example")
        lo.add_node(self.ic_diagram_node)

        ref_in = Node("REF_IN", ntype="input")
        lo.add_node(ref_in)
        vcxo_double = self.ic_diagram_node.get_child("VCXO Doubler")
        lo.add_connection(
            {
                "from": ref_in,
                "to": vcxo_double,
                "rate": self._saved_solution["vcxo"],
            }
        )

        # Update Node values
        node = self.ic_diagram_node.get_child("VCXO Doubler")
        node.value = str(self._saved_solution["vcxo_doubler"])
        node = self.ic_diagram_node.get_child("R2")
        node.value = str(self._saved_solution["r2"])
        node = self.ic_diagram_node.get_child("N2")
        node.value = str(self._saved_solution["n2"])

        # Update VCXO Doubler to R2
        # con = self.ic_diagram_node.get_connection("VCXO Doubler", "R2")
        rate = (
            self._saved_solution["vcxo_doubler"] * self._saved_solution["vcxo"]
        )
        self.ic_diagram_node.update_connection("VCXO Doubler", "R2", rate)

        # Update R2 to PFD
        # con = self.ic_diagram_node.get_connection("R2", "PFD")
        rate = (
            self._saved_solution["vcxo"]
            * self._saved_solution["vcxo_doubler"]
            / self._saved_solution["r2"]
        )
        self.ic_diagram_node.update_connection("R2", "PFD", rate)

        # Update VCO
        # con = self.ic_diagram_node.get_connection("VCO", "Output Dividers")
        self.ic_diagram_node.update_connection(
            "VCO", "Output Dividers", self._saved_solution["vco"]
        )

        # Update diagram with dividers and rates
        d = 0
        output_dividers = self.ic_diagram_node.get_child("Output Dividers")

        for key, val in self._saved_solution["output_clocks"].items():
            clk_node = Node(key, ntype="divider")
            div_value = val["divider"]
            div = output_dividers.get_child(f"D{d}")
            div.value = str(div_value)
            d += 1
            lo.add_node(clk_node)
            lo.add_connection(
                {"from": div, "to": clk_node, "rate": val["rate"]}
            )

        return lo.draw()

    def get_config(self, solution: CpoSolveResult = None) -> Dict:
        """Extract configurations from solver results.

        Collect internal clock chip configuration and output clock definitions
        leading to connected devices (converters, FPGAs)

        Args:
            solution (CpoSolveResult): CPlex solution. Only needed for CPlex solver

        Returns:
            Dict: Dictionary of clocking rates and dividers for configuration

        Raises:
            Exception: If solver is not called first
        """
        if not self._clk_names:
            raise Exception(
                "set_requested_clocks must be called before get_config"
            )

        if solution:
            self.solution = solution

        out_dividers = [self._get_val(x) for x in self.config["out_dividers"]]

        config: Dict = {
            "r2": self._get_val(self.config["r2"]),
            "n2": self._get_val(self.config["n2"]),
            "out_dividers": out_dividers,
            "output_clocks": [],
        }

        if self.vcxo_i:
            vcxo = self._get_val(self.vcxo_i["range"])
            self.vcxo = vcxo

        clk = self.vcxo / config["r2"] * config["n2"]

        output_cfg = {}
        vd = self._get_val(self.config["vcxo_doubler"])
        for i, div in enumerate(out_dividers):
            rate = vd * clk / div
            output_cfg[self._clk_names[i]] = {"rate": rate, "divider": div}

        config["output_clocks"] = output_cfg
        config["vco"] = clk * vd
        config["vcxo"] = self.vcxo
        config["vcxo_doubler"] = vd

        self._saved_solution = config

        return config

    def _setup_solver_constraints(self, vcxo: int) -> None:
        """Apply constraints to solver model.

        Args:
            vcxo (int): VCXO frequency in hertz

        Raises:
            Exception: Invalid solver
        """
        self.vcxo = vcxo

        if self.solver == "gekko":
            self.config = {
                "r2": self.model.Var(integer=True, lb=1, ub=4095, value=1)
            }
            self.config["n2"] = self.model.Var(integer=True, lb=8, ub=4095)
            if isinstance(vcxo, (int, float)):
                vcxo_var = self.model.Const(int(vcxo))
            else:
                vcxo_var = vcxo
            self.config["vcxo_doubler"] = self.model.sos1([1, 2])
            self.config["vcxod"] = self.model.Intermediate(
                self.config["vcxo_doubler"] * vcxo_var
            )
        elif self.solver == "CPLEX":
            self.config = {
                "r2": self._convert_input(self._r2, "r2"),
                "n2": self._convert_input(self._n2, "n2"),
            }
            self.config["vcxo_doubler"] = self._convert_input(
                self._vxco_doubler, "vcxo_doubler"
            )
            self.config["vcxod"] = self._add_intermediate(
                self.config["vcxo_doubler"] * vcxo
            )
        else:
            raise Exception("Unknown solver {}".format(self.solver))

        # PLL2 equations
        self._add_equation(
            [
                self.config["vcxod"] <= self.pfd_max * self.config["r2"],
                self.config["vcxod"] * self.config["n2"]
                <= self.vco_max * self.config["r2"],
                self.config["vcxod"] * self.config["n2"]
                >= self.vco_min * self.config["r2"],
            ]
        )

        # Objectives
        if self.minimize_feedback_dividers:
            if self.solver == "CPLEX":
                self._add_objective(self.config["r2"])
                # self.model.minimize(self.config["r2"])
            elif self.solver == "gekko":
                self.model.Obj(self.config["r2"])
            else:
                raise Exception("Unknown solver {}".format(self.solver))

    def _setup(self, vcxo: int) -> None:
        # Setup clock chip internal constraints

        # FIXME: ADD SPLIT m1 configuration support

        # Convert VCXO into intermediate in case we have range type
        if type(vcxo) not in [int, float]:
            self.vcxo_i = vcxo(self.model)
            vcxo = self.vcxo_i["range"]
        else:
            self.vcxo_i = False

        self._setup_solver_constraints(vcxo)

        # Add requested clocks to output constraints
        self.config["out_dividers"] = []

    def _get_clock_constraint(
        self, clk_name: List[str]
    ) -> Union[int, float, CpoExpr, GK_Intermediate]:
        """Get abstract clock output.

        Args:
            clk_name (str):  String of clock name

        Returns:
            (int or float or CpoExpr or GK_Intermediate): Abstract
                or concrete clock reference

        Raises:
            Exception: Invalid solver
        """
        if self.solver == "gekko":
            __d = self._d if isinstance(self._d, list) else [self._d]

            if __d.sort() != self.d_available.sort():
                raise Exception(
                    "For solver gekko d is not configurable for HMC7044"
                )

            even = self.model.Var(integer=True, lb=3, ub=2047)
            odd = self.model.Intermediate(even * 2)
            od = self.model.sos1([1, 2, 3, 4, 5, odd])

        elif self.solver == "CPLEX":
            od = self._convert_input(self._d, "d_" + str(clk_name))
        else:
            raise Exception("Unknown solver {}".format(self.solver))

        self.config["out_dividers"].append(od)
        return self.config["vcxod"] / self.config["r2"] * self.config["n2"] / od

    def set_requested_clocks(
        self, vcxo: int, out_freqs: List, clk_names: List[str]
    ) -> None:
        """Define necessary clocks to be generated in model.

        Args:
            vcxo (int): VCXO frequency in hertz
            out_freqs (List): list of required clocks to be output
            clk_names (List[str]):  list of strings of clock names

        Raises:
            Exception: If len(out_freqs) != len(clk_names)
        """
        if len(clk_names) != len(out_freqs):
            raise Exception("clk_names is not the same size as out_freqs")
        self._clk_names = clk_names

        # Setup clock chip internal constraints
        self._setup(vcxo)
        # if type(self.vcxo) not in [int,float]:
        #     vcxo = self.vcxo['range']

        self._saved_solution = None

        # Add requested clocks to output constraints
        for d_n, out_freq in enumerate(out_freqs):
            if self.solver == "gekko":
                __d = self._d if isinstance(self._d, list) else [self._d]
                if __d.sort() != self.d_available.sort():
                    raise Exception(
                        "For solver gekko d is not configurable for HMC7044"
                    )

                # even = self.model.Var(integer=True, lb=3, ub=2047)
                # odd = self.model.Intermediate(even * 2)
                # od = self.model.sos1([1, 2, 3, 4, 5, odd])

                # Since d is so disjoint it is very annoying to solve.
                even = self.model.Var(integer=True, lb=1, ub=4094 // 2)

                # odd = self.model.sos1([1, 3, 5])
                odd_i = self.model.Var(integer=True, lb=0, ub=2)
                odd = self.model.Intermediate(1 + odd_i * 2)

                eo = self.model.Var(integer=True, lb=0, ub=1)
                od = self.model.Intermediate(eo * odd + (1 - eo) * even * 2)

            elif self.solver == "CPLEX":
                od = self._convert_input(self._d, f"d_{out_freq}_{d_n}")

            self._add_equation(
                [
                    self.config["vcxod"] * self.config["n2"]
                    == out_freq * self.config["r2"] * od
                ]
            )
            self.config["out_dividers"].append(od)

            # Update diagram to include new divider
            self._update_diagram({f"D{d_n}": od})

d: Union[int, List[int]] property writable

Output dividers.

Valid dividers are 1,2,3,4,5,6->(even)->4094

Returns:

Name	Type	Description
int	Union[int, List[int]]	Current allowable dividers

n2: Union[int, List[int]] property writable

n2: VCO feedback divider.

Valid dividers are 8->65536

Returns:

Name	Type	Description
int	Union[int, List[int]]	Current allowable dividers

r2: Union[int, List[int]] property writable

VCXO input dividers.

Valid dividers are 1->4096

Returns:

Name	Type	Description
int	Union[int, List[int]]	Current allowable dividers

r2_available = [*range(1, 4095 + 1)] class-attribute instance-attribute

Output dividers

vxco_doubler: Union[int, List[int]] property writable

VCXO doubler.

Valid dividers are 1,2

Returns:

Name	Type	Description
int	Union[int, List[int]]	Current doubler value

__init__(model=None, solver='CPLEX')

Initialize HMC7044 clock chip model.

Parameters:

Name	Type	Description	Default
model	Model	Model to add constraints to	None
solver	str	Solver to use. Should be one of "CPLEX" or "gekko"	'CPLEX'

Raises:

Type	Description
Exception	Invalid solver

Source code in adijif/clocks/hmc7044.py

def __init__(
    self, model: Union[GEKKO, CpoModel] = None, solver: str = "CPLEX"
) -> None:
    """Initialize HMC7044 clock chip model.

    Args:
        model (Model): Model to add constraints to
        solver (str): Solver to use. Should be one of "CPLEX" or "gekko"

    Raises:
        Exception: Invalid solver
    """
    super(hmc7044, self).__init__(model, solver)
    if solver == "gekko":
        self.n2_available = [*range(8, 65535 + 1)]
        self._n2 = [*range(8, 65535 + 1)]
    elif solver == "CPLEX":
        self.n2_available = [*range(8, 65535 + 1)]
        self._n2 = [*range(8, 65535 + 1)]
    else:
        raise Exception("Unknown solver {}".format(solver))

draw()

Draw diagram in d2 language for IC alone with reference clock.

Returns:

Name	Type	Description
str	str	Diagram in d2 language

Raises:

Type	Description
Exception	If no solution is saved

Source code in adijif/clocks/hmc7044.py

def draw(self) -> str:
    """Draw diagram in d2 language for IC alone with reference clock.

    Returns:
        str: Diagram in d2 language

    Raises:
        Exception: If no solution is saved
    """
    if not self._saved_solution:
        raise Exception("No solution to draw. Must call solve first.")
    lo = Layout("HMC7044 Example")
    lo.add_node(self.ic_diagram_node)

    ref_in = Node("REF_IN", ntype="input")
    lo.add_node(ref_in)
    vcxo_double = self.ic_diagram_node.get_child("VCXO Doubler")
    lo.add_connection(
        {
            "from": ref_in,
            "to": vcxo_double,
            "rate": self._saved_solution["vcxo"],
        }
    )

    # Update Node values
    node = self.ic_diagram_node.get_child("VCXO Doubler")
    node.value = str(self._saved_solution["vcxo_doubler"])
    node = self.ic_diagram_node.get_child("R2")
    node.value = str(self._saved_solution["r2"])
    node = self.ic_diagram_node.get_child("N2")
    node.value = str(self._saved_solution["n2"])

    # Update VCXO Doubler to R2
    # con = self.ic_diagram_node.get_connection("VCXO Doubler", "R2")
    rate = (
        self._saved_solution["vcxo_doubler"] * self._saved_solution["vcxo"]
    )
    self.ic_diagram_node.update_connection("VCXO Doubler", "R2", rate)

    # Update R2 to PFD
    # con = self.ic_diagram_node.get_connection("R2", "PFD")
    rate = (
        self._saved_solution["vcxo"]
        * self._saved_solution["vcxo_doubler"]
        / self._saved_solution["r2"]
    )
    self.ic_diagram_node.update_connection("R2", "PFD", rate)

    # Update VCO
    # con = self.ic_diagram_node.get_connection("VCO", "Output Dividers")
    self.ic_diagram_node.update_connection(
        "VCO", "Output Dividers", self._saved_solution["vco"]
    )

    # Update diagram with dividers and rates
    d = 0
    output_dividers = self.ic_diagram_node.get_child("Output Dividers")

    for key, val in self._saved_solution["output_clocks"].items():
        clk_node = Node(key, ntype="divider")
        div_value = val["divider"]
        div = output_dividers.get_child(f"D{d}")
        div.value = str(div_value)
        d += 1
        lo.add_node(clk_node)
        lo.add_connection(
            {"from": div, "to": clk_node, "rate": val["rate"]}
        )

    return lo.draw()

get_config(solution=None)

Extract configurations from solver results.

Collect internal clock chip configuration and output clock definitions leading to connected devices (converters, FPGAs)

Parameters:

Name	Type	Description	Default
solution	CpoSolveResult	CPlex solution. Only needed for CPlex solver	None

Returns:

Name	Type	Description
Dict	Dict	Dictionary of clocking rates and dividers for configuration

Raises:

Type	Description
Exception	If solver is not called first

Source code in adijif/clocks/hmc7044.py

def get_config(self, solution: CpoSolveResult = None) -> Dict:
    """Extract configurations from solver results.

    Collect internal clock chip configuration and output clock definitions
    leading to connected devices (converters, FPGAs)

    Args:
        solution (CpoSolveResult): CPlex solution. Only needed for CPlex solver

    Returns:
        Dict: Dictionary of clocking rates and dividers for configuration

    Raises:
        Exception: If solver is not called first
    """
    if not self._clk_names:
        raise Exception(
            "set_requested_clocks must be called before get_config"
        )

    if solution:
        self.solution = solution

    out_dividers = [self._get_val(x) for x in self.config["out_dividers"]]

    config: Dict = {
        "r2": self._get_val(self.config["r2"]),
        "n2": self._get_val(self.config["n2"]),
        "out_dividers": out_dividers,
        "output_clocks": [],
    }

    if self.vcxo_i:
        vcxo = self._get_val(self.vcxo_i["range"])
        self.vcxo = vcxo

    clk = self.vcxo / config["r2"] * config["n2"]

    output_cfg = {}
    vd = self._get_val(self.config["vcxo_doubler"])
    for i, div in enumerate(out_dividers):
        rate = vd * clk / div
        output_cfg[self._clk_names[i]] = {"rate": rate, "divider": div}

    config["output_clocks"] = output_cfg
    config["vco"] = clk * vd
    config["vcxo"] = self.vcxo
    config["vcxo_doubler"] = vd

    self._saved_solution = config

    return config

set_requested_clocks(vcxo, out_freqs, clk_names)

Define necessary clocks to be generated in model.

Parameters:

Name	Type	Description	Default
vcxo	int	VCXO frequency in hertz	required
out_freqs	List	list of required clocks to be output	required
clk_names	List[str]	list of strings of clock names	required

Raises:

Type	Description
Exception	If len(out_freqs) != len(clk_names)

Source code in adijif/clocks/hmc7044.py

def set_requested_clocks(
    self, vcxo: int, out_freqs: List, clk_names: List[str]
) -> None:
    """Define necessary clocks to be generated in model.

    Args:
        vcxo (int): VCXO frequency in hertz
        out_freqs (List): list of required clocks to be output
        clk_names (List[str]):  list of strings of clock names

    Raises:
        Exception: If len(out_freqs) != len(clk_names)
    """
    if len(clk_names) != len(out_freqs):
        raise Exception("clk_names is not the same size as out_freqs")
    self._clk_names = clk_names

    # Setup clock chip internal constraints
    self._setup(vcxo)
    # if type(self.vcxo) not in [int,float]:
    #     vcxo = self.vcxo['range']

    self._saved_solution = None

    # Add requested clocks to output constraints
    for d_n, out_freq in enumerate(out_freqs):
        if self.solver == "gekko":
            __d = self._d if isinstance(self._d, list) else [self._d]
            if __d.sort() != self.d_available.sort():
                raise Exception(
                    "For solver gekko d is not configurable for HMC7044"
                )

            # even = self.model.Var(integer=True, lb=3, ub=2047)
            # odd = self.model.Intermediate(even * 2)
            # od = self.model.sos1([1, 2, 3, 4, 5, odd])

            # Since d is so disjoint it is very annoying to solve.
            even = self.model.Var(integer=True, lb=1, ub=4094 // 2)

            # odd = self.model.sos1([1, 3, 5])
            odd_i = self.model.Var(integer=True, lb=0, ub=2)
            odd = self.model.Intermediate(1 + odd_i * 2)

            eo = self.model.Var(integer=True, lb=0, ub=1)
            od = self.model.Intermediate(eo * odd + (1 - eo) * even * 2)

        elif self.solver == "CPLEX":
            od = self._convert_input(self._d, f"d_{out_freq}_{d_n}")

        self._add_equation(
            [
                self.config["vcxod"] * self.config["n2"]
                == out_freq * self.config["r2"] * od
            ]
        )
        self.config["out_dividers"].append(od)

        # Update diagram to include new divider
        self._update_diagram({f"D{d_n}": od})