Generating HDL boot image for Intel projects

This page is dedicated to the building process of boot image for supported Intel/Altera projects. One key file specific to these projects is the bootloader. It’s role is to initialize the system after the BootROM runs. It bridges the gap between the limited functionality of the BootROM and the end user application, configuring the system as needed before the larger application can run.

In the following links you can find more details on the process and the necessary components:

• Booting and Configuration

• SocBootFromFPGA

• Intel Bootloader

Necessary files for booting up an HDL project

Warning

We do not provide any scripts to automate this process, so please read carefully and follow all the steps to obtain the boot file. We recommend using the latest version of Quartus. Te build flow is the same for the recent versions of Quartus.

To boot a system with Linux + HDL on an Intel board, you need the following files:

• For Arria 10 SoC projects (build example):

  • <boot_mountpoint>/u-boot.img

  • <boot_mountpoint>/fit_spl_fpga.itb

  • <boot_mountpoint>/extlinux/extlinux.conf (keep the directory)

  • <boot_mountpoint>/socfpga_arria10_socdk_sdmmc.dtb

  • <boot_mountpoint>/socfpga_arria10-common/zImage

  • <boot_mountpoint>/u-boot-splx4.sfp (preloader image)

• For Cyclone5 SoC project (build examples: Terasic C5, DE10Nano):

  • <boot_mountpoint>/u-boot.scr

  • <boot_mountpoint>/soc_system.rbf

  • <boot_mountpoint>/extlinux/extlinux.conf (keep the directory)

  • <boot_mountpoint>/socfpga_arria10-common/socfpga.dtb

  • <boot_mountpoint>/zImage

  • <boot_mountpoint>/u-boot-with-spl.sfp (preloader image)

Note

Some files, like fit_spl_fpga.itb or extlinux, were introduced later in the Intel boot flow with the U-Boot image update.

Using Kuiper Linux pre-built images

The built and tested files can be found in our ADI Kuiper Linux release, which can be obtained from here.

Note

Make sure to always use the latest version of Kuiper Linux. If the desired project is not supported anymore, use the last version of Kuiper where it’s present.

The files need to be copied on the BOOT FAT32 partition, with the exception of the preloader image, which needs to be written to the third partition of the mounted device, and extlinux.conf, which should also be in BOOT FAT32 partition, in a folder called ‘extlinux’. That folder may not exist by default (it is deleted automatically in some cases, when the image is build, because it is empty and unused). Pay attention that extlinux.conf for Arria10 and Cyclone5 is slightly different.

Supposing your host is a Linux system, your carrier is an Arria10, the eval board/project is AD9081 and you are using the built files from the Kuiper image mounted at /mnt/BOOT, then you would:

~$

cd /mnt/BOOT

/mnt/BOOT$

cp socfpga_arria10_socdk_ad9081/u-boot.img .

/mnt/BOOT$

cp socfpga_arria10_socdk_ad9081/fit_spl_fpga.itb .

/mnt/BOOT$

mkdir -p extlinux

/mnt/BOOT$

cp socfpga_arria10_socdk_ad9081/extlinux.conf extlinux/

/mnt/BOOT$

cp socfpga_arria10_socdk_ad9081/socfpga_arria10_socdk_sdmmc.dtb .

/mnt/BOOT$

cp socfpga_arria10_common/zImage .

Writing the boot preloader partition requires special attention, first look for the device with BOOT mountpoint and annotate the third partition from the same device:

lsblk

Then, clear the partition with zeros and write the preloader image (in this example, Arria10 SoC’s ./u-boot-splx4.sfp):

$

DEV=mmcblk0p3

$

cd /mnt/BOOT/socfpga_arria10_socdk_ad9081

$

sudo dd if=/dev/zero of=/dev/$DEV oflag=sync status=progress \
    bs=$(sudo blockdev --getsize64 /dev/$DEV) count=1

1+0 records in
1+0 records out
8388608 bytes (8.4 MB, 8.0 MiB) copied, 0.359183 s, 23.4 MB/s

$

sudo dd if=./u-boot-splx4.sfp of=/dev/$DEV oflag=sync status=progress bs=64k

1697+1 records in
1697+1 records out
868996 bytes (869 kB, 849 KiB) copied, 0.21262 s, 4.1 MB/s

Tip

The snippet below can infer the device based on the BOOT partition mountpoint

~$

DEV=$(lsblk | sed -n 's/.*\(\b[s][d-z][a-z][0-9]\)\s*.*\/BOOT/\1/p' | sed 's/^\(...\).*/\1/')

~$

if [ -z "$DEV" ] ; then \
   echo BOOT not found, couldn\'t infer block device ; \
else \
   echo The preloader image partition path likely is /dev/"$DEV"3 ; \
fi

Examples of building the boot image

This is a list of projects supported by us for each carrier. The purpose is to illustrate how to build the different files involved in the process. Each project has its own characteristics (some files may differ from one project to the other).

Note

Each project has its own Linux Kernel Image & Devicetree which needs to be built. Follow these instructions to write the file to your SD card, depending on the operating system that you use (Windows or Linux):

• [Wiki] Building the Intel SoC-FPGA kernel and devicetrees from source

• [Wiki] Linux Download and setting up the image

• [Wiki] Formatting and Flashing SD Cards using Windows

Proceed by cloning the repository, setting the environment to an ARM architecture cross compiler, build the configuration file, build the Kernel image, and lastly build the device tree (specific to each combination of carrier and eval board).

You may notice that in the export CROSS_COMPILE examples there is a “trailing” dash -, and the reason for this is because an export:

~$

export CROSS_COMPILE=/path/to/arm-linux-gnueabihf-

Within the Makefiles, this path becomes /path/to/arm-linux-gnueabihf-gcc (with gcc added at the end).

If your environment already has the compiler in the path (test if which arm-linux-gnueabihf-gcc returns the expected path), you can set CROSS_COMPILE to:

~$

export CROSS_COMPILE=arm-linux-gnueabihf-

The difference between arm-linux-gnueabi-gcc and arm-linux-gnueabihf-gcc is that the latter has hardware floating-point support and may not be available in your default package manager.

Caution

Pay attention to the Quartus version. Based on these versions, different u-boot branches should be checked out. In the coming examples, we used the latest Quartus version available so the corresponding u-boot branches were checked-out.

ADRV9371/Arria 10

• HDL Project: projects/adrv9371x/a10soc

• ADI’s Linux kernel: here

Building the Linux Kernel image and the Devicetree

Linux/Cygwin/WSL

~$

git clone https://github.com/analogdevicesinc/linux.git

~$

cd linux/

~/linux$

# Set architecture and compiler

~/linux$

export ARCH=arm

~/linux$

export CROSS_COMPILE=/path/to/arm-linux-gnueabihf-

~/linux$

# Apply kconfig settings

~/linux$

make socfpga_adi_defconfig

~/linux$

# Build the kernel

~/linux$

make zImage

~/linux$

# Build the devicetree

~/linux$

make socfpga_arria10_socdk_adrv9371.dtb

Building the Hardware Design

Clone the HDL repository, then build the project:

~$

git clone https://github.com/analogdevicesinc/hdl.git

~$

cd hdl/projects/adrv9371x/a10soc

~/hdl/projects/adrv9371x/a10soc$

make

After the design is built, the resulting SRAM Object File (.sof) file shall be converted to a Raw Binary File (.rbf).

If you skipped the last section, ensure to set the architecture and cross compiler environment variables.

Caution

Pay attention to directoy changes to where the commands are run from, and always confirm with pwd to show the current path at you terminal.

$

cd ~/hdl/projects/adrv9371x/a10soc ; pwd

~/hdl/projects/adrv9371x/a10soc

$

quartus_cpf -c --hps -o bitstream_compression=on \
    ./adrv9371x_a10soc.sof soc_system.rbf

Building the Preloader and Bootloader Image

This flow applies starting with release 2021_R1 / Quartus Pro version 20.1. For older versions of the flow see previous versions of this page on wiki Altera SOC Quick Start Guide.

In the HDL project directory, create the software/bootloader folder and clone the u-boot-socfpga image:

$

cd ~/hdl/projects/adrv9371x/a10soc ; pwd

~/hdl/projects/adrv9371x/a10soc

$

mkdir -p software/bootloader

$

cd software/bootloader

$

git clone https://github.com/altera-opensource/u-boot-socfpga.git

Then run the qts filter and build the preloader and bootloader images:

$

cd ~/hdl/projects/adrv9371x/a10soc/software/bootloader ; pwd

~/hdl/projects/adrv9371x/a10soc/software/bootloader

$

cd u-boot-socfpga ; pwd

~/hdl/projects/adrv9371x/a10soc/software/bootloader/u-boot-socfpga

$

git checkout rel_socfpga_v2021.07_22.02.02_pr

$

./arch/arm/mach-socfpga/qts-filter-a10.sh ../../../hps_isw_handoff/hps.xml \
   arch/arm/dts/socfpga_arria10_socdk_sdmmc_handoff.h

$

make socfpga_arria10_defconfig

$

make

Create the SPL image:

$

cd ~/hdl/projects/adrv9371x/a10soc/software/bootloader/u-boot-socfpga ; pwd

~/hdl/projects/adrv9371x/a10soc/software/bootloader/u-boot-socfpga

$

ln -s ../../../soc_system.core.rbf .

$

ln -s ../../../soc_system.periph.rbf .

$

sed -i 's/ghrd_10as066n2/soc_system/g' board/altera/arria10-socdk/fit_spl_fpga.its

$

./tools/mkimage -E -f board/altera/arria10-socdk/fit_spl_fpga.its fit_spl_fpga.itb

Last but not least, create the extlinux.conf Linux configuration file, which will be copied to /BOOT partition of the SD Card, in a folder named extlinux:

$

cd ~/hdl/projects/adrv9371x/a10soc/software/bootloader/u-boot-socfpga ; pwd

~/hdl/projects/adrv9371x/a10soc/software/bootloader/u-boot-socfpga

$

mkdir extlinux

$

printf "\
LABEL Linux Arria10 Default\n\
KERNEL ../zImage\n\
    FDT ../socfpga_arria10_socdk_sdmmc.dtb\n\
    APPEND root=/dev/mmcblk0p2 rw rootwait earlyprintk console=ttyS0,115200n8" \
    > extlinux/extlinux.conf

Configuring the SD Card

Below are the commands to create the preloader and bootloader partition using the Kuiper Linux image as a starting point. Please check every command before running, especially configuring target device mountpoints accordingly (here as /dev/sdz with partition 1 mounted at /media/BOOT/).

Flash the SD Card with the Kuiper Linux image:

~$

time sudo dd if=./2023-12-13-ADI-Kuiper-full.img of=/dev/sdz status=progress bs=4194304

2952+0 records in
2952+0 records out
12381585408 bytes (12 GB, 12 GiB) copied, 838.353 s, 14.8 MB/s

real        14m7.938s
user        0m0.006s
sys 0m0.009s

~$

sync

Mount the /BOOT partition:

$

lsblk

NAME        MAJ:MIN RM   SIZE RO TYPE MOUNTPOINT
sdz           8:48   1  29.1G  0 disk
├─sdz1        8:49   1     2G  0 part
├─sdz2        8:50   1  27.1G  0 part
└─sdz3        8:51   1     8M  0 part

$

mkdir -p /media/BOOT/

$

sudo mount /dev/sdz1 /media/BOOT/

$

lsblk

NAME        MAJ:MIN RM   SIZE RO TYPE MOUNTPOINT
sdz           8:48   1  29.1G  0 disk
├─sdz1        8:49   1     2G  0 part /media/BOOT
├─sdz2        8:50   1  27.1G  0 part
└─sdz3        8:51   1     8M  0 part

Copy the built files to the /BOOT partition:

$

cd ~/hdl/projects/adrv9371x/a10soc ; pwd

~/hdl/projects/adrv9371x/a10soc

$

cp ./software/bootloader/u-boot-socfpga/u-boot.img /media/BOOT/

$

cp ./software/bootloader/u-boot-socfpga/fit_spl_fpga.itb /media/BOOT/

$

mkdir -p /media/BOOT/extlinux

$

cp ./software/bootloader/u-boot-socfpga/extlinux/extlinux.conf /media/BOOT/extlinux/

$

cp ~/linux/arch/arm/boot/dts/socfpga_arria10_socdk_sdmmc.dtb /media/BOOT/

$

cp ~/linux/arch/arm/boot/zImage /media/BOOT/

Unmount the /BOOT partition:

$

sudo umount /dev/sdz1

$

lsblk

NAME        MAJ:MIN RM  SIZE  RO TYPE MOUNTPOINT
sdz           8:48  1   29.1G  0 disk
├─sdz1        8:49  1      2G  0 part
├─sdz2        8:50  1   27.1G  0 part
└─sdz3        8:51  1      8M  0 part

Flash the preloader boot partition:

$

cd ~/hdl/projects/adrv9371x/a10soc/software/bootloader/u-boot-socfpga ; pwd

~/hdl/projects/adrv9371x/a10soc/software/bootloader/u-boot-socfpga

$

sudo dd if=/dev/zero of=/dev/sdz3 oflag=sync status=progress \
    bs=$(sudo blockdev --getsize64 /dev/sdz3) count=1

1+0 records in
1+0 records out
8388608 bytes (8.4 MB, 8.0 MiB) copied, 0.359183 s, 23.4 MB/s

$

sudo dd if=./u-boot-splx4.sfp of=/dev/sdz3

1697+1 records in
1697+1 records out
868996 bytes (869 kB, 849 KiB) copied, 0.21262 s, 4.1 MB/s

ARRADIO/Terasic C5 SoC

• HDL Project:

• ADI’s Linux kernel: here

Building the Linux Kernel image and the Devicetree

Linux/Cygwin/WSL

~$

git clone https://github.com/analogdevicesinc/linux.git

~$

cd linux/

~/linux$

# Set architecture and compiler

~/linux$

export ARCH=arm

~/linux$

export CROSS_COMPILE=/path/to/arm-linux-gnueabihf-

~/linux$

# Apply kconfig settings

~/linux$

make socfpga_adi_defconfig

~/linux$

# Build the kernel

~/linux$

make zImage

~/linux$

# Build the devicetree

~/linux$

make socfpga_cyclone5_sockit_arradio.dtb

Building the Hardware Design

Clone the HDL repository, then build the project:

~$

git clone https://github.com/analogdevicesinc/hdl.git

~$

cd hdl/projects/arradio/c5soc

~/hdl/projects/arradio/c5soc$

make

After the design is built, the resulting SRAM Object File (.sof) file shall be converted to a Raw Binary File (.rbf).

If you skipped the last section, ensure to set the architecture and cross compiler environment variables.

Caution

Pay attention to directory changes to where the commands are run from, and always confirm with pwd to show the current path at you terminal.

$

cd ~/hdl/projects/arradio/c5soc ; pwd

~/hdl/projects/arradio/c5soc

$

quartus_cpf -c -o bitstream_compression=on --hps \
    ./arradio_c5soc.sof soc_system.rbf

Building the Preloader and Bootloader Image

This flow applies starting with release 2021_R1 / Quartus Pro version 20.1. For older versions of the flow see previous versions of this page on wiki Altera SOC Quick Start Guide.

In HDL project directory, create the software/bootloader folder and clone the u-boot-socfpga image. Before that create a new BSP settings file:

$

cd ~/hdl/projects/arradio/c5soc ; pwd

~/hdl/projects/arradio/c5soc

$

mkdir -p software/bootloader

$

embedded_command_shell.sh bsp-create-settings --type spl \
    --bsp-dir software/bootloader \
    --preloader-settings-dir "hps_isw_handoff/system_bd_sys_hps" \
    --settings software/bootloader/settings.bsp

$

cd software/bootloader ; pwd

~/hdl/projects/arradio/c5soc/software/bootloader

$

git clone https://github.com/altera-opensource/u-boot-socfpga.git

$

git checkout socfpga_v2021.10

Then run the qts filter and build the preloader and bootloader images:

$

cd ~/hdl/projects/arradio/c5soc/software/bootloader ; pwd

~/hdl/projects/arradio/c5soc/software/bootloader

$

cd u-boot-socfpga ; pwd

~/hdl/projects/arradio/c5soc/software/bootloader/u-boot-socfpga

$

./arch/arm/mach-socfpga/qts-filter.sh cyclone5 ../../../../../board/altera/cyclone5-socdk/qts/

$

make socfpga_cyclone5_defconfig

$

make

Make u-boot.scr file - this file shall be copied to /BOOT partition of the SD Card:

$

cd ~/hdl/projects/arradio/c5soc/software/bootloader/u-boot-socfpga ; pwd

~/hdl/projects/arradio/c5soc/software/bootloader/u-boot-socfpga

$

echo "load mmc 0:1 \${loadaddr} soc_system.rbf;" > u-boot.txt

$

echo "fpga load 0 \${loadaddr} \$filesize;" >> u-boot.txt

$

./tools/mkimage -A arm -O linux -T script -C none -a 0 -e 0 -n "Cyclone V script" -d u-boot.txt u-boot.scr

Last but not least, create the extlinux.conf Linux configuration file, which will be copied to /BOOT partition of the SD Card, in a folder named extlinux:

$

cd ~/hdl/projects/arradio/c5soc/software/bootloader/u-boot-socfpga ; pwd

~/hdl/projects/arradio/c5soc/software/bootloader/u-boot-socfpga

$

mkdir extlinux

$

printf "\
LABEL Linux C5 SoC Default\n\
KERNEL ../zImage\n\
    FDT ../socfpga.dtb\n\
    APPEND root=/dev/mmcblk0p2 rw rootwait earlyprintk console=ttyS0,115200n8" \
    > extlinux/extlinux.conf

Jumper setup

Here is the jumper configuration for ARRADIO/C5SoC to boot the image from the SD Card:

Jumper	Position
CLOCKSEL0	2-3
CLOCKSEL1	2-3
BOOTSEL0	2-3
BOOTSEL1	2-3
BOOTSEL2	1-2
MSEL0	0
MSEL1	1
MSEL2	0
MSEL3	1
MSEL4	0
CODEC_SEL	0

And set JP2 to 2.5V or 1.8V.

Configuring the SD Card

Below are the commands to create the preloader and bootloader partition using the Kuiper Linux image as a starting point. Please check every command before running, especially configuring target device mountpoints accordingly (here as /dev/sdz with partition 1 mounted at /media/BOOT/).

Flash the SD Card with the Kuiper Linux image:

~$

time sudo dd if=./2023-12-13-ADI-Kuiper-full.img of=/dev/sdz status=progress bs=4194304

2952+0 records in
2952+0 records out
12381585408 bytes (12 GB, 12 GiB) copied, 838.353 s, 14.8 MB/s

real        14m7.938s
user        0m0.006s
sys 0m0.009s

~$

sync

Mount the /BOOT partition:

$

lsblk

NAME        MAJ:MIN RM   SIZE RO TYPE MOUNTPOINT
sdz           8:48   1  29.1G  0 disk
├─sdz1        8:49   1     2G  0 part
├─sdz2        8:50   1  27.1G  0 part
└─sdz3        8:51   1     8M  0 part

$

mkdir -p /media/BOOT/

$

sudo mount /dev/sdz1 /media/BOOT/

$

lsblk

NAME        MAJ:MIN RM   SIZE RO TYPE MOUNTPOINT
sdz           8:48   1  29.1G  0 disk
├─sdz1        8:49   1     2G  0 part /media/BOOT
├─sdz2        8:50   1  27.1G  0 part
└─sdz3        8:51   1     8M  0 part

Copy the built files to the /BOOT partition:

$

cd ~/hdl/projects/arradio/c5soc ; pwd

~/hdl/projects/arradio/c5soc

$

cp ./software/bootloader/u-boot-socfpga/u-boot.scr /media/BOOT/

$

cp soc_system.rbf /media/BOOT/

$

mkdir -p /media/BOOT/extlinux

$

cp ./software/bootloader/u-boot-socfpga/extlinux/extlinux.conf /media/BOOT/extlinux/

$

cp ~/linux/arch/arm/boot/dts/socfpga_cyclone5_sockit_arradio.dtb /media/BOOT/socfpga.dtb

$

cp ~/linux/arch/arm/boot/zImage /media/BOOT/

Unmount the /BOOT partition:

$

sudo umount /dev/sdz1

$

lsblk

NAME        MAJ:MIN RM  SIZE  RO TYPE MOUNTPOINT
sdz           8:48  1   29.1G  0 disk
├─sdz1        8:49  1      2G  0 part
├─sdz2        8:50  1   27.1G  0 part
└─sdz3        8:51  1      8M  0 part

Flash the preloader boot partition:

$

cd ~/hdl/projects/arradio/c5soc/software/bootloader/u-boot-socfpga ; pwd

~/hdl/projects/arradio/c5soc/software/bootloader/u-boot-socfpga

$

sudo dd if=/dev/zero of=/dev/sdz3 oflag=sync status=progress \
    bs=$(sudo blockdev --getsize64 /dev/sdz3) count=1

1+0 records in
1+0 records out
8388608 bytes (8.4 MB, 8.0 MiB) copied, 0.359183 s, 23.4 MB/s

$

sudo dd if=./u-boot-with-spl.sfp of=/dev/sdz3

1697+1 records in
1697+1 records out
868996 bytes (869 kB, 849 KiB) copied, 0.21262 s, 4.1 MB/s

CN0540/DE10Nano

• HDL Project:

• ADI’s Linux kernel: here

Building the Linux Kernel image and the Devicetree

Linux/Cygwin/WSL

~$

git clone https://github.com/analogdevicesinc/linux.git

~$

cd linux/

~/linux$

# Set architecture and compiler

~/linux$

export ARCH=arm

~/linux$

export CROSS_COMPILE=/path/to/arm-linux-gnueabihf-

~/linux$

# Apply kconfig settings

~/linux$

make socfpga_adi_defconfig

~/linux$

# Build the kernel

~/linux$

make zImage

~/linux$

# Build the devicetree

~/linux$

make socfpga_cyclone5_de10_nano_cn0540.dtb

Building the Hardware Design

Clone the HDL repository, then build the project:

~$

git clone https://github.com/analogdevicesinc/hdl.git

~$

cd hdl/projects/cn0540/de10nano

~/hdl/projects/cn0540/de10nano$

make

After the design is built, the resulting SRAM Object File (.sof) file shall be converted to a Raw Binary File (.rbf).

If you skipped the last section, ensure to set the architecture and cross compiler environment variables.

Caution

Pay attention to directory changes to where the commands are run from, and always confirm with pwd to show the current path at you terminal.

$

cd ~/hdl/projects/cn0540/de10nano ; pwd

~/hdl/projects/cn0540/de10nano

$

quartus_cpf -c -o bitstream_compression=on \
    ./cn0540_de10nano.sof soc_system.rbf

Building the Preloader and Bootloader Image

This flow applies starting with release 2021_R1 / Quartus Pro version 20.1. For older versions of the flow see previous versions of this page on wiki Altera SOC Quick Start Guide.

In HDL project directory, create the software/bootloader folder and clone the u-boot-socfpga image. Before that create a new BSP settings file:

$

cd ~/hdl/projects/cn0540/de10nano ; pwd

~/hdl/projects/cn0540/de10nano

$

mkdir -p software/bootloader

$

embedded_command_shell.sh bsp-create-settings --type spl \
    --bsp-dir software/bootloader \
    --preloader-settings-dir "hps_isw_handoff/system_bd_sys_hps" \
    --settings software/bootloader/settings.bsp

$

cd software/bootloader ; pwd

~/hdl/projects/cn0540/de10nano/software/bootloader

$

git clone https://github.com/altera-opensource/u-boot-socfpga.git

$

git checkout socfpga_v2021.10

Then run the qts filter and build the preloader and bootloader images:

$

cd ~/hdl/projects/cn0540/de10nano/software/bootloader ; pwd

~/hdl/projects/cn0540/de10nano/software/bootloader

$

cd u-boot-socfpga ; pwd

~/hdl/projects/cn0540/de10nano/software/bootloader/u-boot-socfpga

$

./arch/arm/mach-socfpga/qts-filter.sh cyclone5 ../../../../../board/altera/cyclone5-socdk/qts/

$

make socfpga_cyclone5_defconfig

$

make

Make u-boot.scr file - this file shall be copied to /BOOT partition of the SD Card:

$

cd ~/hdl/projects/arradio/c5soc/software/bootloader/u-boot-socfpga ; pwd

~/hdl/projects/arradio/c5soc/software/bootloader/u-boot-socfpga

$

echo "load mmc 0:1 \${loadaddr} soc_system.rbf;" > u-boot.txt

$

echo "fpga load 0 \${loadaddr} \$filesize;" >> u-boot.txt

$

./tools/mkimage -A arm -O linux -T script -C none -a 0 -e 0 -n "Cyclone V script" -d u-boot.txt u-boot.scr

Last but not least, create the extlinux.conf Linux configuration file, which will be copied to /BOOT partition of the SD Card, in a folder named extlinux:

$

cd ~/hdl/projects/cn0540/de10nano/software/bootloader/u-boot-socfpga ; pwd

~/hdl/projects/cn0540/de10nano/software/bootloader/u-boot-socfpga

$

mkdir extlinux

$

printf "\
LABEL Linux DE10Nano Default\n\
KERNEL ../zImage\n\
    FDT ../socfpga.dtb\n\
    APPEND root=/dev/mmcblk0p2 rw rootwait earlyprintk console=ttyS0,115200n8" \
    > extlinux/extlinux.conf

Configuring the SD Card

Below is the commands to create the preloader and bootloader partition using the Kuiper Linux image as a starting point. Please check every command before running, especially configuring target device mountpoints accordingly (here as /dev/sdz with partition 1 mounted at /media/BOOT/).

Flash the SD Card with the Kuiper Linux image:

~$

time sudo dd if=./2023-12-13-ADI-Kuiper-full.img of=/dev/sdz status=progress bs=4194304

2952+0 records in
2952+0 records out
12381585408 bytes (12 GB, 12 GiB) copied, 838.353 s, 14.8 MB/s

real        14m7.938s
user        0m0.006s
sys 0m0.009s

~$

sync

Mount the /BOOT partition:

$

lsblk

NAME        MAJ:MIN RM   SIZE RO TYPE MOUNTPOINT
sdz           8:48   1  29.1G  0 disk
├─sdz1        8:49   1     2G  0 part
├─sdz2        8:50   1  27.1G  0 part
└─sdz3        8:51   1     8M  0 part

$

mkdir -p /media/BOOT/

$

sudo mount /dev/sdz1 /media/BOOT/

$

lsblk

NAME        MAJ:MIN RM   SIZE RO TYPE MOUNTPOINT
sdz           8:48   1  29.1G  0 disk
├─sdz1        8:49   1     2G  0 part /media/BOOT
├─sdz2        8:50   1  27.1G  0 part
└─sdz3        8:51   1     8M  0 part

Copy the built files to the /BOOT partition:

$

cd ~/hdl/projects/cn0540/de10nano ; pwd

~/hdl/projects/cn0540/de10nano

$

cp ./software/bootloader/u-boot-socfpga/u-boot.scr /media/BOOT/

$

cp soc_system.rbf /media/BOOT/

$

mkdir -p /media/BOOT/extlinux

$

cp ./software/bootloader/u-boot-socfpga/extlinux/extlinux.conf /media/BOOT/extlinux/

$

cp ~/linux/arch/arm/boot/dts/socfpga_cyclone5_de10_nano_cn0540.dtb /media/BOOT/socfpga.dtb

$

cp ~/linux/arch/arm/boot/zImage /media/BOOT/

Unmount the /BOOT partition:

$

sudo umount /dev/sdz1

$

lsblk

NAME        MAJ:MIN RM  SIZE  RO TYPE MOUNTPOINT
sdz           8:48  1   29.1G  0 disk
├─sdz1        8:49  1      2G  0 part
├─sdz2        8:50  1   27.1G  0 part
└─sdz3        8:51  1      8M  0 part

Flash the preloader boot partition:

$

cd ~/hdl/projects/cn0540/de10nano/software/bootloader/u-boot-socfpga ; pwd

~/hdl/projects/cn0540/de10nano/software/bootloader/u-boot-socfpga

$

sudo dd if=/dev/zero of=/dev/sdz3 oflag=sync status=progress \
    bs=$(sudo blockdev --getsize64 /dev/sdz3) count=1

1+0 records in
1+0 records out
8388608 bytes (8.4 MB, 8.0 MiB) copied, 0.359183 s, 23.4 MB/s

$

sudo dd if=./u-boot-with-spl.sfp of=/dev/sdz3

1697+1 records in
1697+1 records out
868996 bytes (869 kB, 849 KiB) copied, 0.21262 s, 4.1 MB/s

$

sync