JESD204 Interface Framework

The JESD204, JESD204A, JESD204B and the JESD204C data converter serial interface standard was created through the JEDEC committee to standardize and reduce the number of data inputs/outputs between high-speed data converters and other devices, such as FPGAs (field-programmable gate arrays).

Fewer interconnects simplifies layout and allows smaller form factor realization without impacting overall system performance. These attributes are important to address the system size and cost constraints of a range of high-speed ADC applications, including wireless infrastructure (GSM, EDGE, W-CDMA, LTE, CDMA2000, WiMAX, TD-SCDMA) transceiver architectures, software-defined radios, portable instrumentation, medical ultrasound equipment, and Mil/Aero applications such as radar and secure communications.

Analog Devices, Inc. (ADI) is an original participating member of the JEDEC JESD204 standards committee and we have concurrently developed compliant data converter technology and tools, and a comprehensive product roadmap to fully enable our customers to take advantage of this significant interfacing breakthrough.

ADI supplies a full-stack supporting JESD204B/C which provides a fully integrated system level experience. This solution includes:

Hint

How to Obtain a License

When customers and partners download/use software from GitHub, e-mail or similar ways, they are obligated to comply to the terms and conditions of the Software License Agreement. This core is released under two different licenses. You may choose either:

  • Commercial licenses may be purchased from ADI or any authorized distributor by ordering IP-JESD204. This will allow you to use the core in a closed system.

  • GPL 2, this allows you to use the core for any purpose, but you must release anything else that links to the JESD204 core (this would normally be your algorithmic IP). You do not need to sign or purchase anything to use the JESD204 core under the GPL license.

There is only one core – the only difference is the license and support. If you have a question about the license, you can email jesd204-licensing@analog.com.

Details on the JESD204 standard

Glossary

Control characters

Representation

Character

Description

/R/

K28.0

Initial lane alignment sequence multi-frame start

/A/

K28.3

Lane alignment

/Q/

K28.4

Initial lane alignment sequence configuration marker

/K/

K28.5

Code group synchronization

/F/

K28.7

Frame synchronization

Abbreviations

  • CGS - Code Group Synchronization

  • ILAS - Initial Lane Alignment Sequence

  • LMFC - Local Multi Frame Clock

  • LEMC - Local Extended Multiblock Clock

  • MCDA - Multiple Converter Device Alignment

  • NMCDA - No Multiple Converter Device Alignment

  • RBD - RX Buffer Delay

  • EMB - Extended Multiblock

  • EoMB - End-of-multiblock sequence (00001)

  • EoEMB - End of extended multiblock identifier bit

Link parameters

  • L - Lane Count

  • M - Converter Count

  • F - Octets per Frame per Lane

  • S - Samples per Converter per Frame

  • NP - Total Number of Bits per Sample

  • N - Converter Resolution

  • K - Frames per Multiframe

  • HD - High Density User Data Format

  • E - Number of multiblocks in an extended multiblock

Clocks

  • character clock - Clock with which 8b10b characters and octets are generated.

  • conversion clock - Clock used by a converter device to perform the A2D or D2A conversion.

  • link clock - Link parallel clock feeding the link layer, lane rate / 40 or lane rate / 80 for 204B links, lane rate / 66 for 204C 64b66b links

  • device clock - Master clock supplied to the JESD204B device from which all other clock signals must be derived. In context of FPGA is an integer multiple of frame clock, used directly in link, transport and application layers.

  • frame clock - Clock rate at which samples are generated/processed. Has the same rate as the conversion clock, except for interpolating DACs or decimating DACs, where it is slower by the interpolation/decimation factor.

  • line clock - Clock for the high-speed serial interface.

  • local clock - A clock generated inside a JESD204B device.

  • SYSREF clock - Slow clock used for cross-device synchronization purposes.

Important

All clocks inside a JESD204B system must have an integer relationship.

Overview

JESD204B/C is a high-speed serial link for data converters between converter and logic device (FPGA/ASIC):

  • (JESD204B) up to 12.5 Gbps (raw data) per lane, with 8B10B encoding

  • (JESD204C) up to 32.5 Gbps per lane, with 64B66B encoding

  • Up to 32 lanes per link

  • Handles data mapping and framing

  • Multi-chip synchronization

  • Deterministic latency

Key Aspects of JESD204 Standards

  • 8b/10b Embedded Clock

    • DC balanced encoding which guarantees significant transition frequency for use with clock and data recovery (CDR) designs

    • Encoding allows both data and control characters - control characters can be used to specify link alignment, maintenance, monitoring, etc

    • Detection of single bit error events on the link

  • Serial Lane Alignment

    • Using special training patterns with control characters, lanes can be aligned across a “link”

    • Trace-to-trace tolerance may be relaxed, relative to synchronous sampling parallel LVDS designs

  • Serial Lane Maintenance/Monitoring

    • Alignment maintained through the super-frame structure and use of specific “characters” to guarantee alignment

    • Link quality monitored at receiver on a lane by lane basis

    • Link established and dropped by the receiver based on error thresholds

  • Device Clock: A clock signal in the system which is a harmonic of the frame rate of the data on the link. In JESD204B systems, the frame clock is no longer the master system reference.

  • SYNC~

    • A system synchronous, active low signal from the receiver to the transmitter which denotes the state of synchronization

    • Synchronous to the local multiframe clock (LMFC)

    • When SYNC~ is low, the receiver and transmitter are synchronizing

    • SYNC~ and frame clock should have similar compliance in order to ensure proper capture/transmission timing (i.e., LVDS, CMOS, CML)

    • SYNC~ signals may be combined if multiple DACs/ADCs are involved.

  • Lane 0, … , L-1

    • Differential lanes on the link (typically high speed CML)

    • 8B/10B code groups are transmitted MSB first/LSB last

  • SYSREF (Optional)

    • An optional source-synchronous, high slew rate timing resolution signal responsible for resetting device clock dividers (including LMFC) to ensure deterministic latency

    • One shot, “gapped periodic” or periodic

    • Distributed to both ADCs/DACs and ASIC/FPGA logic devices in the system

    • When available, SYSREF is the master timing reference in JESD204B systems since it is responsible for resetting the LMFC references

Deterministic Latency in JESD204B

Latency can be defined as deterministic when the time from the input of the JESD204x transmitter to the output of the JESD204x receiver is consistently the same number of clock cycles. In parallel implementations, deterministic latency is rather simple - clocks are carried with the data. In serial implementations, multiple clock domains exist, which can cause nondeterminism. JESD204 and JESD204A do not contain provisions for guaranteeing deterministic latency.

JESD204B looks to address the deterministic latency issue by specifying 3 device subclasses:

  • Device Subclass 0 - no support for deterministic latency

  • Device Subclass 1 - deterministic latency using SYSREF (above 500 MSPS)

  • Device Subclass 2 - deterministic latency using SYNC~ (up to 500 MSPS)

JESD204 Interface Framework Overview

The JESD204 Interface Framework is a system-level integrated HDL and software framework that handles system-level as well as component-level constraints and dependencies:

  • Valid operating values of a configuration settings

  • Relationship between different configuration settings

  • Constraints are propagated between connected components

  • PLL out frequency constraints will affect converter sample rate constraints and vice versa

  • Diagnostics to detect failure source.

It is an integrated framework covering the whole stack on different facets of system design:

  • Hardware: Reference and rapid prototyping systems

  • HDL: IPs for JESD204 protocol handling

  • Software: Drivers to manage clock-chips, converters and HDL

  • Components have been co-designed for improved interoperability

Key features:

  • Automatic interface configuration based on application settings

  • High-level API

  • Dynamic re-configuration

  • Integration with Matlab/Simulink, Python and GNU radio

The JESD204B standard defines multiple layers, each layer being responsible for a particular function.

The Analog Devices JESD204B HDL solution follows the standard here and defines 4 layers: physical layer, link layer, transport layer and application layer. For the first three layers Analog Devices provides tandard components that can be linked up to provide a full JESD204B protocol processing chain.

Depending on the FPGA and converter combinations that are being interfaced, different components can be chosen for the physical and transport layer. The FPGA defines which physical layer component should be used and the interfaced converter defines which transport layer component should be used.

The link layer component is selected based on the direction of the JESD204B link.

The application layer is user defined and can be used to implement application specific signal processing.

FPGA HDL Support

JESD204B/C Layers

The JESD204B/C standard defines multiple layers, each layer being responsible for a particular function. The Analog Devices JESD204B/C HDL solution follows the current standard and defines 4 layers. Physical layer, link layer, transport layer and application layer. For the first three layers, ADI provides standard components that can be linked to provide a full JESD204B/C protocol processing chain.

Depending on the FPGA and converter combinations that are being interfaced, different components can be chosen for the physical and transport layer. The FPGA defines which physical layer component should be used, meanwhile the interfaced converter defines which transport layer component should be used.

The link layer component is selected based on the direction of the JESD204B/C link.

The application layer is user-defined and can be used to implement application-specific signal processing.

JESD204B/C chain

Physical Layer

Physical layer peripherals are responsible for interfacing and configuring the high-speed serial transceivers. Currently, we have support for GTXE2, GTHE3, GTHE4, GTYE4 for AMD Xilinx and Arria 10 transceivers for Intel.

  • AXI ADXCVR: JESD204B Gigabit Transceiver Register Configuration Peripheral

  • UTIL_ADXCVR: JESD204B Gigabit Transceiver Interface Peripheral for AMD Xilinx FPGAs

Transport Layer

Transport layer peripherals are responsible for converter specific data framing and de-framing.

Interfaces

Interfaces are a well-defined collection of wires that are used to communicate between components. The following interfaces are used to connect components of the HDL JESD204B/C processing stack.

Software Support

Linux

No-OS

Tutorial

  1. System Architecture

  2. Generic JESD204 block designs. This will help you understand the generic blocks for the next steps.

  3. Checkout the HDL Source, and then build either one of:

    1. HDL AMD Xilinx

    2. HDL Altera

  4. Linux

HDL Example Projects

Technical Articles

JESD204B Rapid Prototyping Platforms

JESD204B ADCs

  • AD6673: 80 MHz Bandwidth, Dual IF Receiver

  • AD6674: 385 MHz BW IF Diversity Receiver

  • AD6676: Wideband IF Receiver Subsystem

  • AD6677: 80 MHz Bandwidth, IF Receiver

  • AD6684: 135 MHz Quad IF Receiver

  • AD6688: RF Diversity and 1.2GHz BW Observation Receiver

  • AD9207: 12-bit, 6 GSPS, JESD204B/C Dual ADC

  • AD9208: 14-bit, 3 GSPS, JESD204B, Dual ADC

  • AD9209: 12-bit, 4 GSPS, JESD204B/C, Quad ADC

  • AD9213: 12-bit, 10.25 GSPS, JESD204B, RF ADC

  • AD9234: 12-bit, 1 GSPS/500 MSPS JESD204B, Dual ADC

  • AD9250: 14-bit, 170 MSPS/250 MSPS, JESD204B, Dual ADC

  • AD9625: 12-bit, 2.6 GSPS/2.5 GSPS/2.0 GSPS, 1.3V/2.5V ADC

  • AD9656: Quad, 16-bit, 125 MSPS JESD204B 1.8V ADC

  • AD9680: 14-bit, 1.25 GSPS/1 GSPS/820 MSPS/500MSPS JESD204B, Dual ADC

  • AD9683: 14-bit, 170 MSPS/250 MSPS, JESD204B, ADC

  • AD9690: 14-bit, 500 MSPS / 1 GSPS JESD204B, ADC

  • AD9691: 14-bit, 1.25 GSPS JESD204B, Dual ADC

  • AD9694: 14-bit, 500 MSPS JESD204B, Quad ADC

  • AD9695: 14-bit, 1300 MSPS/625 MSPS,JESD204B, Dual ADC

  • AD9083: 16-Channel, 125 MHz Bandwidth, JESD204B ADC

  • AD9094: 8-bit, 1 GSPS, JESD204B, Quad ADC

JESD204B DACs

  • AD9135: Dual, 11-bit, high dynamic, 2.8 GSPS, TxDAC+ DAC

  • AD9136: Dual, 16-bit, 2.8 GSPS, TxDAC+ DAC

  • AD9144: Quad, 16-bit, 2.8 GSPS, TxDAC+ DAC

  • AD9152: Dual, 16-bit, 2.25 GSPS, TxDAC+ DAC

  • AD9154: Quad, 16-bit, 2.4 GSPS, TxDAC+ DAC

  • AD9161: 11-bit, 12 GSPS, RF DAC

  • AD9162: 16-bit, 12 GSPS, RF DAC

  • AD9163: 16-bit, 12 GSPS, RF DAC and Digital Upconverter

  • AD9164: 16-bit, 12 GSPS, RF DAC and Direct Digital Synthesizer

  • AD9172: Dual, 16-bit, 12.6 GSPS RF DAC with Channelizers

  • AD9173: Dual, 16-bit, 12.6 GSPS RF DAC with Channelizers

  • AD9174: Dual, 16-bit, 12.6 GSPS RF DAC and Direct Digital Synthesizer

  • AD9175: Dual, 11-bit/16-bit, 12.6 GSPS RF DAC with Wideband Channelizers

  • AD9176: Dual, 16-bit, 12.6 GSPS RF DAC with Wideband Channelizers

  • AD9177: Quad, 16-bit, 12 GSPS RF DAC with Wideband Channelizers

JESD204B RF Transceivers

  • AD9371: SDR Integrated, Dual RF Transceiver with Observation Path

  • AD9375: SDR Integrated, Dual RF Transceiver with Observation Path and DPD

  • ADRV9008-1: SDR Integrated, Dual RF Receiver

  • ADRV9008-2: SDR Integrated, Dual RF Transmitter with Observation Path

  • ADRV9009: SDR Integrated, Dual RF Transceiver with Observation Path

JESD204B/C Mixed-Signal Front Ends

  • AD9081: MxFE Quad, 16-bit, 12 GSPS RF DAC and Quad, 12-bit, 4 GSPS RF ADC

  • AD9082: MxFE QUAD, 16-bit, 12 GSPS RF DAC and DUAL, 12-bit, 6 GSPS RF ADC

  • AD9986: 4T2R Direct RF Transmitter and Observation Receiver

  • AD9988: 4T4R Direct RF Receiver and Transmitter

JESD204B Clocking Solutions

  • AD9528: JESD204B Clock Generator with 14 LVDS/HSTL Outputs

  • ADF4371: Microwave Wideband Synthesizer with Integrated VCO

  • HMC7043: High Performance, 3.2 GHz, 14-Output Fanout Buffer

  • HMC7044: High Performance, 3.2 GHz, 14-Output Jitter Attenuator with JESD204B

  • LTC6952: Ultralow Jitter, 4.5GHz PLL, JESD204B/C

Software Support

References