AD7405-FMC HDL project#

Overview#

The EVAL-AD7405 is a full-featured evaluation board designed to allow the user to easily evaluate all features of the AD7405 isolated analog-to-digital converter (ADC).

The provided HDL reference design supports the AD7405 , AD7403 and ADuM7701 devices. One of the main differences between these devices is the type of the digital data lines. In the case of ADuM7701 and AD7403, it is single-ended, and for AD7405 is differential.

Supported boards#

Supported devices#

Supported carriers#

Evaluation board	Carrier	FMC slot
EVAL-AD7405	ZedBoard	FMC-LPC
EVAL-AD7403	ZedBoard	FMC-LPC
EVAL-ADuM7701	ZedBoard	FMC-LPC

Block design#

Block diagram#

The data path and clock domains are depicted in the below diagrams:

Block design for the differential signals (AD7405)#

Block design for the single-ended signals (ADuM7701 and AD7403)#

Configuration modes#

LVDS_CMOS_N: specific to the type of the data and clock signals
- 0 - Single-ended data and clock signals (default)
- 1 - Differential data and clock signals

CPU/Memory interconnects addresses#

The addresses are dependent on the architecture of the FPGA, having an offset added to the base address from HDL (see more at HDL Architecture).

Instance	Zynq/Microblaze
axi_ad7405_dma	0x44A3_0000
axi_adc_clkgen	0x44A4_0000

GPIOs#

GPIO signal	Direction	HDL GPIO EMIO	Software GPIO	Software GPIO
	(from FPGA view)		Zynq-7000	Zynq MP
filter_reset	INOUT	48	102	124
decimation_ratio[15:0]	INOUT	47:32	101:86	125:110

Interrupts#

Below are the Programmable Logic interrupts used in this project.

Instance name	HDL	Linux Zynq	Actual Zynq
axi_ad7405_dma	13	57	89

Building the HDL project#

The design is built upon ADI’s generic HDL reference design framework. ADI distributes the bit/elf files of these projects as part of the ADI Kuiper Linux. If you want to build the sources, ADI makes them available on the HDL repository. To get the source you must clone the HDL repository.

Default (Single-ended data and clock signals):

user@analog:~$ cd hdl/projects/ad7405/zed
user@analog:~/hdl/projects/ad7405/zed$ make

If differential data and clock signals are desired:

user@analog:~$ cd hdl/projects/ad7405/zed
user@analog:~/hdl/projects/ad7405/zed$ make LVDS_CMOS_N=1

A more comprehensive build guide can be found in the Build an HDL project user guide.

Resources#

HDL related#

AD7405-FMC HDL project source code

IP name	Source code link	Documentation link
AXI_CLKGEN	library/axi_clkgen	AXI CLK Generator
AXI_DMAC	library/axi_dmac	AXI DMAC
AXI_HDMI_TX	library/axi_hdmi_tx	AXI HDMI TX
AXI_I2S_ADI	library/axi_i2s_adi	—
AXI_SPDIF_TX	library/axi_spdif_tx	—
AXI_SYSID	library/axi_sysid	AXI System ID
SYSID_ROM	library/sysid_rom	AXI System ID
UTIL_DEC256SINC24B	library/util_dec256sinc24b	—
UTIL_I2C_MIXER	library/util_i2c_mixer	—

More information#

ADI HDL User guide

Support#

Analog Devices, Inc. will provide limited online support for anyone using the reference design with ADI components via the EngineerZone FPGA reference designs forum.

For questions regarding the ADI Linux device drivers, device trees, etc. from our Linux GitHub repository, the team will offer support on the EngineerZone Linux software drivers forum.

For questions concerning the ADI No-OS drivers, from our No-OS GitHub repository, the team will offer support on the EngineerZone microcontroller No-OS drivers forum.

It should be noted, that the older the tools’ versions and release branches are, the lower the chances to receive support from ADI engineers.