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ad9361.h
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1/***************************************************************************/
32#ifndef IIO_FREQUENCY_AD9361_H_
33#define IIO_FREQUENCY_AD9361_H_
34
35#include <stdint.h>
36#include "no_os_gpio.h"
37#include "common.h"
38#include "ad9361_ext_band_ctrl.h"
39
40#define REG_SPI_CONF 0x000 /* SPI Configuration */
41#define REG_MULTICHIP_SYNC_AND_TX_MON_CTRL 0x001 /* Multi-Chip Sync and Tx Mon Control */
42#define REG_TX_ENABLE_FILTER_CTRL 0x002 /* Tx Enable & Filter Control */
43#define REG_RX_ENABLE_FILTER_CTRL 0x003 /* Rx Enable & Filter Control */
44#define REG_INPUT_SELECT 0x004 /* Input Select */
45#define REG_RFPLL_DIVIDERS 0x005 /* RFPLL Dividers */
46#define REG_RX_CLOCK_DATA_DELAY 0x006 /* Rx Clock & Data Delay */
47#define REG_TX_CLOCK_DATA_DELAY 0x007 /* Tx Clock & Data Delay */
48#define REG_CLOCK_ENABLE 0x009 /* Clock Enable */
49#define REG_BBPLL 0x00A /* BBPLL */
50#define REG_TEMP_OFFSET 0x00B /* Offset */
51#define REG_START_TEMP_READING 0x00C /* Start Temp Reading */
52#define REG_TEMP_SENSE2 0x00D /* Temp Sense2 */
53#define REG_TEMPERATURE 0x00E /* Temperature */
54#define REG_TEMP_SENSOR_CONFIG 0x00F /* Temp Sensor Config */
55#define REG_PARALLEL_PORT_CONF_1 0x010 /* Parallel Port Configuration 1 */
56#define REG_PARALLEL_PORT_CONF_2 0x011 /* Parallel Port Configuration 2 */
57#define REG_PARALLEL_PORT_CONF_3 0x012 /* Parallel Port Configuration 3 */
58#define REG_ENSM_MODE 0x013 /* ENSM Mode */
59#define REG_ENSM_CONFIG_1 0x014 /* ENSM Config 1 */
60#define REG_ENSM_CONFIG_2 0x015 /* ENSM Config 2 */
61#define REG_CALIBRATION_CTRL 0x016 /* Calibration Control */
62#define REG_STATE 0x017 /* State */
63#define REG_AUXDAC_1_WORD 0x018 /* AuxDAC 1 Word */
64#define REG_AUXDAC_2_WORD 0x019 /* AuxDAC 2 Word */
65#define REG_AUXDAC_1_CONFIG 0x01A /* AuxDAC 1 Config */
66#define REG_AUXDAC_2_CONFIG 0x01B /* AuxDAC 2 Config */
67#define REG_AUXADC_CLOCK_DIVIDER 0x01C /* AuxADC Clock Divider */
68#define REG_AUXADC_CONFIG 0x01D /* Aux ADC Config */
69#define REG_AUXADC_WORD_MSB 0x01E /* AuxADC Word MSB */
70#define REG_AUXADC_LSB 0x01F /* AuxADC LSB */
71#define REG_AUTO_GPO 0x020 /* Auto GPO */
72#define REG_AGC_GAIN_LOCK_DELAY 0x021 /* AGC Gain Lock Delay */
73#define REG_AGC_ATTACK_DELAY 0x022 /* AGC Attack Delay */
74#define REG_AUXDAC_ENABLE_CTRL 0x023 /* AuxDAC Enable Control */
75#define REG_RX_LOAD_SYNTH_DELAY 0x024 /* RX Load Synth Delay */
76#define REG_TX_LOAD_SYNTH_DELAY 0x025 /* TX Load Synth Delay */
77#define REG_EXTERNAL_LNA_CTRL 0x026 /* External LNA control */
78#define REG_GPO_FORCE_AND_INIT 0x027 /* GPO Force and Init */
79#define REG_GPO0_RX_DELAY 0x028 /* GPO0 Rx delay */
80#define REG_GPO1_RX_DELAY 0x029 /* GPO1 Rx delay */
81#define REG_GPO2_RX_DELAY 0x02A /* GPO2 Rx delay */
82#define REG_GPO3_RX_DELAY 0x02B /* GPO3 Rx delay */
83#define REG_GPO0_TX_DELAY 0x02C /* GPO0 Tx Delay */
84#define REG_GPO1_TX_DELAY 0x02D /* GPO1 Tx Delay */
85#define REG_GPO2_TX_DELAY 0x02E /* GPO2 Tx Delay */
86#define REG_GPO3_TX_DELAY 0x02F /* GPO3 Tx Delay */
87#define REG_AUXDAC1_RX_DELAY 0x030 /* AuxDAC1 Rx Delay */
88#define REG_AUXDAC1_TX_DELAY 0x031 /* AuxDAC1 Tx Delay */
89#define REG_AUXDAC2_RX_DELAY 0x032 /* AuxDAC2 Rx Delay */
90#define REG_AUXDAC2_TX_DELAY 0x033 /* AuxDAC2 Tx Delay */
91#define REG_CTRL_OUTPUT_POINTER 0x035 /* Control Output Pointer */
92#define REG_CTRL_OUTPUT_ENABLE 0x036 /* Control Output Enable */
93#define REG_PRODUCT_ID 0x037 /* Product ID */
94#define REG_REFERENCE_CLOCK_CYCLES 0x03A /* Reference Clock Cycles */
95#define REG_DIGITAL_IO_CTRL 0x03B /* Digital I/O Control */
96#define REG_LVDS_BIAS_CTRL 0x03C /* LVDS Bias control */
97#define REG_LVDS_INVERT_CTRL1 0x03D /* LVDS Invert control1 */
98#define REG_LVDS_INVERT_CTRL2 0x03E /* LVDS Invert control2 */
99#define REG_SDM_CTRL_1 0x03F /* SDM Control 1 */
100#define REG_FRACT_BB_FREQ_WORD_1 0x041 /* Fractional BB Freq Word 1 */
101#define REG_FRACT_BB_FREQ_WORD_2 0x042 /* Fractional BB Freq Word 2 */
102#define REG_FRACT_BB_FREQ_WORD_3 0x043 /* Fractional BB Freq Word 3 */
103#define REG_INTEGER_BB_FREQ_WORD 0x044 /* Integer BB Freq Word */
104#define REG_CLOCK_CTRL 0x045 /* Clock Control */
105#define REG_CP_CURRENT 0x046 /* CP Current */
106#define REG_CP_BLEED_CURRENT 0x047 /* CP Bleed Current */
107#define REG_LOOP_FILTER_1 0x048 /* Loop Filter 1 */
108#define REG_LOOP_FILTER_2 0x049 /* Loop Filter 2 */
109#define REG_LOOP_FILTER_3 0x04A /* Loop Filter 3 */
110#define REG_VCO_CTRL 0x04B /* VCO Control */
111#define REG_VCO_PROGRAM_1 0x04C
112#define REG_VCO_PROGRAM_2 0x04D
113#define REG_SDM_CTRL 0x04E /* SDM Control */
114#define REG_RX_SYNTH_POWER_DOWN_OVERRIDE 0x050 /* Rx Synth Power Down Override */
115#define REG_TX_SYNTH_POWER_DOWN_OVERRIDE 0x051 /* TX Synth Power Down Override */
116#define REG_RX_ANALOG_POWER_DOWN_OVERRIDE_1 0x052 /* Rx Analog Power Down Override 1 */
117#define REG_RX_ANALOG_POWER_DOWN_OVERRIDE_2 0x053 /* Rx Analog Power Down Override 2 */
118#define REG_RX1_ADC_POWER_DOWN_OVERRIDE 0x054 /* Rx1 ADC Power Down Override */
119#define REG_RX2_ADC_POWER_DOWN_OVERRIDE 0x055 /* Rx2 ADC Power Down Override */
120#define REG_TX_ANALOG_POWER_DOWN_OVERRIDE_1 0x056 /* Tx Analog Power Down Override 1 */
121#define REG_ANALOG_POWER_DOWN_OVERRIDE 0x057 /* Analog Power Down Override */
122#define REG_MISC_POWER_DOWN_OVERRIDE 0x058 /* Misc Power Down Override */
123#define REG_CH_1_OVERFLOW 0x05E /* CH 1 Overflow */
124#define REG_CH_2_OVERFLOW 0x05F /* CH 2 Overflow */
125#define REG_TX_FILTER_COEF_ADDR 0x060 /* TX Filter Coefficient Address */
126#define REG_TX_FILTER_COEF_WRITE_DATA_1 0x061 /* TX Filter Coefficient Write Data 1 */
127#define REG_TX_FILTER_COEF_WRITE_DATA_2 0x062 /* TX Filter Coefficient Write Data 2 */
128#define REG_TX_FILTER_COEF_READ_DATA_1 0x063 /* TX Filter Coefficient Read Data 1 */
129#define REG_TX_FILTER_COEF_READ_DATA_2 0x064 /* TX Filter Coefficient Read Data 2 */
130#define REG_TX_FILTER_CONF 0x065 /* TX Filter Configuration */
131#define REG_TX_MON_LOW_GAIN 0x067 /* Tx Mon Low Gain */
132#define REG_TX_MON_HIGH_GAIN 0x068 /* Tx Mon High Gain */
133#define REG_TX_MON_DELAY 0x069 /* Tx Mon Delay */
134#define REG_TX_LEVEL_THRESH 0x06A /* Tx Level Threshold */
135#define REG_TX_RSSI1 0x06B /* TX RSSI1 */
136#define REG_TX_RSSI2 0x06C /* TX RSSI2 */
137#define REG_TX_RSSI_LSB 0x06D /* TX RSSI LSB */
138#define REG_TPM_MODE_ENABLE 0x06E /* TPM Mode Enable */
139#define REG_TX_MON_TEMP_GAIN_COEF 0x06F /* Temp Gain Coefficient */
140#define REG_TX_MON_1_CONFIG 0x070 /* Tx Mon 1 Config */
141#define REG_TX_MON_2_CONFIG 0x071 /* Tx Mon 2 Config */
142#define REG_TX1_ATTEN_0 0x073 /* Tx1 Atten 0 */
143#define REG_TX1_ATTEN_1 0x074 /* Tx1 Atten 1 */
144#define REG_TX2_ATTEN_0 0x075 /* Tx2 Atten 0 */
145#define REG_TX2_ATTEN_1 0x076 /* Tx2 Atten 1 */
146#define REG_TX_ATTEN_OFFSET 0x077 /* Tx Atten Offset */
147#define REG_TX_ATTEN_THRESH 0x078 /* Tx Atten Threshold */
148#define REG_TX1_DIG_ATTEN 0x079 /* Tx1 Dig Attenuation */
149#define REG_TX2_DIG_ATTEN 0x07C /* Tx2 Dig Attenuation */
150#define REG_TX1_SYMBOL_ATTEN 0x07F /* TX1 Symbol Attenuation */
151#define REG_TX2_SYMBOL_ATTEN 0x080 /* TX2 Symbol Attenuation */
152#define REG_TX_SYMBOL_ATTEN_CONFIG 0x081 /* TX Symbol Atten Config */
153#define REG_TX1_OUT_1_PHASE_CORR 0x08E /* Tx1 Out 1 Phase Corr */
154#define REG_TX1_OUT_1_GAIN_CORR 0x08F /* Tx1 Out 1 Gain Corr */
155#define REG_TX2_OUT_1_PHASE_CORR 0x090 /* Tx2 Out 1 Phase Corr */
156#define REG_TX2_OUT_1_GAIN_CORR 0x091 /* Tx2 Out 1 Gain Corr */
157#define REG_TX1_OUT_1_OFFSET_I 0x092 /* Tx1 Out 1 Offset I */
158#define REG_TX1_OUT_1_OFFSET_Q 0x093 /* Tx1 Out 1 Offset Q */
159#define REG_TX2_OUT_1_OFFSET_I 0x094 /* Tx2 Out 1 Offset I */
160#define REG_TX2_OUT_1_OFFSET_Q 0x095 /* Tx2 Out 1 Offset Q */
161#define REG_TX1_OUT_2_PHASE_CORR 0x096 /* Tx1 Out 2 Phase Corr */
162#define REG_TX1_OUT_2_GAIN_CORR 0x097 /* Tx1 Out 2 Gain Corr */
163#define REG_TX2_OUT_2_PHASE_CORR 0x098 /* Tx2 Out 2 Phase Corr */
164#define REG_TX2_OUT_2_GAIN_CORR 0x099 /* Tx2 Out 2 Gain Corr */
165#define REG_TX1_OUT_2_OFFSET_I 0x09A /* Tx1 Out 2 Offset I */
166#define REG_TX1_OUT_2_OFFSET_Q 0x09B /* Tx1 Out 2 Offset Q */
167#define REG_TX2_OUT_2_OFFSET_I 0x09C /* Tx2 Out 2 Offset I */
168#define REG_TX2_OUT_2_OFFSET_Q 0x09D /* Tx2 Out 2 Offset Q */
169#define REG_TX_FORCE_BITS 0x09F /* Force Bits */
170#define REG_QUAD_CAL_NCO_FREQ_PHASE_OFFSET 0x0A0 /* Quad Cal NCO Freq & Phase Offset */
171#define REG_QUAD_CAL_CTRL 0x0A1 /* Quad Cal Control */
172#define REG_KEXP_1 0x0A2 /* Kexp 1 */
173#define REG_KEXP_2 0x0A3 /* Kexp 2 */
174#define REG_QUAD_SETTLE_COUNT 0x0A4 /* QUAD Settle count */
175#define REG_MAG_FTEST_THRESH 0x0A5 /* Mag. Ftest Thresh */
176#define REG_MAG_FTEST_THRESH_2 0x0A6 /* Mag. Ftest Thresh 2 */
177#define REG_QUAD_CAL_STATUS_TX1 0x0A7 /* Quad cal status Tx1 */
178#define REG_QUAD_CAL_STATUS_TX2 0x0A8 /* Quad cal status Tx2 */
179#define REG_QUAD_CAL_COUNT 0x0A9 /* Quad cal Count */
180#define REG_TX_QUAD_FULL_LMT_GAIN 0x0AA /* Tx Quad Full/LMT Gain */
181#define REG_SQUARER_CONFIG 0x0AB /* Squarer Config */
182#define REG_TX_QUAD_CAL_ATTEN 0x0AC /* TX Quad Cal Atten */
183#define REG_THRESH_ACCUM 0x0AD /* Thresh Accum */
184#define REG_TX_QUAD_LPF_GAIN 0x0AE /* Tx Quad LPF Gain */
185#define REG_TXDAC_VDS_I 0x0B0 /* TxDAC Vds I */
186#define REG_TXDAC_VDS_Q 0x0B1 /* TxDAC Vds Q */
187#define REG_TXDAC_GN_I 0x0B2 /* TxDAC gn I */
188#define REG_TXDAC_GN_Q 0x0B3 /* TxDAC gn Q */
189#define REG_TXBBF_OPAMP_A 0x0C0 /* TxBBF OpAmp A */
190#define REG_TXBBF_OPAMP_B 0x0C1 /* TxBBF OpAmp B */
191#define REG_TX_BBF_R1 0x0C2 /* Tx BBF R1 */
192#define REG_TX_BBF_R2 0x0C3 /* Tx BBF R2 */
193#define REG_TX_BBF_R3 0x0C4 /* Tx BBF R3 */
194#define REG_TX_BBF_R4 0x0C5 /* Tx BBF R4 */
195#define REG_TX_BBF_RP 0x0C6 /* Tx BBF RP */
196#define REG_TX_BBF_C1 0x0C7 /* Tx BBF C1 */
197#define REG_TX_BBF_C2 0x0C8 /* Tx BBF C2 */
198#define REG_TX_BBF_CP 0x0C9 /* Tx BBF Cp */
199#define REG_TX_TUNE_CTRL 0x0CA /* Tx Tune Control */
200#define REG_TX_BBF_R2B 0x0CB /* Tx BBF R2b */
201#define REG_TX_BBF_TUNE 0x0CC /* Tx BBF Tune */
202#define REG_CONFIG0 0x0D0 /* Config0 */
203#define REG_RESISTOR 0x0D1 /* Resistor */
204#define REG_CAPACITOR 0x0D2 /* Capacitor */
205#define REG_LO_CM 0x0D3 /* LO CM */
206#define REG_TX_BBF_TUNE_DIVIDER 0x0D6 /* TX BBF Tune Divider */
207#define REG_TX_BBF_TUNE_MODE 0x0D7 /* TX BBF Tune Mode */
208#define REG_RX_FILTER_COEF_ADDR 0x0F0 /* Rx Filter Coeff Addr */
209#define REG_RX_FILTER_COEF_DATA_1 0x0F1 /* Rx Filter Coeff Data 1 */
210#define REG_RX_FILTER_COEF_DATA_2 0x0F2 /* Rx Filter Coeff Data 2 */
211#define REG_RX_FILTER_COEF_READ_DATA_1 0x0F3 /* Rx Filter Coeff Read Data 1 */
212#define REG_RX_FILTER_COEF_READ_DATA_2 0x0F4 /* Rx Filter Coeff Read Data 2 */
213#define REG_RX_FILTER_CONFIG 0x0F5 /* Rx Filter Config */
214#define REG_RX_FILTER_GAIN 0x0F6 /* Rx Filter Gain */
215#define REG_AGC_CONFIG_1 0x0FA /* AGC Config1 */
216#define REG_AGC_CONFIG_2 0x0FB /* AGC config2 */
217#define REG_AGC_CONFIG_3 0x0FC /* AGC Config3 */
218#define REG_MAX_LMT_FULL_GAIN 0x0FD /* Max LMT/Full Gain */
219#define REG_PEAK_WAIT_TIME 0x0FE /* Peak Wait Time */
220#define REG_DIGITAL_GAIN 0x100 /* Digital Gain */
221#define REG_AGC_LOCK_LEVEL 0x101 /* AGC Lock Level */
222#define REG_ADC_NOISE_CORRECTION_FACTOR 0x102 /* ADC noise Correction Factor */
223#define REG_GAIN_STP_CONFIG1 0x103 /* Gain Step Config1 */
224#define REG_ADC_SMALL_OVERLOAD_THRESH 0x104 /* ADC Small Overload Threshold */
225#define REG_ADC_LARGE_OVERLOAD_THRESH 0x105 /* ADC Large Overload Threshold */
226#define REG_GAIN_STP_CONFIG_2 0x106 /* Gain Step Config 2 */
227#define REG_SMALL_LMT_OVERLOAD_THRESH 0x107 /* Small LMT Overload Threshold */
228#define REG_LARGE_LMT_OVERLOAD_THRESH 0x108 /* Large LMT Overload Threshold */
229#define REG_RX1_MANUAL_LMT_FULL_GAIN 0x109 /* Rx1 Manual LMT/Full Gain */
230#define REG_RX1_MANUAL_LPF_GAIN 0x10A /* Rx1 Manual LPF gain */
231#define REG_RX1_MANUAL_DIGITALFORCED_GAIN 0x10B /* Rx1 Manual Digital/Forced Gain */
232#define REG_RX2_MANUAL_LMT_FULL_GAIN 0x10C /* Rx2 Manual LMT/Full Gain */
233#define REG_RX2_MANUAL_LPF_GAIN 0x10D /* Rx2 Manual LPF Gain */
234#define REG_RX2_MANUAL_DIGITALFORCED_GAIN 0x10E /* Rx2 Manual Digital/Forced Gain */
235#define REG_FAST_CONFIG_1 0x110 /* Config 1 */
236#define REG_FAST_CONFIG_2_SETTLING_DELAY 0x111 /* Config 2 & Settling Delay */
237#define REG_FAST_ENERGY_LOST_THRESH 0x112 /* Energy Lost Threshold */
238#define REG_FAST_STRONGER_SIGNAL_THRESH 0x113 /* Stronger Signal Threshold */
239#define REG_FAST_LOW_POWER_THRESH 0x114 /* Low Power Threshold */
240#define REG_FAST_STRONG_SIGNAL_FREEZE 0x115 /* Strong Signal Freeze */
241#define REG_FAST_FINAL_OVER_RANGE_AND_OPT_GAIN 0x116 /* Final Over Range and Opt Gain */
242#define REG_FAST_ENERGY_DETECT_COUNT 0x117 /* Energy Detect Count */
243#define REG_FAST_AGCLL_UPPER_LIMIT 0x118 /* AGCLL Upper Limit */
244#define REG_FAST_GAIN_LOCK_EXIT_COUNT 0x119 /* Gain Lock Exit Count */
245#define REG_FAST_INITIAL_LMT_GAIN_LIMIT 0x11A /* Initial LMT Gain Limit */
246#define REG_FAST_INCREMENT_TIME 0x11B /* Increment Time */
247#define REG_AGC_INNER_LOW_THRESH 0x120 /* AGC Inner Low Threshold */
248#define REG_LMT_OVERLOAD_COUNTERS 0x121 /* LMT Overload Counters */
249#define REG_ADC_OVERLOAD_COUNTERS 0x122 /* ADC Overload Counters */
250#define REG_GAIN_STP1 0x123 /* Gain Step1 */
251#define REG_GAIN_UPDATE_COUNTER1 0x124 /* Gain Update Counter1 */
252#define REG_GAIN_UPDATE_COUNTER2 0x125 /* Gain Update Counter2 */
253#define REG_DIGITAL_SAT_COUNTER 0x128 /* Digital Sat Counter */
254#define REG_OUTER_POWER_THRESHS 0x129 /* Outer Power Thresholds */
255#define REG_GAIN_STP_2 0x12A /* Gain Step 2 */
256#define REG_EXT_LNA_HIGH_GAIN 0x12C /* Ext LNA High Gain */
257#define REG_EXT_LNA_LOW_GAIN 0x12D /* Ext LNA Low Gain */
258#define REG_GAIN_TABLE_ADDRESS 0x130 /* Gain Table Address */
259#define REG_GAIN_TABLE_WRITE_DATA1 0x131 /* Gain Table Write Data1 */
260#define REG_GAIN_TABLE_WRITE_DATA2 0x132 /* Gain Table Write Data2 */
261#define REG_GAIN_TABLE_WRITE_DATA3 0x133 /* Gain Table Write Data 3 */
262#define REG_GAIN_TABLE_READ_DATA1 0x134 /* Gain Table Read Data 1 */
263#define REG_GAIN_TABLE_READ_DATA2 0x135 /* Gain Table Read Data 2 */
264#define REG_GAIN_TABLE_READ_DATA3 0x136 /* Gain Table Read Data 3 */
265#define REG_GAIN_TABLE_CONFIG 0x137 /* Gain Table Config */
266#define REG_GM_SUB_TABLE_ADDRESS 0x138 /* Gm Sub Table Address */
267#define REG_GM_SUB_TABLE_GAIN_WRITE 0x139 /* Gm Sub Table Gain Word Write */
268#define REG_GM_SUB_TABLE_BIAS_WRITE 0x13A /* Gm Sub Table Bias Word Write */
269#define REG_GM_SUB_TABLE_CTRL_WRITE 0x13B /* Gm Sub Table Control Word Write */
270#define REG_GM_SUB_TABLE_GAIN_READ 0x13C /* Gm Sub Table Gain Word Read */
271#define REG_GM_SUB_TABLE_BIAS_READ 0x13D /* Gm Sub Table Bias Word Read */
272#define REG_GM_SUB_TABLE_CTRL_READ 0x13E /* Gm Sub Table Control Word Read */
273#define REG_GM_SUB_TABLE_CONFIG 0x13F /* Gm Sub Table Config */
274#define REG_WORD_ADDRESS 0x140 /* Word Address */
275#define REG_GAIN_DIFF_WORDERROR_WRITE 0x141 /* Gain Diff Word/Error Write */
276#define REG_GAIN_ERROR_READ 0x142 /* Gain Error Read */
277#define REG_CONFIG 0x143 /* Config */
278#define REG_LNA_GAIN_DIFF_READ_BACK 0x144 /* LNA Gain Diff Read Back */
279#define REG_MAX_MIXER_CALIBRATION_GAIN_INDEX 0x145 /* Max Mixer Calibration Gain Index */
280#define REG_TEMP_GAIN_COEF 0x146 /* Temp Gain Coefficient */
281#define REG_SETTLE_TIME 0x147 /* Settle Time */
282#define REG_MEASURE_DURATION 0x148 /* Measure Duration */
283#define REG_CAL_TEMP_SENSOR_WORD 0x149 /* Cal Temp sensor word */
284#define REG_MEASURE_DURATION_01 0x150 /* Measure Duration 0&1 */
285#define REG_MEASURE_DURATION_23 0x151 /* Measure Duration 2&3 */
286#define REG_RSSI_WEIGHT_0 0x152 /* RSSI Weight 0 */
287#define REG_RSSI_WEIGHT_1 0x153 /* RSSI Weight 1 */
288#define REG_RSSI_WEIGHT_2 0x154 /* RSSI Weight 2 */
289#define REG_RSSI_WEIGHT_3 0x155 /* RSSI Weight 3 */
290#define REG_RSSI_DELAY 0x156 /* RSSI delay */
291#define REG_RSSI_WAIT_TIME 0x157 /* RSSI wait time */
292#define REG_RSSI_CONFIG 0x158 /* RSSI Config */
293#define REG_ADC_MEASURE_DURATION_01 0x159 /* ADC Measure Duration 0&1 */
294#define REG_ADC_WEIGHT_0 0x15A /* ADC Weight 0 */
295#define REG_ADC_WEIGHT_1 0x15B /* ADC Weight 1 */
296#define REG_DEC_POWER_MEASURE_DURATION_0 0x15C /* Dec Power Measure Duration 0 */
297#define REG_LNA_GAIN 0x15D /* LNA Gain */
298#define REG_CH1_ADC_POWER 0x160 /* CH1 ADC Power */
299#define REG_CH1_RX_FILTER_POWER 0x161 /* CH1 Rx filter Power */
300#define REG_CH2_ADC_POWER 0x162 /* CH2 ADC Power */
301#define REG_CH2_RX_FILTER_POWER 0x163 /* CH2 Rx filter Power */
302#define REG_RX_QUAD_CAL_LEVEL 0x168 /* Rx Quad Cal Level */
303#define REG_CALIBRATION_CONFIG_1 0x169 /* Calibration Config 1 */
304#define REG_CALIBRATION_CONFIG_2 0x16A /* Calibration config2 */
305#define REG_CALIBRATION_CONFIG_3 0x16B /* Calibration config3 */
306#define REG_CALIB_COUNT 0x16C /* Calib count */
307#define REG_SETTLE_COUNT 0x16D /* Settle count */
308#define REG_RX_QUAD_GAIN1 0x16E /* Rx Quad gain1 */
309#define REG_RX_QUAD_GAIN2 0x16F /* Rx Quad gain2 */
310#define REG_RX1_INPUT_A_PHASE_CORR 0x170 /* Rx1 Input A Phase Corr */
311#define REG_RX1_INPUT_A_GAIN_CORR 0x171 /* Rx1 Input A Gain Corr */
312#define REG_RX2_INPUT_A_PHASE_CORR 0x172 /* Rx2 Input A Phase Corr */
313#define REG_RX2_INPUT_A_GAIN_CORR 0x173 /* Rx2 Input A Gain Corr */
314#define REG_RX1_INPUT_A_Q_OFFSET 0x174 /* Rx1 Input A Q" Offset */
315#define REG_RX1_INPUT_A_OFFSETS 0x175 /* Rx1 Input A Offsets */
316#define REG_INPUT_A_OFFSETS_1 0x176 /* Input A Offsets 1 */
317#define REG_RX2_INPUT_A_OFFSETS 0x177 /* Rx2 Input A Offsets */
318#define REG_RX2_INPUT_A_I_OFFSET 0x178 /* Rx2 Input A "I" Offset */
319#define REG_RX1_INPUT_BC_PHASE_CORR 0x179 /* Rx1 Input B&C Phase Corr */
320#define REG_RX1_INPUT_BC_GAIN_CORR 0x17A /* Rx1 Input B&C Gain Corr */
321#define REG_RX2_INPUT_BC_PHASE_CORR 0x17B /* Rx2 Input B&C Phase Corr */
322#define REG_RX2_INPUT_BC_GAIN_CORR 0x17C /* Rx2 Input B&C Gain Corr */
323#define REG_RX1_INPUT_BC_Q_OFFSET 0x17D /* Rx1 Input B&C "Q" Offset */
324#define REG_RX1_INPUT_BC_OFFSETS 0x17E /* Rx1 Input B&C Offsets */
325#define REG_INPUT_BC_OFFSETS_1 0x17F /* Input B&C Offsets 1 */
326#define REG_RX2_INPUT_BC_OFFSETS 0x180 /* Rx2 Input B&C Offsets */
327#define REG_RX2_INPUT_BC_I_OFFSET 0x181 /* Rx2 Input B&C "I" Offset */
328#define REG_FORCE_BITS 0x182 /* Force Bits */
329#define REG_WAIT_COUNT 0x185 /* Wait Count */
330#define REG_RF_DC_OFFSET_COUNT 0x186 /* RF DC Offset Count */
331#define REG_RF_DC_OFFSET_CONFIG_1 0x187 /* RF DC Offset Config1 */
332#define REG_RF_DC_OFFSET_ATTEN 0x188 /* RF DC Offset Attenuation */
333#define REG_INVERT_BITS 0x189 /* Invert Bits */
334#define REG_DC_OFFSET_CONFIG2 0x18B /* DC Offset Config2 */
335#define REG_RF_CAL_GAIN_INDEX 0x18C /* RF Cal Gain Index */
336#define REG_SOI_THRESH 0x18D /* SOI Threshold */
337#define REG_BB_DC_OFFSET_SHIFT 0x190 /* BB DC Offset Shift */
338#define REG_BB_DC_OFFSET_FAST_SETTLE_SHIFT 0x191 /* BB DC Offset Fast Settle Shift */
339#define REG_BB_FAST_SETTLE_DUR 0x192 /* BB Fast Settle Dur */
340#define REG_BB_DC_OFFSET_COUNT 0x193 /* BB DC Offset Count */
341#define REG_BB_DC_OFFSET_ATTEN 0x194 /* BB DC Offset Attenuation */
342#define REG_RX1_BB_DC_WORD_I_MSB 0x19A /* RX1 BB DC word I MSB */
343#define REG_RX1_BB_DC_WORD_I_LSB 0x19B /* RX1 BB DC word I LSB */
344#define REG_RX1_BB_DC_WORD_Q_MSB 0x19C /* RX1 BB DC word Q MSB */
345#define REG_RX1_BB_DC_WORD_Q_LSB 0x19D /* RX1 BB DC word Q LSB */
346#define REG_RX2_BB_DC_WORD_I_MSB 0x19E /* RX2 BB DC word I MSB */
347#define REG_RX2_BB_DC_WORD_I_LSB 0x19F /* RX2 BB DC word I LSB */
348#define REG_RX2_BB_DC_WORD_Q_MSB 0x1A0 /* RX2 BB DC word Q MSB */
349#define REG_RX2_BB_DC_WORD_Q_LSB 0x1A1 /* RX2 BB DC word Q LSB */
350#define REG_BB_TRACK_CORR_WORD_I_MSB 0x1A2 /* BB Track corr word I MSB */
351#define REG_BB_TRACK_CORR_WORD_I_LSB 0x1A3 /* BB Track corr word I LSB */
352#define REG_BB_TRACK_CORR_WORD_Q_MSB 0x1A4 /* BB Track corr word Q MSB */
353#define REG_BB_TRACK_CORR_WORD_Q_LSB 0x1A5 /* BB Track corr word Q LSB */
354#define REG_RX1_RSSI_SYMBOL 0x1A7 /* Rx1 RSSI Symbol */
355#define REG_RX1_RSSI_PREAMBLE 0x1A8 /* Rx1 RSSI preamble */
356#define REG_RX2_RSSI_SYMBOL 0x1A9 /* Rx2 RSSI symbol */
357#define REG_RX2_RSSI_PREAMBLE 0x1AA /* Rx2 RSSI preamble */
358#define REG_SYMBOL_LSB 0x1AB /* Symbol LSB */
359#define REG_PREAMBLE_LSB 0x1AC /* Preamble LSB */
360#define REG_RX_PATH_GAIN_MSB 0x1AD /* Rx Path Gain */
361#define REG_RX_PATH_GAIN_LSB 0x1AE /* Rx Path Gain */
362#define REG_RX_DIFF_LNA_FORCE 0x1B0 /* Rx Diff LNA Force */
363#define REG_RX_LNA_BIAS_COARSE 0x1B1 /* Rx LNA Bias Coarse */
364#define REG_RX_LNA_BIAS_FINE_0 0x1B2 /* Rx LNA Bias Fine 0 */
365#define REG_RX_LNA_BIAS_FINE_1 0x1B3 /* Rx LNA Bias Fine 1 */
366#define REG_RX_MIX_GM_CONFIG 0x1C0 /* Rx Mix Gm Config */
367#define REG_RX1_MIX_GM_FORCE 0x1C1 /* Rx1 Mix Gm Force */
368#define REG_RX1_MIX_GM_BIAS_FORCE 0x1C2 /* Rx1 Mix Gm Bias (Force) */
369#define REG_RX2_MIX_GM_FORCE 0x1C3 /* Rx2 Mix Gm Force */
370#define REG_RX2_MIX_GM_BIAS_FORCE 0x1C4 /* Rx2 Mix Gm Bias (Force) */
371#define REG_INPUT_A_MSBS 0x1C8 /* Input A MSBs */
372#define REG_INPUT_A_RX1_I 0x1C9 /* Input A RX1 I */
373#define REG_INPUT_A_RX1_Q 0x1CA /* Input A RX1 Q */
374#define REG_INPUT_A_RX2_I 0x1CB /* Input A RX2 I */
375#define REG_INPUT_A_RX2_Q 0x1CC /* Input A RX2 Q */
376#define REG_INPUTS_BC_RX1_I 0x1CD /* Inputs B&C RX1 I */
377#define REG_BAND1_RX1_Q 0x1CE /* Band1 RX1 Q */
378#define REG_INPUTS_BC_RX2_I 0x1CF /* Inputs B&C RX2 I */
379#define REG_INPUTS_BC_RX2_Q 0x1D0 /* Inputs B&C RX2 Q */
380#define REG_INPUTS_BC_MSBS 0x1D1 /* Inputs B&C MSBs */
381#define REG_FORCE_OS_DAC 0x1D2 /* Force OS DAC */
382#define REG_RX_MIX_LO_CM 0x1D5 /* Rx Mix LO CM */
383#define REG_RX_CGB_SEG_ENABLE 0x1D6 /* Rx CGB Seg Enable */
384#define REG_RX_MIX_INPUTBIAS 0x1D7 /* Rx Mix Input/Bias */
385#define REG_RX_TIA_CONFIG 0x1DB /* Rx TIA Config */
386#define REG_TIA1_C_LSB 0x1DC /* TIA1 C LSB */
387#define REG_TIA1_C_MSB 0x1DD /* TIA1 C MSB */
388#define REG_TIA2_C_LSB 0x1DE /* TIA2 C LSB */
389#define REG_TIA2_C_MSB 0x1DF /* TIA2 C MSB */
390#define REG_RX1_BBF_R1A 0x1E0 /* Rx1 BBF R1A */
391#define REG_RX2_BBF_R1A 0x1E1 /* Rx2 BBF R1A */
392#define REG_RX1_TUNE_CTRL 0x1E2 /* Rx1 Tune Control */
393#define REG_RX2_TUNE_CTRL 0x1E3 /* Rx2 Tune Control */
394#define REG_RX1_BBF_R5 0x1E4 /* Rx1 BBF R5 */
395#define REG_RX2_BBF_R5 0x1E5 /* Rx2 BBF R5 */
396#define REG_RX_BBF_R2346 0x1E6 /* Rx BBF R2346 */
397#define REG_RX_BBF_C1_MSB 0x1E7 /* Rx BBF C1 MSB */
398#define REG_RX_BBF_C1_LSB 0x1E8 /* Rx BBF C1 LSB */
399#define REG_RX_BBF_C2_MSB 0x1E9 /* Rx BBF C2 MSB */
400#define REG_RX_BBF_C2_LSB 0x1EA /* Rx BBF C2 LSB */
401#define REG_RX_BBF_C3_MSB 0x1EB /* Rx BBF C3 MSB */
402#define REG_RX_BBF_C3_LSB 0x1EC /* Rx BBF C3 LSB */
403#define REG_RX_BBF_CC1_CTR 0x1ED /* Rx BBF CC1 Ctr */
404#define REG_RX_BBF_POW_RZ_BYTE0 0x1EE /* Rx BBF Pow Rz Byte0 */
405#define REG_RX_BBF_CC2_CTR 0x1EF /* Rx BBF CC2 Ctr */
406#define REG_RX_BBF_POW_RZ_BYTE1 0x1F0 /* Rx BBF Pow Rz Byte1 */
407#define REG_RX_BBF_CC3_CTR 0x1F1 /* Rx BBF CC3 Ctr */
408#define REG_RX_BBF_R5_TUNE 0x1F2 /* Rx BBF R5 Tune */
409#define REG_RX_BBF_TUNE 0x1F3 /* Rx BBF Tune */
410#define REG_RX1_BBF_MAN_GAIN 0x1F4 /* Rx1 BBF Man Gain */
411#define REG_RX2_BBF_MAN_GAIN 0x1F5 /* Rx2 BBF Man Gain */
412#define REG_RX_BBF_TUNE_DIVIDE 0x1F8 /* RX BBF Tune Divide */
413#define REG_RX_BBF_TUNE_CONFIG 0x1F9 /* RX BBF Tune Config */
414#define REG_POLE_GAIN 0x1FA /* Pole gain */
415#define REG_RX_BBBW_MHZ 0x1FB /* Rx BBBW MHz */
416#define REG_RX_BBBW_KHZ 0x1FC /* Rx BBBW kHz */
417#define REG_FB_DAC_CLK_DELAY1 0x201 /* FB DAC Clk Delay1 */
418#define REG_FB_DAC_CLK_DELAY2 0x202 /* FB DAC Clk Delay2 */
419#define REG_FLASH_SAMPLE_CLK_DELAY_3P 0x203 /* Flash Sample Clk Delay 3p */
420#define REG_FLASH_SAMPLE_CLK_DELAY_3N 0x204 /* Flash Sample Clk Delay 3n */
421#define REG_TEST_MUX_2I 0x205 /* Test MUX 2i */
422#define REG_TEST_MUX_2Q 0x206 /* Test MUX 2q */
423#define REG_INTEGRATOR_1_RESISTANCE 0x207 /* Integrator 1 Resistance */
424#define REG_INTEGRATOR_1_CAPACITANCE 0x208 /* Integrator 1 Capacitance */
425#define REG_INTEGRATOR_23_RESISTANCE 0x209 /* Integrator 23 Resistance */
426#define REG_INTEGRATOR_2_RESISTANCE 0x20A /* Integrator 2 Resistance */
427#define REG_INTEGRATOR_2_CAPACITANCE 0x20B /* Integrator 2 Capacitance */
428#define REG_INTEGRATOR_3_RESISTANCE 0x20C /* Integrator 3 Resistance */
429#define REG_INTEGRATOR_3_CAPACITANCE 0x20D /* Integrator 3 Capacitance */
430#define REG_INTEGRATOR_AMP_CC 0x20E /* Integrator Amp Cc */
431#define REG_INT_1_FB_DAC_NMOS_CURRENT_SOURCE 0x20F /* Int 1 FB DAC NMOS Current Source */
432#define REG_INT_1_FB_DAC_NMOS_CASOADE_BIAS_CURRENT 0x210 /* Int 1 FB DAC NMOS Casoade Bias Current */
433#define REG_INT_1_FB_DAC_PMOS_CURRENT_SOURCE 0x211 /* Int 1 FB DAC PMOS Current Source */
434#define REG_INT_2_FB_DAC_NMOS_CURRENT_SOURCE 0x212 /* Int 2 FB DAC NMOS Current Source */
435#define REG_INT_2_FB_DAC_NMOS_CASCODE_BIAS_CURRENT 0x213 /* Int 2 FB DAC NMOS Cascode Bias Current */
436#define REG_INT_2_FB_DAC_PMOS_CURRENT_SOURCE 0x214 /* Int 2 FB DAC PMOS Current Source */
437#define REG_INT_3_FB_DAC_NMOS_CURRENT_SOURCE 0x215 /* Int 3 FB DAC NMOS Current Source */
438#define REG_INT_3_FB_DAC_NMOS_CASCODE_BIAS_CURRENT 0x216 /* Int 3 FB DAC NMOS Cascode Bias Current */
439#define REG_INT_3_FB_DAC_PMOS_CURRENT_SOURCE 0x217 /* Int 3 FB DAC PMOS Current Source */
440#define REG_FB_DAC_BIAS_CURRENT 0x218 /* FB DAC Bias Current */
441#define REG_INT_1_1ST_STAGE_CURRENT 0x219 /* Int 1 1st Stage Current */
442#define REG_INT_1_1ST_STAGE_CASCODE_CURRENT 0x21A /* Int 1 1st Stage Cascode Current */
443#define REG_INT_1_2ND_STAGE_CURRENT 0x21B /* Int 1 2nd Stage Current */
444#define REG_INTEGRATOR_2_1ST_STAGE_CURRENT 0x21C /* Integrator 2 1st Stage Current */
445#define REG_INT_2_1ST_STAGE_CASCODE_CURRENT 0x21D /* Int 2 1st Stage Cascode Current */
446#define REG_INT_2_2ND_STAGE_CURRENT 0x21E /* Int 2 2nd Stage Current */
447#define REG_INT_3_1ST_STAGE_CURRENT 0x21F /* Int 3 1st Stage Current */
448#define REG_INT_3_1ST_STAGE_CASCODE_CURRENT 0x220 /* Int 3 1st Stage Cascode Current */
449#define REG_INT_3_2ND_STAGE_CURRENT 0x221 /* Int 3 2nd Stage Current */
450#define REG_FLASH_BIAS_CURRENT 0x222 /* Flash Bias Current */
451#define REG_FLASH_LADDER_BIAS 0x223 /* Flash Ladder Bias */
452#define REG_FLASH_LADDER_CASCODE_CURRENT 0x224 /* Flash Ladder Cascode Current */
453#define REG_FLASH_LADDER_BIAS2 0x225 /* Flash Ladder Bias2 */
454#define REG_RESET 0x226 /* Reset */
455#define REG_RX_PFD_CONFIG 0x230 /* RX PFD Config */
456#define REG_RX_INTEGER_BYTE_0 0x231 /* RX Integer Byte 0 */
457#define REG_RX_INTEGER_BYTE_1 0x232 /* RX Integer Byte 1 */
458#define REG_RX_FRACT_BYTE_0 0x233 /* RX Fractional Byte 0 */
459#define REG_RX_FRACT_BYTE_1 0x234 /* RX Fractional Byte 1 */
460#define REG_RX_FRACT_BYTE_2 0x235 /* RX Fractional Byte 2 */
461#define REG_RX_FORCE_ALC 0x236 /* RX Force ALC */
462#define REG_RX_FORCE_VCO_TUNE_0 0x237 /* RX Force VCO Tune 0 */
463#define REG_RX_FORCE_VCO_TUNE_1 0x238 /* RX Force VCO Tune 1 */
464#define REG_RX_ALC_VARACTOR 0x239 /* RX ALC/Varactor */
465#define REG_RX_VCO_OUTPUT 0x23A /* RX VCO Output */
466#define REG_RX_CP_CURRENT 0x23B /* RX CP Current */
467#define REG_RX_CP_OFFSET 0x23C /* RX CP Offset */
468#define REG_RX_CP_CONFIG 0x23D /* RX CP Config */
469#define REG_RX_LOOP_FILTER_1 0x23E /* RX Loop Filter 1 */
470#define REG_RX_LOOP_FILTER_2 0x23F /* RX Loop Filter 2 */
471#define REG_RX_LOOP_FILTER_3 0x240 /* RX Loop Filter 3 */
472#define REG_RX_DITHERCP_CAL 0x241 /* RX Dither/CP Cal */
473#define REG_RX_VCO_BIAS_1 0x242 /* RX VCO Bias 1 */
474#define REG_RX_CAL_STATUS 0x244 /* RX Cal Status */
475#define REG_RX_VCO_CAL_REF 0x245 /* RX VCO Cal Ref */
476#define REG_RX_VCO_PD_OVERRIDES 0x246 /* RX VCO Pd Overrides */
477#define REG_RX_CP_OVERRANGE_VCO_LOCK 0x247 /* RX CP Over Range/VCO Lock */
478#define REG_RX_VCO_LDO 0x248 /* RX VCO LDO */
479#define REG_RX_VCO_CAL 0x249 /* RX VCO Cal */
480#define REG_RX_LOCK_DETECT_CONFIG 0x24A /* RX Lock Detect Config */
481#define REG_RX_CP_LEVEL_DETECT 0x24B /* RX CP Level Detect */
482#define REG_RX_DSM_SETUP_0 0x24C /* RX DSM Setup 0 */
483#define REG_RX_DSM_SETUP_1 0x24D /* RX DSM Setup 1 */
484#define REG_RX_CORRECTION_WORD0 0x24E /* RX Correction Word0 */
485#define REG_RX_CORRECTION_WORD1 0x24F /* RX Correction Word1 */
486#define REG_RX_VCO_VARACTOR_CTRL_0 0x250 /* RX VCO Varactor Control 0 */
487#define REG_RX_VCO_VARACTOR_CTRL_1 0x251 /* RX VCO Varactor Control 1 */
488#define REG_RX_FAST_LOCK_SETUP 0x25A /* Rx Fast Lock Setup */
489#define REG_RX_FAST_LOCK_SETUP_INIT_DELAY 0x25B /* Rx Fast Lock Setup Init Delay */
490#define REG_RX_FAST_LOCK_PROGRAM_ADDR 0x25C /* Rx Fast Lock Program Addr */
491#define REG_RX_FAST_LOCK_PROGRAM_DATA 0x25D /* Rx Fast Lock Program Data */
492#define REG_RX_FAST_LOCK_PROGRAM_READ 0x25E /* Rx Fast Lock Program Read */
493#define REG_RX_FAST_LOCK_PROGRAM_CTRL 0x25F /* Rx Fast Lock Program Control */
494#define REG_RX_LO_GEN_POWER_MODE 0x261 /* Rx LO Gen Power Mode */
495#define REG_TX_PFD_CONFIG 0x270 /* TX PFD Config */
496#define REG_TX_INTEGER_BYTE_0 0x271 /* TX Integer Byte 0 */
497#define REG_TX_INTEGER_BYTE_1 0x272 /* TX Integer Byte 1 */
498#define REG_TX_FRACT_BYTE_0 0x273 /* TX Fractional Byte 0 */
499#define REG_TX_FRACT_BYTE_1 0x274 /* TX Fractional Byte 1 */
500#define REG_TX_FRACT_BYTE_2 0x275 /* TX Fractional Byte 2 */
501#define REG_TX_FORCE_ALC 0x276 /* TX Force ALC */
502#define REG_TX_FORCE_VCO_TUNE_0 0x277 /* TX Force VCO Tune 0 */
503#define REG_TX_FORCE_VCO_TUNE_1 0x278 /* TX Force VCO Tune 1 */
504#define REG_TX_ALCVARACT_OR 0x279 /* TX ALC/Varact or */
505#define REG_TX_VCO_OUTPUT 0x27A /* TX VCO Output */
506#define REG_TX_CP_CURRENT 0x27B /* TX CP Current */
507#define REG_TX_CP_OFFSET 0x27C /* TX CP Offset */
508#define REG_TX_CP_CONFIG 0x27D /* TX CP Config */
509#define REG_TX_LOOP_FILTER_1 0x27E /* TX Loop Filter 1 */
510#define REG_TX_LOOP_FILTER_2 0x27F /* TX Loop Filter 2 */
511#define REG_TX_LOOP_FILTER_3 0x280 /* TX Loop Filter 3 */
512#define REG_TX_DITHERCP_CAL 0x281 /* TX Dither/CP Cal */
513#define REG_TX_VCO_BIAS_1 0x282 /* TX VCO Bias 1 */
514#define REG_TX_VCO_BIAS_2 0x283 /* TX VCO Bias 2 */
515#define REG_TX_CAL_STATUS 0x284 /* TX Cal Status */
516#define REG_TX_VCO_CAL_REF 0x285 /* TX VCO Cal Ref */
517#define REG_TX_VCO_PD_OVERRIDES 0x286 /* TX VCO Pd Overrides */
518#define REG_TX_CP_OVERRANGE_VCO_LOCK 0x287 /* TX CP Over Range/VCO Lock */
519#define REG_TX_VCO_LDO 0x288 /* TX VCO LDO */
520#define REG_TX_VCO_CAL 0x289 /* TX VCO Cal */
521#define REG_TX_LOCK_DETECT_CONFIG 0x28A /* TX Lock Detect Config */
522#define REG_TX_CP_LEVEL_DETECT 0x28B /* TX CP Level Detect */
523#define REG_TX_DSM_SETUP_0 0x28C /* TX DSM Setup 0 */
524#define REG_TX_DSM_SETUP_1 0x28D /* TX DSM Setup 1 */
525#define REG_TX_CORRECTION_WORD0 0x28E /* TX Correction Word0 */
526#define REG_TX_CORRECTION_WORD1 0x28F /* TX Correction Word1 */
527#define REG_TX_VCO_VARACTOR_CTRL_0 0x290 /* TX VCO Varactor Control 0 */
528#define REG_TX_VCO_VARACTOR_CTRL_1 0x291 /* TX VCO Varactor Control 1 */
529#define REG_DCXO_COARSE_TUNE 0x292 /* DCXO Coarse Tune */
530#define REG_DCXO_FINE_TUNE_HIGH 0x293 /* DCXO Fine Tune2 */
531#define REG_DCXO_FINE_TUNE_LOW 0x294 /* DCXO Fine Tune1 */
532#define REG_DCXO_CONFIG 0x295 /* DCXO Config */
533#define REG_DCXO_TEMPCO_WRITE 0x296 /* DCXO Tempco Write */
534#define REG_DCXO_TEMPCO_READ 0x297 /* DCXO Tempco Read */
535#define REG_DCXO_TEMPCO_ADDR 0x298 /* DCXO Tempco Addr */
536#define REG_DELTA_T_READ 0x299 /* Delta T Read */
537#define REG_TX_FAST_LOCK_SETUP 0x29A /* Tx Fast Lock Setup */
538#define REG_TX_FAST_LOCK_SETUP_INIT_DELAY 0x29B /* Tx Fast Lock Setup Init Delay */
539#define REG_TX_FAST_LOCK_PROGRAM_ADDR 0x29C /* Tx Fast Lock Program Addr */
540#define REG_TX_FAST_LOCK_PROGRAM_DATA 0x29D /* Tx Fast Lock Program Data */
541#define REG_TX_FAST_LOCK_PROGRAM_READ 0x29E /* Tx Fast Lock Program Read */
542#define REG_TX_FAST_LOCK_PROGRAM_CTRL 0x29F /* Tx Fast Lock Program Ctrl */
543#define REG_TX_LO_GEN_POWER_MODE 0x2A1 /* Tx LO Gen Power Mode */
544#define REG_BANDGAP_CONFIG0 0x2A6 /* Bandgap Config0 */
545#define REG_BANDGAP_CONFIG1 0x2A8 /* Bandgap Config1 */
546#define REG_REF_DIVIDE_CONFIG_1 0x2AB /* Ref Divide Config 1 */
547#define REG_REF_DIVIDE_CONFIG_2 0x2AC /* Ref Divide Config 2 */
548#define REG_GAIN_RX1 0x2B0 /* Gain Rx1 */
549#define REG_LPF_GAIN_RX1 0x2B1 /* LPF Gain Rx1 */
550#define REG_DIG_GAIN_RX1 0x2B2 /* Dig gain Rx1 */
551#define REG_FAST_ATTACK_STATE 0x2B3 /* Fast Attack State */
552#define REG_SLOW_LOOP_STATE 0x2B4 /* Slow Loop State */
553#define REG_GAIN_RX2 0x2B5 /* Gain Rx2 */
554#define REG_LPF_GAIN_RX2 0x2B6 /* LPF Gain Rx2 */
555#define REG_DIG_GAIN_RX2 0x2B7 /* Dig Gain Rx2 */
556#define REG_OVRG_SIGS_RX1 0x2B8 /* Ovrg Sigs Rx1 */
557#define REG_OVRG_SIGS_RX2 0x2B9 /* Ovrg Sigs Rx2 */
558#define REG_CTRL 0x3DF /* Control */
559#define REG_BIST_CONFIG 0x3F4 /* BIST Config */
560#define REG_OBSERVE_CONFIG 0x3F5 /* Observe Config */
561#define REG_BIST_AND_DATA_PORT_TEST_CONFIG 0x3F6 /* BIST and Data Port Test Config */
562#define REG_DAC_TEST_0 0x3FC /* DAC Test 0 */
563#define REG_DAC_TEST_1 0x3FD /* DAC Test 1 */
564#define REG_DAC_TEST_2 0x3FE /* DAC Test 2 */
565
566/*
567* REG_SPI_CONF
568*/
569#define SOFT_RESET (1 << 7) /* Soft Reset */
570#define WIRE3_SPI (1 << 6) /* 3-Wire SPI */
571#define LSB_FIRST (1 << 5) /* LSB First */
572#define _LSB_FIRST (1 << 2) /* LSB First */
573#define _WIRE3_SPI (1 << 1) /* 3-Wire SPI */
574#define _SOFT_RESET (1 << 0) /* Soft reset */
575
576/*
577* REG_MULTICHIP_SYNC_AND_TX_MON_CTRL
578*/
579#define TX2_MONITOR_ENABLE (1 << 6) /* Tx2 Monitor Enable */
580#define TX1_MONITOR_ENABLE (1 << 5) /* Tx1 Monitor Enable */
581#define MCS_RF_ENABLE (1 << 3) /* MCS RF Enable */
582#define MCS_BBPLL_ENABLE (1 << 2) /* MCS BBPLL enable */
583#define MCS_DIGITAL_CLK_ENABLE (1 << 1) /* MCS Digital CLK Enable */
584#define MCS_BB_ENABLE (1 << 0) /* MCS BB Enable */
585
586/*
587* REG_TX_ENABLE_FILTER_CTRL
588*/
589#define THB2_EN (1 << 3) /* THB2 Enable */
590#define THB1_EN (1 << 2) /* THB1 Enable */
591#define TX_CHANNEL_ENABLE(x) (((x) & 0x3) << 6) /* Tx channel Enable<1:0> */
592#define THB3_ENABLE_INTERP(x) (((x) & 0x3) << 4) /* THB3 Enable & Interp<1:0> */
593#define TX_FIR_ENABLE_INTERPOLATION(x) (((x) & 0x3) << 0) /* Tx FIR Enable & Interpolation<1:0> */
594#define TX_1 1
595#define TX_2 2
596#define TX_ENABLE 1
597#define TX_DISABLE 0
598
599/*
600* REG_RX_ENABLE_FILTER_CTRL
601*/
602#define RHB2_EN (1 << 3) /* RHB2 Enable */
603#define RHB1_EN (1 << 2) /* RHB1 Enable */
604#define RX_CHANNEL_ENABLE(x) (((x) & 0x3) << 6) /* Rx channel Enable<1:0> */
605#define DEC3_ENABLE_DECIMATION(x) (((x) & 0x3) << 4) /* DEC3 Enable & Decimation<1:0> */
606#define RX_FIR_ENABLE_DECIMATION(x) (((x) & 0x3) << 0) /* Rx FIR Enable & Decimation<1:0> */
607#define RX_1 1
608#define RX_2 2
609#define RX_ENABLE 1
610#define RX_DISABLE 0
611
612/*
613* REG_INPUT_SELECT
614*/
615#define TX_OUTPUT (1 << 6) /* TX Output */
616#define RX_INPUT(x) (((x) & 0x3F) << 0) /* RX Input <5:0> */
617
618/*
619* REG_RFPLL_DIVIDERS
620*/
621#define TX_VCO_DIVIDER(x) (((x) & 0xF) << 4) /* TX VCO Divider<3:0> */
622#define RX_VCO_DIVIDER(x) (((x) & 0xF) << 0) /* RX VCO Divider<3:0> */
623
624/*
625* REG_RX_CLOCK_DATA_DELAY
626*/
627#define DATA_CLK_DELAY(x) (((x) & 0xF) << 4) /* DATA_CLK Delay<3:0> */
628#define RX_DATA_DELAY(x) (((x) & 0xF) << 0) /* Rx Data Delay <3:0> */
629
630/*
631* REG_TX_CLOCK_DATA_DELAY
632*/
633#define FB_CLK_DELAY(x) (((x) & 0xF) << 4) /* FB_CLK Delay<3:0> */
634#define TX_DATA_DELAY(x) (((x) & 0xF) << 0) /* Tx Data Delay <3:0> */
635
636/*
637* REG_CLOCK_ENABLE
638*/
639#define XO_BYPASS (1 << 4) /* XO Bypass */
640#define DIGITAL_POWER_UP (1 << 2) /* Digital Power Up */
641#define CLOCK_ENABLE_DFLT (1 << 1) /* Set to 1 */
642#define BBPLL_ENABLE (1 << 0) /* BBPLL Enable */
643
644/*
645* REG_BBPLL
646*/
647#define CLKOUT_ENABLE (1 << 4) /* CLKOUT Enable */
648#define DAC_CLK_DIV2 (1 << 3) /* DAC Clk div2 */
649#define CLKOUT_SELECT(x) (((x) & 0x7) << 5) /* CLKOUT Select<2:0> */
650#define BBPLL_DIVIDER(x) (((x) & 0x7) << 0) /* BBPLL Divider <2:0> */
651
652/*
653* REG_START_TEMP_READING
654*/
655#define START_TEMP_READING (1 << 0) /* Start Temp Reading */
656
657/*
658* REG_TEMP_SENSE2
659*/
660#define TEMP_SENSE_PERIODIC_ENABLE (1 << 0) /* Temp Sense Periodic Enable */
661#define MEASUREMENT_TIME_INTERVAL(x) (((x) & 0x7F) << 1) /* Measurement Time Interval<6:0> */
662
663/*
664* REG_TEMP_SENSOR_CONFIG
665*/
666#define TEMP_SENSOR_DECIMATION(x) (((x) & 0x7) << 0) /* Temp Sensor Decimation<2:0> */
667
668/*
669* REG_PARALLEL_PORT_CONF_1
670*/
671#define PP_TX_SWAP_IQ (1 << 7) /* PP Tx Swap IQ */
672#define PP_RX_SWAP_IQ (1 << 6) /* PP Rx Swap IQ */
673#define TX_CHANNEL_SWAP (1 << 5) /* Tx Channel swap */
674#define RX_CHANNEL_SWAP (1 << 4) /* Rx Channel swap */
675#define RX_FRAME_PULSE_MODE (1 << 3) /* Rx Frame Pulse Mode */
676#define R2T2_TIMING (1 << 2) /* 2R2T Timing */
677#define INVERT_DATA_BUS (1 << 1) /* Invert data bus */
678#define INVERT_DATA_CLK (1 << 0) /* Invert DATA CLK */
679
680/*
681* REG_PARALLEL_PORT_CONF_2
682*/
683#define FDD_ALT_WORD_ORDER (1 << 7) /* FDD Alt Word Order */
684#define INVERT_RX1 (1 << 6) /* Invert Rx1 */
685#define INVERT_RX2 (1 << 5) /* Invert Rx2 */
686#define INVERT_TX1 (1 << 4) /* Invert Tx1 */
687#define INVERT_TX2 (1 << 3) /* Invert Tx2 */
688#define INVERT_RX_FRAME (1 << 2) /* Invert Rx Frame */
689#define DELAY_RX_DATA(x) (((x) & 0x3) << 0) /* Delay Rx Data<1:0> */
690
691/*
692* REG_PARALLEL_PORT_CONF_3
693*/
694#define FDD_RX_RATE_2TX_RATE (1 << 7) /* FDD Rx Rate = 2*Tx Rate */
695#define SWAP_PORTS (1 << 6) /* Swap Ports */
696#define SINGLE_DATA_RATE (1 << 5) /* Single Data Rate */
697#define LVDS_MODE (1 << 4) /* LVDS Mode */
698#define HALF_DUPLEX_MODE (1 << 3) /* Half Duplex Mode */
699#define SINGLE_PORT_MODE (1 << 2) /* Single Port Mode */
700#define FULL_PORT (1 << 1) /* Full Port */
701#define FULL_DUPLEX_SWAP_BITS (1 << 0) /* Full Duplex Swap Bits */
702
703/*
704* REG_ENSM_MODE
705*/
706#define FDD_MODE (1 << 0) /* FDD Mode */
707
708/*
709* REG_ENSM_CONFIG_1
710*/
711#define ENABLE_RX_DATA_PORT_FOR_CAL (1 << 7) /* Enable Rx Data Port for Cal */
712#define FORCE_RX_ON (1 << 6) /* Force Rx On */
713#define FORCE_TX_ON (1 << 5) /* Force Tx On */
714#define ENABLE_ENSM_PIN_CTRL (1 << 4) /* Enable ENSM Pin Control */
715#define LEVEL_MODE (1 << 3) /* Level Mode */
716#define FORCE_ALERT_STATE (1 << 2) /* Force Alert State */
717#define AUTO_GAIN_LOCK (1 << 1) /* Auto Gain Lock */
718#define TO_ALERT (1 << 0) /* To Alert */
719
720/*
721* REG_ENSM_CONFIG_2
722*/
723#define FDD_EXTERNAL_CTRL_ENABLE (1 << 7) /* FDD External Control Enable */
724#define POWER_DOWN_RX_SYNTH (1 << 6) /* Power Down Rx Synth */
725#define POWER_DOWN_TX_SYNTH (1 << 5) /* Power Down Tx Synth */
726#define TXNRX_SPI_CTRL (1 << 4) /* TXNRX SPI Control */
727#define SYNTH_ENABLE_PIN_CTRL_MODE (1 << 3) /* Synth Enable Pin Control Mode */
728#define DUAL_SYNTH_MODE (1 << 2) /* Dual Synth Mode */
729#define RX_SYNTH_READY_MASK (1 << 1) /* Rx Synth Ready Mask */
730#define TX_SYNTH_READY_MASK (1 << 0) /* Tx Synth Ready Mask */
731
732/*
733* REG_CALIBRATION_CTRL
734*/
735#define RX_BB_TUNE_CAL (1 << 7) /* Rx BB Tune */
736#define TX_BB_TUNE_CAL (1 << 6) /* Tx BB Tune */
737#define RX_QUAD_CAL (1 << 5) /* Rx Quad Cal */
738#define TX_QUAD_CAL (1 << 4) /* Tx Quad Cal */
739#define RX_GAIN_STEP_CAL (1 << 3) /* Rx Gain Step Cal */
740#define TXMON_CAL (1 << 2)
741#define RFDC_CAL (1 << 1) /* DC Cal RF Start */
742#define BBDC_CAL (1 << 0) /* DC cal BB Start */
743
744
745/*
746* REG_STATE
747*/
748#define CALIBRATION_SEQUENCE_STATE(x) (((x) & 0xF) << 4) /* Calibration Sequence State<3:0> */
749#define ENSM_STATE(x) (((x) & 0xF) << 0) /* ENSM State<3:0> */
750#define ENSM_STATE_SLEEP_WAIT 0x0
751#define ENSM_STATE_ALERT 0x5
752#define ENSM_STATE_TX 0x6
753#define ENSM_STATE_TX_FLUSH 0x7
754#define ENSM_STATE_RX 0x8
755#define ENSM_STATE_RX_FLUSH 0x9
756#define ENSM_STATE_FDD 0xA
757#define ENSM_STATE_FDD_FLUSH 0xB
758#define ENSM_STATE_INVALID 0xFF
759#define ENSM_STATE_SLEEP 0x80
760
761/*
762* REG_AUXDAC_2_WORD
763*/
764#define AUXDAC_2_WORD_MSB(x) (((x) & 0x3F) << 2) /* AuxDAC 2 Word<9:2> */
765#define AUXDAC_1_WORD(x) (((x) & 0x3) << 0) /* AuxDAC 1 Word <1:0> */
766
767/*
768* REG_AUXDAC_1_CONFIG
769*/
770#define COMP_CTRL_1 (1 << 5) /* Comp Ctrl 1 */
771#define AUXDAC1_STP_FACTOR (1 << 4) /* AuxDAC1 Step Factor */
772#define AUXDAC_1_VREF(x) (((x) & 0x3) << 2) /* AuxDAC 1 Vref<1:0> */
773#define AUXDAC_1_WORD_LSB(x) (((x) & 0x3) << 0) /* AuxDAC 2 Word <1:0> */
774
775/*
776* REG_AUXDAC_2_CONFIG
777*/
778#define COMP_CTRL_2 (1 << 5) /* Comp Ctrl 2 */
779#define AUXDAC2_STP_FACTOR (1 << 4) /* AuxDAC2 Step Factor */
780#define AUXDAC_2_VREF(x) (((x) & 0xF) << 2) /* AuxDAC 2 Vref<1:0> */
781#define AUXDAC_2_WORD_LSB(x) (((x) & 0x3) << 0) /* AuxDAC 2 Word <1:0> */
782
783/*
784* REG_AUXADC_CLOCK_DIVIDER
785*/
786#define AUXADC_CLOCK_DIVIDER(x) (((x) & 0x3F) << 0) /* AuxADC Clock Divider<5:0> */
787
788/*
789* REG_AUXADC_CONFIG
790*/
791#define AUXADC_POWER_DOWN (1 << 0) /* AuxADC Power Down */
792#define AUX_ADC_DECIMATION(x) (((x) & 0x7) << 1) /* Aux ADC Decimation<2:0> */
793
794/*
795* REG_AUXADC_LSB
796*/
797#define AUXADC_WORD_LSB(x) (((x) & 0xF) << 0) /* AuxADC Word LSB<3:0> */
798
799/*
800* REG_AUTO_GPO
801*/
802#define GPO_ENABLE_AUTO_RX(x) (((x) & 0xF) << 4) /* GPO Enable Auto Rx<3:0> */
803#define GPO_ENABLE_AUTO_TX(x) (((x) & 0xF) << 0) /* GPO Enable Auto Tx<3:0> */
804
805/*
806* REG_AGC_ATTACK_DELAY
807*/
808#define INVERT_BYPASSED_LNA_POLARITY (1 << 6) /* Invert Bypassed LNA Polarity */
809#define AGC_ATTACK_DELAY(x) (((x) & 0x3F) << 0) /* AGC Attack Delay<5:0> */
810
811/*
812* REG_AUXDAC_ENABLE_CTRL
813*/
814#define AUXDAC_MANUAL_BAR(x) (((x) & 0x3) << 6) /* AuxDac Manual Bar<1:0> */
815#define AUXDAC_AUTO_TX_BAR(x) (((x) & 0x3) << 4) /* AuxDAC Auto Tx Bar<1:0> */
816#define AUXDAC_AUTO_RX_BAR(x) (((x) & 0x3) << 2) /* AuxDAC Auto Rx Bar<1:0> */
817#define AUXDAC_INIT_BAR(x) (((x) & 0x3) << 0) /* AuxDAC Init Bar<1:0> */
818
819/*
820* REG_EXTERNAL_LNA_CTRL
821*/
822#define AUXDAC_MANUAL_SELECT (1 << 7) /* AuxDAC Manual Select */
823#define EXTERNAL_LNA2_CTRL (1 << 6) /* External LNA2 control */
824#define EXTERNAL_LNA1_CTRL (1 << 5) /* External LNA1 control */
825#define GPO_MANUAL_SELECT (1 << 4) /* GPO manual select */
826#define OPEN(x) (((x) & 0xF) << 0) /* Open<3:0> */
827
828/*
829* REG_GPO_FORCE_AND_INIT
830*/
831#define GPO_MANUAL_CTRL(x) (((x) & 0xF) << 4) /* GPO Manual Control<3:0> */
832#define GPO_INIT_STATE(x) (((x) & 0xF) << 0) /* GPO Init State<3:0> */
833
834/*
835* REG_CTRL_OUTPUT_ENABLE
836*/
837#define EN_CTRL7 (1 << 7) /* En ctrl7 */
838#define EN_CTRL6 (1 << 6) /* En ctrl6 */
839#define EN_CTRL5 (1 << 5) /* En ctrl5 */
840#define EN_CTRL4 (1 << 4) /* En ctrl4 */
841#define EN_CTRL3 (1 << 3) /* En ctrl3 */
842#define EN_CTRL2 (1 << 2) /* En ctrl2 */
843#define EN_CTRL1 (1 << 1) /* En ctrl1 */
844#define EN_CTRL0 (1 << 0) /* En ctrl0 */
845
846/*
847* REG_PRODUCT_ID
848*/
849#define PRODUCT_ID_MASK 0xF8
850#define PRODUCT_ID_9361 0x08
851#define REV_MASK 0x07
852
853/*
854* REG_REFERENCE_CLOCK_CYCLES
855*/
856#define REFERENCE_CLOCK_CYCLES_PER_US(x) (((x) & 0x7F) << 0) /* Reference Clock Cycles per us<6:0> */
857
858/*
859* REG_DIGITAL_IO_CTRL
860*/
861#define CLK_OUT_DRIVE (1 << 7) /* CLK Out Drive */
862#define DATACLK_DRIVE (1 << 6) /* DATACLK drive */
863#define DATA_PORT_DRIVE (1 << 2) /* Data Port Drive */
864#define DATACLK_SLEW(x) (((x) & 0x3) << 4) /* DATACLK slew <1:0> */
865#define DATA_PORT_SLEW(x) (((x) & 0x3) << 0) /* Data Port Slew<1:0> */
866
867/*
868* REG_LVDS_BIAS_CTRL
869*/
870#define RX_ON_CHIP_TERM (1 << 5) /* Rx On Chip Term */
871#define LVDS_BYPASS_BIAS_R (1 << 4) /* Bypass Bias R */
872#define LVDS_TX_LO_VCM (1 << 3) /* LVDS Tx LO VCM */
873#define CLK_OUT_SLEW(x) (((x) & 0x3) << 6) /* CLK Out Slew<1:0> */
874#define LVDS_BIAS(x) (((x) & 0x7) << 0) /* LVDS Bias <2:0> */
875
876/*
877* REG_SDM_CTRL_1
878*/
879#define INIT_BB_FO_CAL (1 << 2) /* Init BB FO CAL */
880#define BBPLL_RESET_BAR (1 << 0) /* BBPLL Reset Bar */
881
882/*
883* REG_CLOCK_CTRL
884*/
885#define REF_FREQ_SCALER(x) (((x) & 0x3) << 0) /* Ref Frequency Scaler */
886
887/*
888* REG_CP_CURRENT
889*/
890#define CHARGE_PUMP_CURRENT(x) (((x) & 0x3F) << 0) /* Charge Pump Current<5:0> */
891
892/*
893* REG_CP_BLEED_CURRENT
894*/
895#define MCS_REFCLK_SCALE_EN (1 << 7) /* MCS refclk Scale En */
896
897/*
898* REG_LOOP_FILTER_1
899*/
900#define C1_WORD(x) (((x) & 0x7) << 5) /* C1 Word<2:0> */
901#define R1_WORD(x) (((x) & 0x1F) << 0) /* R1 Word<4:0> */
902
903/*
904* REG_LOOP_FILTER_2
905*/
906#define R2_WORD (1 << 7) /* R2 Word<0> */
907#define C2_WORD(x) (((x) & 0x1F) << 2) /* C2 Word<4:0> */
908#define C1_WORD_LSB(x) (((x) & 0x3) << 0) /* C1 Word<4:3> */
909
910/*
911* REG_LOOP_FILTER_3
912*/
913#define BYPASS_C3 (1 << 7) /* Bypass C3 */
914#define BYPASS_R2 (1 << 6) /* Bypass R2 */
915#define C3_WORD(x) (((x) & 0xF) << 2) /* C3 Word<3:0> */
916#define R2_WORD_LSB(x) (((x) & 0x3) << 0) /* R2 Word<2:1> */
917
918/*
919* REG_VCO_CTRL
920*/
921#define FREQ_CAL_ENABLE (1 << 7) /* Freq Cal Enable */
922#define FREQ_CAL_RESET (1 << 4) /* Freq Cal Reset */
923#define FREQ_CAL_COUNT_LENGTH(x) (((x) & 0x3) << 5) /* Freq Cal Count Length<1:0> */
924
925/*
926* REG_SDM_CTRL
927*/
928#define CAL_CLOCK_DIV_4 (1 << 4) /* Cal Clock div 4 */
929
930/*
931* REG_RX_SYNTH_POWER_DOWN_OVERRIDE
932*/
933#define RX_LO_POWER_DOWN (1 << 4) /* Rx LO Power Down */
934#define RX_SYNTH_VCO_ALC_POWER_DOWN (1 << 3) /* Rx Synth VCO ALC Power Down */
935#define RX_SYNTH_PTAT_POWER_DOWN (1 << 2) /* Rx Synth PTAT Power Down */
936#define RX_SYNTH_VCO_POWER_DOWN (1 << 1) /* Rx Synth VCO Power Down */
937#define RX_SYNTH_VCO_LDO_POWER_DOWN (1 << 0) /* Rx Synth VCO LDO Power Down */
938
939/*
940* REG_TX_SYNTH_POWER_DOWN_OVERRIDE
941*/
942#define TX_LO_POWER_DOWN (1 << 4) /* Tx LO Power Down */
943#define TX_SYNTH_VCO_ALC_POWER_DOWN (1 << 3) /* Tx Synth VCO ALC Power Down */
944#define TX_SYNTH_PTAT_POWER_DOWN (1 << 2) /* Tx Synth PTAT Power Down */
945#define TX_SYNTH_VCO_POWER_DOWN (1 << 1) /* Tx Synth VCO Power Down */
946#define TX_SYNTH_VCO_LDO_POWER_DOWN (1 << 0) /* Tx Synth VCO LDO Power Down */
947
948/*
949* REG_RX_ANALOG_POWER_DOWN_OVERRIDE_1
950*/
951#define RX_OFFSET_DAC_CGIN_POWER_DOWN(x) (((x) & 0x3) << 6) /* Rx Offset DAC CGin Power Down<1:0> */
952#define RX_LMT_OVERLOAD_POWER_DOWN(x) (((x) & 0x3) << 4) /* Rx LMT Overload Power Down<1:0> */
953#define RX_MIXER_GM_POWER_DOWN(x) (((x) & 0x3) << 2) /* Rx Mixer Gm Power Down<1:0> */
954#define RX_CGB_POWER_DOWN(x) (((x) & 0x3) << 0) /* Rx CGB Power Down<1:0> */
955
956/*
957* REG_RX_ANALOG_POWER_DOWN_OVERRIDE_2
958*/
959#define RX_BBF_POWER_DOWN(x) (((x) & 0x3) << 6) /* Rx BBF Power Down<1:0> */
960#define RX_TIA_POWER_DOWN(x) (((x) & 0x3) << 4) /* Rx TIA Power Down<1:0> */
961#define RX_MIXER_POWER_DOWN(x) (((x) & 0x3) << 2) /* Rx Mixer Power Down<1:0> */
962#define RX_OFFSET_DAC_CGOUT_POWER_DOWN(x) (((x) & 0x3) << 0) /* Rx Offset DAC CGOut Power Down<1:0> */
963
964/*
965* REG_TX_ANALOG_POWER_DOWN_OVERRIDE_1
966*/
967#define TX_SECONDARY_FILTER_POWER_DOWN(x) (((x) & 0x3) << 6) /* Tx Secondary Filter Power Down<1:0> */
968#define TX_BBF_POWER_DOWN(x) (((x) & 0x3) << 4) /* Tx BBF Power Down<1:0> */
969#define TX_DAC_POWER_DOWN(x) (((x) & 0x3) << 2) /* Tx DAC Power Down<1:0> */
970#define TX_DAC_BIAS_POWER_DOWN(x) (((x) & 0x3) << 0) /* Tx DAC Bias Power Down<1:0> */
971
972/*
973* REG_ANALOG_POWER_DOWN_OVERRIDE
974*/
975#define RX_EXT_VCO_BUFFER_POWER_DOWN (1 << 5) /* Rx Ext VCO Buffer Power Down */
976#define TX_EXT_VCO_BUFFER_POWER_DOWN (1 << 4) /* Tx Ext VCO Buffer Power Down */
977#define TX_MONITOR_POWER_DOWN(x) (((x) & 0x3) << 2) /* Tx Monitor Power Down<1:0> */
978#define TX_UPCONVERTER_POWER_DOWN(x) (((x) & 0x3) << 0) /* Tx Upconverter Power Down<1:0> */
979
980/*
981* REG_MISC_POWER_DOWN_OVERRIDE
982*/
983#define RX_LNA_POWER_DOWN (1 << 6) /* Rx LNA Power Down */
984#define DCXO_POWER_DOWN (1 << 1) /* DCXO Power Down */
985#define MASTER_BIAS_POWER_DOWN (1 << 0) /* Master Bias Power Down */
986#define RX_CALIBRATION_POWER_DOWN(x) (((x) & 0x3) << 2) /* Rx Calibration Power Down<1:0> */
987
988/*
989* REG_CH_1_OVERFLOW
990*/
991#define BBPLL_LOCK (1 << 7) /* BBPLL Lock */
992#define CH_1_INT3 (1 << 6) /* CH 1 INT3 */
993#define CH1_HB3 (1 << 5) /* CH1 HB3 */
994#define CH1_HB2 (1 << 4) /* CH1 HB2 */
995#define CH1_QEC (1 << 3) /* CH1 QEC */
996#define CH1_HB1 (1 << 2) /* CH1 HB1 */
997#define CH1_TFIR (1 << 1) /* CH1 TFIR */
998#define CH1_RFIR (1 << 0) /* CH1 RFIR */
999
1000/*
1001* REG_CH_2_OVERFLOW
1002*/
1003#define CH2_INT3 (1 << 6) /* CH2 INT3 */
1004#define CH2_HB3 (1 << 5) /* CH2 HB3 */
1005#define CH2_HB2 (1 << 4) /* CH2 HB2 */
1006#define CH2_QEC (1 << 3) /* CH2 QEC */
1007#define CH2_HB1 (1 << 2) /* CH2 HB1 */
1008#define CH2_TFIR (1 << 1) /* CH2 TFIR */
1009#define CH2_RFIR (1 << 0) /* CH2 RFIR */
1010
1011/*
1012* REG_TX_FILTER_CONF
1013*/
1014#define TX_FIR_GAIN_6DB (1 << 0) /* Filter Gain */
1015#define FIR_START_CLK (1 << 1) /* Start Tx/Rx Clock */
1016#define FIR_WRITE (1 << 2) /* Write Tx/Rx */
1017#define FIR_SELECT(x) (((x) & 0x3) << 3) /* Select Tx/Rx CH<1:0> */
1018#define FIR_NUM_TAPS(x) (((x) & 0x7) << 5) /* Number of Taps<2:0> */
1019
1020/*
1021* REG_TX_MON_LOW_GAIN
1022*/
1023#define TX_MON_TRACK (1 << 5) /* Tx Mon Track */
1024#define TX_MON_LOW_GAIN(x) (((x) & 0x1F) << 0) /* Tx Mon Low Gain<4:0> */
1025
1026/*
1027* REG_TX_MON_HIGH_GAIN
1028*/
1029#define TX_MON_HIGH_GAIN(x) (((x) & 0x1F) << 0) /* Tx Mon High Gain<4:0> */
1030
1031/*
1032* REG_TX_LEVEL_THRESH
1033*/
1034#define TX_LEVEL_THRESH(x) (((x) & 0x3F) << 2) /* Tx Level Threshold<5:0> */
1035#define TX_MON_DELAY_COUNTER(x) (((x) & 0x3) << 0) /* Tx Mon Delay Counter<9:8> */
1036
1037/*
1038* REG_TX_RSSI_LSB
1039*/
1040#define TX_RSSI_2 (1 << 1) /* Tx RSSI 2<0> */
1041#define TX_RSSI_1 (1 << 0) /* TX RSSI 1<0> */
1042
1043/*
1044* REG_TPM_MODE_ENABLE
1045*/
1046#define TX2_MON_ENABLE (1 << 7) /* Tx2 Monitor Enable */
1047#define TX1_MON_ENABLE (1 << 5) /* Tx1 Monitor Enable */
1048#define ONE_SHOT_MODE (1 << 6) /* One Shot Mode */
1049#define TX_MON_DURATION(x) (((x) & 0xF) << 0) /* Tx Mon Duration<3:0> */
1050
1051/*
1052* REG_TX_MON_1_CONFIG
1053*/
1054#define TX_MON_1_LO_CM(x) (((x) & 0x3F) << 2) /* Tx Mon 1 LO CM<5:0> */
1055#define TX_MON_1_GAIN(x) (((x) & 0x3) << 0) /* Tx Mon 1 Gain<1:0> */
1056
1057/*
1058* REG_TX_MON_2_CONFIG
1059*/
1060#define TX_MON_2_LO_CM(x) (((x) & 0x3F) << 2) /* Tx Mon 2 LO CM<5:0> */
1061#define TX_MON_2_GAIN(x) (((x) & 0x3) << 0) /* Tx Mon 2 Gain<1:0> */
1062
1063/*
1064* REG_TX1_ATTEN_1
1065*/
1066#define TX_1_ATTEN (1 << 0) /* Tx 1 Atten <8> */
1067
1068/*
1069* REG_TX2_ATTEN_1
1070*/
1071#define TX_2_ATTEN (1 << 0) /* Tx 2 Atten <8> */
1072
1073/*
1074* REG_TX_ATTEN_OFFSET
1075*/
1076#define MASK_CLR_ATTEN_UPDATE (1 << 6) /* Mask Clr Atten Update */
1077#define TX_ATTEN_OFFSET(x) (((x) & 0x3F) << 0) /* Tx Atten Offset<5:0> */
1078
1079/*
1080* REG_TX1_DIG_ATTEN
1081*/
1082#define SEL_TX1_TX2 (1 << 6) /* Sel Tx1 & Ttx2 */
1083
1084/*
1085* REG_TX2_DIG_ATTEN
1086*/
1087#define IMMEDIATELY_UPDATE_TPC_ATTEN (1 << 6) /* Immediately Update TPC Atten */
1088
1089/*
1090* REG_TX1_SYMBOL_ATTEN
1091*/
1092#define TX_1_SYMBOL_ATTEN(x) (((x) & 0x7F) << 0) /* Tx 1 Symbol Attenuation<6:0> */
1093
1094/*
1095* REG_TX2_SYMBOL_ATTEN
1096*/
1097#define TX_2_SYMBOL_ATTEN(x) (((x) & 0x7F) << 0) /* Tx 2 Symbol Attenuation<6:0> */
1098
1099/*
1100* REG_TX_SYMBOL_ATTEN_CONFIG
1101*/
1102#define USE_TX1_PIN_SYMBOL_ATTEN (1 << 3) /* Use Tx1 Pin & Symbol Atten */
1103#define USE_CTRL_IN_FOR_SYMBOL_ATTEN (1 << 1) /* Use CTRL IN for symbol Atten */
1104#define ENABLE_SYMBOL_ATTEN (1 << 0) /* Enable Symbol Atten */
1105
1106/*
1107* REG_TX_FORCE_BITS
1108*/
1109#define FORCE_OUT_2_TX2_OFFSET (1 << 7) /* Force Out 2 Tx2 Offset */
1110#define FORCE_OUT_2_TX1_OFFSET (1 << 6) /* Force Out 2 Tx1 Offset */
1111#define FORCE_OUT_2_TX2_PHASE_GAIN (1 << 5) /* Force Out 2 Tx2 Phase & Gain */
1112#define FORCE_OUT_2_TX1_PHASE_GAIN (1 << 4) /* Force Out 2 Tx1 Phase & Gain */
1113#define FORCE_OUT_1_TX2_OFFSET (1 << 3) /* Force Out 1 Tx2 Offset */
1114#define FORCE_OUT_1_TX1_OFFSET (1 << 2) /* Force Out 1 Tx1 Offset */
1115#define FORCE_OUT_1_TX2_PHASE_GAIN (1 << 1) /* Force Out 1 Tx2 Phase & Gain */
1116#define FORCE_OUT_1_TX1_PHASE_GAIN (1 << 0) /* Force Out 1 Tx1 Phase & Gain */
1117
1118/*
1119* REG_QUAD_CAL_NCO_FREQ_PHASE_OFFSET
1120*/
1121#define RX_NCO_FREQ(x) (((x) & 0x3) << 5) /* Rx NCO Frequency<1:0> */
1122#define RX_NCO_PHASE_OFFSET(x) (((x) & 0x1F) << 0) /* Rx NCO Phase Offset<4:0> */
1123
1124/*
1125* REG_QUAD_CAL_CTRL
1126*/
1127#define FREE_RUN_ENABLE (1 << 7) /* Free Run Enable */
1128#define SETTLE_MAIN_ENABLE (1 << 6) /* Settle Main Enable */
1129#define DC_OFFSET_ENABLE (1 << 5) /* DC Offset Enable */
1130#define GAIN_ENABLE (1 << 4) /* Gain Enable */
1131#define PHASE_ENABLE (1 << 3) /* Phase Enable */
1132#define QUAD_CAL_SOFT_RESET (1 << 2) /* Quad Cal Soft Reset */
1133#define M_DECIM(x) (((x) & 0x3) << 0) /* M<1:0> */
1134
1135/*
1136* REG_KEXP_1
1137*/
1138#define KEXP_TX(x) (((x) & 0x3) << 6) /* Kexp Tx<1:0> */
1139#define KEXP_TX_COMP(x) (((x) & 0x3) << 4) /* Kexp Tx_comp <1:0> */
1140#define KEXP_DC_I(x) (((x) & 0x3) << 2) /* Kexp DC I <1:0> */
1141#define KEXP_DC_Q(x) (((x) & 0x3) << 0) /* Kexp DC Q <1:0> */
1142
1143/*
1144* REG_KEXP_2
1145*/
1146#define INVERT_I_DATA (1 << 5) /* Invert I data */
1147#define INVERT_Q_DATA (1 << 4) /* Invert Q data */
1148#define TX_NCO_FREQ(x) (((x) & 0x3) << 6) /* Tx NCO frequency<1:0> */
1149#define KEXP_PHASE(x) (((x) & 0x3) << 2) /* Kexp Phase <1:0> */
1150#define KEXP_AMP(x) (((x) & 0x3) << 0) /* Kexp Amp <1:0> */
1151
1152/*
1153* REG_QUAD_CAL_STATUS_TX1
1154*/
1155#define TX1_LO_CONV (1 << 1) /* Tx1 LO Conv */
1156#define TX1_SSB_CONV (1 << 0) /* Tx1 SSB Conv */
1157#define TX1_CONVERGENCE_COUNT(x) (((x) & 0x3F) << 2) /* Tx1 Convergence Count<5:0> */
1158
1159/*
1160* REG_QUAD_CAL_STATUS_TX2
1161*/
1162#define TX2_LO_CONV (1 << 1) /* Tx2 LO Conv */
1163#define TX2_SSB_CONV (1 << 0) /* Tx2 SSB Conv */
1164#define TX2_CONVERGENCE_COUNT(x) (((x) & 0x3F) << 2) /* Tx2 Convergence Count<5:0> */
1165
1166/*
1167* REG_TX_QUAD_FULL_LMT_GAIN
1168*/
1169#define RX_FULL_TABLELMT_TABLE_GAIN(x) (((x) & 0x7F) << 0) /* RX Full table/LMT table gain<6:0> */
1170
1171/*
1172* REG_SQUARER_CONFIG
1173*/
1174#define GM_STAGE_TIME_CON_OVERRIDE (1 << 5) /* Gm Stage Time Con Override */
1175#define GM_STAGE_MV_HP_POLE (1 << 4) /* Gm Stage MV HP Pole */
1176#define GM_STAGE_LOWER_CM (1 << 3) /* Gm Stage Lower CM */
1177#define BYPASS_BIAS_R (1 << 0) /* Bypass Bias R */
1178#define VBIAS_CTRL(x) (((x) & 0x3) << 1) /* Vbias Control<1:0> */
1179
1180/*
1181* REG_THRESH_ACCUM
1182*/
1183#define THRESH_ACCUMULATOR(x) (((x) & 0xF) << 0) /* Threshold Accumulator<3:0> */
1184
1185/*
1186* REG_TX_QUAD_LPF_GAIN
1187*/
1188#define RX_LPF_GAIN(x) (((x) & 0x1F) << 0) /* RX LPF gain<4:0> */
1189
1190/*
1191* REG_TXDAC_VDS_I
1192*/
1193#define TXDAC_VDS_I(x) (((x) & 0x3F) << 0) /* TxDAC Vds I<5:0> */
1194
1195/*
1196* REG_TXDAC_VDS_Q
1197*/
1198#define TXDAC_VDS_Q(x) (((x) & 0x3F) << 0) /* TxDAC Vds Q<5:0> */
1199
1200/*
1201* REG_TXDAC_GN_I
1202*/
1203#define TXDAC_GN_I(x) (((x) & 0x3F) << 0) /* txDAC_gn_I<5:0> */
1204
1205/*
1206* REG_TXDAC_GN_Q
1207*/
1208#define TXDAC_GN_Q(x) (((x) & 0x3F) << 0) /* txDAC_gn_Q<5:0> */
1209
1210/*
1211* REG_TXBBF_OPAMP_A
1212*/
1213#define OPAMPA_OUTPUT_BIAS(x) (((x) & 0x3) << 5) /* OpAmpA Output Bias<1:0> */
1214#define OPAMPA_RZ(x) (((x) & 0x3) << 3) /* OpAmpA RZ<1:0> */
1215#define OPAMP_A_CC(x) (((x) & 0x7) << 0) /* OpAmp A CC<2:0> */
1216
1217/*
1218* REG_TXBBF_OPAMP_B
1219*/
1220#define OPAMPB_OUTPUT_BIAS(x) (((x) & 0x3) << 5) /* OpAmpB Output Bias<1:0> */
1221#define OPAMPB_RZ(x) (((x) & 0x3) << 3) /* OpAmpB RZ<1:0> */
1222#define OPAMP_B_CC(x) (((x) & 0x7) << 0) /* OpAmp B CC<2:0> */
1223
1224/*
1225* REG_TX_BBF_R1
1226*/
1227#define OVERRIDE_ENABLE (1 << 7) /* Override enable */
1228#define R1(x) (((x) & 0x1F) << 0) /* R1<4:0> */
1229
1230/*
1231* REG_TX_BBF_R2
1232*/
1233#define R2(x) (((x) & 0x1F) << 0) /* R2<4:0> */
1234
1235/*
1236* REG_TX_BBF_R3
1237*/
1238#define R3(x) (((x) & 0x1F) << 0) /* R3<4:0> */
1239
1240/*
1241* REG_TX_BBF_R4
1242*/
1243#define R4(x) (((x) & 0x1F) << 0) /* R4<4:0> */
1244
1245/*
1246* REG_TX_BBF_RP
1247*/
1248#define RP(x) (((x) & 0x1F) << 0) /* Rp<4:0> */
1249
1250/*
1251* REG_TX_BBF_C1
1252*/
1253#define C1(x) (((x) & 0x3F) << 0) /* C1<5:0> */
1254
1255/*
1256* REG_TX_BBF_C2
1257*/
1258#define C2(x) (((x) & 0x3F) << 0) /* C2<5:0> */
1259
1260/*
1261* REG_TX_BBF_CP
1262*/
1263#define CP(x) (((x) & 0x3F) << 0) /* Cp<5:0> */
1264
1265/*
1266* REG_TX_TUNE_CTRL
1267*/
1268#define PD_TUNE (1 << 2) /* PD Tune */
1269#define TUNER_RESAMPLE (1 << 1) /* Tuner Resample */
1270#define TUNER_RESAMPLE_PHASE (1 << 0) /* Tuner Resample Phase */
1271#define TUNE_CTRL(x) (((x) & 0x3) << 5) /* Tune Control<1:0> */
1272
1273/*
1274* REG_TX_BBF_R2B
1275*/
1276#define TX_BBF_BYPASS_BIAS_R (1 << 7) /* Bypass Bias R */
1277#define R2B_OVR (1 << 5) /* R2b Ovr */
1278#define R2B(x) (((x) & 0x1F) << 0) /* R2b<4:0> */
1279
1280/*
1281* REG_TX_BBF_TUNE
1282*/
1283#define BBF1_COMP_I (1 << 3) /* BBF1 Comp I */
1284#define BBF1_COMP_Q (1 << 2) /* BBF1 Comp Q */
1285#define BBF2_COMP_I (1 << 1) /* BBF2 Comp I */
1286#define BBF2_COMP_Q (1 << 0) /* BBF2 Comp Q */
1287
1288/*
1289* REG_CONFIG0
1290*/
1291#define BIAS(x) (((x) & 0x3) << 6) /* Bias<1:0> */
1292#define RGM(x) (((x) & 0x3) << 4) /* Rgm<1:0> */
1293#define CC(x) (((x) & 0x3) << 2) /* Cc<1:0> */
1294#define AMPBIAS(x) (((x) & 0x3) << 0) /* AmpBias<1:0> */
1295
1296/*
1297* REG_RESISTOR
1298*/
1299#define RESISTOR(x) (((x) & 0xF) << 0) /* Resistor<3:0> */
1300
1301/*
1302* REG_CAPACITOR
1303*/
1304#define CAPACITOR(x) (((x) & 0x3F) << 0) /* Capacitor<5:0> */
1305
1306/*
1307* REG_LO_CM
1308*/
1309#define LO_COMMON_MODE(x) (((x) & 0x3) << 5) /* LO Common Mode<1:0> */
1310
1311/*
1312* REG_TX_BBF_TUNE_MODE
1313*/
1314#define EVALTIME (1 << 4) /* EvalTime */
1315#define TX_BBF_TUNE_DIVIDER (1 << 0) /* TX BBF Tune Divider<8> */
1316#define TUNE_COMP_MASK(x) (((x) & 0x3) << 5) /* Tune Comp Mask<1:0> */
1317#define TUNER_MODE(x) (((x) & 0x7) << 1) /* Tuner Mode<2:0> */
1318
1319/*
1320* REG_RX_FILTER_CONFIG
1321*/
1322#define WRITE_RX (1 << 2) /* Write Rx */
1323#define START_RX_CLOCK (1 << 1) /* Start Rx Clock */
1324#define NUMBER_OF_TAPS(x) (((x) & 0x7) << 5) /* Number of Taps */
1325#define SELECT_RX_CH(x) (((x) & 0x3) << 3) /* Select Rx Ch<1:0> */
1326
1327/*
1328* REG_RX_FILTER_GAIN
1329*/
1330#define FILTER_GAIN(x) (((x) & 0x3) << 0) /* Filter gain<1:0> */
1331
1332/*
1333* REG_AGC_CONFIG_1
1334*/
1335#define DEC_PWR_FOR_LOW_PWR (1 << 7) /* Dec Pwr for Low Pwr */
1336#define DEC_PWR_FOR_LOCK_LEVEL (1 << 6) /* Dec Pwr for Lock Level */
1337#define DEC_PWR_FOR_GAIN_LOCK_EXIT (1 << 5) /* Dec Pwr for Gain Lock Exit */
1338#define SLOW_ATTACK_HYBRID_MODE (1 << 4) /* Slow Attack Hybrid Mode */
1339#define RX2_GAIN_CTRL_SETUP(x) (((x) & 0x3) << 2) /* Rx 2 Gain Control Setup<1:0> */
1340#define RX1_GAIN_CTRL_SETUP(x) (((x) & 0x3) << 0) /* Rx 1 Gain Control Setup<1:0> */
1341#define RX_GAIN_CTL_MASK 0x03
1342#define RX2_GAIN_CTRL_SHIFT 2
1343#define RX1_GAIN_CTRL_SHIFT 0
1344#define RX_GAIN_CTL_MGC 0x00
1345#define RX_GAIN_CTL_AGC_FAST_ATK 0x01
1346#define RX_GAIN_CTL_AGC_SLOW_ATK 0x02
1347#define RX_GAIN_CTL_AGC_SLOW_ATK_HYBD 0x03
1348
1349/*
1350* REG_AGC_CONFIG_2
1351*/
1352#define AGC_SOFT_RESET (1 << 7) /* Soft Reset */
1353#define AGC_GAIN_UNLOCK_CTRL (1 << 6) /* Gain Unlock Control */
1354#define AGC_USE_FULL_GAIN_TABLE (1 << 3) /* Use Full Gain Table */
1355#define DIG_GAIN_EN (1 << 2) /* Enable Digital Gain */
1356#define MAN_GAIN_CTRL_RX2 (1 << 1) /* Manual Gain Control Rx 2 */
1357#define MAN_GAIN_CTRL_RX1 (1 << 0) /* Manual Gain Control Rx 1 */
1358
1359/*
1360* REG_AGC_CONFIG_3
1361*/
1362#define INCDEC_LMT_GAIN (1 << 4) /* Inc/Dec LMT Gain */
1363#define USE_AGC_FOR_LMTLPF_GAIN (1 << 3) /* Use AGC for LMT/LPF Gain */
1364#define MANUAL_INCR_STEP_SIZE(x) (((x) & 0x7) << 5) /* Manual (CTRL_IN) Incr Gain Step Size<2:0> */
1365#define ADC_OVERRANGE_SAMPLE_SIZE(x) (((x) & 0x7) << 0) /* ADC Overrange Sample Size<2:0> */
1366
1367/*
1368* REG_MAX_LMT_FULL_GAIN
1369*/
1370#define MAXIMUM_FULL_TABLELMT_TABLE_INDEX(x) (((x) & 0x7F) << 0) /* Maximum Full Table/LMT Table Index<6:0> */
1371
1372/*
1373* REG_PEAK_WAIT_TIME
1374*/
1375#define MANUAL_CTRL_IN_DECR_GAIN_STP_SIZE(x) (((x) & 0x7) << 5) /* Manual (CTRL_IN) Decr Gain Step Size<2:0> */
1376#define PEAK_OVERLOAD_WAIT_TIME(x) (((x) & 0x1F) << 0) /* Peak Overload Wait Time<4:0> */
1377
1378/*
1379* REG_DIGITAL_GAIN
1380*/
1381#define DIG_GAIN_STP_SIZE(x) (((x) & 0x7) << 5) /* Dig Gain Step Size<2:0> */
1382#define MAXIMUM_DIGITAL_GAIN(x) (((x) & 0x1F) << 0) /* Maximum Digital Gain<4:0> */
1383
1384/*
1385* REG_AGC_LOCK_LEVEL
1386*/
1387#define ENABLE_DIG_SAT_OVRG (1 << 7) /* Enable Dig Sat Ovrg */
1388#define AGC_LOCK_LEVEL_FAST_AGC_INNER_HIGH_THRESH_SLOW(x) (((x) & 0x7F) << 0) /* AGC Lock Level (Fast)/ AGC Inner High Threshold (Slow) <6:0> */
1389
1390/*
1391* REG_GAIN_STP_CONFIG1
1392*/
1393#define LMT_DETECTOR_SETTLING_TIME(x) (((x) & 0x7) << 5) /* LMT Detector Settling Time<2:0> */
1394#define DEC_STP_SIZE_FOR_LARGE_LMT_OVERLOAD(x) (((x) & 0x7) << 2) /* Dec Step Size for: Large LMT Overload/ Full Table Case #3 <2:0> */
1395#define ADC_NOISE_CORRECTION_FACTOR(x) (((x) & 0x3) << 0) /* ADC Noise Correction Factor<1:0> */
1396
1397/*
1398* REG_GAIN_STP_CONFIG_2
1399*/
1400#define DECREMENT_STP_SIZE_FOR_SMALL_LPF_GAIN_CHANGE(x) (((x) & 0x7) << 4) /* Fast Attack Only. Decrement Step Size for: Small LPF Gain Change / Full Table Case #2 <2:0> */
1401#define LARGE_LPF_GAIN_STEP(x) (((x) & 0xF) << 0) /* Decrement Step Size for: Large LPF Gain Change / Full Table Case #1<3:0> */
1402
1403/*
1404* REG_SMALL_LMT_OVERLOAD_THRESH
1405*/
1406#define FORCE_PD_RESET_RX2 (1 << 7) /* Force PD Reset Rx2 */
1407#define FORCE_PD_RESET_RX1 (1 << 6) /* Force PD Reset Rx1 */
1408#define SMALL_LMT_OVERLOAD_THRESH(x) (((x) & 0x3F) << 0) /* Small LMT Overload Threshold<5:0> */
1409
1410/*
1411* REG_LARGE_LMT_OVERLOAD_THRESH
1412*/
1413#define LARGE_LMT_OVERLOAD_THRESH(x) (((x) & 0x3F) << 0) /* Large LMT Overload Threshold<5:0> */
1414
1415/*
1416* REG_RX1_MANUAL_LMT_FULL_GAIN
1417*/
1418#define POWER_MEAS_IN_STATE_5_MSB (1 << 7) /* Power Meas in State 5 <3> */
1419#define RX1_MANUAL_FULL_TABLE_LMT_TABLE_GAIN_INDEX(x) (((x) & 0x7F) << 0) /* Rx1 Manual Full table/LMT table Gain Index<6:0> */
1420#define RX_FULL_TBL_IDX_MASK RX1_MANUAL_FULL_TABLE_LMT_TABLE_GAIN_INDEX(~0)
1421
1422/*
1423* REG_RX1_MANUAL_LPF_GAIN
1424*/
1425#define POWER_MEAS_IN_STATE_5(x) (((x) & 0x7) << 5) /* Power Meas in State 5<2:0> */
1426#define RX1_MANUAL_LPF_GAIN(x) (((x) & 0x1F) << 0) /* Rx1 Manual LPF Gain <4:0> */
1427#define RX_LPF_IDX_MASK RX1_MANUAL_LPF_GAIN(~0)
1428
1429/*
1430* REG_RX1_MANUAL_DIGITALFORCED_GAIN
1431*/
1432#define FORCE_RX1_DIGITAL_GAIN (1 << 5) /* Force Rx1 Digital Gain */
1433#define RX1_MANUALFORCED_DIGITAL_GAIN(x) (((x) & 0x1F) << 0) /* Rx1 Manual/Forced Digital Gain<4:0> */
1434#define RX_DIGITAL_IDX_MASK RX1_MANUALFORCED_DIGITAL_GAIN(~0)
1435/*
1436* REG_RX2_MANUAL_LMT_FULL_GAIN
1437*/
1438#define RX2_MANUAL_FULL_TABLE_LMT_TABLE_GAIN_INDEX(x) (((x) & 0x7F) << 0) /* Rx2 Manual Full table/ LMT table Gain Index<6:0> */
1439
1440/*
1441* REG_RX2_MANUAL_LPF_GAIN
1442*/
1443#define RX2_MANUAL_LPF_GAIN(x) (((x) & 0x1F) << 0) /* Rx2 Manual LPF Gain<4:0> */
1444
1445/*
1446* REG_RX2_MANUAL_DIGITALFORCED_GAIN
1447*/
1448#define FORCE_RX2_DIGITAL_GAIN (1 << 5) /* Force Rx2 Digital Gain */
1449#define RX2_MANUALFORCED_DIGITAL_GAIN(x) (((x) & 0x1F) << 0) /* Rx2 Manual/Forced Digital Gain<4:0> */
1450
1451/*
1452* REG_FAST_CONFIG_1
1453*/
1454#define ENABLE_GAIN_INC_AFTER_GAIN_LOCK (1 << 7) /* Enable Gain Inc after Gain Lock */
1455#define GOTO_OPT_GAIN_IF_ENERGY_LOST_OR_EN_AGC_HIGH (1 << 6) /* Goto Opt Gain if Energy Lost or EN_AGC High */
1456#define GOTO_SET_GAIN_IF_EN_AGC_HIGH (1 << 5) /* Goto Set Gain if EN_AGC High */
1457#define GOTO_SET_GAIN_IF_EXIT_RX_STATE (1 << 4) /* Goto Set Gain if Exit Rx State */
1458#define DONT_UNLOCK_GAIN_IF_ENERGY_LOST (1 << 3) /* Don't Unlock Gain if Energy Lost */
1459#define GOTO_OPTIMIZED_GAIN_IF_EXIT_RX_STATE (1 << 2) /* Goto Optimized Gain if Exit Rx State */
1460#define DONT_UNLOCK_GAIN_IF_LG_ADC_OR_LMT_OVRG (1 << 1) /* Don't Unlock Gain If Lg ADC or LMT Ovrg */
1461#define ENABLE_INCR_GAIN (1 << 0) /* Enable Incr Gain */
1462
1463/*
1464* REG_FAST_CONFIG_2_SETTLING_DELAY
1465*/
1466#define USE_LAST_LOCK_LEVEL_FOR_SET_GAIN (1 << 7) /* Use Last Lock Level for Set Gain */
1467#define ENABLE_LMT_GAIN_INC_FOR_LOCK_LEVEL (1 << 6) /* Enable LMT Gain Inc for Lock Level */
1468#define GOTO_MAX_GAIN_OR_OPT_GAIN_IF_EN_AGC_HIGH (1 << 5) /* Goto Max Gain or Opt Gain if EN_AGC High */
1469#define SETTLING_DELAY(x) (((x) & 0x1F) << 0) /* Settling Delay<4:0> */
1470
1471/*
1472* REG_FAST_ENERGY_LOST_THRESH
1473*/
1474#define POST_LOCK_LEVEL_STP_SIZE_FOR_LPF_TABLE_FULL_TABLE(x) (((x) & 0x3) << 6) /* Post Lock Level Step Size for: LPF Table/ Full Table <1:0> */
1475#define ENERGY_LOST_THRESH(x) (((x) & 0x3F) << 0) /* Energy lost threshold<5:0> */
1476
1477/*
1478* REG_FAST_STRONGER_SIGNAL_THRESH
1479*/
1480#define POST_LOCK_LEVEL_STP_FOR_LMT_TABLE(x) (((x) & 0x3) << 6) /* Post Lock Level Step for LMT Table <1:0> */
1481#define STRONGER_SIGNAL_THRESH(x) (((x) & 0x3F) << 0) /* Stronger Signal Threshold<5:0> */
1482
1483/*
1484* REG_FAST_LOW_POWER_THRESH
1485*/
1486#define DONT_UNLOCK_GAIN_IF_ADC_OVRG (1 << 7) /* Don't unlock gain if ADC Ovrg */
1487#define LOW_POWER_THRESH(x) (((x) & 0x7F) << 0) /* Low Power Threshold<6:0> */
1488
1489/*
1490* REG_FAST_STRONG_SIGNAL_FREEZE
1491*/
1492#define DONT_UNLOCK_GAIN_IF_STRONGER_SIGNAL (1 << 7) /* Don't unlock gain if Stronger Signal */
1493
1494/*
1495* REG_FAST_FINAL_OVER_RANGE_AND_OPT_GAIN
1496*/
1497#define FINAL_OVER_RANGE_COUNT(x) (((x) & 0x7) << 5) /* Final Over Range Count<2:0> */
1498#define OPTIMIZE_GAIN_OFFSET(x) (((x) & 0xF) << 0) /* Optimize Gain Offset<3:0> */
1499
1500/*
1501* REG_FAST_ENERGY_DETECT_COUNT
1502*/
1503#define INCREMENT_GAIN_STP_LPFLMT(x) (((x) & 0x7) << 5) /* Increment Gain Step (LPF/LMT)<2:0> */
1504#define ENERGY_DETECT_COUNT(x) (((x) & 0x1F) << 0) /* Energy Detect count<4:0> */
1505
1506/*
1507* REG_FAST_AGCLL_UPPER_LIMIT
1508*/
1509#define AGCLL_MAX_INCREASE(x) (((x) & 0x3F) << 0) /* AGCLL Max Increase<5:0> */
1510
1511/*
1512* REG_FAST_GAIN_LOCK_EXIT_COUNT
1513*/
1514#define GAIN_LOCK_EXIT_COUNT(x) (((x) & 0x3F) << 0) /* Gain Lock Exit Count<5:0> */
1515
1516/*
1517* REG_FAST_INITIAL_LMT_GAIN_LIMIT
1518*/
1519#define INITIAL_LMT_GAIN_LIMIT(x) (((x) & 0x7F) << 0) /* Initial LMT Gain Limit<6:0> */
1520
1521/*
1522* REG_AGC_INNER_LOW_THRESH
1523*/
1524#define PREVENT_GAIN_INC (1 << 7) /* Prevent Gain Inc */
1525#define AGC_INNER_LOW_THRESH(x) (((x) & 0x7F) << 0) /* AGC Inner Low Threshold<6:0> */
1526
1527/*
1528* REG_LMT_OVERLOAD_COUNTERS
1529*/
1530#define LARGE_LMT_OVERLOAD_EXED_COUNTER(x) (((x) & 0xF) << 4) /* Large LMT Overload Exceeded Counter<3:0> */
1531#define SMALL_LMT_OVERLOAD_EXED_COUNTER(x) (((x) & 0xF) << 0) /* Small LMT Overload Exceeded Counter<3:0> */
1532
1533/*
1534* REG_ADC_OVERLOAD_COUNTERS
1535*/
1536#define LARGE_ADC_OVERLOAD_EXED_COUNTER(x) (((x) & 0xF) << 4) /* Large ADC Overload Exceeded Counter<3:0> */
1537#define SMALL_ADC_OVERLOAD_EXED_COUNTER(x) (((x) & 0xF) << 0) /* Small ADC Overload Exceeded Counter<3:0> */
1538
1539/*
1540* REG_GAIN_STP1
1541*/
1542#define IMMED_GAIN_CHANGE_IF_LG_LMT_OVERLOAD (1 << 7) /* Immed. Gain Change if Lg LMT Overload */
1543#define IMMED_GAIN_CHANGE_IF_LG_ADC_OVERLOAD (1 << 3) /* Immed. Gain Change if Lg ADC Overload */
1544#define AGC_INNER_HIGH_THRESH_EXED_STP_SIZE(x) (((x) & 0x7) << 4) /* AGC Inner High Threshold Exceeded Step Size<2:0> */
1545#define AGC_INNER_LOW_THRESH_EXED_STP_SIZE(x) (((x) & 0x7) << 0) /* AGC Inner Low Threshold Exceeded Step Size<2:0> */
1546
1547/*
1548* REG_DIGITAL_SAT_COUNTER
1549*/
1550#define DOUBLE_GAIN_COUNTER (1 << 5) /* Double Gain Counter */
1551#define ENABLE_SYNC_FOR_GAIN_COUNTER (1 << 4) /* Enable Sync for Gain Counter */
1552#define DIG_SATURATION_EXED_COUNTER(x) (((x) & 0xF) << 0) /* Dig Saturation Exceeded Counter<3:0> */
1553
1554/*
1555* REG_OUTER_POWER_THRESHS
1556*/
1557#define AGC_OUTER_HIGH_THRESH(x) (((x) & 0xF) << 4) /* AGC Outer High Threshold<3:0> */
1558#define AGC_OUTER_LOW_THRESH(x) (((x) & 0xF) << 0) /* AGC Outer Low Threshold<3:0> */
1559
1560/*
1561* REG_GAIN_STP_2
1562*/
1563#define AGC_OUTER_HIGH_THRESH_EXED_STP_SIZE(x) (((x) & 0xF) << 4) /* AGC outer High Threshold Exceeded Step Size<3:0> */
1564#define AGC_OUTER_LOW_THRESH_EXED_STP_SIZE(x) (((x) & 0xF) << 0) /* AGC Outer Low Threshold Exceeded Step Size<3:0> */
1565
1566/*
1567* REG_EXT_LNA_HIGH_GAIN
1568*/
1569#define EXT_LNA_HIGH_GAIN(x) (((x) & 0x3F) << 0) /* Ext LNA High Gain<5:0> */
1570
1571/*
1572* REG_EXT_LNA_LOW_GAIN
1573*/
1574#define EXT_LNA_LOW_GAIN(x) (((x) & 0x3F) << 0) /* Ext LNA Low Gain<5:0> */
1575
1576/*
1577* REG_GAIN_TABLE_ADDRESS
1578*/
1579#define GAIN_TABLE_ADDRESS(x) (((x) & 0x7F) << 0) /* Gain Table Address<6:0> */
1580
1581/*
1582* REG_GAIN_TABLE_WRITE_DATA1
1583*/
1584#define EXT_LNA_CTRL (1 << 7) /* Ext LNA Ctrl */
1585#define LNA_GAIN(x) (((x) & 0x3) << 5) /* LNA Gain <1:0> */
1586#define MIXER_GM_GAIN(x) (((x) & 0x1F) << 0) /* Mixer Gm Gain <4:0> */
1587
1588/*
1589* REG_GAIN_TABLE_WRITE_DATA2
1590*/
1591#define TIA_GAIN (1 << 5) /* TIA Gain */
1592#define LPF_GAIN(x) (((x) & 0x1F) << 0) /* LPF Gain <4:0> */
1593
1594/*
1595* REG_GAIN_TABLE_WRITE_DATA_3
1596*/
1597#define RF_DC_CAL (1 << 5) /* RF DC Cal */
1598#define DIGITAL_GAIN(x) (((x) & 0x1F) << 0) /* Digital Gain <4:0> */
1599
1600/*
1601* REG_GAIN_TABLE_READ_DATA_1
1602*/
1603#define TO_LNA_GAIN(x) (((x) >> 5) & 0x3) /* LNA Gain <1:0> */
1604#define TO_MIXER_GM_GAIN(x) (((x) >> 0) & 0x1F) /* Mixer Gm Gain <4:0> */
1605
1606/*
1607* REG_GAIN_TABLE_READ_DATA_2
1608*/
1609#define TO_LPF_GAIN(x) (((x) >> 0) & 0x1F) /* LPF Gain <4:0> */
1610
1611/*
1612* REG_GAIN_TABLE_READ_DATA_3
1613*/
1614#define TO_DIGITAL_GAIN(x) (((x) >> 0) & 0x1F) /* Digital Gain <4:0> */
1615
1616/*
1617* REG_GAIN_TABLE_CONFIG
1618*/
1619#define WRITE_GAIN_TABLE (1 << 2) /* Write Gain Table */
1620#define START_GAIN_TABLE_CLOCK (1 << 1) /* Start Gain Table Clock */
1621#define RECEIVER_SELECT(x) (((x) & 0x3) << 3) /* Receiver Select<1:0> */
1622#define GT_RX1 1
1623#define GT_RX2 2
1624
1625
1626/*
1627* REG_GM_SUB_TABLE_GAIN_WRITE
1628*/
1629#define GM_SUB_TABLE_GAIN_WRITE(x) (((x) & 0x7F) << 0) /* Gm Sub Table Gain Word Write<6:0> */
1630
1631/*
1632* REG_GM_SUB_TABLE_BIAS_WRITE
1633*/
1634#define GM_SUB_TABLE_BIAS_WRITE(x) (((x) & 0x1F) << 0) /* Gm Sub Table Bias Word Write<4:0> */
1635
1636/*
1637* REG_GM_SUB_TABLE_CTRL_WRITE
1638*/
1639#define GM_SUB_TABLE_CTRL_WRITE(x) (((x) & 0x3F) << 0) /* Gm Sub Table Control Word Write<5:0> */
1640
1641/*
1642* REG_GM_SUB_TABLE_GAIN_READ
1643*/
1644#define GM_SUB_TABLE_GAIN_READ(x) (((x) & 0x7F) << 0) /* Gm Sub Table Gain Word Read<6:0> */
1645
1646/*
1647* REG_GM_SUB_TABLE_BIAS_READ
1648*/
1649#define GM_SUB_TABLE_BIAS_READ(x) (((x) & 0x1F) << 0) /* Gm Sub Table Bias Word Read<4:0> */
1650
1651/*
1652* REG_GM_SUB_TABLE_CTRL_READ
1653*/
1654#define GM_SUB_TABLE_CTRL_READ(x) (((x) & 0x3F) << 0) /* Gm Sub Table Control Word Read<5:0> */
1655
1656/*
1657* REG_GM_SUB_TABLE_CONFIG
1658*/
1659#define WRITE_GM_SUB_TABLE (1 << 2) /* Write Gm Sub Table */
1660#define START_GM_SUB_TABLE_CLOCK (1 << 1) /* Start Gm Sub Table Clock */
1661
1662/*
1663* REG_GAIN_DIFF_WORDERROR_WRITE
1664*/
1665#define CALIB_TABLE_GAIN_DIFFERROR_WORD(x) (((x) & 0x3F) << 0) /* Calib Table Gain Diff/Error Word<5:0> */
1666
1667/*
1668* REG_GAIN_ERROR_READ
1669*/
1670#define CALIB_TABLE_GAIN_ERROR(x) (((x) & 0x1F) << 0) /* Calib Table Gain Error<4:0> */
1671
1672/*
1673* REG_CONFIG
1674*/
1675#define READ_SELECT (1 << 4) /* Read Select */
1676#define WRITE_MIXER_ERROR_TABLE (1 << 3) /* Write Mixer Error Table */
1677#define WRITE_LNA_ERROR_TABLE (1 << 2) /* Write LNA Error Table */
1678#define WRITE_LNA_GAIN_DIFF (1 << 1) /* Write LNA Gain Diff */
1679#define START_CALIB_TABLE_CLOCK (1 << 0) /* Start Calib Table Clock */
1680#define CALIB_TABLE_SELECT(x) (((x) & 0x3) << 5) /* Calib Table Select<1:0> */
1681
1682/*
1683* REG_LNA_GAIN_DIFF_READ_BACK
1684*/
1685#define LNA_CALIB_TABLE_GAIN_DIFFERENCE_WORD(x) (((x) & 0x3F) << 0) /* LNA Calib Table Gain Difference Word<5:0> */
1686
1687/*
1688* REG_MAX_MIXER_CALIBRATION_GAIN_INDEX
1689*/
1690#define MAX_MIXER_CALIBRATION_GAIN_INDEX(x) (((x) & 0x1F) << 0) /* Max Mixer Calibration Gain Index<4:0> */
1691
1692/*
1693* REG_SETTLE_TIME
1694*/
1695#define ENABLE_DIG_GAIN_CORR (1 << 7) /* Enable Dig Gain Corr */
1696#define FORCE_TEMP_SENSOR_FOR_CAL (1 << 6) /* Force Temp Sensor for Cal */
1697#define SETTLE_TIME(x) (((x) & 0x3F) << 0) /* Settle Time<5:0> */
1698
1699/*
1700* REG_MEASURE_DURATION
1701*/
1702#define GAIN_CAL_MEAS_DURATION(x) (((x) & 0xF) << 0) /* Gain Cal Meas Duration<3:0> */
1703
1704/*
1705* REG_MEASURE_DURATION_01
1706*/
1707#define MEASUREMENT_DURATION_1(x) (((x) & 0xF) << 4) /* Measurement duration 1 <3:0> */
1708#define MEASUREMENT_DURATION_0(x) (((x) & 0xF) << 0) /* Measurement duration 0 <3:0> */
1709
1710/*
1711* REG_MEASURE_DURATION_23
1712*/
1713#define MEASUREMENT_DURATION_3(x) (((x) & 0xF) << 4) /* Measurement duration 3 <3:0> */
1714#define MEASUREMENT_DURATION_2(x) (((x) & 0xF) << 0) /* Measurement duration 2 <3:0> */
1715
1716/*
1717* REG_RSSI_CONFIG
1718*/
1719#define START_RSSI_MEAS (1 << 5) /* Start RSSI Meas (Mode 4) */
1720#define ENABLE_ADC_POWER_MEAS (1 << 1) /* Enable ADC Power Meas. */
1721#define DEFAULT_RSSI_MEAS_MODE (1 << 0) /* Default RSSI Meas Mode */
1722#define RFIR_FOR_RSSI_MEASUREMENT(x) (((x) & 0x3) << 6) /* RFIR for RSSI measurement<1:0> */
1723#define RSSI_MODE_SELECT(x) (((x) & 0x7) << 2) /* RSSI Mode Select<2:0> */
1724
1725/*
1726* REG_ADC_MEASURE_DURATION_01
1727*/
1728#define ADC_POWER_MEASUREMENT_DURATION_1(x) (((x) & 0xF) << 4) /* ADC Power Measurement Duration 1<3:0> */
1729#define ADC_POWER_MEASUREMENT_DURATION_0(x) (((x) & 0xF) << 0) /* ADC Power Measurement Duration 0 <3:0> */
1730
1731/*
1732* REG_DEC_POWER_MEASURE_DURATION_0
1733*/
1734#define USE_HB3_OUT_FOR_ADC_PWR_MEAS (1 << 7) /* Use HB3 Out for ADC Pwr Meas */
1735#define USE_HB1_OUT_FOR_DEC_PWR_MEAS (1 << 6) /* Use HB1 Out for Dec pwr Meas */
1736#define ENABLE_DEC_PWR_MEAS (1 << 5) /* Enable Dec Pwr Meas */
1737#define DEFAULT_MODE_ADC_POWER (1 << 4) /* Default Mode ADC Power */
1738#define DEC_POWER_MEASUREMENT_DURATION(x) (((x) & 0xF) << 0) /* Dec Power Measurement Duration <3:0> */
1739
1740/*
1741* REG_LNA_GAIN
1742*/
1743#define DB_GAIN_READBACK_CHANNEL (1 << 0) /* dB Gain Read-back Channel */
1744#define MAX_LNA_GAIN(x) (((x) & 0x7F) << 1) /* Max LNA Gain<6:0> */
1745
1746/*
1747* REG_RX_QUAD_CAL_LEVEL
1748*/
1749#define RX_QUAD_CAL_LEVEL(x) (((x) & 0xF) << 0) /* Rx Quad Cal Level <3 :0> */
1750
1751/*
1752* REG_CALIBRATION_CONFIG_1
1753*/
1754#define ENABLE_PHASE_CORR (1 << 7) /* Enable Phase Corr */
1755#define ENABLE_GAIN_CORR (1 << 6) /* Enable Gain Corr */
1756#define USE_SETTLE_COUNT_FOR_DC_CAL_WAIT (1 << 5) /* Use Settle Count for DC Cal Wait */
1757#define FIXED_DC_CAL_WAIT_TIME (1 << 4) /* Fixed DC Cal Wait Time */
1758#define FREE_RUN_MODE (1 << 3) /* Free Run Mode */
1759#define ENABLE_CORR_WORD_DECIMATION (1 << 2) /* Enable Corr Word Decimation */
1760#define ENABLE_TRACKING_MODE_CH2 (1 << 1) /* Enable Tracking Mode CH2 */
1761#define ENABLE_TRACKING_MODE_CH1 (1 << 0) /* Enable Tracking Mode CH1 */
1762
1763/*
1764* REG_CALIBRATION_CONFIG_2
1765*/
1766#define SOFT_RESET (1 << 7) /* Soft Reset */
1767#define CALIBRATION_CONFIG2_DFLT (0x3 << 5) /* Must be 2'b11 */
1768#define K_EXP_PHASE(x) (((x) & 0x1F) << 0) /* K exp Phase<4:0> */
1769
1770/*
1771* REG_CALIBRATION_CONFIG_3
1772*/
1773#define PREVENT_POS_LOOP_GAIN (1 << 7) /* Prevent Pos Loop Gain */
1774#define K_EXP_AMPLITUDE(x) (((x) & 0x1F) << 0) /* K exp Amplitude<4:0> */
1775
1776/*
1777* REG_RX_QUAD_GAIN1
1778*/
1779#define RX_FULL_TABLELMT_TABLE_GAIN(x) (((x) & 0x7F) << 0) /* Rx Full table/LMT table gain<6:0> */
1780
1781/*
1782* REG_RX_QUAD_GAIN2
1783*/
1784#define CORRECTION_WORD_DECIMATION_M(x) (((x) & 0x7) << 5) /* Correction Word Decimation M<2:0> */
1785#define RX_LPF_GAIN(x) (((x) & 0x1F) << 0) /* Rx LPF gain<4:0> */
1786
1787/*
1788* REG_RX1_INPUT_A_OFFSETS
1789*/
1790#define RX1_INPUT_A_I_DC_OFFSET_LSB(x) (((x) & 0x3F) << 2) /* Rx1 Input A "I" DC Offset<5:0> */
1791#define RX1_INPUT_A_Q_DC_OFFSET(x) (((x) & 0x3) << 0) /* Rx1 Input A "Q" DC Offset<9:8> */
1792
1793/*
1794* REG_INPUT_A_OFFSETS_1
1795*/
1796#define RX2_INPUT_A_Q_DC_OFFSET_LSB(x) (((x) & 0xF) << 4) /* Rx2 Input A "Q" DC Offset<3:0> */
1797#define RX1_INPUT_A_I_DC_OFFSET_MSB(x) (((x) & 0xF) << 0) /* Rx1 Input A "I" DC Offset<9:6> */
1798
1799/*
1800* REG_RX2_INPUT_A_OFFSETS
1801*/
1802#define RX2_INPUT_A_I_DC_OFFSET(x) (((x) & 0x3) << 6) /* Rx2 Input A "I" DC Offset<1:0> */
1803#define RX2_INPUT_A_Q_DC_OFFSET_MSB(x) (((x) & 0x3F) << 0) /* Rx2 Input A "Q" DC Offset<9:4> */
1804
1805/*
1806* REG_RX1_INPUT_BC_OFFSETS
1807*/
1808#define RX1_INPUT_BC_I_DC_OFFSET_LSB(x) (((x) & 0x3F) << 2) /* Rx1 Input B&C "I" DC Offset<5:0> */
1809#define RX1_INPUT_BC_Q_DC_OFFSET(x) (((x) & 0x3) << 0) /* Rx1 Input B&C "Q" DC Offset<9:8> */
1810
1811/*
1812* REG_INPUT_BC_OFFSETS_1
1813*/
1814#define RX2_INPUT_BC_Q_DC_OFFSET_LSB(x) (((x) & 0xF) << 4) /* Rx2 Input B&C "Q" DC Offset<3:0> */
1815#define RX1_INPUT_BC_I_DC_OFFSET_MSB(x) (((x) & 0xF) << 0) /* Rx1 Input B&C "I" DC Offset<9:6> */
1816
1817/*
1818* REG_RX2_INPUT_BC_OFFSETS
1819*/
1820#define RX2_INPUT_BC_I_DC_OFFSET(x) (((x) & 0x3) << 6) /* Rx2 Input B&C "I" DC Offset<1:0> */
1821#define RX2_INPUT_BC_Q_DC_OFFSET_MSB(x) (((x) & 0x3F) << 0) /* Rx2 Input B&C "Q" DC Offset<9:4> */
1822
1823/*
1824* REG_FORCE_BITS
1825*/
1826#define RX2_INPUT_BC_FORCE_OFFSET (1 << 7) /* Rx2 Input B&C Force offset */
1827#define RX1_INPUT_BC_FORCE_OFFSET (1 << 6) /* Rx1 Input B&C Force offset */
1828#define RX2_INPUT_BC_FORCE_PHGAIN (1 << 5) /* Rx2 Input B&C Force Ph/Gain */
1829#define RX1_INPUT_BC_FORCE_PHGAIN (1 << 4) /* Rx1 Input B&C Force Ph/Gain */
1830#define RX2_INPUT_A_FORCE_OFFSET (1 << 3) /* Rx2 Input A Force offset */
1831#define RX1_INPUT_A_FORCE_OFFSET (1 << 2) /* Rx1 Input A Force offset */
1832#define RX2_INPUT_A_FORCE_PHGAIN (1 << 1) /* Rx2 Input A Force Ph/Gain */
1833#define RX1_INPUT_A_FORCE_PHGAIN (1 << 0) /* Rx1 Input A Force Ph/Gain */
1834
1835/*
1836* REG_RF_DC_OFFSET_CONFIG_1
1837*/
1838#define DAC_FS(x) (((x) & 0x3) << 4) /* DAC FS<1:0> */
1839#define RF_DC_CALIBRATION_COUNT(x) (((x) & 0xF) << 0) /* RF DC Calibration Count<3:0> */
1840
1841/*
1842* REG_RF_DC_OFFSET_ATTEN
1843*/
1844#define RF_DC_OFFSET_TABLE_UPDATE_COUNT(x) (((x) & 0x7) << 5) /* RF DC Offset Table Update Count<2:0> */
1845#define RF_DC_OFFSET_ATTEN(x) (((x) & 0x1F) << 0) /* RF DC Offset Attenuation<4:0> */
1846
1847/*
1848* REG_INVERT_BITS
1849*/
1850#define INVERT_RX2_RF_DC_CGIN_WORD (1 << 7) /* Invert Rx2 RF DC CGin Word */
1851#define INVERT_RX1_RF_DC_CGIN_WORD (1 << 6) /* Invert Rx1 RF DC CGin Word */
1852#define INVERT_RX2_RF_DC_CGOUT_WORD (1 << 5) /* Invert Rx2 RF DC CGout Word */
1853#define INVERT_RX1_RF_DC_CGOUT_WORD (1 << 4) /* Invert Rx1 RF DC CGout Word */
1854
1855/*
1856* REG_DC_OFFSET_CONFIG2
1857*/
1858#define USE_WAIT_COUNTER_FOR_RF_DC_INIT_CAL (1 << 7) /* Use Wait Counter for RF DC Init Cal */
1859#define ENABLE_FAST_SETTLE_MODE (1 << 6) /* Enable Fast Settle Mode */
1860#define ENABLE_BB_DC_OFFSET_TRACKING (1 << 5) /* Enable BB DC Offset Tracking */
1861#define RESET_ACC_ON_GAIN_CHANGE (1 << 4) /* Reset Acc on Gain Change */
1862#define ENABLE_RF_OFFSET_TRACKING (1 << 3) /* Enable RF Offset Tracking */
1863#define DC_OFFSET_UPDATE(x) (((x) & 0x7) << 0) /* DC Offset Update<2:0> */
1864
1865/*
1866* REG_RF_CAL_GAIN_INDEX
1867*/
1868#define RF_MINIMUM_CALIBRATION_GAIN_INDEX(x) (((x) & 0x7F) << 0) /* RF Minimum Calibration Gain Index<6:0> */
1869
1870/*
1871* REG_SOI_THRESH
1872*/
1873#define RF_SOI_THRESH(x) (((x) & 0x7F) << 0) /* RF SOI Threshold<6:0> */
1874
1875/*
1876* REG_BB_DC_OFFSET_SHIFT
1877*/
1878#define INCREASE_COUNT_DURATION (1 << 7) /* Increase Count Duration */
1879#define BB_TRACKING_DECIMATE(x) (((x) & 0x3) << 5) /* BB Tracking Decimate<1:0> */
1880#define BB_DC_M_SHIFT(x) (((x) & 0x1F) << 0) /* BB DC M Shift<4:0> */
1881
1882/*
1883* REG_BB_DC_OFFSET_FAST_SETTLE_SHIFT
1884*/
1885#define READ_BACK_CH_SEL (1 << 7) /* Read Back CH Sel */
1886#define UPDATE_TRACKING_WORD (1 << 6) /* Update Tracking Word */
1887#define FORCE_RX_NULL (1 << 5) /* Force Rx Null */
1888#define BB_DC_TRACKING_FAST_SETTLE_M_SHIFT(x) (((x) & 0x1F) << 0) /* BB DC Tracking Fast Settle M Shift<4:0> */
1889
1890/*
1891* REG_BB_DC_OFFSET_ATTEN
1892*/
1893#define BB_DC_OFFSET_ATTEN(x) (((x) & 0xF) << 0) /* BB DC Offset Atten<3:0> */
1894
1895/*
1896* REG_RX1_BB_DC_WORD_I_MSB
1897*/
1898#define RX1_BB_DC_OFFSET_CORRECTION_WORD_I(x) (((x) & 0x7F) << 0) /* RX1 BB DC Offset Correction word I<14:8> */
1899
1900/*
1901* REG_RX1_BB_DC_WORD_Q_MSB
1902*/
1903#define RX1_BB_DC_OFFSET_CORRECTION_WORD_Q(x) (((x) & 0x7F) << 0) /* RX1 BB DC Offset Correction word Q<14:8> */
1904
1905/*
1906* REG_RX2_BB_DC_WORD_I_MSB
1907*/
1908#define RX2_BB_DC_OFFSET_CORRECTION_WORD_I(x) (((x) & 0x7F) << 0) /* RX2 BB DC Offset Correction word I<14:8> */
1909
1910/*
1911* REG_RX2_BB_DC_WORD_Q_MSB
1912*/
1913#define RX2_BB_DC_OFFSET_CORRECTION_WORD_Q(x) (((x) & 0x7F) << 0) /* RX2 BB DC Offset Correction word Q<14:8> */
1914
1915/*
1916* REG_BB_TRACK_CORR_WORD_I_MSB
1917*/
1918#define RX1RX2_BB_DC_OFFSET_TRACKING_CORRECTION_WORD_I(x) (((x) & 0x7F) << 0) /* RX1/RX2 BB DC Offset Tracking correction word I<14:8> */
1919
1920/*
1921* REG_BB_TRACK_CORR_WORD_Q_MSB
1922*/
1923#define RX1RX2_BB_DC_OFFSET_TRACKING_CORRECTION_WORD_Q(x) (((x) & 0x7F) << 0) /* RX1/RX2 BB DC Offset Tracking correction word Q<14:8> */
1924
1925/*
1926* REG_SYMBOL_LSB
1927*/
1928#define RX2_RSSI_SYMBOL (1 << 1) /* Rx2 RSSI symbol <0> */
1929#define RX1_RSSI_SYMBOL (1 << 0) /* Rx1 RSSI symbol <0> */
1930
1931/*
1932* REG_PREAMBLE_LSB
1933*/
1934#define RX2_RSSI_PREAMBLE (1 << 1) /* Rx2 RSSI preamble <0> */
1935#define RX1_RSSI_PREAMBLE (1 << 0) /* Rx1 RSSI preamble <0> */
1936
1937/*
1938* REG_RX1_RSSI_SYMBOL, REG_RX1_RSSI_PREAMBLE,
1939* REG_RX2_RSSI_SYMBOL, REG_RX2_RSSI_PREAMBLE
1940*/
1941#define RSSI_LSB_SHIFT 1
1942#define RSSI_LSB_MASK1 0x01
1943#define RSSI_LSB_MASK2 0x02
1944
1945/*
1946* REG_RX_PATH_GAIN_LSB
1947*/
1948#define RX_PATH_GAIN (1 << 0) /* Rx Path Gain<0> */
1949
1950/*
1951* REG_RX_DIFF_LNA_FORCE
1952*/
1953#define FORCE_RX2_LNA_GAIN (1 << 7) /* Force Rx2 LNA Gain */
1954#define RX2_LNA_BYPASS (1 << 6) /* Rx2 LNA Bypass */
1955#define FORCE_RX1_LNA_GAIN (1 << 3) /* Force Rx1 LNA Gain */
1956#define RX1_LNA_BYPASS (1 << 2) /* Rx1 LNA Bypass */
1957#define RX2_LNA_GAIN(x) (((x) & 0x3) << 4) /* Rx2 LNA Gain<1:0> */
1958#define RX1_LNA_GAIN(x) (((x) & 0x3) << 0) /* Rx1 LNA Gain<1:0> */
1959
1960/*
1961* REG_RX_LNA_BIAS_COARSE
1962*/
1963#define RX_LNA_BIAS_COARSE(x) (((x) & 0xF) << 0) /* Rx LNA Bias Coarse<3:0> */
1964
1965/*
1966* REG_RX_LNA_BIAS_FINE_0
1967*/
1968#define RX_LNA_PCASCODE_BIAS(x) (((x) & 0x7) << 5) /* Rx LNA p-Cascode Bias<2:0> */
1969#define RX_LNA_BIAS(x) (((x) & 0x1F) << 0) /* Rx LNA Bias<4:0> */
1970
1971/*
1972* REG_RX_LNA_BIAS_FINE_1
1973*/
1974#define RX_LNA_P_CASCODE_BIAS_FINE(x) (((x) & 0x3) << 0) /* Rx LNA p- Cascode Bias Fine<4:3> */
1975
1976/*
1977* REG_RX_MIX_GM_CONFIG
1978*/
1979#define RX_MIX_GM_CM_OUT(x) (((x) & 0x7) << 5) /* Rx Mix Gm CM Out<2:0> */
1980#define RX_MIX_GM_PLOAD(x) (((x) & 0x3) << 0) /* Rx Mix Gm pload <1:0> */
1981
1982/*
1983* REG_RX1_MIX_GM_FORCE
1984*/
1985#define FORCE_RX1_MIX_GM (1 << 6) /* Force Rx1 Mix Gm */
1986#define RX1_MIX_GM_GAIN(x) (((x) & 0x3F) << 0) /* Rx1 Mix Gm Gain<5:0> */
1987
1988/*
1989* REG_RX1_MIX_GM_BIAS_FORCE
1990*/
1991#define RX1_MIX_GM_BIAS(x) (((x) & 0x1F) << 0) /* Rx1 Mix Gm Bias<4:0> */
1992
1993/*
1994* REG_RX2_MIX_GM_FORCE
1995*/
1996#define FORCE_RX2_MIX_GM (1 << 6) /* Force Rx2 Mix Gm */
1997#define RX2_MIX_GM_GAIN(x) (((x) & 0x3F) << 0) /* Rx2 Mix Gm Gain<5:0> */
1998
1999/*
2000* REG_RX2_MIX_GM_BIAS_FORCE
2001*/
2002#define RX2_MIX_GM_BIAS(x) (((x) & 0x1F) << 0) /* Rx2 Mix Gm Bias<4:0> */
2003
2004/*
2005* REG_INPUT_A_MSBS
2006*/
2007#define INPUT_A_RX1_Q(x) (((x) & 0x3) << 6) /* Input A RX1 Q<9:8> */
2008#define INPUT_A_RX1_I(x) (((x) & 0x3) << 4) /* Input A RX1 I<9:8> */
2009#define INPUT_A_RX2_I(x) (((x) & 0x3) << 2) /* Input A RX2 I<9:8> */
2010#define INPUT_A_RX2_Q(x) (((x) & 0x3) << 0) /* Input A RX2 Q<9:8> */
2011
2012/*
2013* REG_INPUTS_BC_MSBS
2014*/
2015#define INPUTS_BC_RX1_Q(x) (((x) & 0x3) << 6) /* Inputs B&C RX1 Q<9:8> */
2016#define INPUTS_BC_RX1_I(x) (((x) & 0x3) << 4) /* Inputs B&C RX1 I<9:8> */
2017#define INPUTS_BC_RX2_I(x) (((x) & 0x3) << 2) /* Inputs B&C RX2 I<9:8> */
2018#define INPUTS_BC_RX2_Q(x) (((x) & 0x3) << 0) /* Inputs B&C RX2 Q<9:8> */
2019
2020/*
2021* REG_FORCE_OS_DAC
2022*/
2023#define FORCE_CGIN_DAC (1 << 2) /* Force CGin DAC */
2024
2025/*
2026* REG_RX_MIX_LO_CM
2027*/
2028#define RX_MIX_LO_CM(x) (((x) & 0x3F) << 0) /* Rx Mix LO CM<5:0> */
2029
2030/*
2031* REG_RX_CGB_SEG_ENABLE
2032*/
2033#define RX_CGB_SEG_ENABLE(x) (((x) & 0x3F) << 0) /* Rx CGB Seg Enable<5:0> */
2034
2035/*
2036* REG_RX_MIX_INPUTBIAS
2037*/
2038#define RX_CGB_INPUT_CM_SEL(x) (((x) & 0x3) << 4) /* Rx CGB Input CM Sel<1:0> */
2039#define RX_CGB_BIAS(x) (((x) & 0xF) << 0) /* Rx CGB Bias<3:0> */
2040
2041/*
2042* REG_RX_TIA_CONFIG
2043*/
2044#define TIA2_OVERRIDE_C (1 << 3) /* TIA2 Override C */
2045#define TIA2_OVERRIDE_R (1 << 2) /* TIA2 Override R */
2046#define TIA1_OVERRIDE_C (1 << 1) /* TIA1 Override C */
2047#define TIA1_OVERRIDE_R (1 << 0) /* TIA1 Override R */
2048#define TIA_SEL_CC(x) (((x) & 0x7) << 5) /* TIA Sel CC<2:0> */
2049
2050/*
2051* REG_TIA1_C_LSB
2052*/
2053#define TIA1_RF(x) (((x) & 0x3) << 6) /* TIA1 RF<1:0> */
2054#define TIA1_C_LSB(x) (((x) & 0x3F) << 0) /* TIA1 C LSB<5:0> */
2055
2056/*
2057* REG_TIA1_C_MSB
2058*/
2059#define TIA1_C_MSB(x) (((x) & 0x7F) << 0) /* TIA1 C MSB<6:0> */
2060
2061/*
2062* REG_TIA2_C_LSB
2063*/
2064#define TIA2_RF(x) (((x) & 0x3) << 6) /* TIA2 RF<1:0> */
2065#define TIA2_C_LSB(x) (((x) & 0x3F) << 0) /* TIA2 C LSB<5:0> */
2066
2067/*
2068* REG_TIA2_C_MSB
2069*/
2070#define TIA2_C_MSB(x) (((x) & 0x7F) << 0) /* TIA2 C MSB<6:0> */
2071
2072/*
2073* REG_RX1_BBF_R1A
2074*/
2075#define FORCE_RX1_RESISTORS (1 << 7) /* Force Rx1 Resistors */
2076#define RX1_BBF_R1A(x) (((x) & 0x3F) << 0) /* Rx1 BBF R1A<5:0> */
2077
2078/*
2079* REG_RX2_BBF_R1A
2080*/
2081#define FORCE_RX2_RESISTORS (1 << 7) /* Force Rx2 Resistors */
2082#define RX2_BBF_R1A(x) (((x) & 0x3F) << 0) /* Rx2 BBF R1A<5:0> */
2083
2084/*
2085* REG_RX1_TUNE_CTRL
2086*/
2087#define RX1_TUNE_RESAMPLE_PHASE (1 << 2) /* Rx1 Tune Resample Phase */
2088#define RX1_TUNE_RESAMPLE (1 << 1) /* Rx1 Tune Resample */
2089#define RX1_PD_TUNE (1 << 0) /* Rx1 PD Tune */
2090
2091/*
2092* REG_RX2_TUNE_CTRL
2093*/
2094#define RX2_TUNE_RESAMPLE_PHASE (1 << 2) /* Rx2 Tune Resam ple Phase */
2095#define RX2_TUNE_RESAMPLE (1 << 1) /* Rx2 Tune Resample */
2096#define RX2_PD_TUNE (1 << 0) /* Rx2 PD Tune */
2097
2098/*
2099* REG_RX_BBF_R2346
2100*/
2101#define TUNE_OVERRIDE (1 << 7) /* Tune Override */
2102#define RX_BBF_R2346(x) (((x) & 0x7) << 0) /* Rx BBF R2346<2:0> */
2103
2104/*
2105* REG_RX_BBF_C1_MSB
2106*/
2107#define RX_BBF_C1_MSB(x) (((x) & 0x3F) << 0) /* Rx BBF C1 MSB<5:0> */
2108
2109/*
2110* REG_RX_BBF_C1_LSB
2111*/
2112#define RX_BBF_C1_LSB(x) (((x) & 0x7F) << 0) /* Rx BBF C1 LSB<6:0> */
2113
2114/*
2115* REG_RX_BBF_C2_MSB
2116*/
2117#define RX_BBF_C2_MSB(x) (((x) & 0x3F) << 0) /* Rx BBF C2 MSB<5:0> */
2118
2119/*
2120* REG_RX_BBF_C2_LSB
2121*/
2122#define RX_BBF_C2_LSB(x) (((x) & 0x7F) << 0) /* Rx BBF C2 LSB<6:0> */
2123
2124/*
2125* REG_RX_BBF_C3_MSB
2126*/
2127#define RX_BBF_C3_MSB(x) (((x) & 0x3F) << 0) /* Rx BBF C3 MSB<5:0> */
2128
2129/*
2130* REG_RX_BBF_C3_LSB
2131*/
2132#define RX_BBF_C3_LSB(x) (((x) & 0x7F) << 0) /* Rx BBF C3 LSB<6:0> */
2133
2134/*
2135* REG_RX_BBF_CC1_CTR
2136*/
2137#define RX_BBF_CC1_CTR(x) (((x) & 0x7F) << 0) /* Rx BBF CC1 Ctr<6:0> */
2138
2139/*
2140* REG_RX_BBF_POW_RZ_BYTE0
2141*/
2142#define MUST_BE_ZERO (1 << 7) /* Must be zero */
2143#define RX1_BBF_POW_CTR(x) (((x) & 0x3) << 5) /* Rx1 BBF Pow Ctr<1:0> */
2144#define RX_BBF_RZ1_CTR(x) (((x) & 0x3) << 3) /* Rx BBF Rz1 Ctr<1:0> */
2145
2146/*
2147* REG_RX_BBF_CC2_CTR
2148*/
2149#define RX_BBF_CC2_CTR(x) (((x) & 0x7F) << 0) /* Rx BBF CC2 Ctr<6:0> */
2150
2151/*
2152* REG_RX_BBF_POW_RZ_BYTE1
2153*/
2154#define RX_BBF_POW3_CTR(x) (((x) & 0x3) << 6) /* Rx BBF Pow3 Ctr<1:0> */
2155#define RX_BBF_RZ3_CTR(x) (((x) & 0x3) << 4) /* Rx BBF RZ3 Ctr<1:0> */
2156#define RX_BBF_POW2_CTR(x) (((x) & 0x3) << 2) /* Rx BBF Pow2 Ctr<1:0> */
2157#define RX_BBF_RZ2_CTR(x) (((x) & 0x3) << 0) /* Rx BBF Rz2 Ctr<1:0> */
2158
2159/*
2160* REG_RX_BBF_CC3_CTR
2161*/
2162#define RX_BBF_CC3_CTR(x) (((x) & 0x7F) << 0) /* Rx BBF CC3 Ctr<6:0> */
2163
2164/*
2165* REG_RX_BBF_TUNE
2166*/
2167#define RXBBF_BYPASS_BIAS_R (1 << 7) /* RxBBF Bypass Bias R */
2168#define RX_BBF_R5_TUNE (1 << 4) /* Rx BBF R5 Tune */
2169#define RX1_BBF_TUNE_COMP_I (1 << 3) /* Rx1 BBF Tune Comp I */
2170#define RX1_BBF_TUNE_COMP_Q (1 << 2) /* Rx1 BBF Tune Comp Q */
2171#define RX2_BBF_TUNE_COMP_I (1 << 1) /* Rx2 BBF Tune Comp I */
2172#define RX2_BBF_TUNE_COMP_Q (1 << 0) /* Rx2 BBF Tune Comp Q */
2173#define RX_BBF_TUNE_CTR(x) (((x) & 0x3) << 5) /* Rx BBF Tune Ctr<1:0> */
2174
2175/*
2176* REG_RX1_BBF_MAN_GAIN
2177*/
2178#define RX1_BBF_FORCE_GAIN (1 << 5) /* Rx1 BBF Force Gain */
2179#define RX1_BBF_BQ_GAIN(x) (((x) & 0x3) << 3) /* Rx1 BBF BQ Gain<1:0> */
2180#define RX1_BBF_POLE_GAIN(x) (((x) & 0x7) << 0) /* Rx1 BBF Pole Gain<2:0> */
2181
2182/*
2183* REG_RX2_BBF_MAN_GAIN
2184*/
2185#define RX2_BBF_FORCE_GAIN (1 << 5) /* Rx2 BBF Force Gain */
2186#define RX2_BBF_BQ_GAIN(x) (((x) & 0x3) << 3) /* Rx2 BBF BQ Gain<1:0> */
2187#define RX2_BBF_POLE_GAIN(x) (((x) & 0x7) << 0) /* Rx2 BBF Pole Gain<2:0> */
2188
2189/*
2190* REG_RX_BBF_TUNE_CONFIG
2191*/
2192#define RX_TUNE_EVALTIME (1 << 4) /* Rx Tune Evaltime */
2193#define RX_BBF_TUNE_DIVIDE (1 << 0) /* RX BBF Tune Divide<8> */
2194#define TUNE_COMP_MASK(x) (((x) & 0x3) << 5) /* Tune Comp Mask <1:0> */
2195#define RX_TUNE_MODE(x) (((x) & 0x7) << 1) /* Rx Tune Mode<2:0> */
2196
2197/*
2198* REG_POLE_GAIN
2199*/
2200#define POLE_GAIN_TUNE(x) (((x) & 0x3) << 0) /* Pole Gain Tune<1:0> */
2201
2202/*
2203* REG_RX_BBBW_MHZ
2204*/
2205#define RX_TUNE_BBBW_MHZ(x) (((x) & 0x1F) << 0) /* Rx Tune BBBW MHz<4::0> */
2206
2207/*
2208* REG_RX_BBBW_KHZ
2209*/
2210#define RX_TUNE_BBBW_KHZ(x) (((x) & 0x7F) << 0) /* Rx Tune BBBW kHz<6:0> */
2211
2212/*
2213* REG_RX_PFD_CONFIG
2214*/
2215#define BYPASS_LD_SYNTH (1 << 0) /* Bypass Ld Synth */
2216
2217/*
2218* REG_RX_INTEGER_BYTE_1
2219*/
2220#define SYNTH_INTEGER_WORD(x) (((x) & 0x7) << 0) /* Synthesizer Integer Word<10:8> */
2221
2222/*
2223* REG_RX_FRACT_BYTE_2
2224*/
2225#define SYNTH_FRACT_WORD(x) (((x) & 0x7F) << 0) /* Synthesizer Fractional Word <22:16> */
2226
2227/*
2228* REG_RX_FORCE_VCO_TUNE_1
2229*/
2230#define VCO_CAL_OFFSET(x) (((x) & 0xF) << 3) /* VCO Cal Offset<3:0> */
2231
2232/*
2233* REG_RX_ALC_VARACTOR
2234*/
2235#define INIT_ALC_VALUE(x) (((x) & 0xF) << 4) /* Init ALC Value<3:0> */
2236#define VCO_VARACTOR(x) (((x) & 0xF) << 0) /* VCO Varactor<3:0> */
2237
2238/*
2239* REG_RX_VCO_OUTPUT
2240*/
2241#define PORB_VCO_LOGIC (1 << 6) /* PORb VCO Logic */
2242#define VCO_OUTPUT_LEVEL(x) (((x) & 0xF) << 0) /* VCO Output Level<3:0> */
2243
2244/*
2245* REG_RX_CP_CURRENT
2246*/
2247#define CHARGE_PUMP_CURRENT(x) (((x) & 0x3F) << 0) /* Charge Pump Current<5:0> */
2248
2249/*
2250* REG_RX_CP_OFFSET
2251*/
2252#define SYNTH_RECAL (1 << 7) /* Synth Re-Cal */
2253
2254/*
2255* REG_RX_CP_CONFIG
2256*/
2257#define HALF_VCO_CAL_CLK (1 << 7) /* Half Vco Cal Clk */
2258#define CP_OFFSET_OFF (1 << 4) /* CP Offset Off */
2259#define F_CPCAL (1 << 3) /* F Cpcal */
2260#define CP_CAL_ENABLE (1 << 2) /* Cp Cal Enable */
2261
2262/*
2263* REG_RX_LOOP_FILTER_1
2264*/
2265#define LOOP_FILTER_C2(x) (((x) & 0xF) << 4) /* Loop Filter C2<3:0> */
2266#define LOOP_FILTER_C1(x) (((x) & 0xF) << 0) /* Loop Filter C1<3:0> */
2267
2268/*
2269* REG_RX_LOOP_FILTER_2
2270*/
2271#define LOOP_FILTER_R1(x) (((x) & 0xF) << 4) /* Loop Filter R1<3:0> */
2272#define LOOP_FILTER_C3(x) (((x) & 0xF) << 0) /* Loop Filter C3<3:0> */
2273
2274/*
2275* REG_RX_LOOP_FILTER_3
2276*/
2277#define LOOP_FILTER_BYPASS_R3 (1 << 7) /* Loop Filter Bypass R3 */
2278#define LOOP_FILTER_BYPASS_R1 (1 << 6) /* Loop Filter Bypass R1 */
2279#define LOOP_FILTER_BYPASS_C2 (1 << 5) /* Loop Filter Bypass C2 */
2280#define LOOP_FILTER_BYPASS_C1 (1 << 4) /* Loop Filter Bypass C1 */
2281#define LOOP_FILTER_R3(x) (((x) & 0xF) << 0) /* Loop Filter R3<3:0> */
2282
2283/*
2284* REG_RX_DITHERCP_CAL
2285*/
2286#define FORCED_CP_CAL_WORD(x) (((x) & 0xF) << 0) /* Forced CP Cal Word<3:0> */
2287
2288/*
2289* REG_RX_VCO_BIAS_1
2290*/
2291#define VCO_BIAS_TCF(x) (((x) & 0x3) << 3) /* VCO Bias Tcf<1:0> */
2292#define VCO_BIAS_REF(x) (((x) & 0x7) << 0) /* VCO Bias Ref<2:0> */
2293
2294/*
2295* REG_RX_CAL_STATUS
2296*/
2297#define CP_CAL_VALID (1 << 7) /* CP Cal Valid */
2298#define CP_CAL_DONE (1 << 5) /* CP Cal Done */
2299#define VCO_CAL_BUSY (1 << 4) /* VCO Cal Busy */
2300#define CP_CAL_WORD(x) (((x) & 0xF) << 0) /* CP Cal Word<3:0> */
2301
2302/*
2303* REG_RX_VCO_CAL_REF
2304*/
2305#define VCO_CAL_REF_TCF(x) (((x) & 0x7) << 0) /* VCO Cal Ref Tcf<2:0> */
2306
2307/*
2308* REG_RX_VCO_PD_OVERRIDES
2309*/
2310#define POWER_DOWN_VARACTOR_REF (1 << 3) /* Power Down Varactor Ref */
2311#define PWR_DOWN_VARACT_REF_TCF (1 << 2) /* Pwr Down Varact Ref Tcf */
2312#define POWER_DOWN_CAL_TCF (1 << 1) /* Power Down Cal Tcf */
2313#define POWER_DOWN_VCO_BUFFFER (1 << 0) /* Power Down VCO Bufffer */
2314
2315/*
2316* REG_RX_CP_OVERRANGE_VCO_LOCK
2317*/
2318#define CP_OVRG_HIGH (1 << 7) /* CP Ovrg High */
2319#define CP_OVRG_LOW (1 << 6) /* CP Ovrg Low */
2320#define VCO_LOCK (1 << 1) /* Lock */
2321
2322/*
2323* REG_RX_VCO_LDO
2324*/
2325#define VCO_LDO_BYPASS (1 << 7) /* VCO LDO Bypass */
2326#define VCO_LDO_INRUSH(x) (((x) & 0x3) << 5) /* VCO LDO Inrush<1:0> */
2327#define VCO_LDO_SEL(x) (((x) & 0x7) << 2) /* VCO LDO Sel<2:0> */
2328#define VCO_LDO_VDROP_SEL(x) (((x) & 0x3) << 0) /* VCO LDO Vdrop Sel<1:0> */
2329
2330/*
2331* REG_RX_VCO_CAL
2332*/
2333#define VCO_CAL_EN (1 << 7) /* VCO Cal En */
2334#define VCO_CAL_ALC_WAIT(x) (((x) & 0x7) << 4) /* VCO Cal ALC Wait <2:0> */
2335#define VCO_CAL_COUNT(x) (((x) & 0x3) << 2) /* VCO Cal Count <1:0> */
2336
2337/*
2338* REG_RX_LOCK_DETECT_CONFIG
2339*/
2340#define LOCK_DETECT_COUNT(x) (((x) & 0x3) << 2) /* Lock Detect Count<1:0> */
2341#define LOCK_DETECT_MODE(x) (((x) & 0x3) << 0) /* Lock Detect Mode<1:0> */
2342
2343/*
2344* REG_RX_CP_LEVEL_DETECT
2345*/
2346#define CP_LEVEL_DETECT_POWER_DOWN (1 << 6) /* CP Level Detect Power Down */
2347#define CP_LEVEL_THRESH_LOW(x) (((x) & 0x7) << 3) /* CP Level Threshold Low<2:0> */
2348#define CP_LEVEL_THRESH_HIGH(x) (((x) & 0x7) << 0) /* CP Level Threshold High<2:0> */
2349
2350/*
2351* REG_RX_DSM_SETUP_0
2352*/
2353#define DSM_PROG(x) (((x) & 0xF) << 0) /* DSM Prog<3:0> */
2354
2355/*
2356* REG_RX_DSM_SETUP_1
2357*/
2358#define SIF_CLOCK (1 << 6) /* SIF clock */
2359#define SIF_RESET_BAR (1 << 5) /* SIF Reset Bar */
2360#define SIF_ADDR(x) (((x) & 0x1F) << 0) /* SIF Addr<4:0> */
2361
2362/*
2363* REG_RX_CORRECTION_WORD0
2364*/
2365#define UPDATE_FREQ_WORD (1 << 7) /* Update Freq Word */
2366#define READ_EFFECTIVE_TUNING_WORD (1 << 5) /* Read Effective Tuning Word */
2367#define FREQ_CORRECTION_WORD_MSB(x) (((x) & 0x1F) << 0) /* Frequency Correction Word<11:7> */
2368
2369/*
2370* REG_RX_CORRECTION_WORD1
2371*/
2372#define UPDATE_FREQ_WORD (1 << 7) /* Update Freq Word */
2373#define FREQ_CORRECTION_WORD_LSB(x) (((x) & 0x7F) << 0) /* Frequency Correction Word<6:0> */
2374
2375/*
2376* REG_RX_VCO_VARACTOR_CTRL_0
2377*/
2378#define VCO_VARACTOR_REFERENCE_TCF(x) (((x) & 0x7) << 4) /* VCO Varactor Reference Tcf<2:0> */
2379#define VCO_VARACTOR_OFFSET(x) (((x) & 0xF) << 0) /* VCO Varactor Offset<3:0> */
2380
2381/*
2382* REG_RX_VCO_VARACTOR_CTRL_1
2383*/
2384#define VCO_VARACTOR_REFERENCE(x) (((x) & 0xF) << 0) /* VCO Varactor Reference<3:0> */
2385
2386/*
2387* REG_RX_FAST_LOCK_SETUP
2388*/
2389#define RX_FAST_LOCK_LOAD_SYNTH (1 << 3) /* Rx Fast Lock Load Synth */
2390#define RX_FAST_LOCK_PROFILE_INIT (1 << 2) /* Rx Fast Lock Profile Init */
2391#define RX_FAST_LOCK_PROFILE_PIN_SELECT (1 << 1) /* Rx Fast Lock Profile Pin Select */
2392#define RX_FAST_LOCK_MODE_ENABLE (1 << 0) /* Rx Fast Lock Mode Enable */
2393#define RX_FAST_LOCK_PROFILE(x) (((x) & 0x7) << 5) /* Rx Fast Lock Profile<2:0> */
2394
2395/*
2396* REG_RX_FAST_LOCK_PROGRAM_ADDR
2397*/
2398#define RX_FAST_LOCK_PROFILE_ADDR(x) (((x) & 0x7) << 4) /* Rx Fast Lock Profile<2:0> */
2399#define RX_FAST_LOCK_PROFILE_WORD(x) (((x) & 0xF) << 0) /* Configuration Word <3:0> */
2400
2401
2402/*
2403* REG_RX_FAST_LOCK_PROGRAM_CTRL
2404*/
2405#define RX_FAST_LOCK_PROGRAM_WRITE (1 << 1) /* Rx Fast Lock Program Write */
2406#define RX_FAST_LOCK_PROGRAM_CLOCK_ENABLE (1 << 0) /* Rx Fast Lock Program Clock Enable */
2407
2408#define RX_FAST_LOCK_CONFIG_WORD_NUM 16
2409
2410/*
2411* REG_RX_LO_GEN_POWER_MODE
2412*/
2413#define RX_LO_GEN_POWER_MODE(x) (((x) & 0x3) << 4) /* Power Mode<3:0> */
2414
2415/*
2416* REG_TX_PFD_CONFIG
2417*/
2418#define DIV_TEST_EN (1 << 5) /* Div Test En */
2419#define PFD_CLK_EDGE (1 << 1) /* PFD Clk Edge */
2420#define BYPASS_LD_SYNTH (1 << 0) /* Bypass Ld Synth */
2421#define PFD_WIDTH(x) (((x) & 0x3) << 2) /* PFD Width <1:0> */
2422
2423/*
2424* REG_TX_INTEGER_BYTE_1
2425*/
2426#define SDM_BYPASS (1 << 7) /* SDM Bypass */
2427#define SDM_POWER_DOWN (1 << 6) /* SDM Power Down */
2428#define SYNTH_INTEGER_WORD(x) (((x) & 0x7) << 0) /* Synthesizer Integer Word<10:8> */
2429
2430/*
2431* REG_TX_FRACT_BYTE_2
2432*/
2433#define SYNTH_FRACT_WORD(x) (((x) & 0x7F) << 0) /* Synthesizer Fractional Word <22:16> */
2434
2435/*
2436* REG_TX_FORCE_ALC
2437*/
2438#define FORCE_ALC_ENABLE (1 << 7) /* Force ALC Enable */
2439#define FORCE_ALC_WORD(x) (((x) & 0x7F) << 0) /* Force ALC Word<6:0> */
2440
2441/*
2442* REG_TX_FORCE_VCO_TUNE_1
2443*/
2444#define BYPASS_LOAD_DELAY (1 << 7) /* Bypass Load Delay */
2445#define FORCE_VCO_TUNE_ENABLE (1 << 1) /* Force VCO Tune Enable */
2446#define FORCE_VCO_TUNE (1 << 0) /* Force VCO Tune */
2447#define VCO_CAL_OFFSET(x) (((x) & 0xF) << 3) /* VCO Cal Offset<3:0> */
2448
2449/*
2450* REG_TX_ALCVARACT_OR
2451*/
2452#define INIT_ALC_VALUE(x) (((x) & 0xF) << 4) /* Init ALC Value<3:0> */
2453#define VCO_VARACTOR(x) (((x) & 0xF) << 0) /* VCO Varactor<3:0> */
2454
2455/*
2456* REG_TX_VCO_OUTPUT
2457*/
2458#define PORB_VCO_LOGIC (1 << 6) /* PORb VCO Logic */
2459#define VCO_OUTPUT_LEVEL(x) (((x) & 0xF) << 0) /* VCO Output Level<3:0> */
2460
2461/*
2462* REG_TX_CP_CURRENT
2463*/
2464#define TX_CP_CURRENT_DFLT (1 << 7) /* Set to 1 */
2465#define VTUNE_FORCE (1 << 6) /* Vtune Force */
2466#define CHARGE_PUMP_CURRENT(x) (((x) & 0x3F) << 0) /* Charge Pump Current<5:0> */
2467
2468/*
2469* REG_TX_CP_OFFSET
2470*/
2471#define SYNTH_RECAL (1 << 7) /* Synth Re-Cal */
2472#define CHARGE_PUMP_OFFSET(x) (((x) & 0x3F) << 0) /* Charge Pump Offset<5:0> */
2473
2474/*
2475* REG_TX_CP_CONFIG
2476*/
2477#define HALF_VCO_CAL_CLK (1 << 7) /* Half Vco Cal Clk */
2478#define DITHER_MODE (1 << 6) /* Dither Mode */
2479#define CP_OFFSET_OFF (1 << 4) /* Cp Offset Off */
2480#define F_CPCAL (1 << 3) /* F Cpcal */
2481#define CP_CAL_ENABLE (1 << 2) /* Cp Cal Enable */
2482#define CP_TEST(x) (((x) & 0x3) << 0) /* Cp Test <1:0> */
2483
2484/*
2485* REG_TX_LOOP_FILTER_1
2486*/
2487#define LOOP_FILTER_C2(x) (((x) & 0xF) << 4) /* Loop Filter C2<3:0> */
2488#define LOOP_FILTER_C1(x) (((x) & 0xF) << 0) /* Loop Filter C1<3:0> */
2489
2490/*
2491* REG_TX_LOOP_FILTER_2
2492*/
2493#define LOOP_FILTER_R1(x) (((x) & 0xF) << 4) /* Loop Filter R1<3:0> */
2494#define LOOP_FILTER_C3(x) (((x) & 0xF) << 0) /* Loop Filter C3<3:0> */
2495
2496/*
2497* REG_TX_LOOP_FILTER_3
2498*/
2499#define LOOP_FILTER_BYPASS_R3 (1 << 7) /* Loop Filter Bypass R3 */
2500#define LOOP_FILTER_BYPASS_R1 (1 << 6) /* Loop Filter Bypass R1 */
2501#define LOOP_FILTER_BYPASS_C2 (1 << 5) /* Loop Filter Bypass C2 */
2502#define LOOP_FILTER_BYPASS_C1 (1 << 4) /* Loop Filter Bypass C1 */
2503#define LOOP_FILTER_R3(x) (((x) & 0xF) << 0) /* Loop Filter R3<3:0> */
2504
2505/*
2506* REG_TX_DITHERCP_CAL
2507*/
2508#define NUMBER_SDM_DITHER_BITS(x) (((x) & 0xF) << 4) /* Number SDM Dither Bits<3:0> */
2509#define FORCED_CP_CAL_WORD(x) (((x) & 0xF) << 0) /* Forced CP Cal Word<3:0> */
2510
2511/*
2512* REG_TX_VCO_BIAS_1
2513*/
2514#define MUST_BE_ZEROS(x) (((x) & 0x3) << 5) /* Must be zeros */
2515#define VCO_BIAS_TCF(x) (((x) & 0x3) << 3) /* VCO Bias Tcf<1:0> */
2516#define VCO_BIAS_REF(x) (((x) & 0x7) << 0) /* VCO Bias Ref<2:0> */
2517
2518/*
2519* REG_TX_VCO_BIAS_2
2520*/
2521#define VCO_BYPASS_BIAS_DAC_R (1 << 7) /* VCO Bypass Bias DAC R */
2522#define VCO_COMP_BYPASS_BIAS_R (1 << 4) /* VCO Comp Bypass Bias R */
2523#define BYPASS_PRESCALE_R (1 << 3) /* Bypass Prescale R */
2524#define LAST_ALC_ENABLE (1 << 2) /* Last ALC Enable */
2525#define PRESCALE_BIAS(x) (((x) & 0x3) << 0) /* Prescale Bias <1:0> */
2526
2527/*
2528* REG_TX_CAL_STATUS
2529*/
2530#define CP_CAL_VALID (1 << 7) /* CP Cal Valid */
2531#define COMP_OUT (1 << 6) /* Comp Out */
2532#define CP_CAL_DONE (1 << 5) /* CP Cal Done */
2533#define VCO_CAL_BUSY (1 << 4) /* VCO Cal Busy */
2534#define CP_CAL_WORD(x) (((x) & 0xF) << 0) /* CP Cal Word<3:0> */
2535
2536/*
2537* REG_TX_VCO_CAL_REF
2538*/
2539#define VCO_CAL_REF_MONITOR (1 << 3) /* VCO Cal Ref Monitor */
2540#define VCO_CAL_REF_TCF(x) (((x) & 0x7) << 0) /* VCO Cal Ref Tcf<2:0> */
2541
2542/*
2543* REG_TX_VCO_PD_OVERRIDES
2544*/
2545#define POWER_DOWN_VARACTOR_REF (1 << 3) /* Power Down Varactor Ref */
2546#define POWER_DOWN_VARACT_REF_TCF (1 << 2) /* Power Down Varact Ref Tcf */
2547#define POWER_DOWN_CAL_TCF (1 << 1) /* Power Down Cal Tcf */
2548#define POWER_DOWN_VCO_BUFFFER (1 << 0) /* Power Down VCO Bufffer */
2549
2550/*
2551* REG_TX_CP_OVERRANGE_VCO_LOCK
2552*/
2553#define CP_OVRG_HIGH (1 << 7) /* CP Ovrg High */
2554#define CP_OVRG_LOW (1 << 6) /* CP Ovrg Low */
2555#define VCO_LOCK (1 << 1) /* Lock */
2556
2557/*
2558* REG_TX_VCO_LDO
2559*/
2560#define VCO_LDO_BYPASS (1 << 7) /* VCO LDO Bypass */
2561#define VCO_LDO_INRUSH(x) (((x) & 0x3) << 5) /* VCO LDO Inrush<1:0> */
2562#define VCO_LDO_VOUT_SEL(x) (((x) & 0x7) << 2) /* VCO LDO Vout Sel<2:0> */
2563#define VCO_LDO_VDROP_SEL(x) (((x) & 0x3) << 0) /* VCO LDO Vdrop Sel<1:0> */
2564
2565/*
2566* REG_TX_VCO_CAL
2567*/
2568#define VCO_CAL_EN (1 << 7) /* VCO Cal En */
2569#define VCO_CAL_ALC_WAIT(x) (((x) & 0x7) << 4) /* VCO Cal ALC Wait<2:0) */
2570#define VCO_CAL_COUNT(x) (((x) & 0x3) << 2) /* VCO Cal Count<1:0> */
2571#define FB_CLOCK_ADV(x) (((x) & 0x3) << 0) /* FB Clock Adv<1:0> */
2572
2573/*
2574* REG_TX_LOCK_DETECT_CONFIG
2575*/
2576#define LOCK_DETECT_COUNT(x) (((x) & 0x3) << 2) /* Lock Detect Count<1:0> */
2577#define LOCK_DETECT_MODE(x) (((x) & 0x3) << 0) /* Lock Detect Mode<1:0> */
2578
2579/*
2580* REG_TX_CP_LEVEL_DETECT
2581*/
2582#define CP_LEVEL_DETECT_POWER_DOWN (1 << 6) /* CP Level Detect Power Down */
2583#define CP_LEVEL_DETECT_THRESH_LOW(x) (((x) & 0x7) << 3) /* CP Level Detect Threshold Low<2:0> */
2584#define CP_LEVEL_DETECT_THRESH_HIGH(x) (((x) & 0x7) << 0) /* CP Level Detect Threshold High<2:0> */
2585
2586/*
2587* REG_TX_DSM_SETUP_0
2588*/
2589#define DSM_PROG(x) (((x) & 0xF) << 0) /* DSM Prog<3:0> */
2590
2591/*
2592* REG_TX_DSM_SETUP_1
2593*/
2594#define SIF_CLOCK (1 << 6) /* SIF clock */
2595#define SIF_RESET_BAR (1 << 5) /* SIF Reset Bar */
2596#define SIF_ADDR(x) (((x) & 0x1F) << 0) /* SIF Addr<4:0> */
2597
2598/*
2599* REG_TX_CORRECTION_WORD0
2600*/
2601#define UPDATE_FREQ_WORD (1 << 7) /* Update Freq Word */
2602#define READ_EFFECTIVE_TUNING_WORD (1 << 5) /* Read Effective Tuning Word */
2603#define FREQ_CORRECTION_WORD_MSB(x) (((x) & 0x1F) << 0) /* Frequency Correction Word<11:7> */
2604
2605/*
2606* REG_TX_CORRECTION_WORD1
2607*/
2608#define UPDATE_FREQ_WORD (1 << 7) /* Update Freq Word */
2609#define FREQ_CORRECTION_WORD_LSB(x) (((x) & 0x7F) << 0) /* Frequency Correction Word<6:0> */
2610
2611/*
2612* REG_TX_VCO_VARACTOR_CTRL_0
2613*/
2614#define VCO_VARACTOR_REFERENCE_TCF(x) (((x) & 0x7) << 4) /* VCO Varactor Reference Tcf<2:0> */
2615#define VCO_VARACTOR_OFFSET(x) (((x) & 0xF) << 0) /* VCO Varactor Offset<3:0> */
2616
2617/*
2618* REG_TX_VCO_VARACTOR_CTRL_1
2619*/
2620#define VCO_VARACTOR_REFERENCE(x) (((x) & 0xF) << 0) /* VCO Varactor Reference<3:0> */
2621
2622/*
2623* REG_DCXO_COARSE_TUNE
2624*/
2625#define DCXO_TUNE_COARSE(x) (((x) & 0x3F) << 0) /* DCXO Tune Coarse<5:0> */
2626
2627/*
2628* REG_DCXO_FINE_TUNE_LOW
2629*/
2630#define DCXO_TUNE_FINE_LOW(x) (((x) & 0x1F) << 3) /* DCXO Tune Fine<4:0> */
2631
2632/*
2633* REG_DCXO_FINE_TUNE_HIGH
2634*/
2635#define DCXO_TUNE_FINE_HIGH(x) ((x) >> 5) /* DCXO Tune Fine<12:5> */
2636
2637/*
2638* REG_DCXO_CONFIG
2639*/
2640#define MUST_BE_ZERO (1 << 7) /* Must be zero */
2641#define DCXO_RTAIL(x) (((x) & 0x7) << 4) /* DCXO Rtail<2:0> */
2642#define DCXO_RD(x) (((x) & 0x3) << 2) /* DCXO Rd<1:0> */
2643
2644/*
2645* REG_DCXO_TEMPCO_ADDR
2646*/
2647#define DCXO_TEMPCO_EN (1 << 7) /* DCXO Tempco En */
2648#define DCXO_TEMPCO_CLK (1 << 6) /* DCXO Tempco Clk */
2649#define DCXO_TEMPERATURE_COEF_ADDRESS(x) (((x) & 0x3F) << 0) /* DCXO Temperature Coefficient Address<5:0> */
2650
2651/*
2652* REG_TX_FAST_LOCK_SETUP
2653*/
2654#define TX_FAST_LOCK_LOAD_SYNTH (1 << 3) /* Tx Fast Lock Load Synth */
2655#define TX_FAST_LOCK_PROFILE_INIT (1 << 2) /* Tx Fast Lock Profile Init */
2656#define TX_FAST_LOCK_PROFILE_PIN_SELECT (1 << 1) /* Tx Fast Lock Profile Pin Select */
2657#define TX_FAST_LOCK_MODE_ENABLE (1 << 0) /* Tx Fast Lock Mode Enable */
2658#define TX_FAST_LOCK_PROFILE(x) (((x) & 0x7) << 5) /* Tx Fast Lock Profile<2:0> */
2659
2660/*
2661* REG_TX_FAST_LOCK_PROGRAM_CTRL
2662*/
2663#define TX_FAST_LOCK_PROGRAM_WRITE (1 << 1) /* Tx Fast Lock Program Write */
2664#define TX_FAST_LOCK_PROGRAM_CLOCK_ENABLE (1 << 0) /* Tx Fast Lock Program Clock Enable */
2665
2666/*
2667* REG_TX_LO_GEN_POWER_MODE
2668*/
2669#define TX_LO_GEN_POWER_MODE(x) (((x) & 0xF) << 4) /* Power Mode<3:0> */
2670
2671/*
2672* REG_BANDGAP_CONFIG0
2673*/
2674#define POWER_DOWN_BANDGAP_REF (1 << 7) /* Power Down Bandgap Ref */
2675#define MASTER_BIAS_FILTER_BYPASS (1 << 6) /* Master Bias Filter Bypass */
2676#define MASTER_BIAS_REF_SEL (1 << 5) /* Master Bias Ref Sel */
2677#define MASTER_BIAS_TRIM(x) (((x) & 0x1F) << 0) /* Master Bias Trim<4:0> */
2678
2679/*
2680* REG_BANDGAP_CONFIG1
2681*/
2682#define VCO_LDO_FILTER_BYPASS (1 << 7) /* VCO LDO Filter Bypass */
2683#define VCO_LDO_REF_SEL (1 << 6) /* VCO LDO Ref Sel */
2684#define BANDGAP_REF_RESET (1 << 5) /* Bandgap Ref Reset */
2685#define BANDGAP_TEMP_TRIM(x) (((x) & 0x1F) << 0) /* Bandgap Temp Trim<4:0> */
2686
2687/*
2688* REG_REF_DIVIDE_CONFIG_1
2689*/
2690#define REF_DIVIDE_CONFIG_1_DFLT (1 << 2) /* Set to 1 */
2691#define RX_REF_RESET_BAR (1 << 1) /* Rx Ref Reset Bar */
2692#define RX_REF_DIVIDER_MSB (1 << 0) /* Rx Ref Divider<1> */
2693
2694/*
2695* REG_REF_DIVIDE_CONFIG_2
2696*/
2697#define RX_REF_DIVIDER_LSB (1 << 7) /* Rx Ref Divider< 0> */
2698#define TX_REF_RESET_BAR (1 << 4) /* Tx Ref Reset Bar */
2699#define RX_REF_DOUBLER_FB_DELAY(x) (((x) & 0x3) << 5) /* Rx Ref Doubler FB Delay<1:0> */
2700#define TX_REF_DIVIDER(x) (((x) & 0x3) << 2) /* Tx Ref Divider<1:0> */
2701#define TX_REF_DOUBLER_FB_DELAY(x) (((x) & 0x3) << 0) /* Tx Ref Doubler FB Delay<1:0> */
2702
2703/*
2704* REG_GAIN_RX1,2
2705*/
2706#define FULL_TABLE_GAIN_INDEX(x) (((x) & 0x7F) << 0) /* Full Table Gain Index Rx1/LMT Gain Rx1<6:0> */
2707
2708/*
2709* REG_LPF_GAIN_RX1,2
2710*/
2711#define LPF_GAIN_RX(x) (((x) & 0x1F) << 0) /* LPF gain Rx1<4:0> */
2712
2713/*
2714* REG_DIG_GAIN_RX1,2
2715*/
2716#define DIGITAL_GAIN_RX(x) (((x) & 0x1F) << 0) /* Digital gain Rx1<4:0> */
2717
2718/*
2719* REG_FAST_ATTACK_STATE
2720*/
2721#define FAST_ATTACK_STATE_RX2(x) (((x) & 0x7) << 4) /* Fast Attack State Rx2<2:0> */
2722#define FAST_ATTACK_STATE_RX1(x) (((x) & 0x7) << 0) /* Fast Attack State Rx1<2:0> */
2723#define FAST_ATK_MASK 0x7
2724#define RX1_FAST_ATK_SHIFT 0
2725#define RX2_FAST_ATK_SHIFT 4
2726#define FAST_ATK_RESET 0
2727#define FAST_ATK_PEAK_DETECT 1
2728#define FAST_ATK_PWR_MEASURE 2
2729#define FAST_ATK_FINAL_SETTELING 3
2730#define FAST_ATK_FINAL_OVER 4
2731#define FAST_ATK_GAIN_LOCKED 5
2732
2733/*
2734* REG_SLOW_LOOP_STATE
2735*/
2736#define SLOW_LOOP_STATE_RX2(x) (((x) & 0x7) << 4) /* Slow Loop State Rx2<2:0> */
2737#define SLOW_LOOP_STATE_RX1(x) (((x) & 0x7) << 0) /* Slow Loop State Rx1<2:0> */
2738
2739
2740/*
2741* REG_OVRG_SIGS_RX1,2
2742*/
2743#define GAIN_LOCK_1 (1 << 6) /* Gain Lock 1 */
2744#define LOW_POWER_1 (1 << 5) /* Low Power 1 */
2745#define LARGE_LMT_OL (1 << 4) /* Large LMT OL */
2746#define SMALL_LMT_OL (1 << 3) /* Small LMT OL */
2747#define LARGE_ADC_OL (1 << 2) /* Large ADC OL */
2748#define SMALL_ADC_OL (1 << 1) /* Small ADC OL */
2749#define DIG_SAT (1 << 0) /* Dig Sat */
2750/*
2751* REG_CTRL
2752*/
2753#define CTRL_ENABLE (1 << 0) /* Set to 1 */
2754
2755/*
2756* REG_BIST_CONFIG
2757*/
2758#define TONE_PRBS (1 << 1) /* Tone/ PRBS */
2759#define BIST_ENABLE (1 << 0) /* BIST Enable */
2760#define TONE_FREQ(x) (((x) & 0x3) << 6) /* Tone Frequency<1:0> */
2761#define TONE_LEVEL(x) (((x) & 0x3) << 4) /* Tone Level<1:0> */
2762#define BIST_CTRL_POINT(x) (((x) & 0x3) << 2) /* BIST Control Point <1:0> */
2763
2764/*
2765* REG_OBSERVE_CONFIG
2766*/
2767#define DATA_PORT_SP_HD_LOOP_TEST_OE (1 << 7) /* Data Port SP, HD Loop Test OE */
2768#define RX_MASK (1 << 6) /* Rx Mask */
2769#define CHANNEL (1 << 5) /* Channel */
2770#define DATA_PORT_LOOP_TEST_ENABLE (1 << 0) /* Data Port Loop Test Enable */
2771#define OBSERVATION_POINT(x) (((x) & 0xF) << 1) /* Observation Point<2:0> */
2772
2773/*
2774* REG_BIST_AND_DATA_PORT_TEST_CONFIG
2775*/
2776#define BIST_MASK_CHANNEL_2_Q_DATA (1 << 5) /* BIST Mask Channel 2 Q data */
2777#define BIST_MASK_CHANNEL_2_I_DATA (1 << 4) /* BIST Mask Channel 2 I data */
2778#define BIST_MASK_CHANNEL_1_Q_DATA (1 << 3) /* BIST Mask Channel 1 Q data */
2779#define BIST_MASK_CHANNEL_1_I_DATA (1 << 2) /* BIST Mask Channel 1 I data */
2780#define DATA_PORT_HILOW (1 << 1) /* Data Port Hi/Low */
2781#define USE_DATA_PORT (1 << 0) /* Use Data Port */
2782#define TEMP_SENSE_VBE_TEST(x) (((x) & 0x3) << 6) /* Temp Sense Vbe Test<1:0> */
2783
2784/*
2785* REG_DAC_TEST_2
2786*/
2787#define DAC_TEST_ENABLE (1 << 7) /* DAC Test Enable */
2788#define DAC_TEST_WORD(x) (((x) & 0x7F) << 0) /* DAC test Word <22:16> */
2789
2790/*
2791* SPI Comm Helpers
2792*/
2793#define AD_READ (0 << 15)
2794#define AD_WRITE (1 << 15)
2795#define AD_CNT(x) ((((x) - 1) & 0x7) << 12)
2796#define AD_ADDR(x) ((x) & 0x3FF)
2797
2798
2799/*
2800* AD9361 Limits
2801*/
2802
2803#define RSSI_MULTIPLIER 100
2804#define RSSI_RESOLUTION ((int) (0.25 * RSSI_MULTIPLIER))
2805#define RSSI_MAX_WEIGHT 255
2806
2807#define MAX_LMT_INDEX 40
2808#define MAX_LPF_GAIN 24
2809#define MAX_DIG_GAIN 31
2810
2811#define MAX_BBPLL_FREF 70007000UL /* 70 MHz + 100ppm */
2812#define MIN_BBPLL_FREQ 714928500UL /* 715 MHz - 100ppm */
2813#define MAX_BBPLL_FREQ 1430143000UL /* 1430 MHz + 100ppm */
2814#define MAX_BBPLL_DIV 64
2815#define MIN_BBPLL_DIV 2
2816
2817/*
2818 * The ADC minimum and maximum operating output data rates
2819 * are 25MHz and 640MHz respectively.
2820 * For more information see here: https://ez.analog.com/docs/DOC-12763
2821 */
2822
2823#define MIN_ADC_CLK 25000000U /* 25 MHz */
2824//#define MIN_ADC_CLK (MIN_BBPLL_FREQ / MAX_BBPLL_DIV) /* 11.17MHz */
2825#define MAX_ADC_CLK 640000000U /* 640 MHz */
2826#define MAX_DAC_CLK (MAX_ADC_CLK / 2)
2827
2828/* Associated with outputs of stage */
2829#define MAX_RX_HB1 245760000UL
2830#define MAX_RX_HB2 320000000UL
2831#define MAX_RX_HB3 640000000UL
2832/* Associated with inputs of stage */
2833#define MAX_TX_HB1 160000000UL
2834#define MAX_TX_HB2 320000000UL
2835#define MAX_TX_HB3 320000000UL
2836
2837#define MAX_BASEBAND_RATE 61440000UL
2838
2839#define MAX_MBYTE_SPI 8
2840
2841#define RFPLL_MODULUS 8388593UL
2842#define BBPLL_MODULUS 2088960UL
2843
2844#define MAX_SYNTH_FREF 80008000UL /* 80 MHz + 100ppm */
2845#define MIN_SYNTH_FREF 9999000UL /* 10 MHz - 100ppm */
2846#define MIN_VCO_FREQ_HZ 6000000000ULL
2847#define MAX_CARRIER_FREQ_HZ 6000000000ULL
2848#define MIN_RX_CARRIER_FREQ_HZ 70000000ULL
2849#define MIN_TX_CARRIER_FREQ_HZ 46875001ULL
2850
2851#define AD9363A_MAX_CARRIER_FREQ_HZ 3800000000ULL
2852#define AD9363A_MIN_CARRIER_FREQ_HZ 325000000ULL
2853
2854#define MAX_TX_ATTENUATION_DB 89750
2855
2856/*
2857* Driver
2858*/
2859
2864
2871
2872struct gain_table_info {
2873 uint64_t start;
2874 uint64_t end;
2875 uint8_t max_index;
2876 uint8_t split_table;
2877 int8_t *abs_gain_tbl;
2878 uint8_t (*tab)[3];
2879};
2880
2881enum fir_dest {
2882 FIR_TX1 = 0x01,
2883 FIR_TX2 = 0x02,
2884 FIR_TX1_TX2 = 0x03,
2885 FIR_RX1 = 0x81,
2886 FIR_RX2 = 0x82,
2887 FIR_RX1_RX2 = 0x83,
2888 FIR_IS_RX = 0x80,
2889};
2890
2891struct rf_gain_ctrl {
2892 uint32_t ant;
2893 uint8_t mode;
2894};
2895
2902
2909
2910struct gain_control {
2911 enum rf_gain_ctrl_mode rx1_mode;
2912 enum rf_gain_ctrl_mode rx2_mode;
2913
2914 /* Common */
2915 uint8_t adc_ovr_sample_size; /* 1..8 Sum x samples, AGC_CONFIG_3 */
2916 uint8_t adc_small_overload_thresh; /* 0..255, 0x105 */
2917 uint8_t adc_large_overload_thresh; /* 0..255, 0x104 */
2918
2919 uint16_t lmt_overload_high_thresh; /* 16..800 mV, 0x107 */
2920 uint16_t lmt_overload_low_thresh; /* 16..800 mV, 0x108 */
2921 uint32_t dec_pow_measuremnt_duration; /* Samples, 0x15C */
2922 uint8_t low_power_thresh; /* -64..0 dBFS, 0x114 */
2923 bool use_rx_fir_out_for_dec_pwr_meas; /* clears 0x15C:6 USE_HB1_OUT_FOR_DEC_PWR_MEAS */
2924
2925 bool dig_gain_en; /* should be turned off, since ADI GT doesn't use dig gain */
2926 uint8_t max_dig_gain; /* 0..31 */
2927
2928 /* MGC */
2929 bool mgc_rx1_ctrl_inp_en; /* Enables Pin control on RX1 default SPI ctrl */
2930 bool mgc_rx2_ctrl_inp_en; /* Enables Pin control on RX2 default SPI ctrl */
2931
2932 uint8_t mgc_inc_gain_step; /* 1..8 */
2933 uint8_t mgc_dec_gain_step; /* 1..8 */
2934 uint8_t mgc_split_table_ctrl_inp_gain_mode; /* 0=AGC determine this, 1=only in LPF, 2=only in LMT */
2935
2936 /* AGC */
2937 uint8_t agc_attack_delay_extra_margin_us; /* 0..31 us */
2938
2939 uint8_t agc_outer_thresh_high;
2940 uint8_t agc_outer_thresh_high_dec_steps;
2941 uint8_t agc_inner_thresh_high;
2942 uint8_t agc_inner_thresh_high_dec_steps;
2943 uint8_t agc_inner_thresh_low;
2944 uint8_t agc_inner_thresh_low_inc_steps;
2945 uint8_t agc_outer_thresh_low;
2946 uint8_t agc_outer_thresh_low_inc_steps;
2947
2948 uint8_t adc_small_overload_exceed_counter; /* 0..15, 0x122 */
2949 uint8_t adc_large_overload_exceed_counter; /* 0..15, 0x122 */
2950 uint8_t adc_large_overload_inc_steps; /* 0..15, 0x106 */
2951
2952 bool adc_lmt_small_overload_prevent_gain_inc; /* 0x120 */
2953 bool agc_dig_sat_ovrg_en; /* 0x101:7 ENABLE_DIG_SAT_OVRG */
2954
2955 uint8_t lmt_overload_large_exceed_counter; /* 0..15, 0x121 */
2956 uint8_t lmt_overload_small_exceed_counter; /* 0..15, 0x121 */
2957 uint8_t lmt_overload_large_inc_steps; /* 0..7, 0x121 */
2958
2959 uint8_t dig_saturation_exceed_counter; /* 0..15, 0x128 */
2960 uint8_t dig_gain_step_size; /* 1..8, 0x100 */
2961 bool sync_for_gain_counter_en; /* 0x128:4 !Hybrid */
2962
2963 uint32_t gain_update_interval_us; /* in us */
2964 bool immed_gain_change_if_large_adc_overload; /* 0x123:3 */
2965 bool immed_gain_change_if_large_lmt_overload; /* 0x123:7 */
2966
2967 /*
2968 * Fast AGC
2969 */
2970 uint32_t f_agc_dec_pow_measuremnt_duration; /* Samples, 0x15C */
2971 uint32_t f_agc_state_wait_time_ns; /* 0x117 0..31 RX samples -> time_ns */
2972 /* Fast AGC - Low Power */
2973 bool f_agc_allow_agc_gain_increase; /* 0x110:1 */
2974 uint8_t f_agc_lp_thresh_increment_time; /* 0x11B RX samples */
2975 uint8_t f_agc_lp_thresh_increment_steps; /* 0x117 1..8 */
2976
2977 /* Fast AGC - Lock Level */
2978 uint8_t f_agc_lock_level; /* NOT USED: 0x101 0..-127 dBFS same as agc_inner_thresh_high */
2979 bool f_agc_lock_level_lmt_gain_increase_en; /* 0x111:6 */
2980 uint8_t f_agc_lock_level_gain_increase_upper_limit; /* 0x118 0..63 */
2981 /* Fast AGC - Peak Detectors and Final Settling */
2982 uint8_t f_agc_lpf_final_settling_steps; /* 0x112:6 0..3 (Post Lock Level Step)*/
2983 uint8_t f_agc_lmt_final_settling_steps; /* 0x113:6 0..3 (Post Lock Level Step)*/
2984 uint8_t f_agc_final_overrange_count; /* 0x116:5 0..7 */
2985 /* Fast AGC - Final Power Test */
2986 bool f_agc_gain_increase_after_gain_lock_en; /* 0x110:7 */
2987 /* Fast AGC - Unlocking the Gain */
2988 /* 0 = MAX Gain, 1 = Set Gain, 2 = Optimized Gain */
2989 enum f_agc_target_gain_index_type
2990 f_agc_gain_index_type_after_exit_rx_mode; /* 0x110:[4,2] */
2991 bool f_agc_use_last_lock_level_for_set_gain_en; /* 0x111:7 */
2992 uint8_t f_agc_optimized_gain_offset; /*0x116 0..15 steps */
2993 bool f_agc_rst_gla_stronger_sig_thresh_exceeded_en; /* 0x110:~6 */
2994 uint8_t f_agc_rst_gla_stronger_sig_thresh_above_ll; /*0x113 0..63 dbFS */
2995 bool f_agc_rst_gla_engergy_lost_sig_thresh_exceeded_en; /* 0x110:6 */
2996 bool f_agc_rst_gla_engergy_lost_goto_optim_gain_en; /* 0x110:6 */
2997 uint8_t f_agc_rst_gla_engergy_lost_sig_thresh_below_ll; /* 0x112:6 */
2998 uint8_t f_agc_energy_lost_stronger_sig_gain_lock_exit_cnt; /* 0x119 0..63 RX samples */
2999 bool f_agc_rst_gla_large_adc_overload_en; /*0x110:~1 and 0x114:~7 */
3000 bool f_agc_rst_gla_large_lmt_overload_en; /*0x110:~1 */
3001 bool f_agc_rst_gla_en_agc_pulled_high_en;
3002 /* 0 = Max Gain, 1 = Set Gain, 2 = Optimized Gain, 3 = No Gain Change */
3003
3004 enum f_agc_target_gain_index_type
3005 f_agc_rst_gla_if_en_agc_pulled_high_mode; /* 0x0FB, 0x111 */
3006 uint32_t f_agc_power_measurement_duration_in_state5; /* 0x109, 0x10a RX samples 0..524288*/
3007 uint8_t f_agc_large_overload_inc_steps; /* 0x106 [D6:D4] 0..7 */
3008};
3009
3029
3038
3039struct rssi_control {
3040 enum rssi_restart_mode restart_mode;
3041 bool rssi_unit_is_rx_samples; /* default unit is time */
3042 uint32_t rssi_delay;
3043 uint32_t rssi_wait;
3044 uint32_t rssi_duration;
3045};
3046
3055
3064
3065struct ctrl_outs_control {
3066 uint8_t index;
3067 uint8_t en_mask;
3068};
3069
3078
3087
3112
3126
3136
3146
3156
3157struct ad9361_phy_platform_data {
3158 bool rx2tx2;
3159 bool fdd;
3160 bool fdd_independent_mode;
3161 bool split_gt;
3162 bool use_extclk;
3163 bool ensm_pin_pulse_mode;
3164 bool ensm_pin_ctrl;
3165 bool debug_mode;
3166 bool tdd_use_dual_synth;
3167 bool tdd_skip_vco_cal;
3168 bool use_ext_rx_lo;
3169 bool use_ext_tx_lo;
3170 bool rx1rx2_phase_inversion_en;
3171 bool qec_tracking_slow_mode_en;
3172 uint8_t dc_offset_update_events;
3173 uint8_t dc_offset_attenuation_high;
3174 uint8_t dc_offset_attenuation_low;
3175 uint8_t rf_dc_offset_count_high;
3176 uint8_t rf_dc_offset_count_low;
3177 uint8_t dig_interface_tune_skipmode;
3178 bool dig_interface_tune_fir_disable;
3179 uint8_t lo_powerdown_managed_en;
3180 uint32_t dcxo_coarse;
3181 uint32_t dcxo_fine;
3182 uint32_t rf_rx_input_sel;
3183 uint32_t rf_tx_output_sel;
3184 bool rf_rx_input_sel_lock;
3185 bool rf_tx_output_sel_lock;
3186 uint32_t rx1tx1_mode_use_rx_num;
3187 uint32_t rx1tx1_mode_use_tx_num;
3188 uint32_t rx_path_clks[NUM_RX_CLOCKS];
3189 uint32_t tx_path_clks[NUM_TX_CLOCKS];
3190 uint32_t trx_synth_max_fref;
3191 uint64_t rx_synth_freq;
3192 uint64_t tx_synth_freq;
3193 uint32_t rf_rx_bandwidth_Hz;
3194 uint32_t rf_tx_bandwidth_Hz;
3195 int32_t tx_atten;
3196 bool update_tx_gain_via_alert;
3197 uint32_t rx_fastlock_delay_ns;
3198 uint32_t tx_fastlock_delay_ns;
3199 bool trx_fastlock_pinctrl_en[2];
3200 bool bb_clk_change_dig_tune_en;
3201 bool axi_half_dac_rate_en;
3202
3203 /* RSSI gain-step error factory calibration tables */
3204 uint32_t rssi_lna_err_tbl[4];
3205 uint32_t rssi_mixer_err_tbl[16];
3206 uint32_t rssi_gain_step_calib_reg_val[5];
3207 bool rssi_skip_calib; /* skip live RSSI calib if tables pre-loaded */
3208
3209 enum ad9361_clkout ad9361_clkout_mode;
3210
3211 struct gain_control gain_ctrl;
3212 struct rssi_control rssi_ctrl;
3213 struct port_control port_ctrl;
3214 struct ctrl_outs_control ctrl_outs_ctrl;
3215 struct elna_control elna_ctrl;
3216 struct auxadc_control auxadc_ctrl;
3217 struct auxdac_control auxdac_ctrl;
3218 struct gpo_control gpo_ctrl;
3219 struct tx_monitor_control txmon_ctrl;
3220};
3221
3222struct rf_rx_gain {
3223 uint32_t ant; /* Antenna number to read gain */
3224 int32_t gain_db; /* gain value in dB */
3225 uint32_t fgt_lmt_index; /* Full Gain Table / LNA-MIXER-TIA gain index */
3226 uint32_t lmt_gain; /* LNA-MIXER-TIA gain in dB (Split GT mode only)*/
3227 uint32_t lpf_gain; /* Low pass filter gain in dB / index (Split GT mode only)*/
3228 uint32_t digital_gain; /* Digital gain in dB / index */
3229 /* Debug only */
3230 uint32_t lna_index; /* LNA Index (Split GT mode only) */
3231 uint32_t tia_index; /* TIA Index (Split GT mode only) */
3232 uint32_t mixer_index; /* MIXER Index (Split GT mode only) */
3233
3234};
3235struct rf_rssi {
3236 uint32_t ant; /* Antenna number for which RSSI is reported */
3237 uint32_t symbol; /* Runtime RSSI */
3238 uint32_t preamble; /* Initial RSSI */
3239 int32_t multiplier; /* Multiplier to convert reported RSSI */
3240 uint8_t duration; /* Duration to be considered for measuring */
3241};
3242
3243struct SynthLUT {
3244 uint16_t VCO_MHz;
3245 uint8_t VCO_Output_Level;
3246 uint8_t VCO_Varactor;
3247 uint8_t VCO_Bias_Ref;
3248 uint8_t VCO_Bias_Tcf;
3249 uint8_t VCO_Cal_Offset;
3250 uint8_t VCO_Varactor_Reference;
3251 uint8_t Charge_Pump_Current;
3252 uint8_t LF_C2;
3253 uint8_t LF_C1;
3254 uint8_t LF_R1;
3255 uint8_t LF_C3;
3256 uint8_t LF_R3;
3257};
3258
3259enum {
3260 LUT_FTDD_40,
3261 LUT_FTDD_60,
3262 LUT_FTDD_80,
3263 LUT_FTDD_ENT,
3264};
3265
3290
3291struct ad9361_debugfs_entry {
3292 struct ad9361_rf_phy *phy;
3293 const char *propname;
3294 void *out_value;
3295 uint32_t val;
3296 uint8_t size;
3297 uint8_t cmd;
3298};
3299
3300struct ad9361_fastlock_entry {
3301#define FASTLOOK_INIT 1
3302 uint8_t flags;
3303 uint8_t alc_orig;
3304 uint8_t alc_written;
3305};
3306
3312
3321
3327
3333
3339
3340struct ad9361_rf_phy {
3341 enum dev_id dev_sel;
3342 struct no_os_spi_desc *spi;
3343 struct no_os_gpio_desc *gpio_desc_resetb;
3344 struct no_os_gpio_desc *gpio_desc_sync;
3345 struct no_os_gpio_desc *gpio_desc_cal_sw1;
3346 struct no_os_gpio_desc *gpio_desc_cal_sw2;
3347#ifndef AXI_ADC_NOT_PRESENT
3348 struct axi_adc *rx_adc;
3349 struct axi_dac *tx_dac;
3350#endif
3351 struct no_os_clk *clk_refin;
3352 struct no_os_clk *clks[NUM_AD9361_CLKS];
3353 struct refclk_scale *ref_clk_scale[NUM_AD9361_CLKS];
3354 uint32_t (*ad9361_rfpll_ext_recalc_rate)(struct refclk_scale *clk_priv);
3355 int32_t (*ad9361_rfpll_ext_round_rate)(struct refclk_scale *clk_priv,
3356 uint32_t rate);
3357 int32_t (*ad9361_rfpll_ext_set_rate)(struct refclk_scale *clk_priv,
3358 uint32_t rate);
3359 struct ad9361_phy_platform_data *pdata;
3360 uint8_t prev_ensm_state;
3361 uint8_t curr_ensm_state;
3362 uint8_t cached_rx_rfpll_div;
3363 uint8_t cached_tx_rfpll_div;
3364 uint8_t cached_synth_pd[2];
3365 int32_t tx_quad_lpf_tia_match;
3366 uint32_t current_table;
3367 struct gain_table_info *gt_info;
3368 bool ensm_pin_ctl_en;
3369
3370 bool auto_cal_en;
3371 bool manual_tx_quad_cal_en;
3372 uint64_t last_tx_quad_cal_freq;
3373 uint32_t last_tx_quad_cal_phase;
3374 uint64_t current_tx_lo_freq;
3375 uint64_t current_rx_lo_freq;
3376 bool current_tx_use_tdd_table;
3377 bool current_rx_use_tdd_table;
3378 uint32_t current_rx_path_clks[NUM_RX_CLOCKS];
3379 uint32_t current_tx_path_clks[NUM_TX_CLOCKS];
3380 uint32_t flags;
3381 uint32_t cal_threshold_freq;
3382 uint32_t current_rx_bw_Hz;
3383 uint32_t current_tx_bw_Hz;
3384 uint32_t rxbbf_div;
3385 uint32_t rate_governor;
3386 bool bypass_rx_fir;
3387 bool bypass_tx_fir;
3388 bool rx_eq_2tx;
3389 bool filt_valid;
3390 uint32_t filt_rx_path_clks[NUM_RX_CLOCKS];
3391 uint32_t filt_tx_path_clks[NUM_TX_CLOCKS];
3392 uint32_t filt_rx_bw_Hz;
3393 uint32_t filt_tx_bw_Hz;
3394 uint8_t tx_fir_int;
3395 uint8_t tx_fir_ntaps;
3396 uint8_t rx_fir_dec;
3397 uint8_t rx_fir_ntaps;
3398 uint8_t agc_mode[2];
3399 bool rfdc_track_en;
3400 bool bbdc_track_en;
3401 bool quad_track_en;
3402 bool txmon_tdd_en;
3403 uint16_t auxdac1_value;
3404 uint16_t auxdac2_value;
3405 uint32_t tx1_atten_cached;
3406 uint32_t tx2_atten_cached;
3407 struct ad9361_fastlock fastlock;
3408 struct axiadc_converter *adc_conv;
3409 struct axiadc_state *adc_state;
3410 int32_t bist_loopback_mode;
3411 int32_t bist_config;
3412 enum ad9361_bist_mode bist_prbs_mode;
3413 enum ad9361_bist_mode bist_tone_mode;
3414 uint32_t bist_tone_freq_Hz;
3415 uint32_t bist_tone_level_dB;
3416 uint32_t bist_tone_mask;
3417 bool bbpll_initialized;
3418 struct ad9361_ext_band_ctl *ext_band_ctl;
3419};
3420
3429
3440
3441int32_t ad9361_spi_readm(struct no_os_spi_desc *spi, uint32_t reg,
3442 uint8_t *rbuf, uint32_t num);
3443int32_t ad9361_spi_read(struct no_os_spi_desc *spi, uint32_t reg);
3444int32_t ad9361_reg_read(struct ad9361_rf_phy *phy,
3445 uint32_t reg, uint32_t *val);
3446int32_t ad9361_spi_write(struct no_os_spi_desc *spi,
3447 uint32_t reg, uint32_t val);
3448int32_t ad9361_reg_write(struct ad9361_rf_phy *phy,
3449 uint32_t reg, uint32_t val);
3450int32_t ad9361_reset(struct ad9361_rf_phy *phy);
3451int32_t ad9361_register_clocks(struct ad9361_rf_phy *phy);
3452int32_t ad9361_unregister_clocks(struct ad9361_rf_phy *phy);
3453uint32_t ad9361_gt(struct ad9361_rf_phy *phy);
3454int32_t ad9361_init_gain_tables(struct ad9361_rf_phy *phy);
3455int32_t ad9361_setup(struct ad9361_rf_phy *phy);
3456int32_t ad9361_post_setup(struct ad9361_rf_phy *phy);
3457int32_t ad9361_set_ensm_mode(struct ad9361_rf_phy *phy, bool fdd, bool pinctrl);
3458int32_t ad9361_ensm_set_state(struct ad9361_rf_phy *phy, uint8_t ensm_state,
3459 bool pinctrl);
3460int32_t ad9361_set_rx_gain(struct ad9361_rf_phy *phy,
3461 uint32_t rx_id, struct rf_rx_gain *rx_gain);
3462int32_t ad9361_get_rx_gain(struct ad9361_rf_phy *phy,
3463 uint32_t rx_id, struct rf_rx_gain *rx_gain);
3464int32_t ad9361_update_rf_bandwidth(struct ad9361_rf_phy *phy,
3465 uint32_t rf_rx_bw, uint32_t rf_tx_bw);
3466int32_t ad9361_calculate_rf_clock_chain(struct ad9361_rf_phy *phy,
3467 uint32_t tx_sample_rate,
3468 uint32_t rate_gov,
3469 uint32_t *rx_path_clks,
3470 uint32_t *tx_path_clks);
3471int32_t ad9361_set_trx_clock_chain(struct ad9361_rf_phy *phy,
3472 uint32_t *rx_path_clks,
3473 uint32_t *tx_path_clks);
3474int32_t ad9361_get_trx_clock_chain(struct ad9361_rf_phy *phy,
3475 uint32_t *rx_path_clks,
3476 uint32_t *tx_path_clks);
3477uint32_t ad9361_to_clk(uint64_t freq);
3478uint64_t ad9361_from_clk(uint32_t freq);
3479int32_t ad9361_read_rssi(struct ad9361_rf_phy *phy, struct rf_rssi *rssi);
3480int32_t ad9361_set_gain_ctrl_mode(struct ad9361_rf_phy *phy,
3481 struct rf_gain_ctrl *gain_ctrl);
3482int32_t ad9361_load_fir_filter_coef(struct ad9361_rf_phy *phy,
3483 enum fir_dest dest, int32_t gain_dB,
3484 uint32_t ntaps, short *coef);
3485int32_t ad9361_validate_enable_fir(struct ad9361_rf_phy *phy);
3486int32_t ad9361_set_tx_atten(struct ad9361_rf_phy *phy, uint32_t atten_mdb,
3487 bool tx1, bool tx2, bool immed);
3488int32_t ad9361_get_tx_atten(struct ad9361_rf_phy *phy, uint32_t tx_num);
3489uint32_t ad9361_clk_factor_recalc_rate(struct refclk_scale *clk_priv,
3490 uint32_t parent_rate);
3491int32_t ad9361_clk_factor_round_rate(struct refclk_scale *clk_priv,
3492 uint32_t rate,
3493 uint32_t *prate);
3494int32_t ad9361_clk_factor_set_rate(struct refclk_scale *clk_priv, uint32_t rate,
3495 uint32_t parent_rate);
3496uint32_t ad9361_bbpll_recalc_rate(struct refclk_scale *clk_priv,
3497 uint32_t parent_rate);
3498int32_t ad9361_bbpll_round_rate(struct refclk_scale *clk_priv, uint32_t rate,
3499 uint32_t *prate);
3500int32_t ad9361_bbpll_set_rate(struct refclk_scale *clk_priv, uint32_t rate,
3501 uint32_t parent_rate);
3502uint32_t ad9361_rfpll_int_recalc_rate(struct refclk_scale *clk_priv,
3503 uint32_t parent_rate);
3504int32_t ad9361_rfpll_int_round_rate(struct refclk_scale *clk_priv,
3505 uint32_t rate,
3506 uint32_t *prate);
3507int32_t ad9361_rfpll_int_set_rate(struct refclk_scale *clk_priv, uint32_t rate,
3508 uint32_t parent_rate);
3509uint32_t ad9361_rfpll_dummy_recalc_rate(struct refclk_scale *clk_priv);
3510int32_t ad9361_rfpll_dummy_set_rate(struct refclk_scale *clk_priv,
3511 uint32_t rate);
3512uint32_t ad9361_rfpll_recalc_rate(struct refclk_scale *clk_priv);
3513int32_t ad9361_rfpll_round_rate(struct refclk_scale *clk_priv, uint32_t rate);
3514int32_t ad9361_rfpll_set_rate(struct refclk_scale *clk_priv, uint32_t rate);
3515int32_t ad9361_clk_mux_set_parent(struct refclk_scale *clk_priv, uint8_t index);
3516int32_t ad9361_tracking_control(struct ad9361_rf_phy *phy, bool bbdc_track,
3517 bool rfdc_track, bool rxquad_track);
3518int32_t ad9361_bist_loopback(struct ad9361_rf_phy *phy, int32_t mode);
3519void ad9361_get_bist_loopback(struct ad9361_rf_phy *phy, int32_t *mode);
3520int32_t ad9361_bist_prbs(struct ad9361_rf_phy *phy, enum ad9361_bist_mode mode);
3521void ad9361_get_bist_prbs(struct ad9361_rf_phy *phy,
3522 enum ad9361_bist_mode *mode);
3523int32_t ad9361_bist_tone(struct ad9361_rf_phy *phy,
3524 enum ad9361_bist_mode mode, uint32_t freq_Hz,
3525 uint32_t level_dB, uint32_t mask);
3526void ad9361_get_bist_tone(struct ad9361_rf_phy *phy,
3527 enum ad9361_bist_mode *mode, uint32_t *freq_Hz,
3528 uint32_t *level_dB, uint32_t *mask);
3529int32_t ad9361_rf_port_setup(struct ad9361_rf_phy *phy, bool is_out,
3530 uint32_t rx_inputs, uint32_t txb);
3531int32_t ad9361_mcs(struct ad9361_rf_phy *phy, int32_t step);
3532int32_t ad9361_do_calib_run(struct ad9361_rf_phy *phy, uint32_t cal,
3533 int32_t arg);
3534int32_t ad9361_fastlock_store(struct ad9361_rf_phy *phy, bool tx,
3535 uint32_t profile);
3536int32_t ad9361_fastlock_recall(struct ad9361_rf_phy *phy, bool tx,
3537 uint32_t profile);
3538int32_t ad9361_fastlock_load(struct ad9361_rf_phy *phy, bool tx,
3539 uint32_t profile, uint8_t *values);
3540int32_t ad9361_fastlock_save(struct ad9361_rf_phy *phy, bool tx,
3541 uint32_t profile, uint8_t *values);
3542void ad9361_ensm_force_state(struct ad9361_rf_phy *phy, uint8_t ensm_state);
3543uint8_t ad9361_ensm_get_state(struct ad9361_rf_phy *phy);
3544void ad9361_ensm_restore_state(struct ad9361_rf_phy *phy, uint8_t ensm_state);
3545void ad9361_ensm_restore_prev_state(struct ad9361_rf_phy *phy);
3546int32_t ad9361_set_trx_clock_chain_freq(struct ad9361_rf_phy *phy,
3547 uint32_t freq);
3548int32_t ad9361_find_opt(uint8_t *field, uint32_t size, uint32_t *ret_start);
3549int32_t ad9361_hdl_loopback(struct ad9361_rf_phy *phy, bool enable);
3550int32_t ad9361_dig_interface_timing_analysis(struct ad9361_rf_phy *phy,
3551 char *buf, int32_t buflen);
3552int32_t ad9361_dig_tune(struct ad9361_rf_phy *phy, uint32_t max_freq,
3553 enum dig_tune_flags flags);
3554int32_t ad9361_en_dis_tx(struct ad9361_rf_phy *phy, uint32_t tx_if,
3555 uint32_t enable);
3556int32_t ad9361_en_dis_rx(struct ad9361_rf_phy *phy, uint32_t rx_if,
3557 uint32_t enable);
3558int32_t ad9361_1rx1tx_channel_map(struct ad9361_rf_phy *phy, bool tx,
3559 int32_t channel);
3560int32_t ad9361_rssi_gain_step_calib(struct ad9361_rf_phy *phy);
3561int32_t ad9361_set_dcxo_tune(struct ad9361_rf_phy *phy,
3562 uint32_t coarse, uint32_t fine);
3563int32_t ad9361_tx_mute(struct ad9361_rf_phy *phy, uint32_t state);
3564uint32_t ad9361_validate_rf_bw(struct ad9361_rf_phy *phy, uint32_t bw);
3565int32_t ad9361_get_temp(struct ad9361_rf_phy *phy);
3566int ad9361_synth_lo_powerdown(struct ad9361_rf_phy *phy,
3567 enum synth_pd_ctrl rx,
3568 enum synth_pd_ctrl tx);
3569void ad9361_clear_state(struct ad9361_rf_phy *phy);
3570
3571struct ad9361_dig_tune_data {
3572 uint8_t skip_mode; /* current dig_interface_tune_skipmode */
3573 uint8_t rx_clk_delay; /* tuned RX CLK delay value */
3574 uint8_t rx_data_delay; /* tuned RX DATA delay value */
3575 uint8_t tx_clk_delay; /* tuned TX CLK delay value */
3576 uint8_t tx_data_delay; /* tuned TX DATA delay value */
3577};
3578int32_t ad9361_get_dig_tune_data(struct ad9361_rf_phy *phy,
3579 struct ad9361_dig_tune_data *data);
3580
3581int32_t ad9361_write_clock_data_delays(struct ad9361_rf_phy *phy);
3582int32_t ad9361_read_clock_data_delays(struct ad9361_rf_phy *phy);
3583
3584int32_t ad9361_write_bist_reg(struct ad9361_rf_phy *phy, uint32_t val);
3585
3586int32_t ad9361_ensm_mode_disable_pinctrl(struct ad9361_rf_phy *phy);
3587int32_t ad9361_ensm_mode_restore_pinctrl(struct ad9361_rf_phy *phy);
3588
3589int32_t ad9361_rssi_program_lna_gain(struct ad9361_rf_phy *phy);
3590int32_t ad9361_rssi_write_err_tbl(struct ad9361_rf_phy *phy);
3591
3592int32_t ad9361_set_cal_sw(struct ad9361_rf_phy *phy, uint32_t val);
3593
3594#endif
CLKOUT_DISABLE
@ CLKOUT_DISABLE
Definition ad5758.h:281
ad9361_fastlock_load
int32_t ad9361_fastlock_load(struct ad9361_rf_phy *phy, bool tx, uint32_t profile, uint8_t *values)
Definition ad9361.c:5002
ad9361_bist_mode
ad9361_bist_mode
Definition ad9361.h:3322
BIST_DISABLE
@ BIST_DISABLE
Definition ad9361.h:3323
BIST_INJ_TX
@ BIST_INJ_TX
Definition ad9361.h:3324
BIST_INJ_RX
@ BIST_INJ_RX
Definition ad9361.h:3325
ad9361_rfpll_set_rate
int32_t ad9361_rfpll_set_rate(struct refclk_scale *clk_priv, uint32_t rate)
Definition ad9361.c:7111
ad9361_pdata_rx_freq
ad9361_pdata_rx_freq
Definition ad9361.h:3127
R2_FREQ
@ R2_FREQ
Definition ad9361.h:3130
R1_FREQ
@ R1_FREQ
Definition ad9361.h:3131
RX_SAMPL_FREQ
@ RX_SAMPL_FREQ
Definition ad9361.h:3133
ADC_FREQ
@ ADC_FREQ
Definition ad9361.h:3129
NUM_RX_CLOCKS
@ NUM_RX_CLOCKS
Definition ad9361.h:3134
CLKRF_FREQ
@ CLKRF_FREQ
Definition ad9361.h:3132
BBPLL_FREQ
@ BBPLL_FREQ
Definition ad9361.h:3128
ad9361_get_bist_prbs
void ad9361_get_bist_prbs(struct ad9361_rf_phy *phy, enum ad9361_bist_mode *mode)
Definition ad9361.c:1207
ad9361_tracking_control
int32_t ad9361_tracking_control(struct ad9361_rf_phy *phy, bool bbdc_track, bool rfdc_track, bool rxquad_track)
Definition ad9361.c:3310
ad9361_read_rssi
int32_t ad9361_read_rssi(struct ad9361_rf_phy *phy, struct rf_rssi *rssi)
Definition ad9361.c:2446
ad9361_ensm_get_state
uint8_t ad9361_ensm_get_state(struct ad9361_rf_phy *phy)
Definition ad9361.c:1966
ad9361_reset
int32_t ad9361_reset(struct ad9361_rf_phy *phy)
Definition ad9361.c:1036
ad9361_set_tx_atten
int32_t ad9361_set_tx_atten(struct ad9361_rf_phy *phy, uint32_t atten_mdb, bool tx1, bool tx2, bool immed)
Definition ad9361.c:1634
ad9361_rfpll_dummy_set_rate
int32_t ad9361_rfpll_dummy_set_rate(struct refclk_scale *clk_priv, uint32_t rate)
Definition ad9361.c:7012
ad9361_from_clk
uint64_t ad9361_from_clk(uint32_t freq)
Definition ad9361.c:1395
ad9361_rssi_gain_step_calib
int32_t ad9361_rssi_gain_step_calib(struct ad9361_rf_phy *phy)
Definition ad9361.c:7472
ad9361_rfpll_int_recalc_rate
uint32_t ad9361_rfpll_int_recalc_rate(struct refclk_scale *clk_priv, uint32_t parent_rate)
Definition ad9361.c:6795
ad9361_bbpll_round_rate
int32_t ad9361_bbpll_round_rate(struct refclk_scale *clk_priv, uint32_t rate, uint32_t *prate)
Definition ad9361.c:6616
ad9361_read_clock_data_delays
int32_t ad9361_read_clock_data_delays(struct ad9361_rf_phy *phy)
Definition ad9361.c:7644
ad9361_dig_tune
int32_t ad9361_dig_tune(struct ad9361_rf_phy *phy, uint32_t max_freq, enum dig_tune_flags flags)
Definition ad9361_conv.c:512
ad9361_get_dig_tune_data
int32_t ad9361_get_dig_tune_data(struct ad9361_rf_phy *phy, struct ad9361_dig_tune_data *data)
Definition ad9361.c:7674
ad9361_reg_read
int32_t ad9361_reg_read(struct ad9361_rf_phy *phy, uint32_t reg, uint32_t *val)
Definition ad9361.c:748
ad9361_bist_prbs
int32_t ad9361_bist_prbs(struct ad9361_rf_phy *phy, enum ad9361_bist_mode mode)
Definition ad9361.c:1177
ad9361_reg_write
int32_t ad9361_reg_write(struct ad9361_rf_phy *phy, uint32_t reg, uint32_t val)
Definition ad9361.c:837
ad9361_spi_readm
int32_t ad9361_spi_readm(struct no_os_spi_desc *spi, uint32_t reg, uint8_t *rbuf, uint32_t num)
Definition ad9361.c:688
dig_tune_flags
dig_tune_flags
Definition ad9361.h:3313
RESTORE_DEFAULT
@ RESTORE_DEFAULT
Definition ad9361.h:3319
DO_ODELAY
@ DO_ODELAY
Definition ad9361.h:3317
BE_VERBOSE
@ BE_VERBOSE
Definition ad9361.h:3314
SKIP_STORE_RESULT
@ SKIP_STORE_RESULT
Definition ad9361.h:3318
BE_MOREVERBOSE
@ BE_MOREVERBOSE
Definition ad9361.h:3315
DO_IDELAY
@ DO_IDELAY
Definition ad9361.h:3316
ad9361_ensm_restore_state
void ad9361_ensm_restore_state(struct ad9361_rf_phy *phy, uint8_t ensm_state)
Definition ad9361.c:2057
ad9361_pdata_tx_freq
ad9361_pdata_tx_freq
Definition ad9361.h:3137
DAC_FREQ
@ DAC_FREQ
Definition ad9361.h:3139
T1_FREQ
@ T1_FREQ
Definition ad9361.h:3141
IGNORE
@ IGNORE
Definition ad9361.h:3138
CLKTF_FREQ
@ CLKTF_FREQ
Definition ad9361.h:3142
T2_FREQ
@ T2_FREQ
Definition ad9361.h:3140
TX_SAMPL_FREQ
@ TX_SAMPL_FREQ
Definition ad9361.h:3143
NUM_TX_CLOCKS
@ NUM_TX_CLOCKS
Definition ad9361.h:3144
ad9361_do_calib_run
int32_t ad9361_do_calib_run(struct ad9361_rf_phy *phy, uint32_t cal, int32_t arg)
Definition ad9361.c:5694
rf_gain_ctrl_mode
rf_gain_ctrl_mode
Definition ad9361.h:2896
RF_GAIN_MGC
@ RF_GAIN_MGC
Definition ad9361.h:2897
RF_GAIN_SLOWATTACK_AGC
@ RF_GAIN_SLOWATTACK_AGC
Definition ad9361.h:2899
RF_GAIN_HYBRID_AGC
@ RF_GAIN_HYBRID_AGC
Definition ad9361.h:2900
RF_GAIN_FASTATTACK_AGC
@ RF_GAIN_FASTATTACK_AGC
Definition ad9361.h:2898
ad9361_calculate_rf_clock_chain
int32_t ad9361_calculate_rf_clock_chain(struct ad9361_rf_phy *phy, uint32_t tx_sample_rate, uint32_t rate_gov, uint32_t *rx_path_clks, uint32_t *tx_path_clks)
Definition ad9361.c:4770
ad9361_clkout
ad9361_clkout
Definition ad9361.h:3147
ADC_CLK_DIV_3
@ ADC_CLK_DIV_3
Definition ad9361.h:3151
ADC_CLK_DIV_16
@ ADC_CLK_DIV_16
Definition ad9361.h:3154
ADC_CLK_DIV_8
@ ADC_CLK_DIV_8
Definition ad9361.h:3153
ADC_CLK_DIV_2
@ ADC_CLK_DIV_2
Definition ad9361.h:3150
BUFFERED_XTALN_DCXO
@ BUFFERED_XTALN_DCXO
Definition ad9361.h:3149
ADC_CLK_DIV_4
@ ADC_CLK_DIV_4
Definition ad9361.h:3152
ad9361_unregister_clocks
int32_t ad9361_unregister_clocks(struct ad9361_rf_phy *phy)
Definition ad9361.c:7452
ad9361_set_trx_clock_chain_freq
int32_t ad9361_set_trx_clock_chain_freq(struct ad9361_rf_phy *phy, uint32_t freq)
Definition ad9361.c:4892
ad9361_rfpll_int_round_rate
int32_t ad9361_rfpll_int_round_rate(struct refclk_scale *clk_priv, uint32_t rate, uint32_t *prate)
Definition ad9361.c:6851
ad9361_rfpll_int_set_rate
int32_t ad9361_rfpll_int_set_rate(struct refclk_scale *clk_priv, uint32_t rate, uint32_t parent_rate)
Definition ad9361.c:6880
ad9361_ensm_set_state
int32_t ad9361_ensm_set_state(struct ad9361_rf_phy *phy, uint8_t ensm_state, bool pinctrl)
Definition ad9361.c:4438
LUT_FTDD_40
@ LUT_FTDD_40
Definition ad9361.h:3260
LUT_FTDD_60
@ LUT_FTDD_60
Definition ad9361.h:3261
LUT_FTDD_80
@ LUT_FTDD_80
Definition ad9361.h:3262
LUT_FTDD_ENT
@ LUT_FTDD_ENT
Definition ad9361.h:3263
ad9361_rfpll_dummy_recalc_rate
uint32_t ad9361_rfpll_dummy_recalc_rate(struct refclk_scale *clk_priv)
Definition ad9361.c:6999
ad9361_rssi_program_lna_gain
int32_t ad9361_rssi_program_lna_gain(struct ad9361_rf_phy *phy)
Definition ad9361.c:7569
ad9361_tx_mute
int32_t ad9361_tx_mute(struct ad9361_rf_phy *phy, uint32_t state)
Definition ad9361.c:1698
ad9361_spi_write
int32_t ad9361_spi_write(struct no_os_spi_desc *spi, uint32_t reg, uint32_t val)
Definition ad9361.c:805
ad9361_find_opt
int32_t ad9361_find_opt(uint8_t *field, uint32_t size, uint32_t *ret_start)
Definition ad9361.c:976
ad9361_register_clocks
int32_t ad9361_register_clocks(struct ad9361_rf_phy *phy)
Definition ad9361.c:7337
ad9361_gt
uint32_t ad9361_gt(struct ad9361_rf_phy *phy)
Definition ad9361.c:1368
ad9361_mcs
int32_t ad9361_mcs(struct ad9361_rf_phy *phy, int32_t step)
Definition ad9361.c:5253
ad9361_get_rx_gain
int32_t ad9361_get_rx_gain(struct ad9361_rf_phy *phy, uint32_t rx_id, struct rf_rx_gain *rx_gain)
Definition ad9361.c:1900
ad9361_clear_state
void ad9361_clear_state(struct ad9361_rf_phy *phy)
Definition ad9361.c:5307
ad9361_get_temp
int32_t ad9361_get_temp(struct ad9361_rf_phy *phy)
Definition ad9361.c:4207
ad9361_hdl_loopback
int32_t ad9361_hdl_loopback(struct ad9361_rf_phy *phy, bool enable)
Definition ad9361_conv.c:101
ad9361_rfpll_recalc_rate
uint32_t ad9361_rfpll_recalc_rate(struct refclk_scale *clk_priv)
Definition ad9361.c:7027
ad9361_post_setup
int32_t ad9361_post_setup(struct ad9361_rf_phy *phy)
Definition ad9361_conv.c:592
ad9361_get_tx_atten
int32_t ad9361_get_tx_atten(struct ad9361_rf_phy *phy, uint32_t tx_num)
Definition ad9361.c:1673
ad9361_get_trx_clock_chain
int32_t ad9361_get_trx_clock_chain(struct ad9361_rf_phy *phy, uint32_t *rx_path_clks, uint32_t *tx_path_clks)
Definition ad9361.c:4732
ad9361_get_bist_tone
void ad9361_get_bist_tone(struct ad9361_rf_phy *phy, enum ad9361_bist_mode *mode, uint32_t *freq_Hz, uint32_t *level_dB, uint32_t *mask)
Definition ad9361.c:1279
ad9361_rssi_write_err_tbl
int32_t ad9361_rssi_write_err_tbl(struct ad9361_rf_phy *phy)
Definition ad9361.c:7601
ad9361_update_rf_bandwidth
int32_t ad9361_update_rf_bandwidth(struct ad9361_rf_phy *phy, uint32_t rf_rx_bw, uint32_t rf_tx_bw)
Definition ad9361.c:5735
f_agc_target_gain_index_type
f_agc_target_gain_index_type
Definition ad9361.h:2903
SET_GAIN
@ SET_GAIN
Definition ad9361.h:2905
NO_GAIN_CHANGE
@ NO_GAIN_CHANGE
Definition ad9361.h:2907
OPTIMIZED_GAIN
@ OPTIMIZED_GAIN
Definition ad9361.h:2906
MAX_GAIN
@ MAX_GAIN
Definition ad9361.h:2904
ad9361_clk_factor_recalc_rate
uint32_t ad9361_clk_factor_recalc_rate(struct refclk_scale *clk_priv, uint32_t parent_rate)
Definition ad9361.c:6506
ad9361_fastlock_save
int32_t ad9361_fastlock_save(struct ad9361_rf_phy *phy, bool tx, uint32_t profile, uint8_t *values)
Definition ad9361.c:5233
ad9361_set_rx_gain
int32_t ad9361_set_rx_gain(struct ad9361_rf_phy *phy, uint32_t rx_id, struct rf_rx_gain *rx_gain)
Definition ad9361.c:2212
ad9361_bbpll_set_rate
int32_t ad9361_bbpll_set_rate(struct refclk_scale *clk_priv, uint32_t rate, uint32_t parent_rate)
Definition ad9361.c:6656
ad9361_validate_rf_bw
uint32_t ad9361_validate_rf_bw(struct ad9361_rf_phy *phy, uint32_t bw)
Definition ad9361.c:934
ad9361_ensm_mode_restore_pinctrl
int32_t ad9361_ensm_mode_restore_pinctrl(struct ad9361_rf_phy *phy)
Definition ad9361.c:7719
ad9361_get_bist_loopback
void ad9361_get_bist_loopback(struct ad9361_rf_phy *phy, int32_t *mode)
Definition ad9361.c:1166
ad9361_write_bist_reg
int32_t ad9361_write_bist_reg(struct ad9361_rf_phy *phy, uint32_t val)
Definition ad9361.c:7695
rssi_restart_mode
rssi_restart_mode
Definition ad9361.h:3030
AGC_IN_FAST_ATTACK_MODE_LOCKS_THE_GAIN
@ AGC_IN_FAST_ATTACK_MODE_LOCKS_THE_GAIN
Definition ad9361.h:3031
ENTERS_RX_MODE
@ ENTERS_RX_MODE
Definition ad9361.h:3033
SPI_WRITE_TO_REGISTER
@ SPI_WRITE_TO_REGISTER
Definition ad9361.h:3035
GAIN_CHANGE_OCCURS_OR_EN_AGC_PIN_PULLED_HIGH
@ GAIN_CHANGE_OCCURS_OR_EN_AGC_PIN_PULLED_HIGH
Definition ad9361.h:3036
EN_AGC_PIN_IS_PULLED_HIGH
@ EN_AGC_PIN_IS_PULLED_HIGH
Definition ad9361.h:3032
GAIN_CHANGE_OCCURS
@ GAIN_CHANGE_OCCURS
Definition ad9361.h:3034
ad9361_set_cal_sw
int32_t ad9361_set_cal_sw(struct ad9361_rf_phy *phy, uint32_t val)
Definition ad9361.c:7736
ad9361_clocks
ad9361_clocks
Definition ad9361.h:3266
RX_RFPLL
@ RX_RFPLL
Definition ad9361.h:3285
CLKTF_CLK
@ CLKTF_CLK
Definition ad9361.h:3279
T2_CLK
@ T2_CLK
Definition ad9361.h:3277
R1_CLK
@ R1_CLK
Definition ad9361.h:3273
RX_RFPLL_DUMMY
@ RX_RFPLL_DUMMY
Definition ad9361.h:3283
DAC_CLK
@ DAC_CLK
Definition ad9361.h:3276
TX_RFPLL_INT
@ TX_RFPLL_INT
Definition ad9361.h:3282
TX_RFPLL
@ TX_RFPLL
Definition ad9361.h:3286
TX_REFCLK
@ TX_REFCLK
Definition ad9361.h:3269
NUM_AD9361_CLKS
@ NUM_AD9361_CLKS
Definition ad9361.h:3287
R2_CLK
@ R2_CLK
Definition ad9361.h:3272
BB_REFCLK
@ BB_REFCLK
Definition ad9361.h:3267
RX_RFPLL_INT
@ RX_RFPLL_INT
Definition ad9361.h:3281
CLKRF_CLK
@ CLKRF_CLK
Definition ad9361.h:3274
T1_CLK
@ T1_CLK
Definition ad9361.h:3278
RX_SAMPL_CLK
@ RX_SAMPL_CLK
Definition ad9361.h:3275
EXT_REF_CLK
@ EXT_REF_CLK
Definition ad9361.h:3288
ADC_CLK
@ ADC_CLK
Definition ad9361.h:3271
BBPLL_CLK
@ BBPLL_CLK
Definition ad9361.h:3270
TX_SAMPL_CLK
@ TX_SAMPL_CLK
Definition ad9361.h:3280
TX_RFPLL_DUMMY
@ TX_RFPLL_DUMMY
Definition ad9361.h:3284
RX_REFCLK
@ RX_REFCLK
Definition ad9361.h:3268
ad9361_bbpll_recalc_rate
uint32_t ad9361_bbpll_recalc_rate(struct refclk_scale *clk_priv, uint32_t parent_rate)
Definition ad9361.c:6589
ad9361_clk_factor_round_rate
int32_t ad9361_clk_factor_round_rate(struct refclk_scale *clk_priv, uint32_t rate, uint32_t *prate)
Definition ad9361.c:6524
ad9361_load_fir_filter_coef
int32_t ad9361_load_fir_filter_coef(struct ad9361_rf_phy *phy, enum fir_dest dest, int32_t gain_dB, uint32_t ntaps, short *coef)
ad9361_to_clk
uint32_t ad9361_to_clk(uint64_t freq)
Definition ad9361.c:1384
ad9361_setup
int32_t ad9361_setup(struct ad9361_rf_phy *phy)
Definition ad9361.c:5366
rx_gain_table_type
rx_gain_table_type
Definition ad9361.h:2860
RXGAIN_SPLIT_TBL
@ RXGAIN_SPLIT_TBL
Definition ad9361.h:2862
RXGAIN_FULL_TBL
@ RXGAIN_FULL_TBL
Definition ad9361.h:2861
ad9361_write_clock_data_delays
int32_t ad9361_write_clock_data_delays(struct ad9361_rf_phy *phy)
Definition ad9361.c:7659
ad9361_rfpll_round_rate
int32_t ad9361_rfpll_round_rate(struct refclk_scale *clk_priv, uint32_t rate)
Definition ad9361.c:7069
ad9361_1rx1tx_channel_map
int32_t ad9361_1rx1tx_channel_map(struct ad9361_rf_phy *phy, bool tx, int32_t channel)
Definition ad9361.c:1012
ad9361_synth_lo_powerdown
int ad9361_synth_lo_powerdown(struct ad9361_rf_phy *phy, enum synth_pd_ctrl rx, enum synth_pd_ctrl tx)
Definition ad9361.c:3461
ad9361_ensm_restore_prev_state
void ad9361_ensm_restore_prev_state(struct ad9361_rf_phy *phy)
Definition ad9361.c:2111
ad9361_clk_mux_set_parent
int32_t ad9361_clk_mux_set_parent(struct refclk_scale *clk_priv, uint8_t index)
Definition ad9361.c:7172
ad9361_clk_factor_set_rate
int32_t ad9361_clk_factor_set_rate(struct refclk_scale *clk_priv, uint32_t rate, uint32_t parent_rate)
Definition ad9361.c:6558
ad9361_set_dcxo_tune
int32_t ad9361_set_dcxo_tune(struct ad9361_rf_phy *phy, uint32_t coarse, uint32_t fine)
Definition ad9361.c:3516
fir_dest
fir_dest
Definition ad9361.h:2881
FIR_IS_RX
@ FIR_IS_RX
Definition ad9361.h:2888
FIR_TX1
@ FIR_TX1
Definition ad9361.h:2882
FIR_TX2
@ FIR_TX2
Definition ad9361.h:2883
FIR_RX1_RX2
@ FIR_RX1_RX2
Definition ad9361.h:2887
FIR_TX1_TX2
@ FIR_TX1_TX2
Definition ad9361.h:2884
FIR_RX2
@ FIR_RX2
Definition ad9361.h:2886
FIR_RX1
@ FIR_RX1
Definition ad9361.h:2885
ad9361_fastlock_recall
int32_t ad9361_fastlock_recall(struct ad9361_rf_phy *phy, bool tx, uint32_t profile)
Definition ad9361.c:5177
ad9361_dig_interface_timing_analysis
int32_t ad9361_dig_interface_timing_analysis(struct ad9361_rf_phy *phy, char *buf, int32_t buflen)
Definition ad9361_conv.c:275
ad9361_en_dis_tx
int32_t ad9361_en_dis_tx(struct ad9361_rf_phy *phy, uint32_t tx_if, uint32_t enable)
Definition ad9361.c:1067
ad9361_set_ensm_mode
int32_t ad9361_set_ensm_mode(struct ad9361_rf_phy *phy, bool fdd, bool pinctrl)
Definition ad9361.c:4912
dev_id
dev_id
Definition ad9361.h:3334
ID_AD9364
@ ID_AD9364
Definition ad9361.h:3336
ID_AD9363A
@ ID_AD9363A
Definition ad9361.h:3337
ID_AD9361
@ ID_AD9361
Definition ad9361.h:3335
ad9361_set_gain_ctrl_mode
int32_t ad9361_set_gain_ctrl_mode(struct ad9361_rf_phy *phy, struct rf_gain_ctrl *gain_ctrl)
Definition ad9361.c:2365
ad9361_bist_loopback
int32_t ad9361_bist_loopback(struct ad9361_rf_phy *phy, int32_t mode)
Definition ad9361.c:1119
rx_gain_table_name
rx_gain_table_name
Definition ad9361.h:2865
TBL_1300_4000_MHZ
@ TBL_1300_4000_MHZ
Definition ad9361.h:2867
TBL_4000_6000_MHZ
@ TBL_4000_6000_MHZ
Definition ad9361.h:2868
RXGAIN_TBLS_END
@ RXGAIN_TBLS_END
Definition ad9361.h:2869
TBL_200_1300_MHZ
@ TBL_200_1300_MHZ
Definition ad9361.h:2866
ad9361_ensm_mode_disable_pinctrl
int32_t ad9361_ensm_mode_disable_pinctrl(struct ad9361_rf_phy *phy)
Definition ad9361.c:7707
ad9361_en_dis_rx
int32_t ad9361_en_dis_rx(struct ad9361_rf_phy *phy, uint32_t rx_if, uint32_t enable)
Definition ad9361.c:1084
ad9361_spi_read
int32_t ad9361_spi_read(struct no_os_spi_desc *spi, uint32_t reg)
Definition ad9361.c:729
ad9361_init_gain_tables
int32_t ad9361_init_gain_tables(struct ad9361_rf_phy *phy)
ad9361_set_trx_clock_chain
int32_t ad9361_set_trx_clock_chain(struct ad9361_rf_phy *phy, uint32_t *rx_path_clks, uint32_t *tx_path_clks)
Definition ad9361.c:4644
ad9361_rf_port_setup
int32_t ad9361_rf_port_setup(struct ad9361_rf_phy *phy, bool is_out, uint32_t rx_inputs, uint32_t txb)
Definition ad9361.c:3630
debugfs_cmd
debugfs_cmd
Definition ad9361.h:3430
DBGFS_BIST_PRBS
@ DBGFS_BIST_PRBS
Definition ad9361.h:3434
DBGFS_BIST_TONE
@ DBGFS_BIST_TONE
Definition ad9361.h:3435
DBGFS_BIST_DT_ANALYSIS
@ DBGFS_BIST_DT_ANALYSIS
Definition ad9361.h:3436
DBGFS_RXGAIN_1
@ DBGFS_RXGAIN_1
Definition ad9361.h:3437
DBGFS_LOOPBACK
@ DBGFS_LOOPBACK
Definition ad9361.h:3433
DBGFS_RXGAIN_2
@ DBGFS_RXGAIN_2
Definition ad9361.h:3438
DBGFS_NONE
@ DBGFS_NONE
Definition ad9361.h:3431
DBGFS_INIT
@ DBGFS_INIT
Definition ad9361.h:3432
ad9361_ensm_force_state
void ad9361_ensm_force_state(struct ad9361_rf_phy *phy, uint8_t ensm_state)
Definition ad9361.c:1978
ad9361_validate_enable_fir
int32_t ad9361_validate_enable_fir(struct ad9361_rf_phy *phy)
Definition ad9361.c:6102
ad9361_fastlock_store
int32_t ad9361_fastlock_store(struct ad9361_rf_phy *phy, bool tx, uint32_t profile)
Definition ad9361.c:5045
synth_pd_ctrl
synth_pd_ctrl
Definition ad9361.h:3328
LO_ON
@ LO_ON
Definition ad9361.h:3331
LO_DONTCARE
@ LO_DONTCARE
Definition ad9361.h:3329
LO_OFF
@ LO_OFF
Definition ad9361.h:3330
ad9361_bist_tone
int32_t ad9361_bist_tone(struct ad9361_rf_phy *phy, enum ad9361_bist_mode mode, uint32_t freq_Hz, uint32_t level_dB, uint32_t mask)
Definition ad9361.c:1222
ad9361_ext_band_ctrl.h
profile
CUSTOM_FILE profile
Definition no_os_platform.c:29
common.h
Header file of Common Driver.
no_os_gpio.h
Header file of GPIO Interface.
SynthLUT
Definition ad9361.h:3243
SynthLUT::VCO_Output_Level
uint8_t VCO_Output_Level
Definition ad9361.h:3245
SynthLUT::LF_R1
uint8_t LF_R1
Definition ad9361.h:3254
SynthLUT::VCO_Cal_Offset
uint8_t VCO_Cal_Offset
Definition ad9361.h:3249
SynthLUT::VCO_Bias_Ref
uint8_t VCO_Bias_Ref
Definition ad9361.h:3247
SynthLUT::LF_C3
uint8_t LF_C3
Definition ad9361.h:3255
SynthLUT::VCO_Bias_Tcf
uint8_t VCO_Bias_Tcf
Definition ad9361.h:3248
SynthLUT::VCO_MHz
uint16_t VCO_MHz
Definition ad9361.h:3244
SynthLUT::VCO_Varactor
uint8_t VCO_Varactor
Definition ad9361.h:3246
SynthLUT::LF_C2
uint8_t LF_C2
Definition ad9361.h:3252
SynthLUT::Charge_Pump_Current
uint8_t Charge_Pump_Current
Definition ad9361.h:3251
SynthLUT::LF_R3
uint8_t LF_R3
Definition ad9361.h:3256
SynthLUT::VCO_Varactor_Reference
uint8_t VCO_Varactor_Reference
Definition ad9361.h:3250
SynthLUT::LF_C1
uint8_t LF_C1
Definition ad9361.h:3253
ad9361_debugfs_entry
Definition ad9361.h:3291
ad9361_debugfs_entry::propname
const char * propname
Definition ad9361.h:3293
ad9361_debugfs_entry::cmd
uint8_t cmd
Definition ad9361.h:3297
ad9361_debugfs_entry::size
uint8_t size
Definition ad9361.h:3296
ad9361_debugfs_entry::val
uint32_t val
Definition ad9361.h:3295
ad9361_debugfs_entry::out_value
void * out_value
Definition ad9361.h:3294
ad9361_debugfs_entry::phy
struct ad9361_rf_phy * phy
Definition ad9361.h:3292
ad9361_dig_tune_data
Definition ad9361.h:3571
ad9361_dig_tune_data::rx_data_delay
uint8_t rx_data_delay
Definition ad9361.h:3574
ad9361_dig_tune_data::rx_clk_delay
uint8_t rx_clk_delay
Definition ad9361.h:3573
ad9361_dig_tune_data::tx_clk_delay
uint8_t tx_clk_delay
Definition ad9361.h:3575
ad9361_dig_tune_data::tx_data_delay
uint8_t tx_data_delay
Definition ad9361.h:3576
ad9361_dig_tune_data::skip_mode
uint8_t skip_mode
Definition ad9361.h:3572
ad9361_ext_band_ctl
Definition ad9361_ext_band_ctrl.h:113
ad9361_fastlock_entry
Definition ad9361.h:3300
ad9361_fastlock_entry::flags
uint8_t flags
Definition ad9361.h:3302
ad9361_fastlock_entry::alc_written
uint8_t alc_written
Definition ad9361.h:3304
ad9361_fastlock_entry::alc_orig
uint8_t alc_orig
Definition ad9361.h:3303
ad9361_fastlock
Definition ad9361.h:3307
ad9361_fastlock::save_profile
uint8_t save_profile
Definition ad9361.h:3308
ad9361_fastlock::entry
struct ad9361_fastlock_entry entry[2][8]
Definition ad9361.h:3310
ad9361_fastlock::current_profile
uint8_t current_profile[2]
Definition ad9361.h:3309
ad9361_phy_platform_data
Definition ad9361.h:3157
ad9361_phy_platform_data::dig_interface_tune_skipmode
uint8_t dig_interface_tune_skipmode
Definition ad9361.h:3177
ad9361_phy_platform_data::qec_tracking_slow_mode_en
bool qec_tracking_slow_mode_en
Definition ad9361.h:3171
ad9361_phy_platform_data::tdd_use_dual_synth
bool tdd_use_dual_synth
Definition ad9361.h:3166
ad9361_phy_platform_data::tx_path_clks
uint32_t tx_path_clks[NUM_TX_CLOCKS]
Definition ad9361.h:3189
ad9361_phy_platform_data::fdd
bool fdd
Definition ad9361.h:3159
ad9361_phy_platform_data::gain_ctrl
struct gain_control gain_ctrl
Definition ad9361.h:3211
ad9361_phy_platform_data::tdd_skip_vco_cal
bool tdd_skip_vco_cal
Definition ad9361.h:3167
ad9361_phy_platform_data::rf_rx_bandwidth_Hz
uint32_t rf_rx_bandwidth_Hz
Definition ad9361.h:3193
ad9361_phy_platform_data::rx_synth_freq
uint64_t rx_synth_freq
Definition ad9361.h:3191
ad9361_phy_platform_data::txmon_ctrl
struct tx_monitor_control txmon_ctrl
Definition ad9361.h:3219
ad9361_phy_platform_data::rf_tx_output_sel_lock
bool rf_tx_output_sel_lock
Definition ad9361.h:3185
ad9361_phy_platform_data::rx2tx2
bool rx2tx2
Definition ad9361.h:3158
ad9361_phy_platform_data::rf_tx_output_sel
uint32_t rf_tx_output_sel
Definition ad9361.h:3183
ad9361_phy_platform_data::rx1tx1_mode_use_tx_num
uint32_t rx1tx1_mode_use_tx_num
Definition ad9361.h:3187
ad9361_phy_platform_data::rf_tx_bandwidth_Hz
uint32_t rf_tx_bandwidth_Hz
Definition ad9361.h:3194
ad9361_phy_platform_data::use_extclk
bool use_extclk
Definition ad9361.h:3162
ad9361_phy_platform_data::rf_rx_input_sel
uint32_t rf_rx_input_sel
Definition ad9361.h:3182
ad9361_phy_platform_data::fdd_independent_mode
bool fdd_independent_mode
Definition ad9361.h:3160
ad9361_phy_platform_data::rx_path_clks
uint32_t rx_path_clks[NUM_RX_CLOCKS]
Definition ad9361.h:3188
ad9361_phy_platform_data::use_ext_rx_lo
bool use_ext_rx_lo
Definition ad9361.h:3168
ad9361_phy_platform_data::lo_powerdown_managed_en
uint8_t lo_powerdown_managed_en
Definition ad9361.h:3179
ad9361_phy_platform_data::rx_fastlock_delay_ns
uint32_t rx_fastlock_delay_ns
Definition ad9361.h:3197
ad9361_phy_platform_data::dcxo_fine
uint32_t dcxo_fine
Definition ad9361.h:3181
ad9361_phy_platform_data::bb_clk_change_dig_tune_en
bool bb_clk_change_dig_tune_en
Definition ad9361.h:3200
ad9361_phy_platform_data::tx_atten
int32_t tx_atten
Definition ad9361.h:3195
ad9361_phy_platform_data::rssi_mixer_err_tbl
uint32_t rssi_mixer_err_tbl[16]
Definition ad9361.h:3205
ad9361_phy_platform_data::tx_fastlock_delay_ns
uint32_t tx_fastlock_delay_ns
Definition ad9361.h:3198
ad9361_phy_platform_data::auxadc_ctrl
struct auxadc_control auxadc_ctrl
Definition ad9361.h:3216
ad9361_phy_platform_data::rssi_lna_err_tbl
uint32_t rssi_lna_err_tbl[4]
Definition ad9361.h:3204
ad9361_phy_platform_data::trx_fastlock_pinctrl_en
bool trx_fastlock_pinctrl_en[2]
Definition ad9361.h:3199
ad9361_phy_platform_data::split_gt
bool split_gt
Definition ad9361.h:3161
ad9361_phy_platform_data::rssi_gain_step_calib_reg_val
uint32_t rssi_gain_step_calib_reg_val[5]
Definition ad9361.h:3206
ad9361_phy_platform_data::rx1tx1_mode_use_rx_num
uint32_t rx1tx1_mode_use_rx_num
Definition ad9361.h:3186
ad9361_phy_platform_data::rf_rx_input_sel_lock
bool rf_rx_input_sel_lock
Definition ad9361.h:3184
ad9361_phy_platform_data::dc_offset_attenuation_high
uint8_t dc_offset_attenuation_high
Definition ad9361.h:3173
ad9361_phy_platform_data::ensm_pin_ctrl
bool ensm_pin_ctrl
Definition ad9361.h:3164
ad9361_phy_platform_data::axi_half_dac_rate_en
bool axi_half_dac_rate_en
Definition ad9361.h:3201
ad9361_phy_platform_data::rx1rx2_phase_inversion_en
bool rx1rx2_phase_inversion_en
Definition ad9361.h:3170
ad9361_phy_platform_data::dc_offset_attenuation_low
uint8_t dc_offset_attenuation_low
Definition ad9361.h:3174
ad9361_phy_platform_data::ctrl_outs_ctrl
struct ctrl_outs_control ctrl_outs_ctrl
Definition ad9361.h:3214
ad9361_phy_platform_data::ad9361_clkout_mode
enum ad9361_clkout ad9361_clkout_mode
Definition ad9361.h:3209
ad9361_phy_platform_data::trx_synth_max_fref
uint32_t trx_synth_max_fref
Definition ad9361.h:3190
ad9361_phy_platform_data::ensm_pin_pulse_mode
bool ensm_pin_pulse_mode
Definition ad9361.h:3163
ad9361_phy_platform_data::rf_dc_offset_count_low
uint8_t rf_dc_offset_count_low
Definition ad9361.h:3176
ad9361_phy_platform_data::elna_ctrl
struct elna_control elna_ctrl
Definition ad9361.h:3215
ad9361_phy_platform_data::rssi_ctrl
struct rssi_control rssi_ctrl
Definition ad9361.h:3212
ad9361_phy_platform_data::port_ctrl
struct port_control port_ctrl
Definition ad9361.h:3213
ad9361_phy_platform_data::debug_mode
bool debug_mode
Definition ad9361.h:3165
ad9361_phy_platform_data::auxdac_ctrl
struct auxdac_control auxdac_ctrl
Definition ad9361.h:3217
ad9361_phy_platform_data::dig_interface_tune_fir_disable
bool dig_interface_tune_fir_disable
Definition ad9361.h:3178
ad9361_phy_platform_data::gpo_ctrl
struct gpo_control gpo_ctrl
Definition ad9361.h:3218
ad9361_phy_platform_data::rf_dc_offset_count_high
uint8_t rf_dc_offset_count_high
Definition ad9361.h:3175
ad9361_phy_platform_data::tx_synth_freq
uint64_t tx_synth_freq
Definition ad9361.h:3192
ad9361_phy_platform_data::use_ext_tx_lo
bool use_ext_tx_lo
Definition ad9361.h:3169
ad9361_phy_platform_data::dc_offset_update_events
uint8_t dc_offset_update_events
Definition ad9361.h:3172
ad9361_phy_platform_data::rssi_skip_calib
bool rssi_skip_calib
Definition ad9361.h:3207
ad9361_phy_platform_data::update_tx_gain_via_alert
bool update_tx_gain_via_alert
Definition ad9361.h:3196
ad9361_phy_platform_data::dcxo_coarse
uint32_t dcxo_coarse
Definition ad9361.h:3180
ad9361_rf_phy
Definition ad9361.h:3340
ad9361_rf_phy::rfdc_track_en
bool rfdc_track_en
Definition ad9361.h:3399
ad9361_rf_phy::agc_mode
uint8_t agc_mode[2]
Definition ad9361.h:3398
ad9361_rf_phy::tx1_atten_cached
uint32_t tx1_atten_cached
Definition ad9361.h:3405
ad9361_rf_phy::current_tx_bw_Hz
uint32_t current_tx_bw_Hz
Definition ad9361.h:3383
ad9361_rf_phy::bist_tone_freq_Hz
uint32_t bist_tone_freq_Hz
Definition ad9361.h:3414
ad9361_rf_phy::bypass_tx_fir
bool bypass_tx_fir
Definition ad9361.h:3387
ad9361_rf_phy::dev_sel
enum dev_id dev_sel
Definition ad9361.h:3341
ad9361_rf_phy::gpio_desc_sync
struct no_os_gpio_desc * gpio_desc_sync
Definition ad9361.h:3344
ad9361_rf_phy::auto_cal_en
bool auto_cal_en
Definition ad9361.h:3370
ad9361_rf_phy::adc_state
struct axiadc_state * adc_state
Definition ad9361.h:3409
ad9361_rf_phy::bist_loopback_mode
int32_t bist_loopback_mode
Definition ad9361.h:3410
ad9361_rf_phy::pdata
struct ad9361_phy_platform_data * pdata
Definition ad9361.h:3359
ad9361_rf_phy::spi
struct no_os_spi_desc * spi
Definition ad9361.h:3342
ad9361_rf_phy::rxbbf_div
uint32_t rxbbf_div
Definition ad9361.h:3384
ad9361_rf_phy::rx_adc
struct axi_adc * rx_adc
Definition ad9361.h:3348
ad9361_rf_phy::ref_clk_scale
struct refclk_scale * ref_clk_scale[NUM_AD9361_CLKS]
Definition ad9361.h:3353
ad9361_rf_phy::gt_info
struct gain_table_info * gt_info
Definition ad9361.h:3367
ad9361_rf_phy::rate_governor
uint32_t rate_governor
Definition ad9361.h:3385
ad9361_rf_phy::bist_prbs_mode
enum ad9361_bist_mode bist_prbs_mode
Definition ad9361.h:3412
ad9361_rf_phy::ad9361_rfpll_ext_set_rate
int32_t(* ad9361_rfpll_ext_set_rate)(struct refclk_scale *clk_priv, uint32_t rate)
Definition ad9361.h:3357
ad9361_rf_phy::gpio_desc_cal_sw1
struct no_os_gpio_desc * gpio_desc_cal_sw1
Definition ad9361.h:3345
ad9361_rf_phy::current_rx_path_clks
uint32_t current_rx_path_clks[NUM_RX_CLOCKS]
Definition ad9361.h:3378
ad9361_rf_phy::cached_tx_rfpll_div
uint8_t cached_tx_rfpll_div
Definition ad9361.h:3363
ad9361_rf_phy::bist_tone_mode
enum ad9361_bist_mode bist_tone_mode
Definition ad9361.h:3413
ad9361_rf_phy::auxdac2_value
uint16_t auxdac2_value
Definition ad9361.h:3404
ad9361_rf_phy::bist_tone_level_dB
uint32_t bist_tone_level_dB
Definition ad9361.h:3415
ad9361_rf_phy::tx_dac
struct axi_dac * tx_dac
Definition ad9361.h:3349
ad9361_rf_phy::current_table
uint32_t current_table
Definition ad9361.h:3366
ad9361_rf_phy::clk_refin
struct no_os_clk * clk_refin
Definition ad9361.h:3351
ad9361_rf_phy::adc_conv
struct axiadc_converter * adc_conv
Definition ad9361.h:3408
ad9361_rf_phy::tx_fir_ntaps
uint8_t tx_fir_ntaps
Definition ad9361.h:3395
ad9361_rf_phy::current_rx_bw_Hz
uint32_t current_rx_bw_Hz
Definition ad9361.h:3382
ad9361_rf_phy::cached_rx_rfpll_div
uint8_t cached_rx_rfpll_div
Definition ad9361.h:3362
ad9361_rf_phy::current_rx_use_tdd_table
bool current_rx_use_tdd_table
Definition ad9361.h:3377
ad9361_rf_phy::bypass_rx_fir
bool bypass_rx_fir
Definition ad9361.h:3386
ad9361_rf_phy::tx_quad_lpf_tia_match
int32_t tx_quad_lpf_tia_match
Definition ad9361.h:3365
ad9361_rf_phy::filt_tx_bw_Hz
uint32_t filt_tx_bw_Hz
Definition ad9361.h:3393
ad9361_rf_phy::flags
uint32_t flags
Definition ad9361.h:3380
ad9361_rf_phy::current_rx_lo_freq
uint64_t current_rx_lo_freq
Definition ad9361.h:3375
ad9361_rf_phy::cached_synth_pd
uint8_t cached_synth_pd[2]
Definition ad9361.h:3364
ad9361_rf_phy::current_tx_use_tdd_table
bool current_tx_use_tdd_table
Definition ad9361.h:3376
ad9361_rf_phy::bist_tone_mask
uint32_t bist_tone_mask
Definition ad9361.h:3416
ad9361_rf_phy::txmon_tdd_en
bool txmon_tdd_en
Definition ad9361.h:3402
ad9361_rf_phy::last_tx_quad_cal_freq
uint64_t last_tx_quad_cal_freq
Definition ad9361.h:3372
ad9361_rf_phy::filt_tx_path_clks
uint32_t filt_tx_path_clks[NUM_TX_CLOCKS]
Definition ad9361.h:3391
ad9361_rf_phy::cal_threshold_freq
uint32_t cal_threshold_freq
Definition ad9361.h:3381
ad9361_rf_phy::rx_fir_ntaps
uint8_t rx_fir_ntaps
Definition ad9361.h:3397
ad9361_rf_phy::ensm_pin_ctl_en
bool ensm_pin_ctl_en
Definition ad9361.h:3368
ad9361_rf_phy::manual_tx_quad_cal_en
bool manual_tx_quad_cal_en
Definition ad9361.h:3371
ad9361_rf_phy::fastlock
struct ad9361_fastlock fastlock
Definition ad9361.h:3407
ad9361_rf_phy::rx_eq_2tx
bool rx_eq_2tx
Definition ad9361.h:3388
ad9361_rf_phy::ad9361_rfpll_ext_recalc_rate
uint32_t(* ad9361_rfpll_ext_recalc_rate)(struct refclk_scale *clk_priv)
Definition ad9361.h:3354
ad9361_rf_phy::filt_rx_path_clks
uint32_t filt_rx_path_clks[NUM_RX_CLOCKS]
Definition ad9361.h:3390
ad9361_rf_phy::filt_rx_bw_Hz
uint32_t filt_rx_bw_Hz
Definition ad9361.h:3392
ad9361_rf_phy::auxdac1_value
uint16_t auxdac1_value
Definition ad9361.h:3403
ad9361_rf_phy::gpio_desc_resetb
struct no_os_gpio_desc * gpio_desc_resetb
Definition ad9361.h:3343
ad9361_rf_phy::last_tx_quad_cal_phase
uint32_t last_tx_quad_cal_phase
Definition ad9361.h:3373
ad9361_rf_phy::tx_fir_int
uint8_t tx_fir_int
Definition ad9361.h:3394
ad9361_rf_phy::quad_track_en
bool quad_track_en
Definition ad9361.h:3401
ad9361_rf_phy::prev_ensm_state
uint8_t prev_ensm_state
Definition ad9361.h:3360
ad9361_rf_phy::bist_config
int32_t bist_config
Definition ad9361.h:3411
ad9361_rf_phy::bbdc_track_en
bool bbdc_track_en
Definition ad9361.h:3400
ad9361_rf_phy::filt_valid
bool filt_valid
Definition ad9361.h:3389
ad9361_rf_phy::tx2_atten_cached
uint32_t tx2_atten_cached
Definition ad9361.h:3406
ad9361_rf_phy::gpio_desc_cal_sw2
struct no_os_gpio_desc * gpio_desc_cal_sw2
Definition ad9361.h:3346
ad9361_rf_phy::clks
struct no_os_clk * clks[NUM_AD9361_CLKS]
Definition ad9361.h:3352
ad9361_rf_phy::ext_band_ctl
struct ad9361_ext_band_ctl * ext_band_ctl
Definition ad9361.h:3418
ad9361_rf_phy::current_tx_path_clks
uint32_t current_tx_path_clks[NUM_TX_CLOCKS]
Definition ad9361.h:3379
ad9361_rf_phy::rx_fir_dec
uint8_t rx_fir_dec
Definition ad9361.h:3396
ad9361_rf_phy::curr_ensm_state
uint8_t curr_ensm_state
Definition ad9361.h:3361
ad9361_rf_phy::bbpll_initialized
bool bbpll_initialized
Definition ad9361.h:3417
ad9361_rf_phy::current_tx_lo_freq
uint64_t current_tx_lo_freq
Definition ad9361.h:3374
ad9361_rf_phy::ad9361_rfpll_ext_round_rate
int32_t(* ad9361_rfpll_ext_round_rate)(struct refclk_scale *clk_priv, uint32_t rate)
Definition ad9361.h:3355
auxadc_control
Definition ad9361.h:3079
auxadc_control::offset
int8_t offset
Definition ad9361.h:3080
auxadc_control::auxadc_decimation
uint32_t auxadc_decimation
Definition ad9361.h:3085
auxadc_control::temp_sensor_decimation
uint32_t temp_sensor_decimation
Definition ad9361.h:3082
auxadc_control::auxadc_clock_rate
uint32_t auxadc_clock_rate
Definition ad9361.h:3084
auxadc_control::temp_time_inteval_ms
uint32_t temp_time_inteval_ms
Definition ad9361.h:3081
auxadc_control::periodic_temp_measuremnt
bool periodic_temp_measuremnt
Definition ad9361.h:3083
auxdac_control
Definition ad9361.h:3010
auxdac_control::dac2_in_alert_en
bool dac2_in_alert_en
Definition ad9361.h:3022
auxdac_control::dac2_rx_delay_us
uint8_t dac2_rx_delay_us
Definition ad9361.h:3026
auxdac_control::dac1_tx_delay_us
uint8_t dac1_tx_delay_us
Definition ad9361.h:3025
auxdac_control::dac1_in_rx_en
bool dac1_in_rx_en
Definition ad9361.h:3016
auxdac_control::dac2_in_tx_en
bool dac2_in_tx_en
Definition ad9361.h:3021
auxdac_control::dac1_in_tx_en
bool dac1_in_tx_en
Definition ad9361.h:3017
auxdac_control::dac2_default_value
uint16_t dac2_default_value
Definition ad9361.h:3012
auxdac_control::dac2_in_rx_en
bool dac2_in_rx_en
Definition ad9361.h:3020
auxdac_control::dac1_default_value
uint16_t dac1_default_value
Definition ad9361.h:3011
auxdac_control::dac1_in_alert_en
bool dac1_in_alert_en
Definition ad9361.h:3018
auxdac_control::dac2_tx_delay_us
uint8_t dac2_tx_delay_us
Definition ad9361.h:3027
auxdac_control::auxdac_manual_mode_en
bool auxdac_manual_mode_en
Definition ad9361.h:3014
auxdac_control::dac1_rx_delay_us
uint8_t dac1_rx_delay_us
Definition ad9361.h:3024
axi_adc
AXI ADC Device Descriptor.
Definition axi_adc_core.h:123
axi_dac
AXI DAC Device Descriptor.
Definition axi_dac_core.h:53
axiadc_converter
Definition ad9361_util.h:81
axiadc_state
Definition ad9361_util.h:71
ctrl_outs_control
Definition ad9361.h:3065
ctrl_outs_control::index
uint8_t index
Definition ad9361.h:3066
ctrl_outs_control::en_mask
uint8_t en_mask
Definition ad9361.h:3067
elna_control
Definition ad9361.h:3070
elna_control::bypass_loss_mdB
uint16_t bypass_loss_mdB
Definition ad9361.h:3072
elna_control::elna_2_control_en
bool elna_2_control_en
Definition ad9361.h:3075
elna_control::elna_in_gaintable_all_index_en
bool elna_in_gaintable_all_index_en
Definition ad9361.h:3076
elna_control::elna_1_control_en
bool elna_1_control_en
Definition ad9361.h:3074
elna_control::settling_delay_ns
uint32_t settling_delay_ns
Definition ad9361.h:3073
elna_control::gain_mdB
uint16_t gain_mdB
Definition ad9361.h:3071
gain_control
Definition ad9361.h:2910
gain_control::f_agc_final_overrange_count
uint8_t f_agc_final_overrange_count
Definition ad9361.h:2984
gain_control::agc_attack_delay_extra_margin_us
uint8_t agc_attack_delay_extra_margin_us
Definition ad9361.h:2937
gain_control::f_agc_power_measurement_duration_in_state5
uint32_t f_agc_power_measurement_duration_in_state5
Definition ad9361.h:3006
gain_control::agc_inner_thresh_low_inc_steps
uint8_t agc_inner_thresh_low_inc_steps
Definition ad9361.h:2944
gain_control::f_agc_lock_level_gain_increase_upper_limit
uint8_t f_agc_lock_level_gain_increase_upper_limit
Definition ad9361.h:2980
gain_control::dig_gain_en
bool dig_gain_en
Definition ad9361.h:2925
gain_control::lmt_overload_small_exceed_counter
uint8_t lmt_overload_small_exceed_counter
Definition ad9361.h:2956
gain_control::immed_gain_change_if_large_adc_overload
bool immed_gain_change_if_large_adc_overload
Definition ad9361.h:2964
gain_control::agc_outer_thresh_high
uint8_t agc_outer_thresh_high
Definition ad9361.h:2939
gain_control::adc_small_overload_exceed_counter
uint8_t adc_small_overload_exceed_counter
Definition ad9361.h:2948
gain_control::adc_ovr_sample_size
uint8_t adc_ovr_sample_size
Definition ad9361.h:2915
gain_control::sync_for_gain_counter_en
bool sync_for_gain_counter_en
Definition ad9361.h:2961
gain_control::adc_large_overload_inc_steps
uint8_t adc_large_overload_inc_steps
Definition ad9361.h:2950
gain_control::adc_large_overload_thresh
uint8_t adc_large_overload_thresh
Definition ad9361.h:2917
gain_control::mgc_dec_gain_step
uint8_t mgc_dec_gain_step
Definition ad9361.h:2933
gain_control::f_agc_gain_increase_after_gain_lock_en
bool f_agc_gain_increase_after_gain_lock_en
Definition ad9361.h:2986
gain_control::f_agc_lp_thresh_increment_steps
uint8_t f_agc_lp_thresh_increment_steps
Definition ad9361.h:2975
gain_control::f_agc_optimized_gain_offset
uint8_t f_agc_optimized_gain_offset
Definition ad9361.h:2992
gain_control::f_agc_large_overload_inc_steps
uint8_t f_agc_large_overload_inc_steps
Definition ad9361.h:3007
gain_control::low_power_thresh
uint8_t low_power_thresh
Definition ad9361.h:2922
gain_control::f_agc_gain_index_type_after_exit_rx_mode
enum f_agc_target_gain_index_type f_agc_gain_index_type_after_exit_rx_mode
Definition ad9361.h:2989
gain_control::f_agc_rst_gla_if_en_agc_pulled_high_mode
enum f_agc_target_gain_index_type f_agc_rst_gla_if_en_agc_pulled_high_mode
Definition ad9361.h:3004
gain_control::f_agc_lmt_final_settling_steps
uint8_t f_agc_lmt_final_settling_steps
Definition ad9361.h:2983
gain_control::mgc_rx2_ctrl_inp_en
bool mgc_rx2_ctrl_inp_en
Definition ad9361.h:2930
gain_control::f_agc_lp_thresh_increment_time
uint8_t f_agc_lp_thresh_increment_time
Definition ad9361.h:2974
gain_control::f_agc_lock_level
uint8_t f_agc_lock_level
Definition ad9361.h:2978
gain_control::adc_small_overload_thresh
uint8_t adc_small_overload_thresh
Definition ad9361.h:2916
gain_control::rx2_mode
enum rf_gain_ctrl_mode rx2_mode
Definition ad9361.h:2912
gain_control::agc_inner_thresh_high
uint8_t agc_inner_thresh_high
Definition ad9361.h:2941
gain_control::f_agc_lpf_final_settling_steps
uint8_t f_agc_lpf_final_settling_steps
Definition ad9361.h:2982
gain_control::agc_outer_thresh_low
uint8_t agc_outer_thresh_low
Definition ad9361.h:2945
gain_control::mgc_split_table_ctrl_inp_gain_mode
uint8_t mgc_split_table_ctrl_inp_gain_mode
Definition ad9361.h:2934
gain_control::f_agc_rst_gla_stronger_sig_thresh_exceeded_en
bool f_agc_rst_gla_stronger_sig_thresh_exceeded_en
Definition ad9361.h:2993
gain_control::f_agc_state_wait_time_ns
uint32_t f_agc_state_wait_time_ns
Definition ad9361.h:2971
gain_control::mgc_rx1_ctrl_inp_en
bool mgc_rx1_ctrl_inp_en
Definition ad9361.h:2929
gain_control::use_rx_fir_out_for_dec_pwr_meas
bool use_rx_fir_out_for_dec_pwr_meas
Definition ad9361.h:2923
gain_control::f_agc_rst_gla_engergy_lost_sig_thresh_exceeded_en
bool f_agc_rst_gla_engergy_lost_sig_thresh_exceeded_en
Definition ad9361.h:2995
gain_control::dig_gain_step_size
uint8_t dig_gain_step_size
Definition ad9361.h:2960
gain_control::f_agc_lock_level_lmt_gain_increase_en
bool f_agc_lock_level_lmt_gain_increase_en
Definition ad9361.h:2979
gain_control::agc_dig_sat_ovrg_en
bool agc_dig_sat_ovrg_en
Definition ad9361.h:2953
gain_control::f_agc_rst_gla_engergy_lost_sig_thresh_below_ll
uint8_t f_agc_rst_gla_engergy_lost_sig_thresh_below_ll
Definition ad9361.h:2997
gain_control::f_agc_dec_pow_measuremnt_duration
uint32_t f_agc_dec_pow_measuremnt_duration
Definition ad9361.h:2970
gain_control::dig_saturation_exceed_counter
uint8_t dig_saturation_exceed_counter
Definition ad9361.h:2959
gain_control::f_agc_rst_gla_large_lmt_overload_en
bool f_agc_rst_gla_large_lmt_overload_en
Definition ad9361.h:3000
gain_control::lmt_overload_low_thresh
uint16_t lmt_overload_low_thresh
Definition ad9361.h:2920
gain_control::mgc_inc_gain_step
uint8_t mgc_inc_gain_step
Definition ad9361.h:2932
gain_control::f_agc_energy_lost_stronger_sig_gain_lock_exit_cnt
uint8_t f_agc_energy_lost_stronger_sig_gain_lock_exit_cnt
Definition ad9361.h:2998
gain_control::agc_outer_thresh_low_inc_steps
uint8_t agc_outer_thresh_low_inc_steps
Definition ad9361.h:2946
gain_control::adc_large_overload_exceed_counter
uint8_t adc_large_overload_exceed_counter
Definition ad9361.h:2949
gain_control::f_agc_rst_gla_en_agc_pulled_high_en
bool f_agc_rst_gla_en_agc_pulled_high_en
Definition ad9361.h:3001
gain_control::lmt_overload_large_exceed_counter
uint8_t lmt_overload_large_exceed_counter
Definition ad9361.h:2955
gain_control::f_agc_rst_gla_stronger_sig_thresh_above_ll
uint8_t f_agc_rst_gla_stronger_sig_thresh_above_ll
Definition ad9361.h:2994
gain_control::f_agc_rst_gla_large_adc_overload_en
bool f_agc_rst_gla_large_adc_overload_en
Definition ad9361.h:2999
gain_control::adc_lmt_small_overload_prevent_gain_inc
bool adc_lmt_small_overload_prevent_gain_inc
Definition ad9361.h:2952
gain_control::f_agc_use_last_lock_level_for_set_gain_en
bool f_agc_use_last_lock_level_for_set_gain_en
Definition ad9361.h:2991
gain_control::immed_gain_change_if_large_lmt_overload
bool immed_gain_change_if_large_lmt_overload
Definition ad9361.h:2965
gain_control::dec_pow_measuremnt_duration
uint32_t dec_pow_measuremnt_duration
Definition ad9361.h:2921
gain_control::f_agc_allow_agc_gain_increase
bool f_agc_allow_agc_gain_increase
Definition ad9361.h:2973
gain_control::gain_update_interval_us
uint32_t gain_update_interval_us
Definition ad9361.h:2963
gain_control::agc_inner_thresh_high_dec_steps
uint8_t agc_inner_thresh_high_dec_steps
Definition ad9361.h:2942
gain_control::rx1_mode
enum rf_gain_ctrl_mode rx1_mode
Definition ad9361.h:2911
gain_control::agc_outer_thresh_high_dec_steps
uint8_t agc_outer_thresh_high_dec_steps
Definition ad9361.h:2940
gain_control::max_dig_gain
uint8_t max_dig_gain
Definition ad9361.h:2926
gain_control::agc_inner_thresh_low
uint8_t agc_inner_thresh_low
Definition ad9361.h:2943
gain_control::lmt_overload_high_thresh
uint16_t lmt_overload_high_thresh
Definition ad9361.h:2919
gain_control::f_agc_rst_gla_engergy_lost_goto_optim_gain_en
bool f_agc_rst_gla_engergy_lost_goto_optim_gain_en
Definition ad9361.h:2996
gain_control::lmt_overload_large_inc_steps
uint8_t lmt_overload_large_inc_steps
Definition ad9361.h:2957
gain_table_info
Definition ad9361.h:2872
gain_table_info::start
uint64_t start
Definition ad9361.h:2873
gain_table_info::end
uint64_t end
Definition ad9361.h:2874
gain_table_info::max_index
uint8_t max_index
Definition ad9361.h:2875
gain_table_info::split_table
uint8_t split_table
Definition ad9361.h:2876
gain_table_info::abs_gain_tbl
int8_t * abs_gain_tbl
Definition ad9361.h:2877
gain_table_info::tab
uint8_t(* tab)[3]
Definition ad9361.h:2878
gpo_control
Definition ad9361.h:3088
gpo_control::gpo3_slave_rx_en
bool gpo3_slave_rx_en
Definition ad9361.h:3101
gpo_control::gpo3_tx_delay_us
uint8_t gpo3_tx_delay_us
Definition ad9361.h:3110
gpo_control::gpo1_inactive_state_high_en
bool gpo1_inactive_state_high_en
Definition ad9361.h:3092
gpo_control::gpo3_slave_tx_en
bool gpo3_slave_tx_en
Definition ad9361.h:3102
gpo_control::gpo2_rx_delay_us
uint8_t gpo2_rx_delay_us
Definition ad9361.h:3107
gpo_control::gpo2_slave_rx_en
bool gpo2_slave_rx_en
Definition ad9361.h:3099
gpo_control::gpo3_rx_delay_us
uint8_t gpo3_rx_delay_us
Definition ad9361.h:3109
gpo_control::gpo0_slave_rx_en
bool gpo0_slave_rx_en
Definition ad9361.h:3095
gpo_control::gpo1_slave_rx_en
bool gpo1_slave_rx_en
Definition ad9361.h:3097
gpo_control::gpo1_slave_tx_en
bool gpo1_slave_tx_en
Definition ad9361.h:3098
gpo_control::gpo2_inactive_state_high_en
bool gpo2_inactive_state_high_en
Definition ad9361.h:3093
gpo_control::gpo0_tx_delay_us
uint8_t gpo0_tx_delay_us
Definition ad9361.h:3104
gpo_control::gpo_manual_mode_enable_mask
uint32_t gpo_manual_mode_enable_mask
Definition ad9361.h:3089
gpo_control::gpo2_slave_tx_en
bool gpo2_slave_tx_en
Definition ad9361.h:3100
gpo_control::gpo0_rx_delay_us
uint8_t gpo0_rx_delay_us
Definition ad9361.h:3103
gpo_control::gpo2_tx_delay_us
uint8_t gpo2_tx_delay_us
Definition ad9361.h:3108
gpo_control::gpo0_slave_tx_en
bool gpo0_slave_tx_en
Definition ad9361.h:3096
gpo_control::gpo1_tx_delay_us
uint8_t gpo1_tx_delay_us
Definition ad9361.h:3106
gpo_control::gpo1_rx_delay_us
uint8_t gpo1_rx_delay_us
Definition ad9361.h:3105
gpo_control::gpo3_inactive_state_high_en
bool gpo3_inactive_state_high_en
Definition ad9361.h:3094
gpo_control::gpo_manual_mode_en
bool gpo_manual_mode_en
Definition ad9361.h:3090
gpo_control::gpo0_inactive_state_high_en
bool gpo0_inactive_state_high_en
Definition ad9361.h:3091
no_os_clk
Definition no_os_clk.h:58
no_os_gpio_desc
Structure holding the GPIO descriptor.
Definition no_os_gpio.h:84
no_os_spi_desc
Structure holding SPI descriptor.
Definition no_os_spi.h:180
port_control
Definition ad9361.h:3056
port_control::lvds_invert
uint8_t lvds_invert[2]
Definition ad9361.h:3062
port_control::rx_clk_data_delay
uint8_t rx_clk_data_delay
Definition ad9361.h:3058
port_control::tx_clk_data_delay
uint8_t tx_clk_data_delay
Definition ad9361.h:3059
port_control::lvds_bias_ctrl
uint8_t lvds_bias_ctrl
Definition ad9361.h:3061
port_control::pp_conf
uint8_t pp_conf[3]
Definition ad9361.h:3057
port_control::digital_io_ctrl
uint8_t digital_io_ctrl
Definition ad9361.h:3060
refclk_scale
Definition ad9361.h:3421
refclk_scale::phy
struct ad9361_rf_phy * phy
Definition ad9361.h:3423
refclk_scale::mult
uint32_t mult
Definition ad9361.h:3424
refclk_scale::spi
struct no_os_spi_desc * spi
Definition ad9361.h:3422
refclk_scale::parent_source
enum ad9361_clocks parent_source
Definition ad9361.h:3427
refclk_scale::div
uint32_t div
Definition ad9361.h:3425
refclk_scale::source
enum ad9361_clocks source
Definition ad9361.h:3426
rf_gain_ctrl
Definition ad9361.h:2891
rf_gain_ctrl::ant
uint32_t ant
Definition ad9361.h:2892
rf_gain_ctrl::mode
uint8_t mode
Definition ad9361.h:2893
rf_rssi
Definition ad9361.h:3235
rf_rssi::duration
uint8_t duration
Definition ad9361.h:3240
rf_rssi::preamble
uint32_t preamble
Definition ad9361.h:3238
rf_rssi::ant
uint32_t ant
Definition ad9361.h:3236
rf_rssi::symbol
uint32_t symbol
Definition ad9361.h:3237
rf_rssi::multiplier
int32_t multiplier
Definition ad9361.h:3239
rf_rx_gain
Definition ad9361.h:3222
rf_rx_gain::lna_index
uint32_t lna_index
Definition ad9361.h:3230
rf_rx_gain::ant
uint32_t ant
Definition ad9361.h:3223
rf_rx_gain::mixer_index
uint32_t mixer_index
Definition ad9361.h:3232
rf_rx_gain::tia_index
uint32_t tia_index
Definition ad9361.h:3231
rf_rx_gain::fgt_lmt_index
uint32_t fgt_lmt_index
Definition ad9361.h:3225
rf_rx_gain::gain_db
int32_t gain_db
Definition ad9361.h:3224
rf_rx_gain::lpf_gain
uint32_t lpf_gain
Definition ad9361.h:3227
rf_rx_gain::digital_gain
uint32_t digital_gain
Definition ad9361.h:3228
rf_rx_gain::lmt_gain
uint32_t lmt_gain
Definition ad9361.h:3226
rssi_control
Definition ad9361.h:3039
rssi_control::rssi_delay
uint32_t rssi_delay
Definition ad9361.h:3042
rssi_control::restart_mode
enum rssi_restart_mode restart_mode
Definition ad9361.h:3040
rssi_control::rssi_unit_is_rx_samples
bool rssi_unit_is_rx_samples
Definition ad9361.h:3041
rssi_control::rssi_duration
uint32_t rssi_duration
Definition ad9361.h:3044
rssi_control::rssi_wait
uint32_t rssi_wait
Definition ad9361.h:3043
rx_gain_info
Definition ad9361.h:3047
rx_gain_info::idx_step_offset
int32_t idx_step_offset
Definition ad9361.h:3053
rx_gain_info::starting_gain_db
int32_t starting_gain_db
Definition ad9361.h:3049
rx_gain_info::max_gain_db
int32_t max_gain_db
Definition ad9361.h:3050
rx_gain_info::tbl_type
enum rx_gain_table_type tbl_type
Definition ad9361.h:3048
rx_gain_info::max_idx
int32_t max_idx
Definition ad9361.h:3052
rx_gain_info::gain_step_db
int32_t gain_step_db
Definition ad9361.h:3051
tx_monitor_control
Definition ad9361.h:3113
tx_monitor_control::low_gain_dB
uint8_t low_gain_dB
Definition ad9361.h:3117
tx_monitor_control::high_gain_dB
uint8_t high_gain_dB
Definition ad9361.h:3118
tx_monitor_control::low_high_gain_threshold_mdB
uint32_t low_high_gain_threshold_mdB
Definition ad9361.h:3116
tx_monitor_control::tx1_mon_lo_cm
uint8_t tx1_mon_lo_cm
Definition ad9361.h:3123
tx_monitor_control::tx2_mon_front_end_gain
uint8_t tx2_mon_front_end_gain
Definition ad9361.h:3122
tx_monitor_control::tx_mon_delay
uint16_t tx_mon_delay
Definition ad9361.h:3119
tx_monitor_control::tx_mon_duration
uint16_t tx_mon_duration
Definition ad9361.h:3120
tx_monitor_control::tx_mon_track_en
bool tx_mon_track_en
Definition ad9361.h:3114
tx_monitor_control::tx1_mon_front_end_gain
uint8_t tx1_mon_front_end_gain
Definition ad9361.h:3121
tx_monitor_control::one_shot_mode_en
bool one_shot_mode_en
Definition ad9361.h:3115
tx_monitor_control::tx2_mon_lo_cm
uint8_t tx2_mon_lo_cm
Definition ad9361.h:3124