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ad9361.h
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1/***************************************************************************/
32#ifndef IIO_FREQUENCY_AD9361_H_
33#define IIO_FREQUENCY_AD9361_H_
34
35#include <stdint.h>
36#include "no_os_gpio.h"
37#include "common.h"
38
39#define REG_SPI_CONF 0x000 /* SPI Configuration */
40#define REG_MULTICHIP_SYNC_AND_TX_MON_CTRL 0x001 /* Multi-Chip Sync and Tx Mon Control */
41#define REG_TX_ENABLE_FILTER_CTRL 0x002 /* Tx Enable & Filter Control */
42#define REG_RX_ENABLE_FILTER_CTRL 0x003 /* Rx Enable & Filter Control */
43#define REG_INPUT_SELECT 0x004 /* Input Select */
44#define REG_RFPLL_DIVIDERS 0x005 /* RFPLL Dividers */
45#define REG_RX_CLOCK_DATA_DELAY 0x006 /* Rx Clock & Data Delay */
46#define REG_TX_CLOCK_DATA_DELAY 0x007 /* Tx Clock & Data Delay */
47#define REG_CLOCK_ENABLE 0x009 /* Clock Enable */
48#define REG_BBPLL 0x00A /* BBPLL */
49#define REG_TEMP_OFFSET 0x00B /* Offset */
50#define REG_START_TEMP_READING 0x00C /* Start Temp Reading */
51#define REG_TEMP_SENSE2 0x00D /* Temp Sense2 */
52#define REG_TEMPERATURE 0x00E /* Temperature */
53#define REG_TEMP_SENSOR_CONFIG 0x00F /* Temp Sensor Config */
54#define REG_PARALLEL_PORT_CONF_1 0x010 /* Parallel Port Configuration 1 */
55#define REG_PARALLEL_PORT_CONF_2 0x011 /* Parallel Port Configuration 2 */
56#define REG_PARALLEL_PORT_CONF_3 0x012 /* Parallel Port Configuration 3 */
57#define REG_ENSM_MODE 0x013 /* ENSM Mode */
58#define REG_ENSM_CONFIG_1 0x014 /* ENSM Config 1 */
59#define REG_ENSM_CONFIG_2 0x015 /* ENSM Config 2 */
60#define REG_CALIBRATION_CTRL 0x016 /* Calibration Control */
61#define REG_STATE 0x017 /* State */
62#define REG_AUXDAC_1_WORD 0x018 /* AuxDAC 1 Word */
63#define REG_AUXDAC_2_WORD 0x019 /* AuxDAC 2 Word */
64#define REG_AUXDAC_1_CONFIG 0x01A /* AuxDAC 1 Config */
65#define REG_AUXDAC_2_CONFIG 0x01B /* AuxDAC 2 Config */
66#define REG_AUXADC_CLOCK_DIVIDER 0x01C /* AuxADC Clock Divider */
67#define REG_AUXADC_CONFIG 0x01D /* Aux ADC Config */
68#define REG_AUXADC_WORD_MSB 0x01E /* AuxADC Word MSB */
69#define REG_AUXADC_LSB 0x01F /* AuxADC LSB */
70#define REG_AUTO_GPO 0x020 /* Auto GPO */
71#define REG_AGC_GAIN_LOCK_DELAY 0x021 /* AGC Gain Lock Delay */
72#define REG_AGC_ATTACK_DELAY 0x022 /* AGC Attack Delay */
73#define REG_AUXDAC_ENABLE_CTRL 0x023 /* AuxDAC Enable Control */
74#define REG_RX_LOAD_SYNTH_DELAY 0x024 /* RX Load Synth Delay */
75#define REG_TX_LOAD_SYNTH_DELAY 0x025 /* TX Load Synth Delay */
76#define REG_EXTERNAL_LNA_CTRL 0x026 /* External LNA control */
77#define REG_GPO_FORCE_AND_INIT 0x027 /* GPO Force and Init */
78#define REG_GPO0_RX_DELAY 0x028 /* GPO0 Rx delay */
79#define REG_GPO1_RX_DELAY 0x029 /* GPO1 Rx delay */
80#define REG_GPO2_RX_DELAY 0x02A /* GPO2 Rx delay */
81#define REG_GPO3_RX_DELAY 0x02B /* GPO3 Rx delay */
82#define REG_GPO0_TX_DELAY 0x02C /* GPO0 Tx Delay */
83#define REG_GPO1_TX_DELAY 0x02D /* GPO1 Tx Delay */
84#define REG_GPO2_TX_DELAY 0x02E /* GPO2 Tx Delay */
85#define REG_GPO3_TX_DELAY 0x02F /* GPO3 Tx Delay */
86#define REG_AUXDAC1_RX_DELAY 0x030 /* AuxDAC1 Rx Delay */
87#define REG_AUXDAC1_TX_DELAY 0x031 /* AuxDAC1 Tx Delay */
88#define REG_AUXDAC2_RX_DELAY 0x032 /* AuxDAC2 Rx Delay */
89#define REG_AUXDAC2_TX_DELAY 0x033 /* AuxDAC2 Tx Delay */
90#define REG_CTRL_OUTPUT_POINTER 0x035 /* Control Output Pointer */
91#define REG_CTRL_OUTPUT_ENABLE 0x036 /* Control Output Enable */
92#define REG_PRODUCT_ID 0x037 /* Product ID */
93#define REG_REFERENCE_CLOCK_CYCLES 0x03A /* Reference Clock Cycles */
94#define REG_DIGITAL_IO_CTRL 0x03B /* Digital I/O Control */
95#define REG_LVDS_BIAS_CTRL 0x03C /* LVDS Bias control */
96#define REG_LVDS_INVERT_CTRL1 0x03D /* LVDS Invert control1 */
97#define REG_LVDS_INVERT_CTRL2 0x03E /* LVDS Invert control2 */
98#define REG_SDM_CTRL_1 0x03F /* SDM Control 1 */
99#define REG_FRACT_BB_FREQ_WORD_1 0x041 /* Fractional BB Freq Word 1 */
100#define REG_FRACT_BB_FREQ_WORD_2 0x042 /* Fractional BB Freq Word 2 */
101#define REG_FRACT_BB_FREQ_WORD_3 0x043 /* Fractional BB Freq Word 3 */
102#define REG_INTEGER_BB_FREQ_WORD 0x044 /* Integer BB Freq Word */
103#define REG_CLOCK_CTRL 0x045 /* Clock Control */
104#define REG_CP_CURRENT 0x046 /* CP Current */
105#define REG_CP_BLEED_CURRENT 0x047 /* CP Bleed Current */
106#define REG_LOOP_FILTER_1 0x048 /* Loop Filter 1 */
107#define REG_LOOP_FILTER_2 0x049 /* Loop Filter 2 */
108#define REG_LOOP_FILTER_3 0x04A /* Loop Filter 3 */
109#define REG_VCO_CTRL 0x04B /* VCO Control */
110#define REG_VCO_PROGRAM_1 0x04C
111#define REG_VCO_PROGRAM_2 0x04D
112#define REG_SDM_CTRL 0x04E /* SDM Control */
113#define REG_RX_SYNTH_POWER_DOWN_OVERRIDE 0x050 /* Rx Synth Power Down Override */
114#define REG_TX_SYNTH_POWER_DOWN_OVERRIDE 0x051 /* TX Synth Power Down Override */
115#define REG_RX_ANALOG_POWER_DOWN_OVERRIDE_1 0x052 /* Rx Analog Power Down Override 1 */
116#define REG_RX_ANALOG_POWER_DOWN_OVERRIDE_2 0x053 /* Rx Analog Power Down Override 2 */
117#define REG_RX1_ADC_POWER_DOWN_OVERRIDE 0x054 /* Rx1 ADC Power Down Override */
118#define REG_RX2_ADC_POWER_DOWN_OVERRIDE 0x055 /* Rx2 ADC Power Down Override */
119#define REG_TX_ANALOG_POWER_DOWN_OVERRIDE_1 0x056 /* Tx Analog Power Down Override 1 */
120#define REG_ANALOG_POWER_DOWN_OVERRIDE 0x057 /* Analog Power Down Override */
121#define REG_MISC_POWER_DOWN_OVERRIDE 0x058 /* Misc Power Down Override */
122#define REG_CH_1_OVERFLOW 0x05E /* CH 1 Overflow */
123#define REG_CH_2_OVERFLOW 0x05F /* CH 2 Overflow */
124#define REG_TX_FILTER_COEF_ADDR 0x060 /* TX Filter Coefficient Address */
125#define REG_TX_FILTER_COEF_WRITE_DATA_1 0x061 /* TX Filter Coefficient Write Data 1 */
126#define REG_TX_FILTER_COEF_WRITE_DATA_2 0x062 /* TX Filter Coefficient Write Data 2 */
127#define REG_TX_FILTER_COEF_READ_DATA_1 0x063 /* TX Filter Coefficient Read Data 1 */
128#define REG_TX_FILTER_COEF_READ_DATA_2 0x064 /* TX Filter Coefficient Read Data 2 */
129#define REG_TX_FILTER_CONF 0x065 /* TX Filter Configuration */
130#define REG_TX_MON_LOW_GAIN 0x067 /* Tx Mon Low Gain */
131#define REG_TX_MON_HIGH_GAIN 0x068 /* Tx Mon High Gain */
132#define REG_TX_MON_DELAY 0x069 /* Tx Mon Delay */
133#define REG_TX_LEVEL_THRESH 0x06A /* Tx Level Threshold */
134#define REG_TX_RSSI1 0x06B /* TX RSSI1 */
135#define REG_TX_RSSI2 0x06C /* TX RSSI2 */
136#define REG_TX_RSSI_LSB 0x06D /* TX RSSI LSB */
137#define REG_TPM_MODE_ENABLE 0x06E /* TPM Mode Enable */
138#define REG_TX_MON_TEMP_GAIN_COEF 0x06F /* Temp Gain Coefficient */
139#define REG_TX_MON_1_CONFIG 0x070 /* Tx Mon 1 Config */
140#define REG_TX_MON_2_CONFIG 0x071 /* Tx Mon 2 Config */
141#define REG_TX1_ATTEN_0 0x073 /* Tx1 Atten 0 */
142#define REG_TX1_ATTEN_1 0x074 /* Tx1 Atten 1 */
143#define REG_TX2_ATTEN_0 0x075 /* Tx2 Atten 0 */
144#define REG_TX2_ATTEN_1 0x076 /* Tx2 Atten 1 */
145#define REG_TX_ATTEN_OFFSET 0x077 /* Tx Atten Offset */
146#define REG_TX_ATTEN_THRESH 0x078 /* Tx Atten Threshold */
147#define REG_TX1_DIG_ATTEN 0x079 /* Tx1 Dig Attenuation */
148#define REG_TX2_DIG_ATTEN 0x07C /* Tx2 Dig Attenuation */
149#define REG_TX1_SYMBOL_ATTEN 0x07F /* TX1 Symbol Attenuation */
150#define REG_TX2_SYMBOL_ATTEN 0x080 /* TX2 Symbol Attenuation */
151#define REG_TX_SYMBOL_ATTEN_CONFIG 0x081 /* TX Symbol Atten Config */
152#define REG_TX1_OUT_1_PHASE_CORR 0x08E /* Tx1 Out 1 Phase Corr */
153#define REG_TX1_OUT_1_GAIN_CORR 0x08F /* Tx1 Out 1 Gain Corr */
154#define REG_TX2_OUT_1_PHASE_CORR 0x090 /* Tx2 Out 1 Phase Corr */
155#define REG_TX2_OUT_1_GAIN_CORR 0x091 /* Tx2 Out 1 Gain Corr */
156#define REG_TX1_OUT_1_OFFSET_I 0x092 /* Tx1 Out 1 Offset I */
157#define REG_TX1_OUT_1_OFFSET_Q 0x093 /* Tx1 Out 1 Offset Q */
158#define REG_TX2_OUT_1_OFFSET_I 0x094 /* Tx2 Out 1 Offset I */
159#define REG_TX2_OUT_1_OFFSET_Q 0x095 /* Tx2 Out 1 Offset Q */
160#define REG_TX1_OUT_2_PHASE_CORR 0x096 /* Tx1 Out 2 Phase Corr */
161#define REG_TX1_OUT_2_GAIN_CORR 0x097 /* Tx1 Out 2 Gain Corr */
162#define REG_TX2_OUT_2_PHASE_CORR 0x098 /* Tx2 Out 2 Phase Corr */
163#define REG_TX2_OUT_2_GAIN_CORR 0x099 /* Tx2 Out 2 Gain Corr */
164#define REG_TX1_OUT_2_OFFSET_I 0x09A /* Tx1 Out 2 Offset I */
165#define REG_TX1_OUT_2_OFFSET_Q 0x09B /* Tx1 Out 2 Offset Q */
166#define REG_TX2_OUT_2_OFFSET_I 0x09C /* Tx2 Out 2 Offset I */
167#define REG_TX2_OUT_2_OFFSET_Q 0x09D /* Tx2 Out 2 Offset Q */
168#define REG_TX_FORCE_BITS 0x09F /* Force Bits */
169#define REG_QUAD_CAL_NCO_FREQ_PHASE_OFFSET 0x0A0 /* Quad Cal NCO Freq & Phase Offset */
170#define REG_QUAD_CAL_CTRL 0x0A1 /* Quad Cal Control */
171#define REG_KEXP_1 0x0A2 /* Kexp 1 */
172#define REG_KEXP_2 0x0A3 /* Kexp 2 */
173#define REG_QUAD_SETTLE_COUNT 0x0A4 /* QUAD Settle count */
174#define REG_MAG_FTEST_THRESH 0x0A5 /* Mag. Ftest Thresh */
175#define REG_MAG_FTEST_THRESH_2 0x0A6 /* Mag. Ftest Thresh 2 */
176#define REG_QUAD_CAL_STATUS_TX1 0x0A7 /* Quad cal status Tx1 */
177#define REG_QUAD_CAL_STATUS_TX2 0x0A8 /* Quad cal status Tx2 */
178#define REG_QUAD_CAL_COUNT 0x0A9 /* Quad cal Count */
179#define REG_TX_QUAD_FULL_LMT_GAIN 0x0AA /* Tx Quad Full/LMT Gain */
180#define REG_SQUARER_CONFIG 0x0AB /* Squarer Config */
181#define REG_TX_QUAD_CAL_ATTEN 0x0AC /* TX Quad Cal Atten */
182#define REG_THRESH_ACCUM 0x0AD /* Thresh Accum */
183#define REG_TX_QUAD_LPF_GAIN 0x0AE /* Tx Quad LPF Gain */
184#define REG_TXDAC_VDS_I 0x0B0 /* TxDAC Vds I */
185#define REG_TXDAC_VDS_Q 0x0B1 /* TxDAC Vds Q */
186#define REG_TXDAC_GN_I 0x0B2 /* TxDAC gn I */
187#define REG_TXDAC_GN_Q 0x0B3 /* TxDAC gn Q */
188#define REG_TXBBF_OPAMP_A 0x0C0 /* TxBBF OpAmp A */
189#define REG_TXBBF_OPAMP_B 0x0C1 /* TxBBF OpAmp B */
190#define REG_TX_BBF_R1 0x0C2 /* Tx BBF R1 */
191#define REG_TX_BBF_R2 0x0C3 /* Tx BBF R2 */
192#define REG_TX_BBF_R3 0x0C4 /* Tx BBF R3 */
193#define REG_TX_BBF_R4 0x0C5 /* Tx BBF R4 */
194#define REG_TX_BBF_RP 0x0C6 /* Tx BBF RP */
195#define REG_TX_BBF_C1 0x0C7 /* Tx BBF C1 */
196#define REG_TX_BBF_C2 0x0C8 /* Tx BBF C2 */
197#define REG_TX_BBF_CP 0x0C9 /* Tx BBF Cp */
198#define REG_TX_TUNE_CTRL 0x0CA /* Tx Tune Control */
199#define REG_TX_BBF_R2B 0x0CB /* Tx BBF R2b */
200#define REG_TX_BBF_TUNE 0x0CC /* Tx BBF Tune */
201#define REG_CONFIG0 0x0D0 /* Config0 */
202#define REG_RESISTOR 0x0D1 /* Resistor */
203#define REG_CAPACITOR 0x0D2 /* Capacitor */
204#define REG_LO_CM 0x0D3 /* LO CM */
205#define REG_TX_BBF_TUNE_DIVIDER 0x0D6 /* TX BBF Tune Divider */
206#define REG_TX_BBF_TUNE_MODE 0x0D7 /* TX BBF Tune Mode */
207#define REG_RX_FILTER_COEF_ADDR 0x0F0 /* Rx Filter Coeff Addr */
208#define REG_RX_FILTER_COEF_DATA_1 0x0F1 /* Rx Filter Coeff Data 1 */
209#define REG_RX_FILTER_COEF_DATA_2 0x0F2 /* Rx Filter Coeff Data 2 */
210#define REG_RX_FILTER_COEF_READ_DATA_1 0x0F3 /* Rx Filter Coeff Read Data 1 */
211#define REG_RX_FILTER_COEF_READ_DATA_2 0x0F4 /* Rx Filter Coeff Read Data 2 */
212#define REG_RX_FILTER_CONFIG 0x0F5 /* Rx Filter Config */
213#define REG_RX_FILTER_GAIN 0x0F6 /* Rx Filter Gain */
214#define REG_AGC_CONFIG_1 0x0FA /* AGC Config1 */
215#define REG_AGC_CONFIG_2 0x0FB /* AGC config2 */
216#define REG_AGC_CONFIG_3 0x0FC /* AGC Config3 */
217#define REG_MAX_LMT_FULL_GAIN 0x0FD /* Max LMT/Full Gain */
218#define REG_PEAK_WAIT_TIME 0x0FE /* Peak Wait Time */
219#define REG_DIGITAL_GAIN 0x100 /* Digital Gain */
220#define REG_AGC_LOCK_LEVEL 0x101 /* AGC Lock Level */
221#define REG_ADC_NOISE_CORRECTION_FACTOR 0x102 /* ADC noise Correction Factor */
222#define REG_GAIN_STP_CONFIG1 0x103 /* Gain Step Config1 */
223#define REG_ADC_SMALL_OVERLOAD_THRESH 0x104 /* ADC Small Overload Threshold */
224#define REG_ADC_LARGE_OVERLOAD_THRESH 0x105 /* ADC Large Overload Threshold */
225#define REG_GAIN_STP_CONFIG_2 0x106 /* Gain Step Config 2 */
226#define REG_SMALL_LMT_OVERLOAD_THRESH 0x107 /* Small LMT Overload Threshold */
227#define REG_LARGE_LMT_OVERLOAD_THRESH 0x108 /* Large LMT Overload Threshold */
228#define REG_RX1_MANUAL_LMT_FULL_GAIN 0x109 /* Rx1 Manual LMT/Full Gain */
229#define REG_RX1_MANUAL_LPF_GAIN 0x10A /* Rx1 Manual LPF gain */
230#define REG_RX1_MANUAL_DIGITALFORCED_GAIN 0x10B /* Rx1 Manual Digital/Forced Gain */
231#define REG_RX2_MANUAL_LMT_FULL_GAIN 0x10C /* Rx2 Manual LMT/Full Gain */
232#define REG_RX2_MANUAL_LPF_GAIN 0x10D /* Rx2 Manual LPF Gain */
233#define REG_RX2_MANUAL_DIGITALFORCED_GAIN 0x10E /* Rx2 Manual Digital/Forced Gain */
234#define REG_FAST_CONFIG_1 0x110 /* Config 1 */
235#define REG_FAST_CONFIG_2_SETTLING_DELAY 0x111 /* Config 2 & Settling Delay */
236#define REG_FAST_ENERGY_LOST_THRESH 0x112 /* Energy Lost Threshold */
237#define REG_FAST_STRONGER_SIGNAL_THRESH 0x113 /* Stronger Signal Threshold */
238#define REG_FAST_LOW_POWER_THRESH 0x114 /* Low Power Threshold */
239#define REG_FAST_STRONG_SIGNAL_FREEZE 0x115 /* Strong Signal Freeze */
240#define REG_FAST_FINAL_OVER_RANGE_AND_OPT_GAIN 0x116 /* Final Over Range and Opt Gain */
241#define REG_FAST_ENERGY_DETECT_COUNT 0x117 /* Energy Detect Count */
242#define REG_FAST_AGCLL_UPPER_LIMIT 0x118 /* AGCLL Upper Limit */
243#define REG_FAST_GAIN_LOCK_EXIT_COUNT 0x119 /* Gain Lock Exit Count */
244#define REG_FAST_INITIAL_LMT_GAIN_LIMIT 0x11A /* Initial LMT Gain Limit */
245#define REG_FAST_INCREMENT_TIME 0x11B /* Increment Time */
246#define REG_AGC_INNER_LOW_THRESH 0x120 /* AGC Inner Low Threshold */
247#define REG_LMT_OVERLOAD_COUNTERS 0x121 /* LMT Overload Counters */
248#define REG_ADC_OVERLOAD_COUNTERS 0x122 /* ADC Overload Counters */
249#define REG_GAIN_STP1 0x123 /* Gain Step1 */
250#define REG_GAIN_UPDATE_COUNTER1 0x124 /* Gain Update Counter1 */
251#define REG_GAIN_UPDATE_COUNTER2 0x125 /* Gain Update Counter2 */
252#define REG_DIGITAL_SAT_COUNTER 0x128 /* Digital Sat Counter */
253#define REG_OUTER_POWER_THRESHS 0x129 /* Outer Power Thresholds */
254#define REG_GAIN_STP_2 0x12A /* Gain Step 2 */
255#define REG_EXT_LNA_HIGH_GAIN 0x12C /* Ext LNA High Gain */
256#define REG_EXT_LNA_LOW_GAIN 0x12D /* Ext LNA Low Gain */
257#define REG_GAIN_TABLE_ADDRESS 0x130 /* Gain Table Address */
258#define REG_GAIN_TABLE_WRITE_DATA1 0x131 /* Gain Table Write Data1 */
259#define REG_GAIN_TABLE_WRITE_DATA2 0x132 /* Gain Table Write Data2 */
260#define REG_GAIN_TABLE_WRITE_DATA3 0x133 /* Gain Table Write Data 3 */
261#define REG_GAIN_TABLE_READ_DATA1 0x134 /* Gain Table Read Data 1 */
262#define REG_GAIN_TABLE_READ_DATA2 0x135 /* Gain Table Read Data 2 */
263#define REG_GAIN_TABLE_READ_DATA3 0x136 /* Gain Table Read Data 3 */
264#define REG_GAIN_TABLE_CONFIG 0x137 /* Gain Table Config */
265#define REG_GM_SUB_TABLE_ADDRESS 0x138 /* Gm Sub Table Address */
266#define REG_GM_SUB_TABLE_GAIN_WRITE 0x139 /* Gm Sub Table Gain Word Write */
267#define REG_GM_SUB_TABLE_BIAS_WRITE 0x13A /* Gm Sub Table Bias Word Write */
268#define REG_GM_SUB_TABLE_CTRL_WRITE 0x13B /* Gm Sub Table Control Word Write */
269#define REG_GM_SUB_TABLE_GAIN_READ 0x13C /* Gm Sub Table Gain Word Read */
270#define REG_GM_SUB_TABLE_BIAS_READ 0x13D /* Gm Sub Table Bias Word Read */
271#define REG_GM_SUB_TABLE_CTRL_READ 0x13E /* Gm Sub Table Control Word Read */
272#define REG_GM_SUB_TABLE_CONFIG 0x13F /* Gm Sub Table Config */
273#define REG_WORD_ADDRESS 0x140 /* Word Address */
274#define REG_GAIN_DIFF_WORDERROR_WRITE 0x141 /* Gain Diff Word/Error Write */
275#define REG_GAIN_ERROR_READ 0x142 /* Gain Error Read */
276#define REG_CONFIG 0x143 /* Config */
277#define REG_LNA_GAIN_DIFF_READ_BACK 0x144 /* LNA Gain Diff Read Back */
278#define REG_MAX_MIXER_CALIBRATION_GAIN_INDEX 0x145 /* Max Mixer Calibration Gain Index */
279#define REG_TEMP_GAIN_COEF 0x146 /* Temp Gain Coefficient */
280#define REG_SETTLE_TIME 0x147 /* Settle Time */
281#define REG_MEASURE_DURATION 0x148 /* Measure Duration */
282#define REG_CAL_TEMP_SENSOR_WORD 0x149 /* Cal Temp sensor word */
283#define REG_MEASURE_DURATION_01 0x150 /* Measure Duration 0&1 */
284#define REG_MEASURE_DURATION_23 0x151 /* Measure Duration 2&3 */
285#define REG_RSSI_WEIGHT_0 0x152 /* RSSI Weight 0 */
286#define REG_RSSI_WEIGHT_1 0x153 /* RSSI Weight 1 */
287#define REG_RSSI_WEIGHT_2 0x154 /* RSSI Weight 2 */
288#define REG_RSSI_WEIGHT_3 0x155 /* RSSI Weight 3 */
289#define REG_RSSI_DELAY 0x156 /* RSSI delay */
290#define REG_RSSI_WAIT_TIME 0x157 /* RSSI wait time */
291#define REG_RSSI_CONFIG 0x158 /* RSSI Config */
292#define REG_ADC_MEASURE_DURATION_01 0x159 /* ADC Measure Duration 0&1 */
293#define REG_ADC_WEIGHT_0 0x15A /* ADC Weight 0 */
294#define REG_ADC_WEIGHT_1 0x15B /* ADC Weight 1 */
295#define REG_DEC_POWER_MEASURE_DURATION_0 0x15C /* Dec Power Measure Duration 0 */
296#define REG_LNA_GAIN 0x15D /* LNA Gain */
297#define REG_CH1_ADC_POWER 0x160 /* CH1 ADC Power */
298#define REG_CH1_RX_FILTER_POWER 0x161 /* CH1 Rx filter Power */
299#define REG_CH2_ADC_POWER 0x162 /* CH2 ADC Power */
300#define REG_CH2_RX_FILTER_POWER 0x163 /* CH2 Rx filter Power */
301#define REG_RX_QUAD_CAL_LEVEL 0x168 /* Rx Quad Cal Level */
302#define REG_CALIBRATION_CONFIG_1 0x169 /* Calibration Config 1 */
303#define REG_CALIBRATION_CONFIG_2 0x16A /* Calibration config2 */
304#define REG_CALIBRATION_CONFIG_3 0x16B /* Calibration config3 */
305#define REG_CALIB_COUNT 0x16C /* Calib count */
306#define REG_SETTLE_COUNT 0x16D /* Settle count */
307#define REG_RX_QUAD_GAIN1 0x16E /* Rx Quad gain1 */
308#define REG_RX_QUAD_GAIN2 0x16F /* Rx Quad gain2 */
309#define REG_RX1_INPUT_A_PHASE_CORR 0x170 /* Rx1 Input A Phase Corr */
310#define REG_RX1_INPUT_A_GAIN_CORR 0x171 /* Rx1 Input A Gain Corr */
311#define REG_RX2_INPUT_A_PHASE_CORR 0x172 /* Rx2 Input A Phase Corr */
312#define REG_RX2_INPUT_A_GAIN_CORR 0x173 /* Rx2 Input A Gain Corr */
313#define REG_RX1_INPUT_A_Q_OFFSET 0x174 /* Rx1 Input A Q" Offset */
314#define REG_RX1_INPUT_A_OFFSETS 0x175 /* Rx1 Input A Offsets */
315#define REG_INPUT_A_OFFSETS_1 0x176 /* Input A Offsets 1 */
316#define REG_RX2_INPUT_A_OFFSETS 0x177 /* Rx2 Input A Offsets */
317#define REG_RX2_INPUT_A_I_OFFSET 0x178 /* Rx2 Input A "I" Offset */
318#define REG_RX1_INPUT_BC_PHASE_CORR 0x179 /* Rx1 Input B&C Phase Corr */
319#define REG_RX1_INPUT_BC_GAIN_CORR 0x17A /* Rx1 Input B&C Gain Corr */
320#define REG_RX2_INPUT_BC_PHASE_CORR 0x17B /* Rx2 Input B&C Phase Corr */
321#define REG_RX2_INPUT_BC_GAIN_CORR 0x17C /* Rx2 Input B&C Gain Corr */
322#define REG_RX1_INPUT_BC_Q_OFFSET 0x17D /* Rx1 Input B&C "Q" Offset */
323#define REG_RX1_INPUT_BC_OFFSETS 0x17E /* Rx1 Input B&C Offsets */
324#define REG_INPUT_BC_OFFSETS_1 0x17F /* Input B&C Offsets 1 */
325#define REG_RX2_INPUT_BC_OFFSETS 0x180 /* Rx2 Input B&C Offsets */
326#define REG_RX2_INPUT_BC_I_OFFSET 0x181 /* Rx2 Input B&C "I" Offset */
327#define REG_FORCE_BITS 0x182 /* Force Bits */
328#define REG_WAIT_COUNT 0x185 /* Wait Count */
329#define REG_RF_DC_OFFSET_COUNT 0x186 /* RF DC Offset Count */
330#define REG_RF_DC_OFFSET_CONFIG_1 0x187 /* RF DC Offset Config1 */
331#define REG_RF_DC_OFFSET_ATTEN 0x188 /* RF DC Offset Attenuation */
332#define REG_INVERT_BITS 0x189 /* Invert Bits */
333#define REG_DC_OFFSET_CONFIG2 0x18B /* DC Offset Config2 */
334#define REG_RF_CAL_GAIN_INDEX 0x18C /* RF Cal Gain Index */
335#define REG_SOI_THRESH 0x18D /* SOI Threshold */
336#define REG_BB_DC_OFFSET_SHIFT 0x190 /* BB DC Offset Shift */
337#define REG_BB_DC_OFFSET_FAST_SETTLE_SHIFT 0x191 /* BB DC Offset Fast Settle Shift */
338#define REG_BB_FAST_SETTLE_DUR 0x192 /* BB Fast Settle Dur */
339#define REG_BB_DC_OFFSET_COUNT 0x193 /* BB DC Offset Count */
340#define REG_BB_DC_OFFSET_ATTEN 0x194 /* BB DC Offset Attenuation */
341#define REG_RX1_BB_DC_WORD_I_MSB 0x19A /* RX1 BB DC word I MSB */
342#define REG_RX1_BB_DC_WORD_I_LSB 0x19B /* RX1 BB DC word I LSB */
343#define REG_RX1_BB_DC_WORD_Q_MSB 0x19C /* RX1 BB DC word Q MSB */
344#define REG_RX1_BB_DC_WORD_Q_LSB 0x19D /* RX1 BB DC word Q LSB */
345#define REG_RX2_BB_DC_WORD_I_MSB 0x19E /* RX2 BB DC word I MSB */
346#define REG_RX2_BB_DC_WORD_I_LSB 0x19F /* RX2 BB DC word I LSB */
347#define REG_RX2_BB_DC_WORD_Q_MSB 0x1A0 /* RX2 BB DC word Q MSB */
348#define REG_RX2_BB_DC_WORD_Q_LSB 0x1A1 /* RX2 BB DC word Q LSB */
349#define REG_BB_TRACK_CORR_WORD_I_MSB 0x1A2 /* BB Track corr word I MSB */
350#define REG_BB_TRACK_CORR_WORD_I_LSB 0x1A3 /* BB Track corr word I LSB */
351#define REG_BB_TRACK_CORR_WORD_Q_MSB 0x1A4 /* BB Track corr word Q MSB */
352#define REG_BB_TRACK_CORR_WORD_Q_LSB 0x1A5 /* BB Track corr word Q LSB */
353#define REG_RX1_RSSI_SYMBOL 0x1A7 /* Rx1 RSSI Symbol */
354#define REG_RX1_RSSI_PREAMBLE 0x1A8 /* Rx1 RSSI preamble */
355#define REG_RX2_RSSI_SYMBOL 0x1A9 /* Rx2 RSSI symbol */
356#define REG_RX2_RSSI_PREAMBLE 0x1AA /* Rx2 RSSI preamble */
357#define REG_SYMBOL_LSB 0x1AB /* Symbol LSB */
358#define REG_PREAMBLE_LSB 0x1AC /* Preamble LSB */
359#define REG_RX_PATH_GAIN_MSB 0x1AD /* Rx Path Gain */
360#define REG_RX_PATH_GAIN_LSB 0x1AE /* Rx Path Gain */
361#define REG_RX_DIFF_LNA_FORCE 0x1B0 /* Rx Diff LNA Force */
362#define REG_RX_LNA_BIAS_COARSE 0x1B1 /* Rx LNA Bias Coarse */
363#define REG_RX_LNA_BIAS_FINE_0 0x1B2 /* Rx LNA Bias Fine 0 */
364#define REG_RX_LNA_BIAS_FINE_1 0x1B3 /* Rx LNA Bias Fine 1 */
365#define REG_RX_MIX_GM_CONFIG 0x1C0 /* Rx Mix Gm Config */
366#define REG_RX1_MIX_GM_FORCE 0x1C1 /* Rx1 Mix Gm Force */
367#define REG_RX1_MIX_GM_BIAS_FORCE 0x1C2 /* Rx1 Mix Gm Bias (Force) */
368#define REG_RX2_MIX_GM_FORCE 0x1C3 /* Rx2 Mix Gm Force */
369#define REG_RX2_MIX_GM_BIAS_FORCE 0x1C4 /* Rx2 Mix Gm Bias (Force) */
370#define REG_INPUT_A_MSBS 0x1C8 /* Input A MSBs */
371#define REG_INPUT_A_RX1_I 0x1C9 /* Input A RX1 I */
372#define REG_INPUT_A_RX1_Q 0x1CA /* Input A RX1 Q */
373#define REG_INPUT_A_RX2_I 0x1CB /* Input A RX2 I */
374#define REG_INPUT_A_RX2_Q 0x1CC /* Input A RX2 Q */
375#define REG_INPUTS_BC_RX1_I 0x1CD /* Inputs B&C RX1 I */
376#define REG_BAND1_RX1_Q 0x1CE /* Band1 RX1 Q */
377#define REG_INPUTS_BC_RX2_I 0x1CF /* Inputs B&C RX2 I */
378#define REG_INPUTS_BC_RX2_Q 0x1D0 /* Inputs B&C RX2 Q */
379#define REG_INPUTS_BC_MSBS 0x1D1 /* Inputs B&C MSBs */
380#define REG_FORCE_OS_DAC 0x1D2 /* Force OS DAC */
381#define REG_RX_MIX_LO_CM 0x1D5 /* Rx Mix LO CM */
382#define REG_RX_CGB_SEG_ENABLE 0x1D6 /* Rx CGB Seg Enable */
383#define REG_RX_MIX_INPUTBIAS 0x1D7 /* Rx Mix Input/Bias */
384#define REG_RX_TIA_CONFIG 0x1DB /* Rx TIA Config */
385#define REG_TIA1_C_LSB 0x1DC /* TIA1 C LSB */
386#define REG_TIA1_C_MSB 0x1DD /* TIA1 C MSB */
387#define REG_TIA2_C_LSB 0x1DE /* TIA2 C LSB */
388#define REG_TIA2_C_MSB 0x1DF /* TIA2 C MSB */
389#define REG_RX1_BBF_R1A 0x1E0 /* Rx1 BBF R1A */
390#define REG_RX2_BBF_R1A 0x1E1 /* Rx2 BBF R1A */
391#define REG_RX1_TUNE_CTRL 0x1E2 /* Rx1 Tune Control */
392#define REG_RX2_TUNE_CTRL 0x1E3 /* Rx2 Tune Control */
393#define REG_RX1_BBF_R5 0x1E4 /* Rx1 BBF R5 */
394#define REG_RX2_BBF_R5 0x1E5 /* Rx2 BBF R5 */
395#define REG_RX_BBF_R2346 0x1E6 /* Rx BBF R2346 */
396#define REG_RX_BBF_C1_MSB 0x1E7 /* Rx BBF C1 MSB */
397#define REG_RX_BBF_C1_LSB 0x1E8 /* Rx BBF C1 LSB */
398#define REG_RX_BBF_C2_MSB 0x1E9 /* Rx BBF C2 MSB */
399#define REG_RX_BBF_C2_LSB 0x1EA /* Rx BBF C2 LSB */
400#define REG_RX_BBF_C3_MSB 0x1EB /* Rx BBF C3 MSB */
401#define REG_RX_BBF_C3_LSB 0x1EC /* Rx BBF C3 LSB */
402#define REG_RX_BBF_CC1_CTR 0x1ED /* Rx BBF CC1 Ctr */
403#define REG_RX_BBF_POW_RZ_BYTE0 0x1EE /* Rx BBF Pow Rz Byte0 */
404#define REG_RX_BBF_CC2_CTR 0x1EF /* Rx BBF CC2 Ctr */
405#define REG_RX_BBF_POW_RZ_BYTE1 0x1F0 /* Rx BBF Pow Rz Byte1 */
406#define REG_RX_BBF_CC3_CTR 0x1F1 /* Rx BBF CC3 Ctr */
407#define REG_RX_BBF_R5_TUNE 0x1F2 /* Rx BBF R5 Tune */
408#define REG_RX_BBF_TUNE 0x1F3 /* Rx BBF Tune */
409#define REG_RX1_BBF_MAN_GAIN 0x1F4 /* Rx1 BBF Man Gain */
410#define REG_RX2_BBF_MAN_GAIN 0x1F5 /* Rx2 BBF Man Gain */
411#define REG_RX_BBF_TUNE_DIVIDE 0x1F8 /* RX BBF Tune Divide */
412#define REG_RX_BBF_TUNE_CONFIG 0x1F9 /* RX BBF Tune Config */
413#define REG_POLE_GAIN 0x1FA /* Pole gain */
414#define REG_RX_BBBW_MHZ 0x1FB /* Rx BBBW MHz */
415#define REG_RX_BBBW_KHZ 0x1FC /* Rx BBBW kHz */
416#define REG_FB_DAC_CLK_DELAY1 0x201 /* FB DAC Clk Delay1 */
417#define REG_FB_DAC_CLK_DELAY2 0x202 /* FB DAC Clk Delay2 */
418#define REG_FLASH_SAMPLE_CLK_DELAY_3P 0x203 /* Flash Sample Clk Delay 3p */
419#define REG_FLASH_SAMPLE_CLK_DELAY_3N 0x204 /* Flash Sample Clk Delay 3n */
420#define REG_TEST_MUX_2I 0x205 /* Test MUX 2i */
421#define REG_TEST_MUX_2Q 0x206 /* Test MUX 2q */
422#define REG_INTEGRATOR_1_RESISTANCE 0x207 /* Integrator 1 Resistance */
423#define REG_INTEGRATOR_1_CAPACITANCE 0x208 /* Integrator 1 Capacitance */
424#define REG_INTEGRATOR_23_RESISTANCE 0x209 /* Integrator 23 Resistance */
425#define REG_INTEGRATOR_2_RESISTANCE 0x20A /* Integrator 2 Resistance */
426#define REG_INTEGRATOR_2_CAPACITANCE 0x20B /* Integrator 2 Capacitance */
427#define REG_INTEGRATOR_3_RESISTANCE 0x20C /* Integrator 3 Resistance */
428#define REG_INTEGRATOR_3_CAPACITANCE 0x20D /* Integrator 3 Capacitance */
429#define REG_INTEGRATOR_AMP_CC 0x20E /* Integrator Amp Cc */
430#define REG_INT_1_FB_DAC_NMOS_CURRENT_SOURCE 0x20F /* Int 1 FB DAC NMOS Current Source */
431#define REG_INT_1_FB_DAC_NMOS_CASOADE_BIAS_CURRENT 0x210 /* Int 1 FB DAC NMOS Casoade Bias Current */
432#define REG_INT_1_FB_DAC_PMOS_CURRENT_SOURCE 0x211 /* Int 1 FB DAC PMOS Current Source */
433#define REG_INT_2_FB_DAC_NMOS_CURRENT_SOURCE 0x212 /* Int 2 FB DAC NMOS Current Source */
434#define REG_INT_2_FB_DAC_NMOS_CASCODE_BIAS_CURRENT 0x213 /* Int 2 FB DAC NMOS Cascode Bias Current */
435#define REG_INT_2_FB_DAC_PMOS_CURRENT_SOURCE 0x214 /* Int 2 FB DAC PMOS Current Source */
436#define REG_INT_3_FB_DAC_NMOS_CURRENT_SOURCE 0x215 /* Int 3 FB DAC NMOS Current Source */
437#define REG_INT_3_FB_DAC_NMOS_CASCODE_BIAS_CURRENT 0x216 /* Int 3 FB DAC NMOS Cascode Bias Current */
438#define REG_INT_3_FB_DAC_PMOS_CURRENT_SOURCE 0x217 /* Int 3 FB DAC PMOS Current Source */
439#define REG_FB_DAC_BIAS_CURRENT 0x218 /* FB DAC Bias Current */
440#define REG_INT_1_1ST_STAGE_CURRENT 0x219 /* Int 1 1st Stage Current */
441#define REG_INT_1_1ST_STAGE_CASCODE_CURRENT 0x21A /* Int 1 1st Stage Cascode Current */
442#define REG_INT_1_2ND_STAGE_CURRENT 0x21B /* Int 1 2nd Stage Current */
443#define REG_INTEGRATOR_2_1ST_STAGE_CURRENT 0x21C /* Integrator 2 1st Stage Current */
444#define REG_INT_2_1ST_STAGE_CASCODE_CURRENT 0x21D /* Int 2 1st Stage Cascode Current */
445#define REG_INT_2_2ND_STAGE_CURRENT 0x21E /* Int 2 2nd Stage Current */
446#define REG_INT_3_1ST_STAGE_CURRENT 0x21F /* Int 3 1st Stage Current */
447#define REG_INT_3_1ST_STAGE_CASCODE_CURRENT 0x220 /* Int 3 1st Stage Cascode Current */
448#define REG_INT_3_2ND_STAGE_CURRENT 0x221 /* Int 3 2nd Stage Current */
449#define REG_FLASH_BIAS_CURRENT 0x222 /* Flash Bias Current */
450#define REG_FLASH_LADDER_BIAS 0x223 /* Flash Ladder Bias */
451#define REG_FLASH_LADDER_CASCODE_CURRENT 0x224 /* Flash Ladder Cascode Current */
452#define REG_FLASH_LADDER_BIAS2 0x225 /* Flash Ladder Bias2 */
453#define REG_RESET 0x226 /* Reset */
454#define REG_RX_PFD_CONFIG 0x230 /* RX PFD Config */
455#define REG_RX_INTEGER_BYTE_0 0x231 /* RX Integer Byte 0 */
456#define REG_RX_INTEGER_BYTE_1 0x232 /* RX Integer Byte 1 */
457#define REG_RX_FRACT_BYTE_0 0x233 /* RX Fractional Byte 0 */
458#define REG_RX_FRACT_BYTE_1 0x234 /* RX Fractional Byte 1 */
459#define REG_RX_FRACT_BYTE_2 0x235 /* RX Fractional Byte 2 */
460#define REG_RX_FORCE_ALC 0x236 /* RX Force ALC */
461#define REG_RX_FORCE_VCO_TUNE_0 0x237 /* RX Force VCO Tune 0 */
462#define REG_RX_FORCE_VCO_TUNE_1 0x238 /* RX Force VCO Tune 1 */
463#define REG_RX_ALC_VARACTOR 0x239 /* RX ALC/Varactor */
464#define REG_RX_VCO_OUTPUT 0x23A /* RX VCO Output */
465#define REG_RX_CP_CURRENT 0x23B /* RX CP Current */
466#define REG_RX_CP_OFFSET 0x23C /* RX CP Offset */
467#define REG_RX_CP_CONFIG 0x23D /* RX CP Config */
468#define REG_RX_LOOP_FILTER_1 0x23E /* RX Loop Filter 1 */
469#define REG_RX_LOOP_FILTER_2 0x23F /* RX Loop Filter 2 */
470#define REG_RX_LOOP_FILTER_3 0x240 /* RX Loop Filter 3 */
471#define REG_RX_DITHERCP_CAL 0x241 /* RX Dither/CP Cal */
472#define REG_RX_VCO_BIAS_1 0x242 /* RX VCO Bias 1 */
473#define REG_RX_CAL_STATUS 0x244 /* RX Cal Status */
474#define REG_RX_VCO_CAL_REF 0x245 /* RX VCO Cal Ref */
475#define REG_RX_VCO_PD_OVERRIDES 0x246 /* RX VCO Pd Overrides */
476#define REG_RX_CP_OVERRANGE_VCO_LOCK 0x247 /* RX CP Over Range/VCO Lock */
477#define REG_RX_VCO_LDO 0x248 /* RX VCO LDO */
478#define REG_RX_VCO_CAL 0x249 /* RX VCO Cal */
479#define REG_RX_LOCK_DETECT_CONFIG 0x24A /* RX Lock Detect Config */
480#define REG_RX_CP_LEVEL_DETECT 0x24B /* RX CP Level Detect */
481#define REG_RX_DSM_SETUP_0 0x24C /* RX DSM Setup 0 */
482#define REG_RX_DSM_SETUP_1 0x24D /* RX DSM Setup 1 */
483#define REG_RX_CORRECTION_WORD0 0x24E /* RX Correction Word0 */
484#define REG_RX_CORRECTION_WORD1 0x24F /* RX Correction Word1 */
485#define REG_RX_VCO_VARACTOR_CTRL_0 0x250 /* RX VCO Varactor Control 0 */
486#define REG_RX_VCO_VARACTOR_CTRL_1 0x251 /* RX VCO Varactor Control 1 */
487#define REG_RX_FAST_LOCK_SETUP 0x25A /* Rx Fast Lock Setup */
488#define REG_RX_FAST_LOCK_SETUP_INIT_DELAY 0x25B /* Rx Fast Lock Setup Init Delay */
489#define REG_RX_FAST_LOCK_PROGRAM_ADDR 0x25C /* Rx Fast Lock Program Addr */
490#define REG_RX_FAST_LOCK_PROGRAM_DATA 0x25D /* Rx Fast Lock Program Data */
491#define REG_RX_FAST_LOCK_PROGRAM_READ 0x25E /* Rx Fast Lock Program Read */
492#define REG_RX_FAST_LOCK_PROGRAM_CTRL 0x25F /* Rx Fast Lock Program Control */
493#define REG_RX_LO_GEN_POWER_MODE 0x261 /* Rx LO Gen Power Mode */
494#define REG_TX_PFD_CONFIG 0x270 /* TX PFD Config */
495#define REG_TX_INTEGER_BYTE_0 0x271 /* TX Integer Byte 0 */
496#define REG_TX_INTEGER_BYTE_1 0x272 /* TX Integer Byte 1 */
497#define REG_TX_FRACT_BYTE_0 0x273 /* TX Fractional Byte 0 */
498#define REG_TX_FRACT_BYTE_1 0x274 /* TX Fractional Byte 1 */
499#define REG_TX_FRACT_BYTE_2 0x275 /* TX Fractional Byte 2 */
500#define REG_TX_FORCE_ALC 0x276 /* TX Force ALC */
501#define REG_TX_FORCE_VCO_TUNE_0 0x277 /* TX Force VCO Tune 0 */
502#define REG_TX_FORCE_VCO_TUNE_1 0x278 /* TX Force VCO Tune 1 */
503#define REG_TX_ALCVARACT_OR 0x279 /* TX ALC/Varact or */
504#define REG_TX_VCO_OUTPUT 0x27A /* TX VCO Output */
505#define REG_TX_CP_CURRENT 0x27B /* TX CP Current */
506#define REG_TX_CP_OFFSET 0x27C /* TX CP Offset */
507#define REG_TX_CP_CONFIG 0x27D /* TX CP Config */
508#define REG_TX_LOOP_FILTER_1 0x27E /* TX Loop Filter 1 */
509#define REG_TX_LOOP_FILTER_2 0x27F /* TX Loop Filter 2 */
510#define REG_TX_LOOP_FILTER_3 0x280 /* TX Loop Filter 3 */
511#define REG_TX_DITHERCP_CAL 0x281 /* TX Dither/CP Cal */
512#define REG_TX_VCO_BIAS_1 0x282 /* TX VCO Bias 1 */
513#define REG_TX_VCO_BIAS_2 0x283 /* TX VCO Bias 2 */
514#define REG_TX_CAL_STATUS 0x284 /* TX Cal Status */
515#define REG_TX_VCO_CAL_REF 0x285 /* TX VCO Cal Ref */
516#define REG_TX_VCO_PD_OVERRIDES 0x286 /* TX VCO Pd Overrides */
517#define REG_TX_CP_OVERRANGE_VCO_LOCK 0x287 /* TX CP Over Range/VCO Lock */
518#define REG_TX_VCO_LDO 0x288 /* TX VCO LDO */
519#define REG_TX_VCO_CAL 0x289 /* TX VCO Cal */
520#define REG_TX_LOCK_DETECT_CONFIG 0x28A /* TX Lock Detect Config */
521#define REG_TX_CP_LEVEL_DETECT 0x28B /* TX CP Level Detect */
522#define REG_TX_DSM_SETUP_0 0x28C /* TX DSM Setup 0 */
523#define REG_TX_DSM_SETUP_1 0x28D /* TX DSM Setup 1 */
524#define REG_TX_CORRECTION_WORD0 0x28E /* TX Correction Word0 */
525#define REG_TX_CORRECTION_WORD1 0x28F /* TX Correction Word1 */
526#define REG_TX_VCO_VARACTOR_CTRL_0 0x290 /* TX VCO Varactor Control 0 */
527#define REG_TX_VCO_VARACTOR_CTRL_1 0x291 /* TX VCO Varactor Control 1 */
528#define REG_DCXO_COARSE_TUNE 0x292 /* DCXO Coarse Tune */
529#define REG_DCXO_FINE_TUNE_HIGH 0x293 /* DCXO Fine Tune2 */
530#define REG_DCXO_FINE_TUNE_LOW 0x294 /* DCXO Fine Tune1 */
531#define REG_DCXO_CONFIG 0x295 /* DCXO Config */
532#define REG_DCXO_TEMPCO_WRITE 0x296 /* DCXO Tempco Write */
533#define REG_DCXO_TEMPCO_READ 0x297 /* DCXO Tempco Read */
534#define REG_DCXO_TEMPCO_ADDR 0x298 /* DCXO Tempco Addr */
535#define REG_DELTA_T_READ 0x299 /* Delta T Read */
536#define REG_TX_FAST_LOCK_SETUP 0x29A /* Tx Fast Lock Setup */
537#define REG_TX_FAST_LOCK_SETUP_INIT_DELAY 0x29B /* Tx Fast Lock Setup Init Delay */
538#define REG_TX_FAST_LOCK_PROGRAM_ADDR 0x29C /* Tx Fast Lock Program Addr */
539#define REG_TX_FAST_LOCK_PROGRAM_DATA 0x29D /* Tx Fast Lock Program Data */
540#define REG_TX_FAST_LOCK_PROGRAM_READ 0x29E /* Tx Fast Lock Program Read */
541#define REG_TX_FAST_LOCK_PROGRAM_CTRL 0x29F /* Tx Fast Lock Program Ctrl */
542#define REG_TX_LO_GEN_POWER_MODE 0x2A1 /* Tx LO Gen Power Mode */
543#define REG_BANDGAP_CONFIG0 0x2A6 /* Bandgap Config0 */
544#define REG_BANDGAP_CONFIG1 0x2A8 /* Bandgap Config1 */
545#define REG_REF_DIVIDE_CONFIG_1 0x2AB /* Ref Divide Config 1 */
546#define REG_REF_DIVIDE_CONFIG_2 0x2AC /* Ref Divide Config 2 */
547#define REG_GAIN_RX1 0x2B0 /* Gain Rx1 */
548#define REG_LPF_GAIN_RX1 0x2B1 /* LPF Gain Rx1 */
549#define REG_DIG_GAIN_RX1 0x2B2 /* Dig gain Rx1 */
550#define REG_FAST_ATTACK_STATE 0x2B3 /* Fast Attack State */
551#define REG_SLOW_LOOP_STATE 0x2B4 /* Slow Loop State */
552#define REG_GAIN_RX2 0x2B5 /* Gain Rx2 */
553#define REG_LPF_GAIN_RX2 0x2B6 /* LPF Gain Rx2 */
554#define REG_DIG_GAIN_RX2 0x2B7 /* Dig Gain Rx2 */
555#define REG_OVRG_SIGS_RX1 0x2B8 /* Ovrg Sigs Rx1 */
556#define REG_OVRG_SIGS_RX2 0x2B9 /* Ovrg Sigs Rx2 */
557#define REG_CTRL 0x3DF /* Control */
558#define REG_BIST_CONFIG 0x3F4 /* BIST Config */
559#define REG_OBSERVE_CONFIG 0x3F5 /* Observe Config */
560#define REG_BIST_AND_DATA_PORT_TEST_CONFIG 0x3F6 /* BIST and Data Port Test Config */
561#define REG_DAC_TEST_0 0x3FC /* DAC Test 0 */
562#define REG_DAC_TEST_1 0x3FD /* DAC Test 1 */
563#define REG_DAC_TEST_2 0x3FE /* DAC Test 2 */
564
565/*
566* REG_SPI_CONF
567*/
568#define SOFT_RESET (1 << 7) /* Soft Reset */
569#define WIRE3_SPI (1 << 6) /* 3-Wire SPI */
570#define LSB_FIRST (1 << 5) /* LSB First */
571#define _LSB_FIRST (1 << 2) /* LSB First */
572#define _WIRE3_SPI (1 << 1) /* 3-Wire SPI */
573#define _SOFT_RESET (1 << 0) /* Soft reset */
574
575/*
576* REG_MULTICHIP_SYNC_AND_TX_MON_CTRL
577*/
578#define TX2_MONITOR_ENABLE (1 << 6) /* Tx2 Monitor Enable */
579#define TX1_MONITOR_ENABLE (1 << 5) /* Tx1 Monitor Enable */
580#define MCS_RF_ENABLE (1 << 3) /* MCS RF Enable */
581#define MCS_BBPLL_ENABLE (1 << 2) /* MCS BBPLL enable */
582#define MCS_DIGITAL_CLK_ENABLE (1 << 1) /* MCS Digital CLK Enable */
583#define MCS_BB_ENABLE (1 << 0) /* MCS BB Enable */
584
585/*
586* REG_TX_ENABLE_FILTER_CTRL
587*/
588#define THB2_EN (1 << 3) /* THB2 Enable */
589#define THB1_EN (1 << 2) /* THB1 Enable */
590#define TX_CHANNEL_ENABLE(x) (((x) & 0x3) << 6) /* Tx channel Enable<1:0> */
591#define THB3_ENABLE_INTERP(x) (((x) & 0x3) << 4) /* THB3 Enable & Interp<1:0> */
592#define TX_FIR_ENABLE_INTERPOLATION(x) (((x) & 0x3) << 0) /* Tx FIR Enable & Interpolation<1:0> */
593#define TX_1 1
594#define TX_2 2
595#define TX_ENABLE 1
596#define TX_DISABLE 0
597
598/*
599* REG_RX_ENABLE_FILTER_CTRL
600*/
601#define RHB2_EN (1 << 3) /* RHB2 Enable */
602#define RHB1_EN (1 << 2) /* RHB1 Enable */
603#define RX_CHANNEL_ENABLE(x) (((x) & 0x3) << 6) /* Rx channel Enable<1:0> */
604#define DEC3_ENABLE_DECIMATION(x) (((x) & 0x3) << 4) /* DEC3 Enable & Decimation<1:0> */
605#define RX_FIR_ENABLE_DECIMATION(x) (((x) & 0x3) << 0) /* Rx FIR Enable & Decimation<1:0> */
606#define RX_1 1
607#define RX_2 2
608#define RX_ENABLE 1
609#define RX_DISABLE 0
610
611/*
612* REG_INPUT_SELECT
613*/
614#define TX_OUTPUT (1 << 6) /* TX Output */
615#define RX_INPUT(x) (((x) & 0x3F) << 0) /* RX Input <5:0> */
616
617/*
618* REG_RFPLL_DIVIDERS
619*/
620#define TX_VCO_DIVIDER(x) (((x) & 0xF) << 4) /* TX VCO Divider<3:0> */
621#define RX_VCO_DIVIDER(x) (((x) & 0xF) << 0) /* RX VCO Divider<3:0> */
622
623/*
624* REG_RX_CLOCK_DATA_DELAY
625*/
626#define DATA_CLK_DELAY(x) (((x) & 0xF) << 4) /* DATA_CLK Delay<3:0> */
627#define RX_DATA_DELAY(x) (((x) & 0xF) << 0) /* Rx Data Delay <3:0> */
628
629/*
630* REG_TX_CLOCK_DATA_DELAY
631*/
632#define FB_CLK_DELAY(x) (((x) & 0xF) << 4) /* FB_CLK Delay<3:0> */
633#define TX_DATA_DELAY(x) (((x) & 0xF) << 0) /* Tx Data Delay <3:0> */
634
635/*
636* REG_CLOCK_ENABLE
637*/
638#define XO_BYPASS (1 << 4) /* XO Bypass */
639#define DIGITAL_POWER_UP (1 << 2) /* Digital Power Up */
640#define CLOCK_ENABLE_DFLT (1 << 1) /* Set to 1 */
641#define BBPLL_ENABLE (1 << 0) /* BBPLL Enable */
642
643/*
644* REG_BBPLL
645*/
646#define CLKOUT_ENABLE (1 << 4) /* CLKOUT Enable */
647#define DAC_CLK_DIV2 (1 << 3) /* DAC Clk div2 */
648#define CLKOUT_SELECT(x) (((x) & 0x7) << 5) /* CLKOUT Select<2:0> */
649#define BBPLL_DIVIDER(x) (((x) & 0x7) << 0) /* BBPLL Divider <2:0> */
650
651/*
652* REG_START_TEMP_READING
653*/
654#define START_TEMP_READING (1 << 0) /* Start Temp Reading */
655
656/*
657* REG_TEMP_SENSE2
658*/
659#define TEMP_SENSE_PERIODIC_ENABLE (1 << 0) /* Temp Sense Periodic Enable */
660#define MEASUREMENT_TIME_INTERVAL(x) (((x) & 0x7F) << 1) /* Measurement Time Interval<6:0> */
661
662/*
663* REG_TEMP_SENSOR_CONFIG
664*/
665#define TEMP_SENSOR_DECIMATION(x) (((x) & 0x7) << 0) /* Temp Sensor Decimation<2:0> */
666
667/*
668* REG_PARALLEL_PORT_CONF_1
669*/
670#define PP_TX_SWAP_IQ (1 << 7) /* PP Tx Swap IQ */
671#define PP_RX_SWAP_IQ (1 << 6) /* PP Rx Swap IQ */
672#define TX_CHANNEL_SWAP (1 << 5) /* Tx Channel swap */
673#define RX_CHANNEL_SWAP (1 << 4) /* Rx Channel swap */
674#define RX_FRAME_PULSE_MODE (1 << 3) /* Rx Frame Pulse Mode */
675#define R2T2_TIMING (1 << 2) /* 2R2T Timing */
676#define INVERT_DATA_BUS (1 << 1) /* Invert data bus */
677#define INVERT_DATA_CLK (1 << 0) /* Invert DATA CLK */
678
679/*
680* REG_PARALLEL_PORT_CONF_2
681*/
682#define FDD_ALT_WORD_ORDER (1 << 7) /* FDD Alt Word Order */
683#define INVERT_RX1 (1 << 6) /* Invert Rx1 */
684#define INVERT_RX2 (1 << 5) /* Invert Rx2 */
685#define INVERT_TX1 (1 << 4) /* Invert Tx1 */
686#define INVERT_TX2 (1 << 3) /* Invert Tx2 */
687#define INVERT_RX_FRAME (1 << 2) /* Invert Rx Frame */
688#define DELAY_RX_DATA(x) (((x) & 0x3) << 0) /* Delay Rx Data<1:0> */
689
690/*
691* REG_PARALLEL_PORT_CONF_3
692*/
693#define FDD_RX_RATE_2TX_RATE (1 << 7) /* FDD Rx Rate = 2*Tx Rate */
694#define SWAP_PORTS (1 << 6) /* Swap Ports */
695#define SINGLE_DATA_RATE (1 << 5) /* Single Data Rate */
696#define LVDS_MODE (1 << 4) /* LVDS Mode */
697#define HALF_DUPLEX_MODE (1 << 3) /* Half Duplex Mode */
698#define SINGLE_PORT_MODE (1 << 2) /* Single Port Mode */
699#define FULL_PORT (1 << 1) /* Full Port */
700#define FULL_DUPLEX_SWAP_BITS (1 << 0) /* Full Duplex Swap Bits */
701
702/*
703* REG_ENSM_MODE
704*/
705#define FDD_MODE (1 << 0) /* FDD Mode */
706
707/*
708* REG_ENSM_CONFIG_1
709*/
710#define ENABLE_RX_DATA_PORT_FOR_CAL (1 << 7) /* Enable Rx Data Port for Cal */
711#define FORCE_RX_ON (1 << 6) /* Force Rx On */
712#define FORCE_TX_ON (1 << 5) /* Force Tx On */
713#define ENABLE_ENSM_PIN_CTRL (1 << 4) /* Enable ENSM Pin Control */
714#define LEVEL_MODE (1 << 3) /* Level Mode */
715#define FORCE_ALERT_STATE (1 << 2) /* Force Alert State */
716#define AUTO_GAIN_LOCK (1 << 1) /* Auto Gain Lock */
717#define TO_ALERT (1 << 0) /* To Alert */
718
719/*
720* REG_ENSM_CONFIG_2
721*/
722#define FDD_EXTERNAL_CTRL_ENABLE (1 << 7) /* FDD External Control Enable */
723#define POWER_DOWN_RX_SYNTH (1 << 6) /* Power Down Rx Synth */
724#define POWER_DOWN_TX_SYNTH (1 << 5) /* Power Down Tx Synth */
725#define TXNRX_SPI_CTRL (1 << 4) /* TXNRX SPI Control */
726#define SYNTH_ENABLE_PIN_CTRL_MODE (1 << 3) /* Synth Enable Pin Control Mode */
727#define DUAL_SYNTH_MODE (1 << 2) /* Dual Synth Mode */
728#define RX_SYNTH_READY_MASK (1 << 1) /* Rx Synth Ready Mask */
729#define TX_SYNTH_READY_MASK (1 << 0) /* Tx Synth Ready Mask */
730
731/*
732* REG_CALIBRATION_CTRL
733*/
734#define RX_BB_TUNE_CAL (1 << 7) /* Rx BB Tune */
735#define TX_BB_TUNE_CAL (1 << 6) /* Tx BB Tune */
736#define RX_QUAD_CAL (1 << 5) /* Rx Quad Cal */
737#define TX_QUAD_CAL (1 << 4) /* Tx Quad Cal */
738#define RX_GAIN_STEP_CAL (1 << 3) /* Rx Gain Step Cal */
739#define TXMON_CAL (1 << 2)
740#define RFDC_CAL (1 << 1) /* DC Cal RF Start */
741#define BBDC_CAL (1 << 0) /* DC cal BB Start */
742
743
744/*
745* REG_STATE
746*/
747#define CALIBRATION_SEQUENCE_STATE(x) (((x) & 0xF) << 4) /* Calibration Sequence State<3:0> */
748#define ENSM_STATE(x) (((x) & 0xF) << 0) /* ENSM State<3:0> */
749#define ENSM_STATE_SLEEP_WAIT 0x0
750#define ENSM_STATE_ALERT 0x5
751#define ENSM_STATE_TX 0x6
752#define ENSM_STATE_TX_FLUSH 0x7
753#define ENSM_STATE_RX 0x8
754#define ENSM_STATE_RX_FLUSH 0x9
755#define ENSM_STATE_FDD 0xA
756#define ENSM_STATE_FDD_FLUSH 0xB
757#define ENSM_STATE_INVALID 0xFF
758#define ENSM_STATE_SLEEP 0x80
759
760/*
761* REG_AUXDAC_2_WORD
762*/
763#define AUXDAC_2_WORD_MSB(x) (((x) & 0x3F) << 2) /* AuxDAC 2 Word<9:2> */
764#define AUXDAC_1_WORD(x) (((x) & 0x3) << 0) /* AuxDAC 1 Word <1:0> */
765
766/*
767* REG_AUXDAC_1_CONFIG
768*/
769#define COMP_CTRL_1 (1 << 5) /* Comp Ctrl 1 */
770#define AUXDAC1_STP_FACTOR (1 << 4) /* AuxDAC1 Step Factor */
771#define AUXDAC_1_VREF(x) (((x) & 0x3) << 2) /* AuxDAC 1 Vref<1:0> */
772#define AUXDAC_1_WORD_LSB(x) (((x) & 0x3) << 0) /* AuxDAC 2 Word <1:0> */
773
774/*
775* REG_AUXDAC_2_CONFIG
776*/
777#define COMP_CTRL_2 (1 << 5) /* Comp Ctrl 2 */
778#define AUXDAC2_STP_FACTOR (1 << 4) /* AuxDAC2 Step Factor */
779#define AUXDAC_2_VREF(x) (((x) & 0xF) << 2) /* AuxDAC 2 Vref<1:0> */
780#define AUXDAC_2_WORD_LSB(x) (((x) & 0x3) << 0) /* AuxDAC 2 Word <1:0> */
781
782/*
783* REG_AUXADC_CLOCK_DIVIDER
784*/
785#define AUXADC_CLOCK_DIVIDER(x) (((x) & 0x3F) << 0) /* AuxADC Clock Divider<5:0> */
786
787/*
788* REG_AUXADC_CONFIG
789*/
790#define AUXADC_POWER_DOWN (1 << 0) /* AuxADC Power Down */
791#define AUX_ADC_DECIMATION(x) (((x) & 0x7) << 1) /* Aux ADC Decimation<2:0> */
792
793/*
794* REG_AUXADC_LSB
795*/
796#define AUXADC_WORD_LSB(x) (((x) & 0xF) << 0) /* AuxADC Word LSB<3:0> */
797
798/*
799* REG_AUTO_GPO
800*/
801#define GPO_ENABLE_AUTO_RX(x) (((x) & 0xF) << 4) /* GPO Enable Auto Rx<3:0> */
802#define GPO_ENABLE_AUTO_TX(x) (((x) & 0xF) << 0) /* GPO Enable Auto Tx<3:0> */
803
804/*
805* REG_AGC_ATTACK_DELAY
806*/
807#define INVERT_BYPASSED_LNA_POLARITY (1 << 6) /* Invert Bypassed LNA Polarity */
808#define AGC_ATTACK_DELAY(x) (((x) & 0x3F) << 0) /* AGC Attack Delay<5:0> */
809
810/*
811* REG_AUXDAC_ENABLE_CTRL
812*/
813#define AUXDAC_MANUAL_BAR(x) (((x) & 0x3) << 6) /* AuxDac Manual Bar<1:0> */
814#define AUXDAC_AUTO_TX_BAR(x) (((x) & 0x3) << 4) /* AuxDAC Auto Tx Bar<1:0> */
815#define AUXDAC_AUTO_RX_BAR(x) (((x) & 0x3) << 2) /* AuxDAC Auto Rx Bar<1:0> */
816#define AUXDAC_INIT_BAR(x) (((x) & 0x3) << 0) /* AuxDAC Init Bar<1:0> */
817
818/*
819* REG_EXTERNAL_LNA_CTRL
820*/
821#define AUXDAC_MANUAL_SELECT (1 << 7) /* AuxDAC Manual Select */
822#define EXTERNAL_LNA2_CTRL (1 << 6) /* External LNA2 control */
823#define EXTERNAL_LNA1_CTRL (1 << 5) /* External LNA1 control */
824#define GPO_MANUAL_SELECT (1 << 4) /* GPO manual select */
825#define OPEN(x) (((x) & 0xF) << 0) /* Open<3:0> */
826
827/*
828* REG_GPO_FORCE_AND_INIT
829*/
830#define GPO_MANUAL_CTRL(x) (((x) & 0xF) << 4) /* GPO Manual Control<3:0> */
831#define GPO_INIT_STATE(x) (((x) & 0xF) << 0) /* GPO Init State<3:0> */
832
833/*
834* REG_CTRL_OUTPUT_ENABLE
835*/
836#define EN_CTRL7 (1 << 7) /* En ctrl7 */
837#define EN_CTRL6 (1 << 6) /* En ctrl6 */
838#define EN_CTRL5 (1 << 5) /* En ctrl5 */
839#define EN_CTRL4 (1 << 4) /* En ctrl4 */
840#define EN_CTRL3 (1 << 3) /* En ctrl3 */
841#define EN_CTRL2 (1 << 2) /* En ctrl2 */
842#define EN_CTRL1 (1 << 1) /* En ctrl1 */
843#define EN_CTRL0 (1 << 0) /* En ctrl0 */
844
845/*
846* REG_PRODUCT_ID
847*/
848#define PRODUCT_ID_MASK 0xF8
849#define PRODUCT_ID_9361 0x08
850#define REV_MASK 0x07
851
852/*
853* REG_REFERENCE_CLOCK_CYCLES
854*/
855#define REFERENCE_CLOCK_CYCLES_PER_US(x) (((x) & 0x7F) << 0) /* Reference Clock Cycles per us<6:0> */
856
857/*
858* REG_DIGITAL_IO_CTRL
859*/
860#define CLK_OUT_DRIVE (1 << 7) /* CLK Out Drive */
861#define DATACLK_DRIVE (1 << 6) /* DATACLK drive */
862#define DATA_PORT_DRIVE (1 << 2) /* Data Port Drive */
863#define DATACLK_SLEW(x) (((x) & 0x3) << 4) /* DATACLK slew <1:0> */
864#define DATA_PORT_SLEW(x) (((x) & 0x3) << 0) /* Data Port Slew<1:0> */
865
866/*
867* REG_LVDS_BIAS_CTRL
868*/
869#define RX_ON_CHIP_TERM (1 << 5) /* Rx On Chip Term */
870#define LVDS_BYPASS_BIAS_R (1 << 4) /* Bypass Bias R */
871#define LVDS_TX_LO_VCM (1 << 3) /* LVDS Tx LO VCM */
872#define CLK_OUT_SLEW(x) (((x) & 0x3) << 6) /* CLK Out Slew<1:0> */
873#define LVDS_BIAS(x) (((x) & 0x7) << 0) /* LVDS Bias <2:0> */
874
875/*
876* REG_SDM_CTRL_1
877*/
878#define INIT_BB_FO_CAL (1 << 2) /* Init BB FO CAL */
879#define BBPLL_RESET_BAR (1 << 0) /* BBPLL Reset Bar */
880
881/*
882* REG_CLOCK_CTRL
883*/
884#define REF_FREQ_SCALER(x) (((x) & 0x3) << 0) /* Ref Frequency Scaler */
885
886/*
887* REG_CP_CURRENT
888*/
889#define CHARGE_PUMP_CURRENT(x) (((x) & 0x3F) << 0) /* Charge Pump Current<5:0> */
890
891/*
892* REG_CP_BLEED_CURRENT
893*/
894#define MCS_REFCLK_SCALE_EN (1 << 7) /* MCS refclk Scale En */
895
896/*
897* REG_LOOP_FILTER_1
898*/
899#define C1_WORD(x) (((x) & 0x7) << 5) /* C1 Word<2:0> */
900#define R1_WORD(x) (((x) & 0x1F) << 0) /* R1 Word<4:0> */
901
902/*
903* REG_LOOP_FILTER_2
904*/
905#define R2_WORD (1 << 7) /* R2 Word<0> */
906#define C2_WORD(x) (((x) & 0x1F) << 2) /* C2 Word<4:0> */
907#define C1_WORD_LSB(x) (((x) & 0x3) << 0) /* C1 Word<4:3> */
908
909/*
910* REG_LOOP_FILTER_3
911*/
912#define BYPASS_C3 (1 << 7) /* Bypass C3 */
913#define BYPASS_R2 (1 << 6) /* Bypass R2 */
914#define C3_WORD(x) (((x) & 0xF) << 2) /* C3 Word<3:0> */
915#define R2_WORD_LSB(x) (((x) & 0x3) << 0) /* R2 Word<2:1> */
916
917/*
918* REG_VCO_CTRL
919*/
920#define FREQ_CAL_ENABLE (1 << 7) /* Freq Cal Enable */
921#define FREQ_CAL_RESET (1 << 4) /* Freq Cal Reset */
922#define FREQ_CAL_COUNT_LENGTH(x) (((x) & 0x3) << 5) /* Freq Cal Count Length<1:0> */
923
924/*
925* REG_SDM_CTRL
926*/
927#define CAL_CLOCK_DIV_4 (1 << 4) /* Cal Clock div 4 */
928
929/*
930* REG_RX_SYNTH_POWER_DOWN_OVERRIDE
931*/
932#define RX_LO_POWER_DOWN (1 << 4) /* Rx LO Power Down */
933#define RX_SYNTH_VCO_ALC_POWER_DOWN (1 << 3) /* Rx Synth VCO ALC Power Down */
934#define RX_SYNTH_PTAT_POWER_DOWN (1 << 2) /* Rx Synth PTAT Power Down */
935#define RX_SYNTH_VCO_POWER_DOWN (1 << 1) /* Rx Synth VCO Power Down */
936#define RX_SYNTH_VCO_LDO_POWER_DOWN (1 << 0) /* Rx Synth VCO LDO Power Down */
937
938/*
939* REG_TX_SYNTH_POWER_DOWN_OVERRIDE
940*/
941#define TX_LO_POWER_DOWN (1 << 4) /* Tx LO Power Down */
942#define TX_SYNTH_VCO_ALC_POWER_DOWN (1 << 3) /* Tx Synth VCO ALC Power Down */
943#define TX_SYNTH_PTAT_POWER_DOWN (1 << 2) /* Tx Synth PTAT Power Down */
944#define TX_SYNTH_VCO_POWER_DOWN (1 << 1) /* Tx Synth VCO Power Down */
945#define TX_SYNTH_VCO_LDO_POWER_DOWN (1 << 0) /* Tx Synth VCO LDO Power Down */
946
947/*
948* REG_RX_ANALOG_POWER_DOWN_OVERRIDE_1
949*/
950#define RX_OFFSET_DAC_CGIN_POWER_DOWN(x) (((x) & 0x3) << 6) /* Rx Offset DAC CGin Power Down<1:0> */
951#define RX_LMT_OVERLOAD_POWER_DOWN(x) (((x) & 0x3) << 4) /* Rx LMT Overload Power Down<1:0> */
952#define RX_MIXER_GM_POWER_DOWN(x) (((x) & 0x3) << 2) /* Rx Mixer Gm Power Down<1:0> */
953#define RX_CGB_POWER_DOWN(x) (((x) & 0x3) << 0) /* Rx CGB Power Down<1:0> */
954
955/*
956* REG_RX_ANALOG_POWER_DOWN_OVERRIDE_2
957*/
958#define RX_BBF_POWER_DOWN(x) (((x) & 0x3) << 6) /* Rx BBF Power Down<1:0> */
959#define RX_TIA_POWER_DOWN(x) (((x) & 0x3) << 4) /* Rx TIA Power Down<1:0> */
960#define RX_MIXER_POWER_DOWN(x) (((x) & 0x3) << 2) /* Rx Mixer Power Down<1:0> */
961#define RX_OFFSET_DAC_CGOUT_POWER_DOWN(x) (((x) & 0x3) << 0) /* Rx Offset DAC CGOut Power Down<1:0> */
962
963/*
964* REG_TX_ANALOG_POWER_DOWN_OVERRIDE_1
965*/
966#define TX_SECONDARY_FILTER_POWER_DOWN(x) (((x) & 0x3) << 6) /* Tx Secondary Filter Power Down<1:0> */
967#define TX_BBF_POWER_DOWN(x) (((x) & 0x3) << 4) /* Tx BBF Power Down<1:0> */
968#define TX_DAC_POWER_DOWN(x) (((x) & 0x3) << 2) /* Tx DAC Power Down<1:0> */
969#define TX_DAC_BIAS_POWER_DOWN(x) (((x) & 0x3) << 0) /* Tx DAC Bias Power Down<1:0> */
970
971/*
972* REG_ANALOG_POWER_DOWN_OVERRIDE
973*/
974#define RX_EXT_VCO_BUFFER_POWER_DOWN (1 << 5) /* Rx Ext VCO Buffer Power Down */
975#define TX_EXT_VCO_BUFFER_POWER_DOWN (1 << 4) /* Tx Ext VCO Buffer Power Down */
976#define TX_MONITOR_POWER_DOWN(x) (((x) & 0x3) << 2) /* Tx Monitor Power Down<1:0> */
977#define TX_UPCONVERTER_POWER_DOWN(x) (((x) & 0x3) << 0) /* Tx Upconverter Power Down<1:0> */
978
979/*
980* REG_MISC_POWER_DOWN_OVERRIDE
981*/
982#define RX_LNA_POWER_DOWN (1 << 6) /* Rx LNA Power Down */
983#define DCXO_POWER_DOWN (1 << 1) /* DCXO Power Down */
984#define MASTER_BIAS_POWER_DOWN (1 << 0) /* Master Bias Power Down */
985#define RX_CALIBRATION_POWER_DOWN(x) (((x) & 0x3) << 2) /* Rx Calibration Power Down<1:0> */
986
987/*
988* REG_CH_1_OVERFLOW
989*/
990#define BBPLL_LOCK (1 << 7) /* BBPLL Lock */
991#define CH_1_INT3 (1 << 6) /* CH 1 INT3 */
992#define CH1_HB3 (1 << 5) /* CH1 HB3 */
993#define CH1_HB2 (1 << 4) /* CH1 HB2 */
994#define CH1_QEC (1 << 3) /* CH1 QEC */
995#define CH1_HB1 (1 << 2) /* CH1 HB1 */
996#define CH1_TFIR (1 << 1) /* CH1 TFIR */
997#define CH1_RFIR (1 << 0) /* CH1 RFIR */
998
999/*
1000* REG_CH_2_OVERFLOW
1001*/
1002#define CH2_INT3 (1 << 6) /* CH2 INT3 */
1003#define CH2_HB3 (1 << 5) /* CH2 HB3 */
1004#define CH2_HB2 (1 << 4) /* CH2 HB2 */
1005#define CH2_QEC (1 << 3) /* CH2 QEC */
1006#define CH2_HB1 (1 << 2) /* CH2 HB1 */
1007#define CH2_TFIR (1 << 1) /* CH2 TFIR */
1008#define CH2_RFIR (1 << 0) /* CH2 RFIR */
1009
1010/*
1011* REG_TX_FILTER_CONF
1012*/
1013#define TX_FIR_GAIN_6DB (1 << 0) /* Filter Gain */
1014#define FIR_START_CLK (1 << 1) /* Start Tx/Rx Clock */
1015#define FIR_WRITE (1 << 2) /* Write Tx/Rx */
1016#define FIR_SELECT(x) (((x) & 0x3) << 3) /* Select Tx/Rx CH<1:0> */
1017#define FIR_NUM_TAPS(x) (((x) & 0x7) << 5) /* Number of Taps<2:0> */
1018
1019/*
1020* REG_TX_MON_LOW_GAIN
1021*/
1022#define TX_MON_TRACK (1 << 5) /* Tx Mon Track */
1023#define TX_MON_LOW_GAIN(x) (((x) & 0x1F) << 0) /* Tx Mon Low Gain<4:0> */
1024
1025/*
1026* REG_TX_MON_HIGH_GAIN
1027*/
1028#define TX_MON_HIGH_GAIN(x) (((x) & 0x1F) << 0) /* Tx Mon High Gain<4:0> */
1029
1030/*
1031* REG_TX_LEVEL_THRESH
1032*/
1033#define TX_LEVEL_THRESH(x) (((x) & 0x3F) << 2) /* Tx Level Threshold<5:0> */
1034#define TX_MON_DELAY_COUNTER(x) (((x) & 0x3) << 0) /* Tx Mon Delay Counter<9:8> */
1035
1036/*
1037* REG_TX_RSSI_LSB
1038*/
1039#define TX_RSSI_2 (1 << 1) /* Tx RSSI 2<0> */
1040#define TX_RSSI_1 (1 << 0) /* TX RSSI 1<0> */
1041
1042/*
1043* REG_TPM_MODE_ENABLE
1044*/
1045#define TX2_MON_ENABLE (1 << 7) /* Tx2 Monitor Enable */
1046#define TX1_MON_ENABLE (1 << 5) /* Tx1 Monitor Enable */
1047#define ONE_SHOT_MODE (1 << 6) /* One Shot Mode */
1048#define TX_MON_DURATION(x) (((x) & 0xF) << 0) /* Tx Mon Duration<3:0> */
1049
1050/*
1051* REG_TX_MON_1_CONFIG
1052*/
1053#define TX_MON_1_LO_CM(x) (((x) & 0x3F) << 2) /* Tx Mon 1 LO CM<5:0> */
1054#define TX_MON_1_GAIN(x) (((x) & 0x3) << 0) /* Tx Mon 1 Gain<1:0> */
1055
1056/*
1057* REG_TX_MON_2_CONFIG
1058*/
1059#define TX_MON_2_LO_CM(x) (((x) & 0x3F) << 2) /* Tx Mon 2 LO CM<5:0> */
1060#define TX_MON_2_GAIN(x) (((x) & 0x3) << 0) /* Tx Mon 2 Gain<1:0> */
1061
1062/*
1063* REG_TX1_ATTEN_1
1064*/
1065#define TX_1_ATTEN (1 << 0) /* Tx 1 Atten <8> */
1066
1067/*
1068* REG_TX2_ATTEN_1
1069*/
1070#define TX_2_ATTEN (1 << 0) /* Tx 2 Atten <8> */
1071
1072/*
1073* REG_TX_ATTEN_OFFSET
1074*/
1075#define MASK_CLR_ATTEN_UPDATE (1 << 6) /* Mask Clr Atten Update */
1076#define TX_ATTEN_OFFSET(x) (((x) & 0x3F) << 0) /* Tx Atten Offset<5:0> */
1077
1078/*
1079* REG_TX1_DIG_ATTEN
1080*/
1081#define SEL_TX1_TX2 (1 << 6) /* Sel Tx1 & Ttx2 */
1082
1083/*
1084* REG_TX2_DIG_ATTEN
1085*/
1086#define IMMEDIATELY_UPDATE_TPC_ATTEN (1 << 6) /* Immediately Update TPC Atten */
1087
1088/*
1089* REG_TX1_SYMBOL_ATTEN
1090*/
1091#define TX_1_SYMBOL_ATTEN(x) (((x) & 0x7F) << 0) /* Tx 1 Symbol Attenuation<6:0> */
1092
1093/*
1094* REG_TX2_SYMBOL_ATTEN
1095*/
1096#define TX_2_SYMBOL_ATTEN(x) (((x) & 0x7F) << 0) /* Tx 2 Symbol Attenuation<6:0> */
1097
1098/*
1099* REG_TX_SYMBOL_ATTEN_CONFIG
1100*/
1101#define USE_TX1_PIN_SYMBOL_ATTEN (1 << 3) /* Use Tx1 Pin & Symbol Atten */
1102#define USE_CTRL_IN_FOR_SYMBOL_ATTEN (1 << 1) /* Use CTRL IN for symbol Atten */
1103#define ENABLE_SYMBOL_ATTEN (1 << 0) /* Enable Symbol Atten */
1104
1105/*
1106* REG_TX_FORCE_BITS
1107*/
1108#define FORCE_OUT_2_TX2_OFFSET (1 << 7) /* Force Out 2 Tx2 Offset */
1109#define FORCE_OUT_2_TX1_OFFSET (1 << 6) /* Force Out 2 Tx1 Offset */
1110#define FORCE_OUT_2_TX2_PHASE_GAIN (1 << 5) /* Force Out 2 Tx2 Phase & Gain */
1111#define FORCE_OUT_2_TX1_PHASE_GAIN (1 << 4) /* Force Out 2 Tx1 Phase & Gain */
1112#define FORCE_OUT_1_TX2_OFFSET (1 << 3) /* Force Out 1 Tx2 Offset */
1113#define FORCE_OUT_1_TX1_OFFSET (1 << 2) /* Force Out 1 Tx1 Offset */
1114#define FORCE_OUT_1_TX2_PHASE_GAIN (1 << 1) /* Force Out 1 Tx2 Phase & Gain */
1115#define FORCE_OUT_1_TX1_PHASE_GAIN (1 << 0) /* Force Out 1 Tx1 Phase & Gain */
1116
1117/*
1118* REG_QUAD_CAL_NCO_FREQ_PHASE_OFFSET
1119*/
1120#define RX_NCO_FREQ(x) (((x) & 0x3) << 5) /* Rx NCO Frequency<1:0> */
1121#define RX_NCO_PHASE_OFFSET(x) (((x) & 0x1F) << 0) /* Rx NCO Phase Offset<4:0> */
1122
1123/*
1124* REG_QUAD_CAL_CTRL
1125*/
1126#define FREE_RUN_ENABLE (1 << 7) /* Free Run Enable */
1127#define SETTLE_MAIN_ENABLE (1 << 6) /* Settle Main Enable */
1128#define DC_OFFSET_ENABLE (1 << 5) /* DC Offset Enable */
1129#define GAIN_ENABLE (1 << 4) /* Gain Enable */
1130#define PHASE_ENABLE (1 << 3) /* Phase Enable */
1131#define QUAD_CAL_SOFT_RESET (1 << 2) /* Quad Cal Soft Reset */
1132#define M_DECIM(x) (((x) & 0x3) << 0) /* M<1:0> */
1133
1134/*
1135* REG_KEXP_1
1136*/
1137#define KEXP_TX(x) (((x) & 0x3) << 6) /* Kexp Tx<1:0> */
1138#define KEXP_TX_COMP(x) (((x) & 0x3) << 4) /* Kexp Tx_comp <1:0> */
1139#define KEXP_DC_I(x) (((x) & 0x3) << 2) /* Kexp DC I <1:0> */
1140#define KEXP_DC_Q(x) (((x) & 0x3) << 0) /* Kexp DC Q <1:0> */
1141
1142/*
1143* REG_KEXP_2
1144*/
1145#define INVERT_I_DATA (1 << 5) /* Invert I data */
1146#define INVERT_Q_DATA (1 << 4) /* Invert Q data */
1147#define TX_NCO_FREQ(x) (((x) & 0x3) << 6) /* Tx NCO frequency<1:0> */
1148#define KEXP_PHASE(x) (((x) & 0x3) << 2) /* Kexp Phase <1:0> */
1149#define KEXP_AMP(x) (((x) & 0x3) << 0) /* Kexp Amp <1:0> */
1150
1151/*
1152* REG_QUAD_CAL_STATUS_TX1
1153*/
1154#define TX1_LO_CONV (1 << 1) /* Tx1 LO Conv */
1155#define TX1_SSB_CONV (1 << 0) /* Tx1 SSB Conv */
1156#define TX1_CONVERGENCE_COUNT(x) (((x) & 0x3F) << 2) /* Tx1 Convergence Count<5:0> */
1157
1158/*
1159* REG_QUAD_CAL_STATUS_TX2
1160*/
1161#define TX2_LO_CONV (1 << 1) /* Tx2 LO Conv */
1162#define TX2_SSB_CONV (1 << 0) /* Tx2 SSB Conv */
1163#define TX2_CONVERGENCE_COUNT(x) (((x) & 0x3F) << 2) /* Tx2 Convergence Count<5:0> */
1164
1165/*
1166* REG_TX_QUAD_FULL_LMT_GAIN
1167*/
1168#define RX_FULL_TABLELMT_TABLE_GAIN(x) (((x) & 0x7F) << 0) /* RX Full table/LMT table gain<6:0> */
1169
1170/*
1171* REG_SQUARER_CONFIG
1172*/
1173#define GM_STAGE_TIME_CON_OVERRIDE (1 << 5) /* Gm Stage Time Con Override */
1174#define GM_STAGE_MV_HP_POLE (1 << 4) /* Gm Stage MV HP Pole */
1175#define GM_STAGE_LOWER_CM (1 << 3) /* Gm Stage Lower CM */
1176#define BYPASS_BIAS_R (1 << 0) /* Bypass Bias R */
1177#define VBIAS_CTRL(x) (((x) & 0x3) << 1) /* Vbias Control<1:0> */
1178
1179/*
1180* REG_THRESH_ACCUM
1181*/
1182#define THRESH_ACCUMULATOR(x) (((x) & 0xF) << 0) /* Threshold Accumulator<3:0> */
1183
1184/*
1185* REG_TX_QUAD_LPF_GAIN
1186*/
1187#define RX_LPF_GAIN(x) (((x) & 0x1F) << 0) /* RX LPF gain<4:0> */
1188
1189/*
1190* REG_TXDAC_VDS_I
1191*/
1192#define TXDAC_VDS_I(x) (((x) & 0x3F) << 0) /* TxDAC Vds I<5:0> */
1193
1194/*
1195* REG_TXDAC_VDS_Q
1196*/
1197#define TXDAC_VDS_Q(x) (((x) & 0x3F) << 0) /* TxDAC Vds Q<5:0> */
1198
1199/*
1200* REG_TXDAC_GN_I
1201*/
1202#define TXDAC_GN_I(x) (((x) & 0x3F) << 0) /* txDAC_gn_I<5:0> */
1203
1204/*
1205* REG_TXDAC_GN_Q
1206*/
1207#define TXDAC_GN_Q(x) (((x) & 0x3F) << 0) /* txDAC_gn_Q<5:0> */
1208
1209/*
1210* REG_TXBBF_OPAMP_A
1211*/
1212#define OPAMPA_OUTPUT_BIAS(x) (((x) & 0x3) << 5) /* OpAmpA Output Bias<1:0> */
1213#define OPAMPA_RZ(x) (((x) & 0x3) << 3) /* OpAmpA RZ<1:0> */
1214#define OPAMP_A_CC(x) (((x) & 0x7) << 0) /* OpAmp A CC<2:0> */
1215
1216/*
1217* REG_TXBBF_OPAMP_B
1218*/
1219#define OPAMPB_OUTPUT_BIAS(x) (((x) & 0x3) << 5) /* OpAmpB Output Bias<1:0> */
1220#define OPAMPB_RZ(x) (((x) & 0x3) << 3) /* OpAmpB RZ<1:0> */
1221#define OPAMP_B_CC(x) (((x) & 0x7) << 0) /* OpAmp B CC<2:0> */
1222
1223/*
1224* REG_TX_BBF_R1
1225*/
1226#define OVERRIDE_ENABLE (1 << 7) /* Override enable */
1227#define R1(x) (((x) & 0x1F) << 0) /* R1<4:0> */
1228
1229/*
1230* REG_TX_BBF_R2
1231*/
1232#define R2(x) (((x) & 0x1F) << 0) /* R2<4:0> */
1233
1234/*
1235* REG_TX_BBF_R3
1236*/
1237#define R3(x) (((x) & 0x1F) << 0) /* R3<4:0> */
1238
1239/*
1240* REG_TX_BBF_R4
1241*/
1242#define R4(x) (((x) & 0x1F) << 0) /* R4<4:0> */
1243
1244/*
1245* REG_TX_BBF_RP
1246*/
1247#define RP(x) (((x) & 0x1F) << 0) /* Rp<4:0> */
1248
1249/*
1250* REG_TX_BBF_C1
1251*/
1252#define C1(x) (((x) & 0x3F) << 0) /* C1<5:0> */
1253
1254/*
1255* REG_TX_BBF_C2
1256*/
1257#define C2(x) (((x) & 0x3F) << 0) /* C2<5:0> */
1258
1259/*
1260* REG_TX_BBF_CP
1261*/
1262#define CP(x) (((x) & 0x3F) << 0) /* Cp<5:0> */
1263
1264/*
1265* REG_TX_TUNE_CTRL
1266*/
1267#define PD_TUNE (1 << 2) /* PD Tune */
1268#define TUNER_RESAMPLE (1 << 1) /* Tuner Resample */
1269#define TUNER_RESAMPLE_PHASE (1 << 0) /* Tuner Resample Phase */
1270#define TUNE_CTRL(x) (((x) & 0x3) << 5) /* Tune Control<1:0> */
1271
1272/*
1273* REG_TX_BBF_R2B
1274*/
1275#define TX_BBF_BYPASS_BIAS_R (1 << 7) /* Bypass Bias R */
1276#define R2B_OVR (1 << 5) /* R2b Ovr */
1277#define R2B(x) (((x) & 0x1F) << 0) /* R2b<4:0> */
1278
1279/*
1280* REG_TX_BBF_TUNE
1281*/
1282#define BBF1_COMP_I (1 << 3) /* BBF1 Comp I */
1283#define BBF1_COMP_Q (1 << 2) /* BBF1 Comp Q */
1284#define BBF2_COMP_I (1 << 1) /* BBF2 Comp I */
1285#define BBF2_COMP_Q (1 << 0) /* BBF2 Comp Q */
1286
1287/*
1288* REG_CONFIG0
1289*/
1290#define BIAS(x) (((x) & 0x3) << 6) /* Bias<1:0> */
1291#define RGM(x) (((x) & 0x3) << 4) /* Rgm<1:0> */
1292#define CC(x) (((x) & 0x3) << 2) /* Cc<1:0> */
1293#define AMPBIAS(x) (((x) & 0x3) << 0) /* AmpBias<1:0> */
1294
1295/*
1296* REG_RESISTOR
1297*/
1298#define RESISTOR(x) (((x) & 0xF) << 0) /* Resistor<3:0> */
1299
1300/*
1301* REG_CAPACITOR
1302*/
1303#define CAPACITOR(x) (((x) & 0x3F) << 0) /* Capacitor<5:0> */
1304
1305/*
1306* REG_LO_CM
1307*/
1308#define LO_COMMON_MODE(x) (((x) & 0x3) << 5) /* LO Common Mode<1:0> */
1309
1310/*
1311* REG_TX_BBF_TUNE_MODE
1312*/
1313#define EVALTIME (1 << 4) /* EvalTime */
1314#define TX_BBF_TUNE_DIVIDER (1 << 0) /* TX BBF Tune Divider<8> */
1315#define TUNE_COMP_MASK(x) (((x) & 0x3) << 5) /* Tune Comp Mask<1:0> */
1316#define TUNER_MODE(x) (((x) & 0x7) << 1) /* Tuner Mode<2:0> */
1317
1318/*
1319* REG_RX_FILTER_CONFIG
1320*/
1321#define WRITE_RX (1 << 2) /* Write Rx */
1322#define START_RX_CLOCK (1 << 1) /* Start Rx Clock */
1323#define NUMBER_OF_TAPS(x) (((x) & 0x7) << 5) /* Number of Taps */
1324#define SELECT_RX_CH(x) (((x) & 0x3) << 3) /* Select Rx Ch<1:0> */
1325
1326/*
1327* REG_RX_FILTER_GAIN
1328*/
1329#define FILTER_GAIN(x) (((x) & 0x3) << 0) /* Filter gain<1:0> */
1330
1331/*
1332* REG_AGC_CONFIG_1
1333*/
1334#define DEC_PWR_FOR_LOW_PWR (1 << 7) /* Dec Pwr for Low Pwr */
1335#define DEC_PWR_FOR_LOCK_LEVEL (1 << 6) /* Dec Pwr for Lock Level */
1336#define DEC_PWR_FOR_GAIN_LOCK_EXIT (1 << 5) /* Dec Pwr for Gain Lock Exit */
1337#define SLOW_ATTACK_HYBRID_MODE (1 << 4) /* Slow Attack Hybrid Mode */
1338#define RX2_GAIN_CTRL_SETUP(x) (((x) & 0x3) << 2) /* Rx 2 Gain Control Setup<1:0> */
1339#define RX1_GAIN_CTRL_SETUP(x) (((x) & 0x3) << 0) /* Rx 1 Gain Control Setup<1:0> */
1340#define RX_GAIN_CTL_MASK 0x03
1341#define RX2_GAIN_CTRL_SHIFT 2
1342#define RX1_GAIN_CTRL_SHIFT 0
1343#define RX_GAIN_CTL_MGC 0x00
1344#define RX_GAIN_CTL_AGC_FAST_ATK 0x01
1345#define RX_GAIN_CTL_AGC_SLOW_ATK 0x02
1346#define RX_GAIN_CTL_AGC_SLOW_ATK_HYBD 0x03
1347
1348/*
1349* REG_AGC_CONFIG_2
1350*/
1351#define AGC_SOFT_RESET (1 << 7) /* Soft Reset */
1352#define AGC_GAIN_UNLOCK_CTRL (1 << 6) /* Gain Unlock Control */
1353#define AGC_USE_FULL_GAIN_TABLE (1 << 3) /* Use Full Gain Table */
1354#define DIG_GAIN_EN (1 << 2) /* Enable Digital Gain */
1355#define MAN_GAIN_CTRL_RX2 (1 << 1) /* Manual Gain Control Rx 2 */
1356#define MAN_GAIN_CTRL_RX1 (1 << 0) /* Manual Gain Control Rx 1 */
1357
1358/*
1359* REG_AGC_CONFIG_3
1360*/
1361#define INCDEC_LMT_GAIN (1 << 4) /* Inc/Dec LMT Gain */
1362#define USE_AGC_FOR_LMTLPF_GAIN (1 << 3) /* Use AGC for LMT/LPF Gain */
1363#define MANUAL_INCR_STEP_SIZE(x) (((x) & 0x7) << 5) /* Manual (CTRL_IN) Incr Gain Step Size<2:0> */
1364#define ADC_OVERRANGE_SAMPLE_SIZE(x) (((x) & 0x7) << 0) /* ADC Overrange Sample Size<2:0> */
1365
1366/*
1367* REG_MAX_LMT_FULL_GAIN
1368*/
1369#define MAXIMUM_FULL_TABLELMT_TABLE_INDEX(x) (((x) & 0x7F) << 0) /* Maximum Full Table/LMT Table Index<6:0> */
1370
1371/*
1372* REG_PEAK_WAIT_TIME
1373*/
1374#define MANUAL_CTRL_IN_DECR_GAIN_STP_SIZE(x) (((x) & 0x7) << 5) /* Manual (CTRL_IN) Decr Gain Step Size<2:0> */
1375#define PEAK_OVERLOAD_WAIT_TIME(x) (((x) & 0x1F) << 0) /* Peak Overload Wait Time<4:0> */
1376
1377/*
1378* REG_DIGITAL_GAIN
1379*/
1380#define DIG_GAIN_STP_SIZE(x) (((x) & 0x7) << 5) /* Dig Gain Step Size<2:0> */
1381#define MAXIMUM_DIGITAL_GAIN(x) (((x) & 0x1F) << 0) /* Maximum Digital Gain<4:0> */
1382
1383/*
1384* REG_AGC_LOCK_LEVEL
1385*/
1386#define ENABLE_DIG_SAT_OVRG (1 << 7) /* Enable Dig Sat Ovrg */
1387#define AGC_LOCK_LEVEL_FAST_AGC_INNER_HIGH_THRESH_SLOW(x) (((x) & 0x7F) << 0) /* AGC Lock Level (Fast)/ AGC Inner High Threshold (Slow) <6:0> */
1388
1389/*
1390* REG_GAIN_STP_CONFIG1
1391*/
1392#define LMT_DETECTOR_SETTLING_TIME(x) (((x) & 0x7) << 5) /* LMT Detector Settling Time<2:0> */
1393#define DEC_STP_SIZE_FOR_LARGE_LMT_OVERLOAD(x) (((x) & 0x7) << 2) /* Dec Step Size for: Large LMT Overload/ Full Table Case #3 <2:0> */
1394#define ADC_NOISE_CORRECTION_FACTOR(x) (((x) & 0x3) << 0) /* ADC Noise Correction Factor<1:0> */
1395
1396/*
1397* REG_GAIN_STP_CONFIG_2
1398*/
1399#define DECREMENT_STP_SIZE_FOR_SMALL_LPF_GAIN_CHANGE(x) (((x) & 0x7) << 4) /* Fast Attack Only. Decrement Step Size for: Small LPF Gain Change / Full Table Case #2 <2:0> */
1400#define LARGE_LPF_GAIN_STEP(x) (((x) & 0xF) << 0) /* Decrement Step Size for: Large LPF Gain Change / Full Table Case #1<3:0> */
1401
1402/*
1403* REG_SMALL_LMT_OVERLOAD_THRESH
1404*/
1405#define FORCE_PD_RESET_RX2 (1 << 7) /* Force PD Reset Rx2 */
1406#define FORCE_PD_RESET_RX1 (1 << 6) /* Force PD Reset Rx1 */
1407#define SMALL_LMT_OVERLOAD_THRESH(x) (((x) & 0x3F) << 0) /* Small LMT Overload Threshold<5:0> */
1408
1409/*
1410* REG_LARGE_LMT_OVERLOAD_THRESH
1411*/
1412#define LARGE_LMT_OVERLOAD_THRESH(x) (((x) & 0x3F) << 0) /* Large LMT Overload Threshold<5:0> */
1413
1414/*
1415* REG_RX1_MANUAL_LMT_FULL_GAIN
1416*/
1417#define POWER_MEAS_IN_STATE_5_MSB (1 << 7) /* Power Meas in State 5 <3> */
1418#define RX1_MANUAL_FULL_TABLE_LMT_TABLE_GAIN_INDEX(x) (((x) & 0x7F) << 0) /* Rx1 Manual Full table/LMT table Gain Index<6:0> */
1419#define RX_FULL_TBL_IDX_MASK RX1_MANUAL_FULL_TABLE_LMT_TABLE_GAIN_INDEX(~0)
1420
1421/*
1422* REG_RX1_MANUAL_LPF_GAIN
1423*/
1424#define POWER_MEAS_IN_STATE_5(x) (((x) & 0x7) << 5) /* Power Meas in State 5<2:0> */
1425#define RX1_MANUAL_LPF_GAIN(x) (((x) & 0x1F) << 0) /* Rx1 Manual LPF Gain <4:0> */
1426#define RX_LPF_IDX_MASK RX1_MANUAL_LPF_GAIN(~0)
1427
1428/*
1429* REG_RX1_MANUAL_DIGITALFORCED_GAIN
1430*/
1431#define FORCE_RX1_DIGITAL_GAIN (1 << 5) /* Force Rx1 Digital Gain */
1432#define RX1_MANUALFORCED_DIGITAL_GAIN(x) (((x) & 0x1F) << 0) /* Rx1 Manual/Forced Digital Gain<4:0> */
1433#define RX_DIGITAL_IDX_MASK RX1_MANUALFORCED_DIGITAL_GAIN(~0)
1434/*
1435* REG_RX2_MANUAL_LMT_FULL_GAIN
1436*/
1437#define RX2_MANUAL_FULL_TABLE_LMT_TABLE_GAIN_INDEX(x) (((x) & 0x7F) << 0) /* Rx2 Manual Full table/ LMT table Gain Index<6:0> */
1438
1439/*
1440* REG_RX2_MANUAL_LPF_GAIN
1441*/
1442#define RX2_MANUAL_LPF_GAIN(x) (((x) & 0x1F) << 0) /* Rx2 Manual LPF Gain<4:0> */
1443
1444/*
1445* REG_RX2_MANUAL_DIGITALFORCED_GAIN
1446*/
1447#define FORCE_RX2_DIGITAL_GAIN (1 << 5) /* Force Rx2 Digital Gain */
1448#define RX2_MANUALFORCED_DIGITAL_GAIN(x) (((x) & 0x1F) << 0) /* Rx2 Manual/Forced Digital Gain<4:0> */
1449
1450/*
1451* REG_FAST_CONFIG_1
1452*/
1453#define ENABLE_GAIN_INC_AFTER_GAIN_LOCK (1 << 7) /* Enable Gain Inc after Gain Lock */
1454#define GOTO_OPT_GAIN_IF_ENERGY_LOST_OR_EN_AGC_HIGH (1 << 6) /* Goto Opt Gain if Energy Lost or EN_AGC High */
1455#define GOTO_SET_GAIN_IF_EN_AGC_HIGH (1 << 5) /* Goto Set Gain if EN_AGC High */
1456#define GOTO_SET_GAIN_IF_EXIT_RX_STATE (1 << 4) /* Goto Set Gain if Exit Rx State */
1457#define DONT_UNLOCK_GAIN_IF_ENERGY_LOST (1 << 3) /* Don't Unlock Gain if Energy Lost */
1458#define GOTO_OPTIMIZED_GAIN_IF_EXIT_RX_STATE (1 << 2) /* Goto Optimized Gain if Exit Rx State */
1459#define DONT_UNLOCK_GAIN_IF_LG_ADC_OR_LMT_OVRG (1 << 1) /* Don't Unlock Gain If Lg ADC or LMT Ovrg */
1460#define ENABLE_INCR_GAIN (1 << 0) /* Enable Incr Gain */
1461
1462/*
1463* REG_FAST_CONFIG_2_SETTLING_DELAY
1464*/
1465#define USE_LAST_LOCK_LEVEL_FOR_SET_GAIN (1 << 7) /* Use Last Lock Level for Set Gain */
1466#define ENABLE_LMT_GAIN_INC_FOR_LOCK_LEVEL (1 << 6) /* Enable LMT Gain Inc for Lock Level */
1467#define GOTO_MAX_GAIN_OR_OPT_GAIN_IF_EN_AGC_HIGH (1 << 5) /* Goto Max Gain or Opt Gain if EN_AGC High */
1468#define SETTLING_DELAY(x) (((x) & 0x1F) << 0) /* Settling Delay<4:0> */
1469
1470/*
1471* REG_FAST_ENERGY_LOST_THRESH
1472*/
1473#define POST_LOCK_LEVEL_STP_SIZE_FOR_LPF_TABLE_FULL_TABLE(x) (((x) & 0x3) << 6) /* Post Lock Level Step Size for: LPF Table/ Full Table <1:0> */
1474#define ENERGY_LOST_THRESH(x) (((x) & 0x3F) << 0) /* Energy lost threshold<5:0> */
1475
1476/*
1477* REG_FAST_STRONGER_SIGNAL_THRESH
1478*/
1479#define POST_LOCK_LEVEL_STP_FOR_LMT_TABLE(x) (((x) & 0x3) << 6) /* Post Lock Level Step for LMT Table <1:0> */
1480#define STRONGER_SIGNAL_THRESH(x) (((x) & 0x3F) << 0) /* Stronger Signal Threshold<5:0> */
1481
1482/*
1483* REG_FAST_LOW_POWER_THRESH
1484*/
1485#define DONT_UNLOCK_GAIN_IF_ADC_OVRG (1 << 7) /* Don't unlock gain if ADC Ovrg */
1486#define LOW_POWER_THRESH(x) (((x) & 0x7F) << 0) /* Low Power Threshold<6:0> */
1487
1488/*
1489* REG_FAST_STRONG_SIGNAL_FREEZE
1490*/
1491#define DONT_UNLOCK_GAIN_IF_STRONGER_SIGNAL (1 << 7) /* Don't unlock gain if Stronger Signal */
1492
1493/*
1494* REG_FAST_FINAL_OVER_RANGE_AND_OPT_GAIN
1495*/
1496#define FINAL_OVER_RANGE_COUNT(x) (((x) & 0x7) << 5) /* Final Over Range Count<2:0> */
1497#define OPTIMIZE_GAIN_OFFSET(x) (((x) & 0xF) << 0) /* Optimize Gain Offset<3:0> */
1498
1499/*
1500* REG_FAST_ENERGY_DETECT_COUNT
1501*/
1502#define INCREMENT_GAIN_STP_LPFLMT(x) (((x) & 0x7) << 5) /* Increment Gain Step (LPF/LMT)<2:0> */
1503#define ENERGY_DETECT_COUNT(x) (((x) & 0x1F) << 0) /* Energy Detect count<4:0> */
1504
1505/*
1506* REG_FAST_AGCLL_UPPER_LIMIT
1507*/
1508#define AGCLL_MAX_INCREASE(x) (((x) & 0x3F) << 0) /* AGCLL Max Increase<5:0> */
1509
1510/*
1511* REG_FAST_GAIN_LOCK_EXIT_COUNT
1512*/
1513#define GAIN_LOCK_EXIT_COUNT(x) (((x) & 0x3F) << 0) /* Gain Lock Exit Count<5:0> */
1514
1515/*
1516* REG_FAST_INITIAL_LMT_GAIN_LIMIT
1517*/
1518#define INITIAL_LMT_GAIN_LIMIT(x) (((x) & 0x7F) << 0) /* Initial LMT Gain Limit<6:0> */
1519
1520/*
1521* REG_AGC_INNER_LOW_THRESH
1522*/
1523#define PREVENT_GAIN_INC (1 << 7) /* Prevent Gain Inc */
1524#define AGC_INNER_LOW_THRESH(x) (((x) & 0x7F) << 0) /* AGC Inner Low Threshold<6:0> */
1525
1526/*
1527* REG_LMT_OVERLOAD_COUNTERS
1528*/
1529#define LARGE_LMT_OVERLOAD_EXED_COUNTER(x) (((x) & 0xF) << 4) /* Large LMT Overload Exceeded Counter<3:0> */
1530#define SMALL_LMT_OVERLOAD_EXED_COUNTER(x) (((x) & 0xF) << 0) /* Small LMT Overload Exceeded Counter<3:0> */
1531
1532/*
1533* REG_ADC_OVERLOAD_COUNTERS
1534*/
1535#define LARGE_ADC_OVERLOAD_EXED_COUNTER(x) (((x) & 0xF) << 4) /* Large ADC Overload Exceeded Counter<3:0> */
1536#define SMALL_ADC_OVERLOAD_EXED_COUNTER(x) (((x) & 0xF) << 0) /* Small ADC Overload Exceeded Counter<3:0> */
1537
1538/*
1539* REG_GAIN_STP1
1540*/
1541#define IMMED_GAIN_CHANGE_IF_LG_LMT_OVERLOAD (1 << 7) /* Immed. Gain Change if Lg LMT Overload */
1542#define IMMED_GAIN_CHANGE_IF_LG_ADC_OVERLOAD (1 << 3) /* Immed. Gain Change if Lg ADC Overload */
1543#define AGC_INNER_HIGH_THRESH_EXED_STP_SIZE(x) (((x) & 0x7) << 4) /* AGC Inner High Threshold Exceeded Step Size<2:0> */
1544#define AGC_INNER_LOW_THRESH_EXED_STP_SIZE(x) (((x) & 0x7) << 0) /* AGC Inner Low Threshold Exceeded Step Size<2:0> */
1545
1546/*
1547* REG_DIGITAL_SAT_COUNTER
1548*/
1549#define DOUBLE_GAIN_COUNTER (1 << 5) /* Double Gain Counter */
1550#define ENABLE_SYNC_FOR_GAIN_COUNTER (1 << 4) /* Enable Sync for Gain Counter */
1551#define DIG_SATURATION_EXED_COUNTER(x) (((x) & 0xF) << 0) /* Dig Saturation Exceeded Counter<3:0> */
1552
1553/*
1554* REG_OUTER_POWER_THRESHS
1555*/
1556#define AGC_OUTER_HIGH_THRESH(x) (((x) & 0xF) << 4) /* AGC Outer High Threshold<3:0> */
1557#define AGC_OUTER_LOW_THRESH(x) (((x) & 0xF) << 0) /* AGC Outer Low Threshold<3:0> */
1558
1559/*
1560* REG_GAIN_STP_2
1561*/
1562#define AGC_OUTER_HIGH_THRESH_EXED_STP_SIZE(x) (((x) & 0xF) << 4) /* AGC outer High Threshold Exceeded Step Size<3:0> */
1563#define AGC_OUTER_LOW_THRESH_EXED_STP_SIZE(x) (((x) & 0xF) << 0) /* AGC Outer Low Threshold Exceeded Step Size<3:0> */
1564
1565/*
1566* REG_EXT_LNA_HIGH_GAIN
1567*/
1568#define EXT_LNA_HIGH_GAIN(x) (((x) & 0x3F) << 0) /* Ext LNA High Gain<5:0> */
1569
1570/*
1571* REG_EXT_LNA_LOW_GAIN
1572*/
1573#define EXT_LNA_LOW_GAIN(x) (((x) & 0x3F) << 0) /* Ext LNA Low Gain<5:0> */
1574
1575/*
1576* REG_GAIN_TABLE_ADDRESS
1577*/
1578#define GAIN_TABLE_ADDRESS(x) (((x) & 0x7F) << 0) /* Gain Table Address<6:0> */
1579
1580/*
1581* REG_GAIN_TABLE_WRITE_DATA1
1582*/
1583#define EXT_LNA_CTRL (1 << 7) /* Ext LNA Ctrl */
1584#define LNA_GAIN(x) (((x) & 0x3) << 5) /* LNA Gain <1:0> */
1585#define MIXER_GM_GAIN(x) (((x) & 0x1F) << 0) /* Mixer Gm Gain <4:0> */
1586
1587/*
1588* REG_GAIN_TABLE_WRITE_DATA2
1589*/
1590#define TIA_GAIN (1 << 5) /* TIA Gain */
1591#define LPF_GAIN(x) (((x) & 0x1F) << 0) /* LPF Gain <4:0> */
1592
1593/*
1594* REG_GAIN_TABLE_WRITE_DATA_3
1595*/
1596#define RF_DC_CAL (1 << 5) /* RF DC Cal */
1597#define DIGITAL_GAIN(x) (((x) & 0x1F) << 0) /* Digital Gain <4:0> */
1598
1599/*
1600* REG_GAIN_TABLE_READ_DATA_1
1601*/
1602#define TO_LNA_GAIN(x) (((x) >> 5) & 0x3) /* LNA Gain <1:0> */
1603#define TO_MIXER_GM_GAIN(x) (((x) >> 0) & 0x1F) /* Mixer Gm Gain <4:0> */
1604
1605/*
1606* REG_GAIN_TABLE_READ_DATA_2
1607*/
1608#define TO_LPF_GAIN(x) (((x) >> 0) & 0x1F) /* LPF Gain <4:0> */
1609
1610/*
1611* REG_GAIN_TABLE_READ_DATA_3
1612*/
1613#define TO_DIGITAL_GAIN(x) (((x) >> 0) & 0x1F) /* Digital Gain <4:0> */
1614
1615/*
1616* REG_GAIN_TABLE_CONFIG
1617*/
1618#define WRITE_GAIN_TABLE (1 << 2) /* Write Gain Table */
1619#define START_GAIN_TABLE_CLOCK (1 << 1) /* Start Gain Table Clock */
1620#define RECEIVER_SELECT(x) (((x) & 0x3) << 3) /* Receiver Select<1:0> */
1621#define GT_RX1 1
1622#define GT_RX2 2
1623
1624
1625/*
1626* REG_GM_SUB_TABLE_GAIN_WRITE
1627*/
1628#define GM_SUB_TABLE_GAIN_WRITE(x) (((x) & 0x7F) << 0) /* Gm Sub Table Gain Word Write<6:0> */
1629
1630/*
1631* REG_GM_SUB_TABLE_BIAS_WRITE
1632*/
1633#define GM_SUB_TABLE_BIAS_WRITE(x) (((x) & 0x1F) << 0) /* Gm Sub Table Bias Word Write<4:0> */
1634
1635/*
1636* REG_GM_SUB_TABLE_CTRL_WRITE
1637*/
1638#define GM_SUB_TABLE_CTRL_WRITE(x) (((x) & 0x3F) << 0) /* Gm Sub Table Control Word Write<5:0> */
1639
1640/*
1641* REG_GM_SUB_TABLE_GAIN_READ
1642*/
1643#define GM_SUB_TABLE_GAIN_READ(x) (((x) & 0x7F) << 0) /* Gm Sub Table Gain Word Read<6:0> */
1644
1645/*
1646* REG_GM_SUB_TABLE_BIAS_READ
1647*/
1648#define GM_SUB_TABLE_BIAS_READ(x) (((x) & 0x1F) << 0) /* Gm Sub Table Bias Word Read<4:0> */
1649
1650/*
1651* REG_GM_SUB_TABLE_CTRL_READ
1652*/
1653#define GM_SUB_TABLE_CTRL_READ(x) (((x) & 0x3F) << 0) /* Gm Sub Table Control Word Read<5:0> */
1654
1655/*
1656* REG_GM_SUB_TABLE_CONFIG
1657*/
1658#define WRITE_GM_SUB_TABLE (1 << 2) /* Write Gm Sub Table */
1659#define START_GM_SUB_TABLE_CLOCK (1 << 1) /* Start Gm Sub Table Clock */
1660
1661/*
1662* REG_GAIN_DIFF_WORDERROR_WRITE
1663*/
1664#define CALIB_TABLE_GAIN_DIFFERROR_WORD(x) (((x) & 0x3F) << 0) /* Calib Table Gain Diff/Error Word<5:0> */
1665
1666/*
1667* REG_GAIN_ERROR_READ
1668*/
1669#define CALIB_TABLE_GAIN_ERROR(x) (((x) & 0x1F) << 0) /* Calib Table Gain Error<4:0> */
1670
1671/*
1672* REG_CONFIG
1673*/
1674#define READ_SELECT (1 << 4) /* Read Select */
1675#define WRITE_MIXER_ERROR_TABLE (1 << 3) /* Write Mixer Error Table */
1676#define WRITE_LNA_ERROR_TABLE (1 << 2) /* Write LNA Error Table */
1677#define WRITE_LNA_GAIN_DIFF (1 << 1) /* Write LNA Gain Diff */
1678#define START_CALIB_TABLE_CLOCK (1 << 0) /* Start Calib Table Clock */
1679#define CALIB_TABLE_SELECT(x) (((x) & 0x3) << 5) /* Calib Table Select<1:0> */
1680
1681/*
1682* REG_LNA_GAIN_DIFF_READ_BACK
1683*/
1684#define LNA_CALIB_TABLE_GAIN_DIFFERENCE_WORD(x) (((x) & 0x3F) << 0) /* LNA Calib Table Gain Difference Word<5:0> */
1685
1686/*
1687* REG_MAX_MIXER_CALIBRATION_GAIN_INDEX
1688*/
1689#define MAX_MIXER_CALIBRATION_GAIN_INDEX(x) (((x) & 0x1F) << 0) /* Max Mixer Calibration Gain Index<4:0> */
1690
1691/*
1692* REG_SETTLE_TIME
1693*/
1694#define ENABLE_DIG_GAIN_CORR (1 << 7) /* Enable Dig Gain Corr */
1695#define FORCE_TEMP_SENSOR_FOR_CAL (1 << 6) /* Force Temp Sensor for Cal */
1696#define SETTLE_TIME(x) (((x) & 0x3F) << 0) /* Settle Time<5:0> */
1697
1698/*
1699* REG_MEASURE_DURATION
1700*/
1701#define GAIN_CAL_MEAS_DURATION(x) (((x) & 0xF) << 0) /* Gain Cal Meas Duration<3:0> */
1702
1703/*
1704* REG_MEASURE_DURATION_01
1705*/
1706#define MEASUREMENT_DURATION_1(x) (((x) & 0xF) << 4) /* Measurement duration 1 <3:0> */
1707#define MEASUREMENT_DURATION_0(x) (((x) & 0xF) << 0) /* Measurement duration 0 <3:0> */
1708
1709/*
1710* REG_MEASURE_DURATION_23
1711*/
1712#define MEASUREMENT_DURATION_3(x) (((x) & 0xF) << 4) /* Measurement duration 3 <3:0> */
1713#define MEASUREMENT_DURATION_2(x) (((x) & 0xF) << 0) /* Measurement duration 2 <3:0> */
1714
1715/*
1716* REG_RSSI_CONFIG
1717*/
1718#define START_RSSI_MEAS (1 << 5) /* Start RSSI Meas (Mode 4) */
1719#define ENABLE_ADC_POWER_MEAS (1 << 1) /* Enable ADC Power Meas. */
1720#define DEFAULT_RSSI_MEAS_MODE (1 << 0) /* Default RSSI Meas Mode */
1721#define RFIR_FOR_RSSI_MEASUREMENT(x) (((x) & 0x3) << 6) /* RFIR for RSSI measurement<1:0> */
1722#define RSSI_MODE_SELECT(x) (((x) & 0x7) << 2) /* RSSI Mode Select<2:0> */
1723
1724/*
1725* REG_ADC_MEASURE_DURATION_01
1726*/
1727#define ADC_POWER_MEASUREMENT_DURATION_1(x) (((x) & 0xF) << 4) /* ADC Power Measurement Duration 1<3:0> */
1728#define ADC_POWER_MEASUREMENT_DURATION_0(x) (((x) & 0xF) << 0) /* ADC Power Measurement Duration 0 <3:0> */
1729
1730/*
1731* REG_DEC_POWER_MEASURE_DURATION_0
1732*/
1733#define USE_HB3_OUT_FOR_ADC_PWR_MEAS (1 << 7) /* Use HB3 Out for ADC Pwr Meas */
1734#define USE_HB1_OUT_FOR_DEC_PWR_MEAS (1 << 6) /* Use HB1 Out for Dec pwr Meas */
1735#define ENABLE_DEC_PWR_MEAS (1 << 5) /* Enable Dec Pwr Meas */
1736#define DEFAULT_MODE_ADC_POWER (1 << 4) /* Default Mode ADC Power */
1737#define DEC_POWER_MEASUREMENT_DURATION(x) (((x) & 0xF) << 0) /* Dec Power Measurement Duration <3:0> */
1738
1739/*
1740* REG_LNA_GAIN
1741*/
1742#define DB_GAIN_READBACK_CHANNEL (1 << 0) /* dB Gain Read-back Channel */
1743#define MAX_LNA_GAIN(x) (((x) & 0x7F) << 1) /* Max LNA Gain<6:0> */
1744
1745/*
1746* REG_RX_QUAD_CAL_LEVEL
1747*/
1748#define RX_QUAD_CAL_LEVEL(x) (((x) & 0xF) << 0) /* Rx Quad Cal Level <3 :0> */
1749
1750/*
1751* REG_CALIBRATION_CONFIG_1
1752*/
1753#define ENABLE_PHASE_CORR (1 << 7) /* Enable Phase Corr */
1754#define ENABLE_GAIN_CORR (1 << 6) /* Enable Gain Corr */
1755#define USE_SETTLE_COUNT_FOR_DC_CAL_WAIT (1 << 5) /* Use Settle Count for DC Cal Wait */
1756#define FIXED_DC_CAL_WAIT_TIME (1 << 4) /* Fixed DC Cal Wait Time */
1757#define FREE_RUN_MODE (1 << 3) /* Free Run Mode */
1758#define ENABLE_CORR_WORD_DECIMATION (1 << 2) /* Enable Corr Word Decimation */
1759#define ENABLE_TRACKING_MODE_CH2 (1 << 1) /* Enable Tracking Mode CH2 */
1760#define ENABLE_TRACKING_MODE_CH1 (1 << 0) /* Enable Tracking Mode CH1 */
1761
1762/*
1763* REG_CALIBRATION_CONFIG_2
1764*/
1765#define SOFT_RESET (1 << 7) /* Soft Reset */
1766#define CALIBRATION_CONFIG2_DFLT (0x3 << 5) /* Must be 2'b11 */
1767#define K_EXP_PHASE(x) (((x) & 0x1F) << 0) /* K exp Phase<4:0> */
1768
1769/*
1770* REG_CALIBRATION_CONFIG_3
1771*/
1772#define PREVENT_POS_LOOP_GAIN (1 << 7) /* Prevent Pos Loop Gain */
1773#define K_EXP_AMPLITUDE(x) (((x) & 0x1F) << 0) /* K exp Amplitude<4:0> */
1774
1775/*
1776* REG_RX_QUAD_GAIN1
1777*/
1778#define RX_FULL_TABLELMT_TABLE_GAIN(x) (((x) & 0x7F) << 0) /* Rx Full table/LMT table gain<6:0> */
1779
1780/*
1781* REG_RX_QUAD_GAIN2
1782*/
1783#define CORRECTION_WORD_DECIMATION_M(x) (((x) & 0x7) << 5) /* Correction Word Decimation M<2:0> */
1784#define RX_LPF_GAIN(x) (((x) & 0x1F) << 0) /* Rx LPF gain<4:0> */
1785
1786/*
1787* REG_RX1_INPUT_A_OFFSETS
1788*/
1789#define RX1_INPUT_A_I_DC_OFFSET_LSB(x) (((x) & 0x3F) << 2) /* Rx1 Input A "I" DC Offset<5:0> */
1790#define RX1_INPUT_A_Q_DC_OFFSET(x) (((x) & 0x3) << 0) /* Rx1 Input A "Q" DC Offset<9:8> */
1791
1792/*
1793* REG_INPUT_A_OFFSETS_1
1794*/
1795#define RX2_INPUT_A_Q_DC_OFFSET_LSB(x) (((x) & 0xF) << 4) /* Rx2 Input A "Q" DC Offset<3:0> */
1796#define RX1_INPUT_A_I_DC_OFFSET_MSB(x) (((x) & 0xF) << 0) /* Rx1 Input A "I" DC Offset<9:6> */
1797
1798/*
1799* REG_RX2_INPUT_A_OFFSETS
1800*/
1801#define RX2_INPUT_A_I_DC_OFFSET(x) (((x) & 0x3) << 6) /* Rx2 Input A "I" DC Offset<1:0> */
1802#define RX2_INPUT_A_Q_DC_OFFSET_MSB(x) (((x) & 0x3F) << 0) /* Rx2 Input A "Q" DC Offset<9:4> */
1803
1804/*
1805* REG_RX1_INPUT_BC_OFFSETS
1806*/
1807#define RX1_INPUT_BC_I_DC_OFFSET_LSB(x) (((x) & 0x3F) << 2) /* Rx1 Input B&C "I" DC Offset<5:0> */
1808#define RX1_INPUT_BC_Q_DC_OFFSET(x) (((x) & 0x3) << 0) /* Rx1 Input B&C "Q" DC Offset<9:8> */
1809
1810/*
1811* REG_INPUT_BC_OFFSETS_1
1812*/
1813#define RX2_INPUT_BC_Q_DC_OFFSET_LSB(x) (((x) & 0xF) << 4) /* Rx2 Input B&C "Q" DC Offset<3:0> */
1814#define RX1_INPUT_BC_I_DC_OFFSET_MSB(x) (((x) & 0xF) << 0) /* Rx1 Input B&C "I" DC Offset<9:6> */
1815
1816/*
1817* REG_RX2_INPUT_BC_OFFSETS
1818*/
1819#define RX2_INPUT_BC_I_DC_OFFSET(x) (((x) & 0x3) << 6) /* Rx2 Input B&C "I" DC Offset<1:0> */
1820#define RX2_INPUT_BC_Q_DC_OFFSET_MSB(x) (((x) & 0x3F) << 0) /* Rx2 Input B&C "Q" DC Offset<9:4> */
1821
1822/*
1823* REG_FORCE_BITS
1824*/
1825#define RX2_INPUT_BC_FORCE_OFFSET (1 << 7) /* Rx2 Input B&C Force offset */
1826#define RX1_INPUT_BC_FORCE_OFFSET (1 << 6) /* Rx1 Input B&C Force offset */
1827#define RX2_INPUT_BC_FORCE_PHGAIN (1 << 5) /* Rx2 Input B&C Force Ph/Gain */
1828#define RX1_INPUT_BC_FORCE_PHGAIN (1 << 4) /* Rx1 Input B&C Force Ph/Gain */
1829#define RX2_INPUT_A_FORCE_OFFSET (1 << 3) /* Rx2 Input A Force offset */
1830#define RX1_INPUT_A_FORCE_OFFSET (1 << 2) /* Rx1 Input A Force offset */
1831#define RX2_INPUT_A_FORCE_PHGAIN (1 << 1) /* Rx2 Input A Force Ph/Gain */
1832#define RX1_INPUT_A_FORCE_PHGAIN (1 << 0) /* Rx1 Input A Force Ph/Gain */
1833
1834/*
1835* REG_RF_DC_OFFSET_CONFIG_1
1836*/
1837#define DAC_FS(x) (((x) & 0x3) << 4) /* DAC FS<1:0> */
1838#define RF_DC_CALIBRATION_COUNT(x) (((x) & 0xF) << 0) /* RF DC Calibration Count<3:0> */
1839
1840/*
1841* REG_RF_DC_OFFSET_ATTEN
1842*/
1843#define RF_DC_OFFSET_TABLE_UPDATE_COUNT(x) (((x) & 0x7) << 5) /* RF DC Offset Table Update Count<2:0> */
1844#define RF_DC_OFFSET_ATTEN(x) (((x) & 0x1F) << 0) /* RF DC Offset Attenuation<4:0> */
1845
1846/*
1847* REG_INVERT_BITS
1848*/
1849#define INVERT_RX2_RF_DC_CGIN_WORD (1 << 7) /* Invert Rx2 RF DC CGin Word */
1850#define INVERT_RX1_RF_DC_CGIN_WORD (1 << 6) /* Invert Rx1 RF DC CGin Word */
1851#define INVERT_RX2_RF_DC_CGOUT_WORD (1 << 5) /* Invert Rx2 RF DC CGout Word */
1852#define INVERT_RX1_RF_DC_CGOUT_WORD (1 << 4) /* Invert Rx1 RF DC CGout Word */
1853
1854/*
1855* REG_DC_OFFSET_CONFIG2
1856*/
1857#define USE_WAIT_COUNTER_FOR_RF_DC_INIT_CAL (1 << 7) /* Use Wait Counter for RF DC Init Cal */
1858#define ENABLE_FAST_SETTLE_MODE (1 << 6) /* Enable Fast Settle Mode */
1859#define ENABLE_BB_DC_OFFSET_TRACKING (1 << 5) /* Enable BB DC Offset Tracking */
1860#define RESET_ACC_ON_GAIN_CHANGE (1 << 4) /* Reset Acc on Gain Change */
1861#define ENABLE_RF_OFFSET_TRACKING (1 << 3) /* Enable RF Offset Tracking */
1862#define DC_OFFSET_UPDATE(x) (((x) & 0x7) << 0) /* DC Offset Update<2:0> */
1863
1864/*
1865* REG_RF_CAL_GAIN_INDEX
1866*/
1867#define RF_MINIMUM_CALIBRATION_GAIN_INDEX(x) (((x) & 0x7F) << 0) /* RF Minimum Calibration Gain Index<6:0> */
1868
1869/*
1870* REG_SOI_THRESH
1871*/
1872#define RF_SOI_THRESH(x) (((x) & 0x7F) << 0) /* RF SOI Threshold<6:0> */
1873
1874/*
1875* REG_BB_DC_OFFSET_SHIFT
1876*/
1877#define INCREASE_COUNT_DURATION (1 << 7) /* Increase Count Duration */
1878#define BB_TRACKING_DECIMATE(x) (((x) & 0x3) << 5) /* BB Tracking Decimate<1:0> */
1879#define BB_DC_M_SHIFT(x) (((x) & 0x1F) << 0) /* BB DC M Shift<4:0> */
1880
1881/*
1882* REG_BB_DC_OFFSET_FAST_SETTLE_SHIFT
1883*/
1884#define READ_BACK_CH_SEL (1 << 7) /* Read Back CH Sel */
1885#define UPDATE_TRACKING_WORD (1 << 6) /* Update Tracking Word */
1886#define FORCE_RX_NULL (1 << 5) /* Force Rx Null */
1887#define BB_DC_TRACKING_FAST_SETTLE_M_SHIFT(x) (((x) & 0x1F) << 0) /* BB DC Tracking Fast Settle M Shift<4:0> */
1888
1889/*
1890* REG_BB_DC_OFFSET_ATTEN
1891*/
1892#define BB_DC_OFFSET_ATTEN(x) (((x) & 0xF) << 0) /* BB DC Offset Atten<3:0> */
1893
1894/*
1895* REG_RX1_BB_DC_WORD_I_MSB
1896*/
1897#define RX1_BB_DC_OFFSET_CORRECTION_WORD_I(x) (((x) & 0x7F) << 0) /* RX1 BB DC Offset Correction word I<14:8> */
1898
1899/*
1900* REG_RX1_BB_DC_WORD_Q_MSB
1901*/
1902#define RX1_BB_DC_OFFSET_CORRECTION_WORD_Q(x) (((x) & 0x7F) << 0) /* RX1 BB DC Offset Correction word Q<14:8> */
1903
1904/*
1905* REG_RX2_BB_DC_WORD_I_MSB
1906*/
1907#define RX2_BB_DC_OFFSET_CORRECTION_WORD_I(x) (((x) & 0x7F) << 0) /* RX2 BB DC Offset Correction word I<14:8> */
1908
1909/*
1910* REG_RX2_BB_DC_WORD_Q_MSB
1911*/
1912#define RX2_BB_DC_OFFSET_CORRECTION_WORD_Q(x) (((x) & 0x7F) << 0) /* RX2 BB DC Offset Correction word Q<14:8> */
1913
1914/*
1915* REG_BB_TRACK_CORR_WORD_I_MSB
1916*/
1917#define RX1RX2_BB_DC_OFFSET_TRACKING_CORRECTION_WORD_I(x) (((x) & 0x7F) << 0) /* RX1/RX2 BB DC Offset Tracking correction word I<14:8> */
1918
1919/*
1920* REG_BB_TRACK_CORR_WORD_Q_MSB
1921*/
1922#define RX1RX2_BB_DC_OFFSET_TRACKING_CORRECTION_WORD_Q(x) (((x) & 0x7F) << 0) /* RX1/RX2 BB DC Offset Tracking correction word Q<14:8> */
1923
1924/*
1925* REG_SYMBOL_LSB
1926*/
1927#define RX2_RSSI_SYMBOL (1 << 1) /* Rx2 RSSI symbol <0> */
1928#define RX1_RSSI_SYMBOL (1 << 0) /* Rx1 RSSI symbol <0> */
1929
1930/*
1931* REG_PREAMBLE_LSB
1932*/
1933#define RX2_RSSI_PREAMBLE (1 << 1) /* Rx2 RSSI preamble <0> */
1934#define RX1_RSSI_PREAMBLE (1 << 0) /* Rx1 RSSI preamble <0> */
1935
1936/*
1937* REG_RX1_RSSI_SYMBOL, REG_RX1_RSSI_PREAMBLE,
1938* REG_RX2_RSSI_SYMBOL, REG_RX2_RSSI_PREAMBLE
1939*/
1940#define RSSI_LSB_SHIFT 1
1941#define RSSI_LSB_MASK1 0x01
1942#define RSSI_LSB_MASK2 0x02
1943
1944/*
1945* REG_RX_PATH_GAIN_LSB
1946*/
1947#define RX_PATH_GAIN (1 << 0) /* Rx Path Gain<0> */
1948
1949/*
1950* REG_RX_DIFF_LNA_FORCE
1951*/
1952#define FORCE_RX2_LNA_GAIN (1 << 7) /* Force Rx2 LNA Gain */
1953#define RX2_LNA_BYPASS (1 << 6) /* Rx2 LNA Bypass */
1954#define FORCE_RX1_LNA_GAIN (1 << 3) /* Force Rx1 LNA Gain */
1955#define RX1_LNA_BYPASS (1 << 2) /* Rx1 LNA Bypass */
1956#define RX2_LNA_GAIN(x) (((x) & 0x3) << 4) /* Rx2 LNA Gain<1:0> */
1957#define RX1_LNA_GAIN(x) (((x) & 0x3) << 0) /* Rx1 LNA Gain<1:0> */
1958
1959/*
1960* REG_RX_LNA_BIAS_COARSE
1961*/
1962#define RX_LNA_BIAS_COARSE(x) (((x) & 0xF) << 0) /* Rx LNA Bias Coarse<3:0> */
1963
1964/*
1965* REG_RX_LNA_BIAS_FINE_0
1966*/
1967#define RX_LNA_PCASCODE_BIAS(x) (((x) & 0x7) << 5) /* Rx LNA p-Cascode Bias<2:0> */
1968#define RX_LNA_BIAS(x) (((x) & 0x1F) << 0) /* Rx LNA Bias<4:0> */
1969
1970/*
1971* REG_RX_LNA_BIAS_FINE_1
1972*/
1973#define RX_LNA_P_CASCODE_BIAS_FINE(x) (((x) & 0x3) << 0) /* Rx LNA p- Cascode Bias Fine<4:3> */
1974
1975/*
1976* REG_RX_MIX_GM_CONFIG
1977*/
1978#define RX_MIX_GM_CM_OUT(x) (((x) & 0x7) << 5) /* Rx Mix Gm CM Out<2:0> */
1979#define RX_MIX_GM_PLOAD(x) (((x) & 0x3) << 0) /* Rx Mix Gm pload <1:0> */
1980
1981/*
1982* REG_RX1_MIX_GM_FORCE
1983*/
1984#define FORCE_RX1_MIX_GM (1 << 6) /* Force Rx1 Mix Gm */
1985#define RX1_MIX_GM_GAIN(x) (((x) & 0x3F) << 0) /* Rx1 Mix Gm Gain<5:0> */
1986
1987/*
1988* REG_RX1_MIX_GM_BIAS_FORCE
1989*/
1990#define RX1_MIX_GM_BIAS(x) (((x) & 0x1F) << 0) /* Rx1 Mix Gm Bias<4:0> */
1991
1992/*
1993* REG_RX2_MIX_GM_FORCE
1994*/
1995#define FORCE_RX2_MIX_GM (1 << 6) /* Force Rx2 Mix Gm */
1996#define RX2_MIX_GM_GAIN(x) (((x) & 0x3F) << 0) /* Rx2 Mix Gm Gain<5:0> */
1997
1998/*
1999* REG_RX2_MIX_GM_BIAS_FORCE
2000*/
2001#define RX2_MIX_GM_BIAS(x) (((x) & 0x1F) << 0) /* Rx2 Mix Gm Bias<4:0> */
2002
2003/*
2004* REG_INPUT_A_MSBS
2005*/
2006#define INPUT_A_RX1_Q(x) (((x) & 0x3) << 6) /* Input A RX1 Q<9:8> */
2007#define INPUT_A_RX1_I(x) (((x) & 0x3) << 4) /* Input A RX1 I<9:8> */
2008#define INPUT_A_RX2_I(x) (((x) & 0x3) << 2) /* Input A RX2 I<9:8> */
2009#define INPUT_A_RX2_Q(x) (((x) & 0x3) << 0) /* Input A RX2 Q<9:8> */
2010
2011/*
2012* REG_INPUTS_BC_MSBS
2013*/
2014#define INPUTS_BC_RX1_Q(x) (((x) & 0x3) << 6) /* Inputs B&C RX1 Q<9:8> */
2015#define INPUTS_BC_RX1_I(x) (((x) & 0x3) << 4) /* Inputs B&C RX1 I<9:8> */
2016#define INPUTS_BC_RX2_I(x) (((x) & 0x3) << 2) /* Inputs B&C RX2 I<9:8> */
2017#define INPUTS_BC_RX2_Q(x) (((x) & 0x3) << 0) /* Inputs B&C RX2 Q<9:8> */
2018
2019/*
2020* REG_FORCE_OS_DAC
2021*/
2022#define FORCE_CGIN_DAC (1 << 2) /* Force CGin DAC */
2023
2024/*
2025* REG_RX_MIX_LO_CM
2026*/
2027#define RX_MIX_LO_CM(x) (((x) & 0x3F) << 0) /* Rx Mix LO CM<5:0> */
2028
2029/*
2030* REG_RX_CGB_SEG_ENABLE
2031*/
2032#define RX_CGB_SEG_ENABLE(x) (((x) & 0x3F) << 0) /* Rx CGB Seg Enable<5:0> */
2033
2034/*
2035* REG_RX_MIX_INPUTBIAS
2036*/
2037#define RX_CGB_INPUT_CM_SEL(x) (((x) & 0x3) << 4) /* Rx CGB Input CM Sel<1:0> */
2038#define RX_CGB_BIAS(x) (((x) & 0xF) << 0) /* Rx CGB Bias<3:0> */
2039
2040/*
2041* REG_RX_TIA_CONFIG
2042*/
2043#define TIA2_OVERRIDE_C (1 << 3) /* TIA2 Override C */
2044#define TIA2_OVERRIDE_R (1 << 2) /* TIA2 Override R */
2045#define TIA1_OVERRIDE_C (1 << 1) /* TIA1 Override C */
2046#define TIA1_OVERRIDE_R (1 << 0) /* TIA1 Override R */
2047#define TIA_SEL_CC(x) (((x) & 0x7) << 5) /* TIA Sel CC<2:0> */
2048
2049/*
2050* REG_TIA1_C_LSB
2051*/
2052#define TIA1_RF(x) (((x) & 0x3) << 6) /* TIA1 RF<1:0> */
2053#define TIA1_C_LSB(x) (((x) & 0x3F) << 0) /* TIA1 C LSB<5:0> */
2054
2055/*
2056* REG_TIA1_C_MSB
2057*/
2058#define TIA1_C_MSB(x) (((x) & 0x7F) << 0) /* TIA1 C MSB<6:0> */
2059
2060/*
2061* REG_TIA2_C_LSB
2062*/
2063#define TIA2_RF(x) (((x) & 0x3) << 6) /* TIA2 RF<1:0> */
2064#define TIA2_C_LSB(x) (((x) & 0x3F) << 0) /* TIA2 C LSB<5:0> */
2065
2066/*
2067* REG_TIA2_C_MSB
2068*/
2069#define TIA2_C_MSB(x) (((x) & 0x7F) << 0) /* TIA2 C MSB<6:0> */
2070
2071/*
2072* REG_RX1_BBF_R1A
2073*/
2074#define FORCE_RX1_RESISTORS (1 << 7) /* Force Rx1 Resistors */
2075#define RX1_BBF_R1A(x) (((x) & 0x3F) << 0) /* Rx1 BBF R1A<5:0> */
2076
2077/*
2078* REG_RX2_BBF_R1A
2079*/
2080#define FORCE_RX2_RESISTORS (1 << 7) /* Force Rx2 Resistors */
2081#define RX2_BBF_R1A(x) (((x) & 0x3F) << 0) /* Rx2 BBF R1A<5:0> */
2082
2083/*
2084* REG_RX1_TUNE_CTRL
2085*/
2086#define RX1_TUNE_RESAMPLE_PHASE (1 << 2) /* Rx1 Tune Resample Phase */
2087#define RX1_TUNE_RESAMPLE (1 << 1) /* Rx1 Tune Resample */
2088#define RX1_PD_TUNE (1 << 0) /* Rx1 PD Tune */
2089
2090/*
2091* REG_RX2_TUNE_CTRL
2092*/
2093#define RX2_TUNE_RESAMPLE_PHASE (1 << 2) /* Rx2 Tune Resam ple Phase */
2094#define RX2_TUNE_RESAMPLE (1 << 1) /* Rx2 Tune Resample */
2095#define RX2_PD_TUNE (1 << 0) /* Rx2 PD Tune */
2096
2097/*
2098* REG_RX_BBF_R2346
2099*/
2100#define TUNE_OVERRIDE (1 << 7) /* Tune Override */
2101#define RX_BBF_R2346(x) (((x) & 0x7) << 0) /* Rx BBF R2346<2:0> */
2102
2103/*
2104* REG_RX_BBF_C1_MSB
2105*/
2106#define RX_BBF_C1_MSB(x) (((x) & 0x3F) << 0) /* Rx BBF C1 MSB<5:0> */
2107
2108/*
2109* REG_RX_BBF_C1_LSB
2110*/
2111#define RX_BBF_C1_LSB(x) (((x) & 0x7F) << 0) /* Rx BBF C1 LSB<6:0> */
2112
2113/*
2114* REG_RX_BBF_C2_MSB
2115*/
2116#define RX_BBF_C2_MSB(x) (((x) & 0x3F) << 0) /* Rx BBF C2 MSB<5:0> */
2117
2118/*
2119* REG_RX_BBF_C2_LSB
2120*/
2121#define RX_BBF_C2_LSB(x) (((x) & 0x7F) << 0) /* Rx BBF C2 LSB<6:0> */
2122
2123/*
2124* REG_RX_BBF_C3_MSB
2125*/
2126#define RX_BBF_C3_MSB(x) (((x) & 0x3F) << 0) /* Rx BBF C3 MSB<5:0> */
2127
2128/*
2129* REG_RX_BBF_C3_LSB
2130*/
2131#define RX_BBF_C3_LSB(x) (((x) & 0x7F) << 0) /* Rx BBF C3 LSB<6:0> */
2132
2133/*
2134* REG_RX_BBF_CC1_CTR
2135*/
2136#define RX_BBF_CC1_CTR(x) (((x) & 0x7F) << 0) /* Rx BBF CC1 Ctr<6:0> */
2137
2138/*
2139* REG_RX_BBF_POW_RZ_BYTE0
2140*/
2141#define MUST_BE_ZERO (1 << 7) /* Must be zero */
2142#define RX1_BBF_POW_CTR(x) (((x) & 0x3) << 5) /* Rx1 BBF Pow Ctr<1:0> */
2143#define RX_BBF_RZ1_CTR(x) (((x) & 0x3) << 3) /* Rx BBF Rz1 Ctr<1:0> */
2144
2145/*
2146* REG_RX_BBF_CC2_CTR
2147*/
2148#define RX_BBF_CC2_CTR(x) (((x) & 0x7F) << 0) /* Rx BBF CC2 Ctr<6:0> */
2149
2150/*
2151* REG_RX_BBF_POW_RZ_BYTE1
2152*/
2153#define RX_BBF_POW3_CTR(x) (((x) & 0x3) << 6) /* Rx BBF Pow3 Ctr<1:0> */
2154#define RX_BBF_RZ3_CTR(x) (((x) & 0x3) << 4) /* Rx BBF RZ3 Ctr<1:0> */
2155#define RX_BBF_POW2_CTR(x) (((x) & 0x3) << 2) /* Rx BBF Pow2 Ctr<1:0> */
2156#define RX_BBF_RZ2_CTR(x) (((x) & 0x3) << 0) /* Rx BBF Rz2 Ctr<1:0> */
2157
2158/*
2159* REG_RX_BBF_CC3_CTR
2160*/
2161#define RX_BBF_CC3_CTR(x) (((x) & 0x7F) << 0) /* Rx BBF CC3 Ctr<6:0> */
2162
2163/*
2164* REG_RX_BBF_TUNE
2165*/
2166#define RXBBF_BYPASS_BIAS_R (1 << 7) /* RxBBF Bypass Bias R */
2167#define RX_BBF_R5_TUNE (1 << 4) /* Rx BBF R5 Tune */
2168#define RX1_BBF_TUNE_COMP_I (1 << 3) /* Rx1 BBF Tune Comp I */
2169#define RX1_BBF_TUNE_COMP_Q (1 << 2) /* Rx1 BBF Tune Comp Q */
2170#define RX2_BBF_TUNE_COMP_I (1 << 1) /* Rx2 BBF Tune Comp I */
2171#define RX2_BBF_TUNE_COMP_Q (1 << 0) /* Rx2 BBF Tune Comp Q */
2172#define RX_BBF_TUNE_CTR(x) (((x) & 0x3) << 5) /* Rx BBF Tune Ctr<1:0> */
2173
2174/*
2175* REG_RX1_BBF_MAN_GAIN
2176*/
2177#define RX1_BBF_FORCE_GAIN (1 << 5) /* Rx1 BBF Force Gain */
2178#define RX1_BBF_BQ_GAIN(x) (((x) & 0x3) << 3) /* Rx1 BBF BQ Gain<1:0> */
2179#define RX1_BBF_POLE_GAIN(x) (((x) & 0x7) << 0) /* Rx1 BBF Pole Gain<2:0> */
2180
2181/*
2182* REG_RX2_BBF_MAN_GAIN
2183*/
2184#define RX2_BBF_FORCE_GAIN (1 << 5) /* Rx2 BBF Force Gain */
2185#define RX2_BBF_BQ_GAIN(x) (((x) & 0x3) << 3) /* Rx2 BBF BQ Gain<1:0> */
2186#define RX2_BBF_POLE_GAIN(x) (((x) & 0x7) << 0) /* Rx2 BBF Pole Gain<2:0> */
2187
2188/*
2189* REG_RX_BBF_TUNE_CONFIG
2190*/
2191#define RX_TUNE_EVALTIME (1 << 4) /* Rx Tune Evaltime */
2192#define RX_BBF_TUNE_DIVIDE (1 << 0) /* RX BBF Tune Divide<8> */
2193#define TUNE_COMP_MASK(x) (((x) & 0x3) << 5) /* Tune Comp Mask <1:0> */
2194#define RX_TUNE_MODE(x) (((x) & 0x7) << 1) /* Rx Tune Mode<2:0> */
2195
2196/*
2197* REG_POLE_GAIN
2198*/
2199#define POLE_GAIN_TUNE(x) (((x) & 0x3) << 0) /* Pole Gain Tune<1:0> */
2200
2201/*
2202* REG_RX_BBBW_MHZ
2203*/
2204#define RX_TUNE_BBBW_MHZ(x) (((x) & 0x1F) << 0) /* Rx Tune BBBW MHz<4::0> */
2205
2206/*
2207* REG_RX_BBBW_KHZ
2208*/
2209#define RX_TUNE_BBBW_KHZ(x) (((x) & 0x7F) << 0) /* Rx Tune BBBW kHz<6:0> */
2210
2211/*
2212* REG_RX_PFD_CONFIG
2213*/
2214#define BYPASS_LD_SYNTH (1 << 0) /* Bypass Ld Synth */
2215
2216/*
2217* REG_RX_INTEGER_BYTE_1
2218*/
2219#define SYNTH_INTEGER_WORD(x) (((x) & 0x7) << 0) /* Synthesizer Integer Word<10:8> */
2220
2221/*
2222* REG_RX_FRACT_BYTE_2
2223*/
2224#define SYNTH_FRACT_WORD(x) (((x) & 0x7F) << 0) /* Synthesizer Fractional Word <22:16> */
2225
2226/*
2227* REG_RX_FORCE_VCO_TUNE_1
2228*/
2229#define VCO_CAL_OFFSET(x) (((x) & 0xF) << 3) /* VCO Cal Offset<3:0> */
2230
2231/*
2232* REG_RX_ALC_VARACTOR
2233*/
2234#define INIT_ALC_VALUE(x) (((x) & 0xF) << 4) /* Init ALC Value<3:0> */
2235#define VCO_VARACTOR(x) (((x) & 0xF) << 0) /* VCO Varactor<3:0> */
2236
2237/*
2238* REG_RX_VCO_OUTPUT
2239*/
2240#define PORB_VCO_LOGIC (1 << 6) /* PORb VCO Logic */
2241#define VCO_OUTPUT_LEVEL(x) (((x) & 0xF) << 0) /* VCO Output Level<3:0> */
2242
2243/*
2244* REG_RX_CP_CURRENT
2245*/
2246#define CHARGE_PUMP_CURRENT(x) (((x) & 0x3F) << 0) /* Charge Pump Current<5:0> */
2247
2248/*
2249* REG_RX_CP_OFFSET
2250*/
2251#define SYNTH_RECAL (1 << 7) /* Synth Re-Cal */
2252
2253/*
2254* REG_RX_CP_CONFIG
2255*/
2256#define HALF_VCO_CAL_CLK (1 << 7) /* Half Vco Cal Clk */
2257#define CP_OFFSET_OFF (1 << 4) /* CP Offset Off */
2258#define F_CPCAL (1 << 3) /* F Cpcal */
2259#define CP_CAL_ENABLE (1 << 2) /* Cp Cal Enable */
2260
2261/*
2262* REG_RX_LOOP_FILTER_1
2263*/
2264#define LOOP_FILTER_C2(x) (((x) & 0xF) << 4) /* Loop Filter C2<3:0> */
2265#define LOOP_FILTER_C1(x) (((x) & 0xF) << 0) /* Loop Filter C1<3:0> */
2266
2267/*
2268* REG_RX_LOOP_FILTER_2
2269*/
2270#define LOOP_FILTER_R1(x) (((x) & 0xF) << 4) /* Loop Filter R1<3:0> */
2271#define LOOP_FILTER_C3(x) (((x) & 0xF) << 0) /* Loop Filter C3<3:0> */
2272
2273/*
2274* REG_RX_LOOP_FILTER_3
2275*/
2276#define LOOP_FILTER_BYPASS_R3 (1 << 7) /* Loop Filter Bypass R3 */
2277#define LOOP_FILTER_BYPASS_R1 (1 << 6) /* Loop Filter Bypass R1 */
2278#define LOOP_FILTER_BYPASS_C2 (1 << 5) /* Loop Filter Bypass C2 */
2279#define LOOP_FILTER_BYPASS_C1 (1 << 4) /* Loop Filter Bypass C1 */
2280#define LOOP_FILTER_R3(x) (((x) & 0xF) << 0) /* Loop Filter R3<3:0> */
2281
2282/*
2283* REG_RX_DITHERCP_CAL
2284*/
2285#define FORCED_CP_CAL_WORD(x) (((x) & 0xF) << 0) /* Forced CP Cal Word<3:0> */
2286
2287/*
2288* REG_RX_VCO_BIAS_1
2289*/
2290#define VCO_BIAS_TCF(x) (((x) & 0x3) << 3) /* VCO Bias Tcf<1:0> */
2291#define VCO_BIAS_REF(x) (((x) & 0x7) << 0) /* VCO Bias Ref<2:0> */
2292
2293/*
2294* REG_RX_CAL_STATUS
2295*/
2296#define CP_CAL_VALID (1 << 7) /* CP Cal Valid */
2297#define CP_CAL_DONE (1 << 5) /* CP Cal Done */
2298#define VCO_CAL_BUSY (1 << 4) /* VCO Cal Busy */
2299#define CP_CAL_WORD(x) (((x) & 0xF) << 0) /* CP Cal Word<3:0> */
2300
2301/*
2302* REG_RX_VCO_CAL_REF
2303*/
2304#define VCO_CAL_REF_TCF(x) (((x) & 0x7) << 0) /* VCO Cal Ref Tcf<2:0> */
2305
2306/*
2307* REG_RX_VCO_PD_OVERRIDES
2308*/
2309#define POWER_DOWN_VARACTOR_REF (1 << 3) /* Power Down Varactor Ref */
2310#define PWR_DOWN_VARACT_REF_TCF (1 << 2) /* Pwr Down Varact Ref Tcf */
2311#define POWER_DOWN_CAL_TCF (1 << 1) /* Power Down Cal Tcf */
2312#define POWER_DOWN_VCO_BUFFFER (1 << 0) /* Power Down VCO Bufffer */
2313
2314/*
2315* REG_RX_CP_OVERRANGE_VCO_LOCK
2316*/
2317#define CP_OVRG_HIGH (1 << 7) /* CP Ovrg High */
2318#define CP_OVRG_LOW (1 << 6) /* CP Ovrg Low */
2319#define VCO_LOCK (1 << 1) /* Lock */
2320
2321/*
2322* REG_RX_VCO_LDO
2323*/
2324#define VCO_LDO_BYPASS (1 << 7) /* VCO LDO Bypass */
2325#define VCO_LDO_INRUSH(x) (((x) & 0x3) << 5) /* VCO LDO Inrush<1:0> */
2326#define VCO_LDO_SEL(x) (((x) & 0x7) << 2) /* VCO LDO Sel<2:0> */
2327#define VCO_LDO_VDROP_SEL(x) (((x) & 0x3) << 0) /* VCO LDO Vdrop Sel<1:0> */
2328
2329/*
2330* REG_RX_VCO_CAL
2331*/
2332#define VCO_CAL_EN (1 << 7) /* VCO Cal En */
2333#define VCO_CAL_ALC_WAIT(x) (((x) & 0x7) << 4) /* VCO Cal ALC Wait <2:0> */
2334#define VCO_CAL_COUNT(x) (((x) & 0x3) << 2) /* VCO Cal Count <1:0> */
2335
2336/*
2337* REG_RX_LOCK_DETECT_CONFIG
2338*/
2339#define LOCK_DETECT_COUNT(x) (((x) & 0x3) << 2) /* Lock Detect Count<1:0> */
2340#define LOCK_DETECT_MODE(x) (((x) & 0x3) << 0) /* Lock Detect Mode<1:0> */
2341
2342/*
2343* REG_RX_CP_LEVEL_DETECT
2344*/
2345#define CP_LEVEL_DETECT_POWER_DOWN (1 << 6) /* CP Level Detect Power Down */
2346#define CP_LEVEL_THRESH_LOW(x) (((x) & 0x7) << 3) /* CP Level Threshold Low<2:0> */
2347#define CP_LEVEL_THRESH_HIGH(x) (((x) & 0x7) << 0) /* CP Level Threshold High<2:0> */
2348
2349/*
2350* REG_RX_DSM_SETUP_0
2351*/
2352#define DSM_PROG(x) (((x) & 0xF) << 0) /* DSM Prog<3:0> */
2353
2354/*
2355* REG_RX_DSM_SETUP_1
2356*/
2357#define SIF_CLOCK (1 << 6) /* SIF clock */
2358#define SIF_RESET_BAR (1 << 5) /* SIF Reset Bar */
2359#define SIF_ADDR(x) (((x) & 0x1F) << 0) /* SIF Addr<4:0> */
2360
2361/*
2362* REG_RX_CORRECTION_WORD0
2363*/
2364#define UPDATE_FREQ_WORD (1 << 7) /* Update Freq Word */
2365#define READ_EFFECTIVE_TUNING_WORD (1 << 5) /* Read Effective Tuning Word */
2366#define FREQ_CORRECTION_WORD_MSB(x) (((x) & 0x1F) << 0) /* Frequency Correction Word<11:7> */
2367
2368/*
2369* REG_RX_CORRECTION_WORD1
2370*/
2371#define UPDATE_FREQ_WORD (1 << 7) /* Update Freq Word */
2372#define FREQ_CORRECTION_WORD_LSB(x) (((x) & 0x7F) << 0) /* Frequency Correction Word<6:0> */
2373
2374/*
2375* REG_RX_VCO_VARACTOR_CTRL_0
2376*/
2377#define VCO_VARACTOR_REFERENCE_TCF(x) (((x) & 0x7) << 4) /* VCO Varactor Reference Tcf<2:0> */
2378#define VCO_VARACTOR_OFFSET(x) (((x) & 0xF) << 0) /* VCO Varactor Offset<3:0> */
2379
2380/*
2381* REG_RX_VCO_VARACTOR_CTRL_1
2382*/
2383#define VCO_VARACTOR_REFERENCE(x) (((x) & 0xF) << 0) /* VCO Varactor Reference<3:0> */
2384
2385/*
2386* REG_RX_FAST_LOCK_SETUP
2387*/
2388#define RX_FAST_LOCK_LOAD_SYNTH (1 << 3) /* Rx Fast Lock Load Synth */
2389#define RX_FAST_LOCK_PROFILE_INIT (1 << 2) /* Rx Fast Lock Profile Init */
2390#define RX_FAST_LOCK_PROFILE_PIN_SELECT (1 << 1) /* Rx Fast Lock Profile Pin Select */
2391#define RX_FAST_LOCK_MODE_ENABLE (1 << 0) /* Rx Fast Lock Mode Enable */
2392#define RX_FAST_LOCK_PROFILE(x) (((x) & 0x7) << 5) /* Rx Fast Lock Profile<2:0> */
2393
2394/*
2395* REG_RX_FAST_LOCK_PROGRAM_ADDR
2396*/
2397#define RX_FAST_LOCK_PROFILE_ADDR(x) (((x) & 0x7) << 4) /* Rx Fast Lock Profile<2:0> */
2398#define RX_FAST_LOCK_PROFILE_WORD(x) (((x) & 0xF) << 0) /* Configuration Word <3:0> */
2399
2400
2401/*
2402* REG_RX_FAST_LOCK_PROGRAM_CTRL
2403*/
2404#define RX_FAST_LOCK_PROGRAM_WRITE (1 << 1) /* Rx Fast Lock Program Write */
2405#define RX_FAST_LOCK_PROGRAM_CLOCK_ENABLE (1 << 0) /* Rx Fast Lock Program Clock Enable */
2406
2407#define RX_FAST_LOCK_CONFIG_WORD_NUM 16
2408
2409/*
2410* REG_RX_LO_GEN_POWER_MODE
2411*/
2412#define RX_LO_GEN_POWER_MODE(x) (((x) & 0x3) << 4) /* Power Mode<3:0> */
2413
2414/*
2415* REG_TX_PFD_CONFIG
2416*/
2417#define DIV_TEST_EN (1 << 5) /* Div Test En */
2418#define PFD_CLK_EDGE (1 << 1) /* PFD Clk Edge */
2419#define BYPASS_LD_SYNTH (1 << 0) /* Bypass Ld Synth */
2420#define PFD_WIDTH(x) (((x) & 0x3) << 2) /* PFD Width <1:0> */
2421
2422/*
2423* REG_TX_INTEGER_BYTE_1
2424*/
2425#define SDM_BYPASS (1 << 7) /* SDM Bypass */
2426#define SDM_POWER_DOWN (1 << 6) /* SDM Power Down */
2427#define SYNTH_INTEGER_WORD(x) (((x) & 0x7) << 0) /* Synthesizer Integer Word<10:8> */
2428
2429/*
2430* REG_TX_FRACT_BYTE_2
2431*/
2432#define SYNTH_FRACT_WORD(x) (((x) & 0x7F) << 0) /* Synthesizer Fractional Word <22:16> */
2433
2434/*
2435* REG_TX_FORCE_ALC
2436*/
2437#define FORCE_ALC_ENABLE (1 << 7) /* Force ALC Enable */
2438#define FORCE_ALC_WORD(x) (((x) & 0x7F) << 0) /* Force ALC Word<6:0> */
2439
2440/*
2441* REG_TX_FORCE_VCO_TUNE_1
2442*/
2443#define BYPASS_LOAD_DELAY (1 << 7) /* Bypass Load Delay */
2444#define FORCE_VCO_TUNE_ENABLE (1 << 1) /* Force VCO Tune Enable */
2445#define FORCE_VCO_TUNE (1 << 0) /* Force VCO Tune */
2446#define VCO_CAL_OFFSET(x) (((x) & 0xF) << 3) /* VCO Cal Offset<3:0> */
2447
2448/*
2449* REG_TX_ALCVARACT_OR
2450*/
2451#define INIT_ALC_VALUE(x) (((x) & 0xF) << 4) /* Init ALC Value<3:0> */
2452#define VCO_VARACTOR(x) (((x) & 0xF) << 0) /* VCO Varactor<3:0> */
2453
2454/*
2455* REG_TX_VCO_OUTPUT
2456*/
2457#define PORB_VCO_LOGIC (1 << 6) /* PORb VCO Logic */
2458#define VCO_OUTPUT_LEVEL(x) (((x) & 0xF) << 0) /* VCO Output Level<3:0> */
2459
2460/*
2461* REG_TX_CP_CURRENT
2462*/
2463#define TX_CP_CURRENT_DFLT (1 << 7) /* Set to 1 */
2464#define VTUNE_FORCE (1 << 6) /* Vtune Force */
2465#define CHARGE_PUMP_CURRENT(x) (((x) & 0x3F) << 0) /* Charge Pump Current<5:0> */
2466
2467/*
2468* REG_TX_CP_OFFSET
2469*/
2470#define SYNTH_RECAL (1 << 7) /* Synth Re-Cal */
2471#define CHARGE_PUMP_OFFSET(x) (((x) & 0x3F) << 0) /* Charge Pump Offset<5:0> */
2472
2473/*
2474* REG_TX_CP_CONFIG
2475*/
2476#define HALF_VCO_CAL_CLK (1 << 7) /* Half Vco Cal Clk */
2477#define DITHER_MODE (1 << 6) /* Dither Mode */
2478#define CP_OFFSET_OFF (1 << 4) /* Cp Offset Off */
2479#define F_CPCAL (1 << 3) /* F Cpcal */
2480#define CP_CAL_ENABLE (1 << 2) /* Cp Cal Enable */
2481#define CP_TEST(x) (((x) & 0x3) << 0) /* Cp Test <1:0> */
2482
2483/*
2484* REG_TX_LOOP_FILTER_1
2485*/
2486#define LOOP_FILTER_C2(x) (((x) & 0xF) << 4) /* Loop Filter C2<3:0> */
2487#define LOOP_FILTER_C1(x) (((x) & 0xF) << 0) /* Loop Filter C1<3:0> */
2488
2489/*
2490* REG_TX_LOOP_FILTER_2
2491*/
2492#define LOOP_FILTER_R1(x) (((x) & 0xF) << 4) /* Loop Filter R1<3:0> */
2493#define LOOP_FILTER_C3(x) (((x) & 0xF) << 0) /* Loop Filter C3<3:0> */
2494
2495/*
2496* REG_TX_LOOP_FILTER_3
2497*/
2498#define LOOP_FILTER_BYPASS_R3 (1 << 7) /* Loop Filter Bypass R3 */
2499#define LOOP_FILTER_BYPASS_R1 (1 << 6) /* Loop Filter Bypass R1 */
2500#define LOOP_FILTER_BYPASS_C2 (1 << 5) /* Loop Filter Bypass C2 */
2501#define LOOP_FILTER_BYPASS_C1 (1 << 4) /* Loop Filter Bypass C1 */
2502#define LOOP_FILTER_R3(x) (((x) & 0xF) << 0) /* Loop Filter R3<3:0> */
2503
2504/*
2505* REG_TX_DITHERCP_CAL
2506*/
2507#define NUMBER_SDM_DITHER_BITS(x) (((x) & 0xF) << 4) /* Number SDM Dither Bits<3:0> */
2508#define FORCED_CP_CAL_WORD(x) (((x) & 0xF) << 0) /* Forced CP Cal Word<3:0> */
2509
2510/*
2511* REG_TX_VCO_BIAS_1
2512*/
2513#define MUST_BE_ZEROS(x) (((x) & 0x3) << 5) /* Must be zeros */
2514#define VCO_BIAS_TCF(x) (((x) & 0x3) << 3) /* VCO Bias Tcf<1:0> */
2515#define VCO_BIAS_REF(x) (((x) & 0x7) << 0) /* VCO Bias Ref<2:0> */
2516
2517/*
2518* REG_TX_VCO_BIAS_2
2519*/
2520#define VCO_BYPASS_BIAS_DAC_R (1 << 7) /* VCO Bypass Bias DAC R */
2521#define VCO_COMP_BYPASS_BIAS_R (1 << 4) /* VCO Comp Bypass Bias R */
2522#define BYPASS_PRESCALE_R (1 << 3) /* Bypass Prescale R */
2523#define LAST_ALC_ENABLE (1 << 2) /* Last ALC Enable */
2524#define PRESCALE_BIAS(x) (((x) & 0x3) << 0) /* Prescale Bias <1:0> */
2525
2526/*
2527* REG_TX_CAL_STATUS
2528*/
2529#define CP_CAL_VALID (1 << 7) /* CP Cal Valid */
2530#define COMP_OUT (1 << 6) /* Comp Out */
2531#define CP_CAL_DONE (1 << 5) /* CP Cal Done */
2532#define VCO_CAL_BUSY (1 << 4) /* VCO Cal Busy */
2533#define CP_CAL_WORD(x) (((x) & 0xF) << 0) /* CP Cal Word<3:0> */
2534
2535/*
2536* REG_TX_VCO_CAL_REF
2537*/
2538#define VCO_CAL_REF_MONITOR (1 << 3) /* VCO Cal Ref Monitor */
2539#define VCO_CAL_REF_TCF(x) (((x) & 0x7) << 0) /* VCO Cal Ref Tcf<2:0> */
2540
2541/*
2542* REG_TX_VCO_PD_OVERRIDES
2543*/
2544#define POWER_DOWN_VARACTOR_REF (1 << 3) /* Power Down Varactor Ref */
2545#define POWER_DOWN_VARACT_REF_TCF (1 << 2) /* Power Down Varact Ref Tcf */
2546#define POWER_DOWN_CAL_TCF (1 << 1) /* Power Down Cal Tcf */
2547#define POWER_DOWN_VCO_BUFFFER (1 << 0) /* Power Down VCO Bufffer */
2548
2549/*
2550* REG_TX_CP_OVERRANGE_VCO_LOCK
2551*/
2552#define CP_OVRG_HIGH (1 << 7) /* CP Ovrg High */
2553#define CP_OVRG_LOW (1 << 6) /* CP Ovrg Low */
2554#define VCO_LOCK (1 << 1) /* Lock */
2555
2556/*
2557* REG_TX_VCO_LDO
2558*/
2559#define VCO_LDO_BYPASS (1 << 7) /* VCO LDO Bypass */
2560#define VCO_LDO_INRUSH(x) (((x) & 0x3) << 5) /* VCO LDO Inrush<1:0> */
2561#define VCO_LDO_VOUT_SEL(x) (((x) & 0x7) << 2) /* VCO LDO Vout Sel<2:0> */
2562#define VCO_LDO_VDROP_SEL(x) (((x) & 0x3) << 0) /* VCO LDO Vdrop Sel<1:0> */
2563
2564/*
2565* REG_TX_VCO_CAL
2566*/
2567#define VCO_CAL_EN (1 << 7) /* VCO Cal En */
2568#define VCO_CAL_ALC_WAIT(x) (((x) & 0x7) << 4) /* VCO Cal ALC Wait<2:0) */
2569#define VCO_CAL_COUNT(x) (((x) & 0x3) << 2) /* VCO Cal Count<1:0> */
2570#define FB_CLOCK_ADV(x) (((x) & 0x3) << 0) /* FB Clock Adv<1:0> */
2571
2572/*
2573* REG_TX_LOCK_DETECT_CONFIG
2574*/
2575#define LOCK_DETECT_COUNT(x) (((x) & 0x3) << 2) /* Lock Detect Count<1:0> */
2576#define LOCK_DETECT_MODE(x) (((x) & 0x3) << 0) /* Lock Detect Mode<1:0> */
2577
2578/*
2579* REG_TX_CP_LEVEL_DETECT
2580*/
2581#define CP_LEVEL_DETECT_POWER_DOWN (1 << 6) /* CP Level Detect Power Down */
2582#define CP_LEVEL_DETECT_THRESH_LOW(x) (((x) & 0x7) << 3) /* CP Level Detect Threshold Low<2:0> */
2583#define CP_LEVEL_DETECT_THRESH_HIGH(x) (((x) & 0x7) << 0) /* CP Level Detect Threshold High<2:0> */
2584
2585/*
2586* REG_TX_DSM_SETUP_0
2587*/
2588#define DSM_PROG(x) (((x) & 0xF) << 0) /* DSM Prog<3:0> */
2589
2590/*
2591* REG_TX_DSM_SETUP_1
2592*/
2593#define SIF_CLOCK (1 << 6) /* SIF clock */
2594#define SIF_RESET_BAR (1 << 5) /* SIF Reset Bar */
2595#define SIF_ADDR(x) (((x) & 0x1F) << 0) /* SIF Addr<4:0> */
2596
2597/*
2598* REG_TX_CORRECTION_WORD0
2599*/
2600#define UPDATE_FREQ_WORD (1 << 7) /* Update Freq Word */
2601#define READ_EFFECTIVE_TUNING_WORD (1 << 5) /* Read Effective Tuning Word */
2602#define FREQ_CORRECTION_WORD_MSB(x) (((x) & 0x1F) << 0) /* Frequency Correction Word<11:7> */
2603
2604/*
2605* REG_TX_CORRECTION_WORD1
2606*/
2607#define UPDATE_FREQ_WORD (1 << 7) /* Update Freq Word */
2608#define FREQ_CORRECTION_WORD_LSB(x) (((x) & 0x7F) << 0) /* Frequency Correction Word<6:0> */
2609
2610/*
2611* REG_TX_VCO_VARACTOR_CTRL_0
2612*/
2613#define VCO_VARACTOR_REFERENCE_TCF(x) (((x) & 0x7) << 4) /* VCO Varactor Reference Tcf<2:0> */
2614#define VCO_VARACTOR_OFFSET(x) (((x) & 0xF) << 0) /* VCO Varactor Offset<3:0> */
2615
2616/*
2617* REG_TX_VCO_VARACTOR_CTRL_1
2618*/
2619#define VCO_VARACTOR_REFERENCE(x) (((x) & 0xF) << 0) /* VCO Varactor Reference<3:0> */
2620
2621/*
2622* REG_DCXO_COARSE_TUNE
2623*/
2624#define DCXO_TUNE_COARSE(x) (((x) & 0x3F) << 0) /* DCXO Tune Coarse<5:0> */
2625
2626/*
2627* REG_DCXO_FINE_TUNE_LOW
2628*/
2629#define DCXO_TUNE_FINE_LOW(x) (((x) & 0x1F) << 3) /* DCXO Tune Fine<4:0> */
2630
2631/*
2632* REG_DCXO_FINE_TUNE_HIGH
2633*/
2634#define DCXO_TUNE_FINE_HIGH(x) ((x) >> 5) /* DCXO Tune Fine<12:5> */
2635
2636/*
2637* REG_DCXO_CONFIG
2638*/
2639#define MUST_BE_ZERO (1 << 7) /* Must be zero */
2640#define DCXO_RTAIL(x) (((x) & 0x7) << 4) /* DCXO Rtail<2:0> */
2641#define DCXO_RD(x) (((x) & 0x3) << 2) /* DCXO Rd<1:0> */
2642
2643/*
2644* REG_DCXO_TEMPCO_ADDR
2645*/
2646#define DCXO_TEMPCO_EN (1 << 7) /* DCXO Tempco En */
2647#define DCXO_TEMPCO_CLK (1 << 6) /* DCXO Tempco Clk */
2648#define DCXO_TEMPERATURE_COEF_ADDRESS(x) (((x) & 0x3F) << 0) /* DCXO Temperature Coefficient Address<5:0> */
2649
2650/*
2651* REG_TX_FAST_LOCK_SETUP
2652*/
2653#define TX_FAST_LOCK_LOAD_SYNTH (1 << 3) /* Tx Fast Lock Load Synth */
2654#define TX_FAST_LOCK_PROFILE_INIT (1 << 2) /* Tx Fast Lock Profile Init */
2655#define TX_FAST_LOCK_PROFILE_PIN_SELECT (1 << 1) /* Tx Fast Lock Profile Pin Select */
2656#define TX_FAST_LOCK_MODE_ENABLE (1 << 0) /* Tx Fast Lock Mode Enable */
2657#define TX_FAST_LOCK_PROFILE(x) (((x) & 0x7) << 5) /* Tx Fast Lock Profile<2:0> */
2658
2659/*
2660* REG_TX_FAST_LOCK_PROGRAM_CTRL
2661*/
2662#define TX_FAST_LOCK_PROGRAM_WRITE (1 << 1) /* Tx Fast Lock Program Write */
2663#define TX_FAST_LOCK_PROGRAM_CLOCK_ENABLE (1 << 0) /* Tx Fast Lock Program Clock Enable */
2664
2665/*
2666* REG_TX_LO_GEN_POWER_MODE
2667*/
2668#define TX_LO_GEN_POWER_MODE(x) (((x) & 0xF) << 4) /* Power Mode<3:0> */
2669
2670/*
2671* REG_BANDGAP_CONFIG0
2672*/
2673#define POWER_DOWN_BANDGAP_REF (1 << 7) /* Power Down Bandgap Ref */
2674#define MASTER_BIAS_FILTER_BYPASS (1 << 6) /* Master Bias Filter Bypass */
2675#define MASTER_BIAS_REF_SEL (1 << 5) /* Master Bias Ref Sel */
2676#define MASTER_BIAS_TRIM(x) (((x) & 0x1F) << 0) /* Master Bias Trim<4:0> */
2677
2678/*
2679* REG_BANDGAP_CONFIG1
2680*/
2681#define VCO_LDO_FILTER_BYPASS (1 << 7) /* VCO LDO Filter Bypass */
2682#define VCO_LDO_REF_SEL (1 << 6) /* VCO LDO Ref Sel */
2683#define BANDGAP_REF_RESET (1 << 5) /* Bandgap Ref Reset */
2684#define BANDGAP_TEMP_TRIM(x) (((x) & 0x1F) << 0) /* Bandgap Temp Trim<4:0> */
2685
2686/*
2687* REG_REF_DIVIDE_CONFIG_1
2688*/
2689#define REF_DIVIDE_CONFIG_1_DFLT (1 << 2) /* Set to 1 */
2690#define RX_REF_RESET_BAR (1 << 1) /* Rx Ref Reset Bar */
2691#define RX_REF_DIVIDER_MSB (1 << 0) /* Rx Ref Divider<1> */
2692
2693/*
2694* REG_REF_DIVIDE_CONFIG_2
2695*/
2696#define RX_REF_DIVIDER_LSB (1 << 7) /* Rx Ref Divider< 0> */
2697#define TX_REF_RESET_BAR (1 << 4) /* Tx Ref Reset Bar */
2698#define RX_REF_DOUBLER_FB_DELAY(x) (((x) & 0x3) << 5) /* Rx Ref Doubler FB Delay<1:0> */
2699#define TX_REF_DIVIDER(x) (((x) & 0x3) << 2) /* Tx Ref Divider<1:0> */
2700#define TX_REF_DOUBLER_FB_DELAY(x) (((x) & 0x3) << 0) /* Tx Ref Doubler FB Delay<1:0> */
2701
2702/*
2703* REG_GAIN_RX1,2
2704*/
2705#define FULL_TABLE_GAIN_INDEX(x) (((x) & 0x7F) << 0) /* Full Table Gain Index Rx1/LMT Gain Rx1<6:0> */
2706
2707/*
2708* REG_LPF_GAIN_RX1,2
2709*/
2710#define LPF_GAIN_RX(x) (((x) & 0x1F) << 0) /* LPF gain Rx1<4:0> */
2711
2712/*
2713* REG_DIG_GAIN_RX1,2
2714*/
2715#define DIGITAL_GAIN_RX(x) (((x) & 0x1F) << 0) /* Digital gain Rx1<4:0> */
2716
2717/*
2718* REG_FAST_ATTACK_STATE
2719*/
2720#define FAST_ATTACK_STATE_RX2(x) (((x) & 0x7) << 4) /* Fast Attack State Rx2<2:0> */
2721#define FAST_ATTACK_STATE_RX1(x) (((x) & 0x7) << 0) /* Fast Attack State Rx1<2:0> */
2722#define FAST_ATK_MASK 0x7
2723#define RX1_FAST_ATK_SHIFT 0
2724#define RX2_FAST_ATK_SHIFT 4
2725#define FAST_ATK_RESET 0
2726#define FAST_ATK_PEAK_DETECT 1
2727#define FAST_ATK_PWR_MEASURE 2
2728#define FAST_ATK_FINAL_SETTELING 3
2729#define FAST_ATK_FINAL_OVER 4
2730#define FAST_ATK_GAIN_LOCKED 5
2731
2732/*
2733* REG_SLOW_LOOP_STATE
2734*/
2735#define SLOW_LOOP_STATE_RX2(x) (((x) & 0x7) << 4) /* Slow Loop State Rx2<2:0> */
2736#define SLOW_LOOP_STATE_RX1(x) (((x) & 0x7) << 0) /* Slow Loop State Rx1<2:0> */
2737
2738
2739/*
2740* REG_OVRG_SIGS_RX1,2
2741*/
2742#define GAIN_LOCK_1 (1 << 6) /* Gain Lock 1 */
2743#define LOW_POWER_1 (1 << 5) /* Low Power 1 */
2744#define LARGE_LMT_OL (1 << 4) /* Large LMT OL */
2745#define SMALL_LMT_OL (1 << 3) /* Small LMT OL */
2746#define LARGE_ADC_OL (1 << 2) /* Large ADC OL */
2747#define SMALL_ADC_OL (1 << 1) /* Small ADC OL */
2748#define DIG_SAT (1 << 0) /* Dig Sat */
2749/*
2750* REG_CTRL
2751*/
2752#define CTRL_ENABLE (1 << 0) /* Set to 1 */
2753
2754/*
2755* REG_BIST_CONFIG
2756*/
2757#define TONE_PRBS (1 << 1) /* Tone/ PRBS */
2758#define BIST_ENABLE (1 << 0) /* BIST Enable */
2759#define TONE_FREQ(x) (((x) & 0x3) << 6) /* Tone Frequency<1:0> */
2760#define TONE_LEVEL(x) (((x) & 0x3) << 4) /* Tone Level<1:0> */
2761#define BIST_CTRL_POINT(x) (((x) & 0x3) << 2) /* BIST Control Point <1:0> */
2762
2763/*
2764* REG_OBSERVE_CONFIG
2765*/
2766#define DATA_PORT_SP_HD_LOOP_TEST_OE (1 << 7) /* Data Port SP, HD Loop Test OE */
2767#define RX_MASK (1 << 6) /* Rx Mask */
2768#define CHANNEL (1 << 5) /* Channel */
2769#define DATA_PORT_LOOP_TEST_ENABLE (1 << 0) /* Data Port Loop Test Enable */
2770#define OBSERVATION_POINT(x) (((x) & 0xF) << 1) /* Observation Point<2:0> */
2771
2772/*
2773* REG_BIST_AND_DATA_PORT_TEST_CONFIG
2774*/
2775#define BIST_MASK_CHANNEL_2_Q_DATA (1 << 5) /* BIST Mask Channel 2 Q data */
2776#define BIST_MASK_CHANNEL_2_I_DATA (1 << 4) /* BIST Mask Channel 2 I data */
2777#define BIST_MASK_CHANNEL_1_Q_DATA (1 << 3) /* BIST Mask Channel 1 Q data */
2778#define BIST_MASK_CHANNEL_1_I_DATA (1 << 2) /* BIST Mask Channel 1 I data */
2779#define DATA_PORT_HILOW (1 << 1) /* Data Port Hi/Low */
2780#define USE_DATA_PORT (1 << 0) /* Use Data Port */
2781#define TEMP_SENSE_VBE_TEST(x) (((x) & 0x3) << 6) /* Temp Sense Vbe Test<1:0> */
2782
2783/*
2784* REG_DAC_TEST_2
2785*/
2786#define DAC_TEST_ENABLE (1 << 7) /* DAC Test Enable */
2787#define DAC_TEST_WORD(x) (((x) & 0x7F) << 0) /* DAC test Word <22:16> */
2788
2789/*
2790* SPI Comm Helpers
2791*/
2792#define AD_READ (0 << 15)
2793#define AD_WRITE (1 << 15)
2794#define AD_CNT(x) ((((x) - 1) & 0x7) << 12)
2795#define AD_ADDR(x) ((x) & 0x3FF)
2796
2797
2798/*
2799* AD9361 Limits
2800*/
2801
2802#define RSSI_MULTIPLIER 100
2803#define RSSI_RESOLUTION ((int) (0.25 * RSSI_MULTIPLIER))
2804#define RSSI_MAX_WEIGHT 255
2805
2806#define MAX_LMT_INDEX 40
2807#define MAX_LPF_GAIN 24
2808#define MAX_DIG_GAIN 31
2809
2810#define MAX_BBPLL_FREF 70007000UL /* 70 MHz + 100ppm */
2811#define MIN_BBPLL_FREQ 714928500UL /* 715 MHz - 100ppm */
2812#define MAX_BBPLL_FREQ 1430143000UL /* 1430 MHz + 100ppm */
2813#define MAX_BBPLL_DIV 64
2814#define MIN_BBPLL_DIV 2
2815
2816/*
2817 * The ADC minimum and maximum operating output data rates
2818 * are 25MHz and 640MHz respectively.
2819 * For more information see here: https://ez.analog.com/docs/DOC-12763
2820 */
2821
2822#define MIN_ADC_CLK 25000000U /* 25 MHz */
2823//#define MIN_ADC_CLK (MIN_BBPLL_FREQ / MAX_BBPLL_DIV) /* 11.17MHz */
2824#define MAX_ADC_CLK 640000000U /* 640 MHz */
2825#define MAX_DAC_CLK (MAX_ADC_CLK / 2)
2826
2827/* Associated with outputs of stage */
2828#define MAX_RX_HB1 245760000UL
2829#define MAX_RX_HB2 320000000UL
2830#define MAX_RX_HB3 640000000UL
2831/* Associated with inputs of stage */
2832#define MAX_TX_HB1 160000000UL
2833#define MAX_TX_HB2 320000000UL
2834#define MAX_TX_HB3 320000000UL
2835
2836#define MAX_BASEBAND_RATE 61440000UL
2837
2838#define MAX_MBYTE_SPI 8
2839
2840#define RFPLL_MODULUS 8388593UL
2841#define BBPLL_MODULUS 2088960UL
2842
2843#define MAX_SYNTH_FREF 80008000UL /* 80 MHz + 100ppm */
2844#define MIN_SYNTH_FREF 9999000UL /* 10 MHz - 100ppm */
2845#define MIN_VCO_FREQ_HZ 6000000000ULL
2846#define MAX_CARRIER_FREQ_HZ 6000000000ULL
2847#define MIN_RX_CARRIER_FREQ_HZ 70000000ULL
2848#define MIN_TX_CARRIER_FREQ_HZ 46875001ULL
2849
2850#define AD9363A_MAX_CARRIER_FREQ_HZ 3800000000ULL
2851#define AD9363A_MIN_CARRIER_FREQ_HZ 325000000ULL
2852
2853#define MAX_TX_ATTENUATION_DB 89750
2854
2855/*
2856* Driver
2857*/
2858
2863
2870
2871struct gain_table_info {
2872 uint64_t start;
2873 uint64_t end;
2874 uint8_t max_index;
2875 uint8_t split_table;
2876 int8_t *abs_gain_tbl;
2877 uint8_t (*tab)[3];
2878};
2879
2880enum fir_dest {
2881 FIR_TX1 = 0x01,
2882 FIR_TX2 = 0x02,
2883 FIR_TX1_TX2 = 0x03,
2884 FIR_RX1 = 0x81,
2885 FIR_RX2 = 0x82,
2886 FIR_RX1_RX2 = 0x83,
2887 FIR_IS_RX = 0x80,
2888};
2889
2890struct rf_gain_ctrl {
2891 uint32_t ant;
2892 uint8_t mode;
2893};
2894
2901
2908
2909struct gain_control {
2910 enum rf_gain_ctrl_mode rx1_mode;
2911 enum rf_gain_ctrl_mode rx2_mode;
2912
2913 /* Common */
2914 uint8_t adc_ovr_sample_size; /* 1..8 Sum x samples, AGC_CONFIG_3 */
2915 uint8_t adc_small_overload_thresh; /* 0..255, 0x105 */
2916 uint8_t adc_large_overload_thresh; /* 0..255, 0x104 */
2917
2918 uint16_t lmt_overload_high_thresh; /* 16..800 mV, 0x107 */
2919 uint16_t lmt_overload_low_thresh; /* 16..800 mV, 0x108 */
2920 uint16_t dec_pow_measuremnt_duration; /* Samples, 0x15C */
2921 uint8_t low_power_thresh; /* -64..0 dBFS, 0x114 */
2922 bool use_rx_fir_out_for_dec_pwr_meas; /* clears 0x15C:6 USE_HB1_OUT_FOR_DEC_PWR_MEAS */
2923
2924 bool dig_gain_en; /* should be turned off, since ADI GT doesn't use dig gain */
2925 uint8_t max_dig_gain; /* 0..31 */
2926
2927 /* MGC */
2928 bool mgc_rx1_ctrl_inp_en; /* Enables Pin control on RX1 default SPI ctrl */
2929 bool mgc_rx2_ctrl_inp_en; /* Enables Pin control on RX2 default SPI ctrl */
2930
2931 uint8_t mgc_inc_gain_step; /* 1..8 */
2932 uint8_t mgc_dec_gain_step; /* 1..8 */
2933 uint8_t mgc_split_table_ctrl_inp_gain_mode; /* 0=AGC determine this, 1=only in LPF, 2=only in LMT */
2934
2935 /* AGC */
2936 uint8_t agc_attack_delay_extra_margin_us; /* 0..31 us */
2937
2938 uint8_t agc_outer_thresh_high;
2939 uint8_t agc_outer_thresh_high_dec_steps;
2940 uint8_t agc_inner_thresh_high;
2941 uint8_t agc_inner_thresh_high_dec_steps;
2942 uint8_t agc_inner_thresh_low;
2943 uint8_t agc_inner_thresh_low_inc_steps;
2944 uint8_t agc_outer_thresh_low;
2945 uint8_t agc_outer_thresh_low_inc_steps;
2946
2947 uint8_t adc_small_overload_exceed_counter; /* 0..15, 0x122 */
2948 uint8_t adc_large_overload_exceed_counter; /* 0..15, 0x122 */
2949 uint8_t adc_large_overload_inc_steps; /* 0..15, 0x106 */
2950
2951 bool adc_lmt_small_overload_prevent_gain_inc; /* 0x120 */
2952
2953 uint8_t lmt_overload_large_exceed_counter; /* 0..15, 0x121 */
2954 uint8_t lmt_overload_small_exceed_counter; /* 0..15, 0x121 */
2955 uint8_t lmt_overload_large_inc_steps; /* 0..7, 0x121 */
2956
2957 uint8_t dig_saturation_exceed_counter; /* 0..15, 0x128 */
2958 uint8_t dig_gain_step_size; /* 1..8, 0x100 */
2959 bool sync_for_gain_counter_en; /* 0x128:4 !Hybrid */
2960
2961 uint32_t gain_update_interval_us; /* in us */
2962 bool immed_gain_change_if_large_adc_overload; /* 0x123:3 */
2963 bool immed_gain_change_if_large_lmt_overload; /* 0x123:7 */
2964
2965 /*
2966 * Fast AGC
2967 */
2968 uint32_t f_agc_dec_pow_measuremnt_duration; /* Samples, 0x15C */
2969 uint32_t f_agc_state_wait_time_ns; /* 0x117 0..31 RX samples -> time_ns */
2970 /* Fast AGC - Low Power */
2971 bool f_agc_allow_agc_gain_increase; /* 0x110:1 */
2972 uint8_t f_agc_lp_thresh_increment_time; /* 0x11B RX samples */
2973 uint8_t f_agc_lp_thresh_increment_steps; /* 0x117 1..8 */
2974
2975 /* Fast AGC - Lock Level */
2976 uint8_t f_agc_lock_level; /* NOT USED: 0x101 0..-127 dBFS same as agc_inner_thresh_high */
2977 bool f_agc_lock_level_lmt_gain_increase_en; /* 0x111:6 */
2978 uint8_t f_agc_lock_level_gain_increase_upper_limit; /* 0x118 0..63 */
2979 /* Fast AGC - Peak Detectors and Final Settling */
2980 uint8_t f_agc_lpf_final_settling_steps; /* 0x112:6 0..3 (Post Lock Level Step)*/
2981 uint8_t f_agc_lmt_final_settling_steps; /* 0x113:6 0..3 (Post Lock Level Step)*/
2982 uint8_t f_agc_final_overrange_count; /* 0x116:5 0..7 */
2983 /* Fast AGC - Final Power Test */
2984 bool f_agc_gain_increase_after_gain_lock_en; /* 0x110:7 */
2985 /* Fast AGC - Unlocking the Gain */
2986 /* 0 = MAX Gain, 1 = Set Gain, 2 = Optimized Gain */
2987 enum f_agc_target_gain_index_type
2988 f_agc_gain_index_type_after_exit_rx_mode; /* 0x110:[4,2] */
2989 bool f_agc_use_last_lock_level_for_set_gain_en; /* 0x111:7 */
2990 uint8_t f_agc_optimized_gain_offset; /*0x116 0..15 steps */
2991 bool f_agc_rst_gla_stronger_sig_thresh_exceeded_en; /* 0x110:~6 */
2992 uint8_t f_agc_rst_gla_stronger_sig_thresh_above_ll; /*0x113 0..63 dbFS */
2993 bool f_agc_rst_gla_engergy_lost_sig_thresh_exceeded_en; /* 0x110:6 */
2994 bool f_agc_rst_gla_engergy_lost_goto_optim_gain_en; /* 0x110:6 */
2995 uint8_t f_agc_rst_gla_engergy_lost_sig_thresh_below_ll; /* 0x112:6 */
2996 uint8_t f_agc_energy_lost_stronger_sig_gain_lock_exit_cnt; /* 0x119 0..63 RX samples */
2997 bool f_agc_rst_gla_large_adc_overload_en; /*0x110:~1 and 0x114:~7 */
2998 bool f_agc_rst_gla_large_lmt_overload_en; /*0x110:~1 */
2999 bool f_agc_rst_gla_en_agc_pulled_high_en;
3000 /* 0 = Max Gain, 1 = Set Gain, 2 = Optimized Gain, 3 = No Gain Change */
3001
3002 enum f_agc_target_gain_index_type
3003 f_agc_rst_gla_if_en_agc_pulled_high_mode; /* 0x0FB, 0x111 */
3004 uint8_t f_agc_power_measurement_duration_in_state5; /* 0x109, 0x10a RX samples 0..524288*/
3005 uint8_t f_agc_large_overload_inc_steps; /* 0x106 [D6:D4] 0..7 */
3006};
3007
3027
3036
3037struct rssi_control {
3038 enum rssi_restart_mode restart_mode;
3039 bool rssi_unit_is_rx_samples; /* default unit is time */
3040 uint32_t rssi_delay;
3041 uint32_t rssi_wait;
3042 uint32_t rssi_duration;
3043};
3044
3053
3062
3063struct ctrl_outs_control {
3064 uint8_t index;
3065 uint8_t en_mask;
3066};
3067
3076
3085
3110
3124
3134
3144
3154
3155struct ad9361_phy_platform_data {
3156 bool rx2tx2;
3157 bool fdd;
3158 bool fdd_independent_mode;
3159 bool split_gt;
3160 bool use_extclk;
3161 bool ensm_pin_pulse_mode;
3162 bool ensm_pin_ctrl;
3163 bool debug_mode;
3164 bool tdd_use_dual_synth;
3165 bool tdd_skip_vco_cal;
3166 bool use_ext_rx_lo;
3167 bool use_ext_tx_lo;
3168 bool rx1rx2_phase_inversion_en;
3169 bool qec_tracking_slow_mode_en;
3170 uint8_t dc_offset_update_events;
3171 uint8_t dc_offset_attenuation_high;
3172 uint8_t dc_offset_attenuation_low;
3173 uint8_t rf_dc_offset_count_high;
3174 uint8_t rf_dc_offset_count_low;
3175 uint8_t dig_interface_tune_skipmode;
3176 uint8_t dig_interface_tune_fir_disable;
3177 uint8_t lo_powerdown_managed_en;
3178 uint32_t dcxo_coarse;
3179 uint32_t dcxo_fine;
3180 uint32_t rf_rx_input_sel;
3181 uint32_t rf_tx_output_sel;
3182 uint32_t rx1tx1_mode_use_rx_num;
3183 uint32_t rx1tx1_mode_use_tx_num;
3184 uint32_t rx_path_clks[NUM_RX_CLOCKS];
3185 uint32_t tx_path_clks[NUM_TX_CLOCKS];
3186 uint32_t trx_synth_max_fref;
3187 uint64_t rx_synth_freq;
3188 uint64_t tx_synth_freq;
3189 uint32_t rf_rx_bandwidth_Hz;
3190 uint32_t rf_tx_bandwidth_Hz;
3191 int32_t tx_atten;
3192 bool update_tx_gain_via_alert;
3193 uint32_t rx_fastlock_delay_ns;
3194 uint32_t tx_fastlock_delay_ns;
3195 bool trx_fastlock_pinctrl_en[2];
3196
3197 enum ad9361_clkout ad9361_clkout_mode;
3198
3199 struct gain_control gain_ctrl;
3200 struct rssi_control rssi_ctrl;
3201 struct port_control port_ctrl;
3202 struct ctrl_outs_control ctrl_outs_ctrl;
3203 struct elna_control elna_ctrl;
3204 struct auxadc_control auxadc_ctrl;
3205 struct auxdac_control auxdac_ctrl;
3206 struct gpo_control gpo_ctrl;
3207 struct tx_monitor_control txmon_ctrl;
3208};
3209
3210struct rf_rx_gain {
3211 uint32_t ant; /* Antenna number to read gain */
3212 int32_t gain_db; /* gain value in dB */
3213 uint32_t fgt_lmt_index; /* Full Gain Table / LNA-MIXER-TIA gain index */
3214 uint32_t lmt_gain; /* LNA-MIXER-TIA gain in dB (Split GT mode only)*/
3215 uint32_t lpf_gain; /* Low pass filter gain in dB / index (Split GT mode only)*/
3216 uint32_t digital_gain; /* Digital gain in dB / index */
3217 /* Debug only */
3218 uint32_t lna_index; /* LNA Index (Split GT mode only) */
3219 uint32_t tia_index; /* TIA Index (Split GT mode only) */
3220 uint32_t mixer_index; /* MIXER Index (Split GT mode only) */
3221
3222};
3223struct rf_rssi {
3224 uint32_t ant; /* Antenna number for which RSSI is reported */
3225 uint32_t symbol; /* Runtime RSSI */
3226 uint32_t preamble; /* Initial RSSI */
3227 int32_t multiplier; /* Multiplier to convert reported RSSI */
3228 uint8_t duration; /* Duration to be considered for measuring */
3229};
3230
3231struct SynthLUT {
3232 uint16_t VCO_MHz;
3233 uint8_t VCO_Output_Level;
3234 uint8_t VCO_Varactor;
3235 uint8_t VCO_Bias_Ref;
3236 uint8_t VCO_Bias_Tcf;
3237 uint8_t VCO_Cal_Offset;
3238 uint8_t VCO_Varactor_Reference;
3239 uint8_t Charge_Pump_Current;
3240 uint8_t LF_C2;
3241 uint8_t LF_C1;
3242 uint8_t LF_R1;
3243 uint8_t LF_C3;
3244 uint8_t LF_R3;
3245};
3246
3247enum {
3248 LUT_FTDD_40,
3249 LUT_FTDD_60,
3250 LUT_FTDD_80,
3251 LUT_FTDD_ENT,
3252};
3253
3278
3279struct ad9361_debugfs_entry {
3280 struct ad9361_rf_phy *phy;
3281 const char *propname;
3282 void *out_value;
3283 uint32_t val;
3284 uint8_t size;
3285 uint8_t cmd;
3286};
3287
3288struct ad9361_fastlock_entry {
3289#define FASTLOOK_INIT 1
3290 uint8_t flags;
3291 uint8_t alc_orig;
3292 uint8_t alc_written;
3293};
3294
3300
3309
3315
3321
3327
3328struct ad9361_rf_phy {
3329 enum dev_id dev_sel;
3330 struct no_os_spi_desc *spi;
3331 struct no_os_gpio_desc *gpio_desc_resetb;
3332 struct no_os_gpio_desc *gpio_desc_sync;
3333 struct no_os_gpio_desc *gpio_desc_cal_sw1;
3334 struct no_os_gpio_desc *gpio_desc_cal_sw2;
3335#ifndef AXI_ADC_NOT_PRESENT
3336 struct axi_adc *rx_adc;
3337 struct axi_dac *tx_dac;
3338#endif
3339 struct no_os_clk *clk_refin;
3340 struct no_os_clk *clks[NUM_AD9361_CLKS];
3341 struct refclk_scale *ref_clk_scale[NUM_AD9361_CLKS];
3342 uint32_t (*ad9361_rfpll_ext_recalc_rate)(struct refclk_scale *clk_priv);
3343 int32_t (*ad9361_rfpll_ext_round_rate)(struct refclk_scale *clk_priv,
3344 uint32_t rate);
3345 int32_t (*ad9361_rfpll_ext_set_rate)(struct refclk_scale *clk_priv,
3346 uint32_t rate);
3347 struct ad9361_phy_platform_data *pdata;
3348 uint8_t prev_ensm_state;
3349 uint8_t curr_ensm_state;
3350 uint8_t cached_rx_rfpll_div;
3351 uint8_t cached_tx_rfpll_div;
3352 uint8_t cached_synth_pd[2];
3353 int32_t tx_quad_lpf_tia_match;
3354 uint32_t current_table;
3355 struct gain_table_info *gt_info;
3356 bool ensm_pin_ctl_en;
3357
3358 bool auto_cal_en;
3359 bool manual_tx_quad_cal_en;
3360 uint64_t last_tx_quad_cal_freq;
3361 uint32_t last_tx_quad_cal_phase;
3362 uint64_t current_tx_lo_freq;
3363 uint64_t current_rx_lo_freq;
3364 bool current_tx_use_tdd_table;
3365 bool current_rx_use_tdd_table;
3366 uint32_t current_rx_path_clks[NUM_RX_CLOCKS];
3367 uint32_t current_tx_path_clks[NUM_TX_CLOCKS];
3368 uint32_t flags;
3369 uint32_t cal_threshold_freq;
3370 uint32_t current_rx_bw_Hz;
3371 uint32_t current_tx_bw_Hz;
3372 uint32_t rxbbf_div;
3373 uint32_t rate_governor;
3374 bool bypass_rx_fir;
3375 bool bypass_tx_fir;
3376 bool rx_eq_2tx;
3377 bool filt_valid;
3378 uint32_t filt_rx_path_clks[NUM_RX_CLOCKS];
3379 uint32_t filt_tx_path_clks[NUM_TX_CLOCKS];
3380 uint32_t filt_rx_bw_Hz;
3381 uint32_t filt_tx_bw_Hz;
3382 uint8_t tx_fir_int;
3383 uint8_t tx_fir_ntaps;
3384 uint8_t rx_fir_dec;
3385 uint8_t rx_fir_ntaps;
3386 uint8_t agc_mode[2];
3387 bool rfdc_track_en;
3388 bool bbdc_track_en;
3389 bool quad_track_en;
3390 bool txmon_tdd_en;
3391 uint16_t auxdac1_value;
3392 uint16_t auxdac2_value;
3393 uint32_t tx1_atten_cached;
3394 uint32_t tx2_atten_cached;
3395 struct ad9361_fastlock fastlock;
3396 struct axiadc_converter *adc_conv;
3397 struct axiadc_state *adc_state;
3398 int32_t bist_loopback_mode;
3399 int32_t bist_config;
3400 enum ad9361_bist_mode bist_prbs_mode;
3401 enum ad9361_bist_mode bist_tone_mode;
3402 uint32_t bist_tone_freq_Hz;
3403 uint32_t bist_tone_level_dB;
3404 uint32_t bist_tone_mask;
3405 bool bbpll_initialized;
3406};
3407
3416
3427
3428int32_t ad9361_spi_readm(struct no_os_spi_desc *spi, uint32_t reg,
3429 uint8_t *rbuf, uint32_t num);
3430int32_t ad9361_spi_read(struct no_os_spi_desc *spi, uint32_t reg);
3431int32_t ad9361_reg_read(struct ad9361_rf_phy *phy,
3432 uint32_t reg, uint32_t *val);
3433int32_t ad9361_spi_write(struct no_os_spi_desc *spi,
3434 uint32_t reg, uint32_t val);
3435int32_t ad9361_reg_write(struct ad9361_rf_phy *phy,
3436 uint32_t reg, uint32_t val);
3437int32_t ad9361_reset(struct ad9361_rf_phy *phy);
3438int32_t ad9361_register_clocks(struct ad9361_rf_phy *phy);
3439int32_t ad9361_unregister_clocks(struct ad9361_rf_phy *phy);
3440uint32_t ad9361_gt(struct ad9361_rf_phy *phy);
3441int32_t ad9361_init_gain_tables(struct ad9361_rf_phy *phy);
3442int32_t ad9361_setup(struct ad9361_rf_phy *phy);
3443int32_t ad9361_post_setup(struct ad9361_rf_phy *phy);
3444int32_t ad9361_set_ensm_mode(struct ad9361_rf_phy *phy, bool fdd, bool pinctrl);
3445int32_t ad9361_ensm_set_state(struct ad9361_rf_phy *phy, uint8_t ensm_state,
3446 bool pinctrl);
3447int32_t ad9361_set_rx_gain(struct ad9361_rf_phy *phy,
3448 uint32_t rx_id, struct rf_rx_gain *rx_gain);
3449int32_t ad9361_get_rx_gain(struct ad9361_rf_phy *phy,
3450 uint32_t rx_id, struct rf_rx_gain *rx_gain);
3451int32_t ad9361_update_rf_bandwidth(struct ad9361_rf_phy *phy,
3452 uint32_t rf_rx_bw, uint32_t rf_tx_bw);
3453int32_t ad9361_calculate_rf_clock_chain(struct ad9361_rf_phy *phy,
3454 uint32_t tx_sample_rate,
3455 uint32_t rate_gov,
3456 uint32_t *rx_path_clks,
3457 uint32_t *tx_path_clks);
3458int32_t ad9361_set_trx_clock_chain(struct ad9361_rf_phy *phy,
3459 uint32_t *rx_path_clks,
3460 uint32_t *tx_path_clks);
3461int32_t ad9361_get_trx_clock_chain(struct ad9361_rf_phy *phy,
3462 uint32_t *rx_path_clks,
3463 uint32_t *tx_path_clks);
3464uint32_t ad9361_to_clk(uint64_t freq);
3465uint64_t ad9361_from_clk(uint32_t freq);
3466int32_t ad9361_read_rssi(struct ad9361_rf_phy *phy, struct rf_rssi *rssi);
3467int32_t ad9361_set_gain_ctrl_mode(struct ad9361_rf_phy *phy,
3468 struct rf_gain_ctrl *gain_ctrl);
3469int32_t ad9361_load_fir_filter_coef(struct ad9361_rf_phy *phy,
3470 enum fir_dest dest, int32_t gain_dB,
3471 uint32_t ntaps, short *coef);
3472int32_t ad9361_validate_enable_fir(struct ad9361_rf_phy *phy);
3473int32_t ad9361_set_tx_atten(struct ad9361_rf_phy *phy, uint32_t atten_mdb,
3474 bool tx1, bool tx2, bool immed);
3475int32_t ad9361_get_tx_atten(struct ad9361_rf_phy *phy, uint32_t tx_num);
3476uint32_t ad9361_clk_factor_recalc_rate(struct refclk_scale *clk_priv,
3477 uint32_t parent_rate);
3478int32_t ad9361_clk_factor_round_rate(struct refclk_scale *clk_priv,
3479 uint32_t rate,
3480 uint32_t *prate);
3481int32_t ad9361_clk_factor_set_rate(struct refclk_scale *clk_priv, uint32_t rate,
3482 uint32_t parent_rate);
3483uint32_t ad9361_bbpll_recalc_rate(struct refclk_scale *clk_priv,
3484 uint32_t parent_rate);
3485int32_t ad9361_bbpll_round_rate(struct refclk_scale *clk_priv, uint32_t rate,
3486 uint32_t *prate);
3487int32_t ad9361_bbpll_set_rate(struct refclk_scale *clk_priv, uint32_t rate,
3488 uint32_t parent_rate);
3489uint32_t ad9361_rfpll_int_recalc_rate(struct refclk_scale *clk_priv,
3490 uint32_t parent_rate);
3491int32_t ad9361_rfpll_int_round_rate(struct refclk_scale *clk_priv,
3492 uint32_t rate,
3493 uint32_t *prate);
3494int32_t ad9361_rfpll_int_set_rate(struct refclk_scale *clk_priv, uint32_t rate,
3495 uint32_t parent_rate);
3496uint32_t ad9361_rfpll_dummy_recalc_rate(struct refclk_scale *clk_priv);
3497int32_t ad9361_rfpll_dummy_set_rate(struct refclk_scale *clk_priv,
3498 uint32_t rate);
3499uint32_t ad9361_rfpll_recalc_rate(struct refclk_scale *clk_priv);
3500int32_t ad9361_rfpll_round_rate(struct refclk_scale *clk_priv, uint32_t rate);
3501int32_t ad9361_rfpll_set_rate(struct refclk_scale *clk_priv, uint32_t rate);
3502int32_t ad9361_clk_mux_set_parent(struct refclk_scale *clk_priv, uint8_t index);
3503int32_t ad9361_tracking_control(struct ad9361_rf_phy *phy, bool bbdc_track,
3504 bool rfdc_track, bool rxquad_track);
3505int32_t ad9361_bist_loopback(struct ad9361_rf_phy *phy, int32_t mode);
3506void ad9361_get_bist_loopback(struct ad9361_rf_phy *phy, int32_t *mode);
3507int32_t ad9361_bist_prbs(struct ad9361_rf_phy *phy, enum ad9361_bist_mode mode);
3508void ad9361_get_bist_prbs(struct ad9361_rf_phy *phy,
3509 enum ad9361_bist_mode *mode);
3510int32_t ad9361_bist_tone(struct ad9361_rf_phy *phy,
3511 enum ad9361_bist_mode mode, uint32_t freq_Hz,
3512 uint32_t level_dB, uint32_t mask);
3513void ad9361_get_bist_tone(struct ad9361_rf_phy *phy,
3514 enum ad9361_bist_mode *mode, uint32_t *freq_Hz,
3515 uint32_t *level_dB, uint32_t *mask);
3516int32_t ad9361_rf_port_setup(struct ad9361_rf_phy *phy, bool is_out,
3517 uint32_t rx_inputs, uint32_t txb);
3518int32_t ad9361_mcs(struct ad9361_rf_phy *phy, int32_t step);
3519int32_t ad9361_do_calib_run(struct ad9361_rf_phy *phy, uint32_t cal,
3520 int32_t arg);
3521int32_t ad9361_fastlock_store(struct ad9361_rf_phy *phy, bool tx,
3522 uint32_t profile);
3523int32_t ad9361_fastlock_recall(struct ad9361_rf_phy *phy, bool tx,
3524 uint32_t profile);
3525int32_t ad9361_fastlock_load(struct ad9361_rf_phy *phy, bool tx,
3526 uint32_t profile, uint8_t *values);
3527int32_t ad9361_fastlock_save(struct ad9361_rf_phy *phy, bool tx,
3528 uint32_t profile, uint8_t *values);
3529void ad9361_ensm_force_state(struct ad9361_rf_phy *phy, uint8_t ensm_state);
3530uint8_t ad9361_ensm_get_state(struct ad9361_rf_phy *phy);
3531void ad9361_ensm_restore_state(struct ad9361_rf_phy *phy, uint8_t ensm_state);
3532void ad9361_ensm_restore_prev_state(struct ad9361_rf_phy *phy);
3533int32_t ad9361_set_trx_clock_chain_freq(struct ad9361_rf_phy *phy,
3534 uint32_t freq);
3535int32_t ad9361_find_opt(uint8_t *field, uint32_t size, uint32_t *ret_start);
3536int32_t ad9361_hdl_loopback(struct ad9361_rf_phy *phy, bool enable);
3537int32_t ad9361_dig_interface_timing_analysis(struct ad9361_rf_phy *phy,
3538 char *buf, int32_t buflen);
3539int32_t ad9361_dig_tune(struct ad9361_rf_phy *phy, uint32_t max_freq,
3540 enum dig_tune_flags flags);
3541int32_t ad9361_en_dis_tx(struct ad9361_rf_phy *phy, uint32_t tx_if,
3542 uint32_t enable);
3543int32_t ad9361_en_dis_rx(struct ad9361_rf_phy *phy, uint32_t rx_if,
3544 uint32_t enable);
3545int32_t ad9361_1rx1tx_channel_map(struct ad9361_rf_phy *phy, bool tx,
3546 int32_t channel);
3547int32_t ad9361_rssi_gain_step_calib(struct ad9361_rf_phy *phy);
3548int32_t ad9361_set_dcxo_tune(struct ad9361_rf_phy *phy,
3549 uint32_t coarse, uint32_t fine);
3550int32_t ad9361_tx_mute(struct ad9361_rf_phy *phy, uint32_t state);
3551uint32_t ad9361_validate_rf_bw(struct ad9361_rf_phy *phy, uint32_t bw);
3552int32_t ad9361_get_temp(struct ad9361_rf_phy *phy);
3553int ad9361_synth_lo_powerdown(struct ad9361_rf_phy *phy,
3554 enum synth_pd_ctrl rx,
3555 enum synth_pd_ctrl tx);
3556void ad9361_clear_state(struct ad9361_rf_phy *phy);
3557#endif
CLKOUT_DISABLE
@ CLKOUT_DISABLE
Definition ad5758.h:281
ad9361_fastlock_load
int32_t ad9361_fastlock_load(struct ad9361_rf_phy *phy, bool tx, uint32_t profile, uint8_t *values)
Definition ad9361.c:4986
ad9361_bist_mode
ad9361_bist_mode
Definition ad9361.h:3310
BIST_DISABLE
@ BIST_DISABLE
Definition ad9361.h:3311
BIST_INJ_TX
@ BIST_INJ_TX
Definition ad9361.h:3312
BIST_INJ_RX
@ BIST_INJ_RX
Definition ad9361.h:3313
ad9361_rfpll_set_rate
int32_t ad9361_rfpll_set_rate(struct refclk_scale *clk_priv, uint32_t rate)
Definition ad9361.c:7081
ad9361_pdata_rx_freq
ad9361_pdata_rx_freq
Definition ad9361.h:3125
R2_FREQ
@ R2_FREQ
Definition ad9361.h:3128
R1_FREQ
@ R1_FREQ
Definition ad9361.h:3129
RX_SAMPL_FREQ
@ RX_SAMPL_FREQ
Definition ad9361.h:3131
ADC_FREQ
@ ADC_FREQ
Definition ad9361.h:3127
NUM_RX_CLOCKS
@ NUM_RX_CLOCKS
Definition ad9361.h:3132
CLKRF_FREQ
@ CLKRF_FREQ
Definition ad9361.h:3130
BBPLL_FREQ
@ BBPLL_FREQ
Definition ad9361.h:3126
ad9361_get_bist_prbs
void ad9361_get_bist_prbs(struct ad9361_rf_phy *phy, enum ad9361_bist_mode *mode)
Definition ad9361.c:1207
ad9361_tracking_control
int32_t ad9361_tracking_control(struct ad9361_rf_phy *phy, bool bbdc_track, bool rfdc_track, bool rxquad_track)
Definition ad9361.c:3305
ad9361_read_rssi
int32_t ad9361_read_rssi(struct ad9361_rf_phy *phy, struct rf_rssi *rssi)
Definition ad9361.c:2441
ad9361_ensm_get_state
uint8_t ad9361_ensm_get_state(struct ad9361_rf_phy *phy)
Definition ad9361.c:1967
ad9361_reset
int32_t ad9361_reset(struct ad9361_rf_phy *phy)
Definition ad9361.c:1036
ad9361_set_tx_atten
int32_t ad9361_set_tx_atten(struct ad9361_rf_phy *phy, uint32_t atten_mdb, bool tx1, bool tx2, bool immed)
Definition ad9361.c:1633
ad9361_rfpll_dummy_set_rate
int32_t ad9361_rfpll_dummy_set_rate(struct refclk_scale *clk_priv, uint32_t rate)
Definition ad9361.c:6982
ad9361_from_clk
uint64_t ad9361_from_clk(uint32_t freq)
Definition ad9361.c:1394
ad9361_rssi_gain_step_calib
int32_t ad9361_rssi_gain_step_calib(struct ad9361_rf_phy *phy)
Definition ad9361.c:7410
ad9361_rfpll_int_recalc_rate
uint32_t ad9361_rfpll_int_recalc_rate(struct refclk_scale *clk_priv, uint32_t parent_rate)
Definition ad9361.c:6765
ad9361_bbpll_round_rate
int32_t ad9361_bbpll_round_rate(struct refclk_scale *clk_priv, uint32_t rate, uint32_t *prate)
Definition ad9361.c:6586
ad9361_dig_tune
int32_t ad9361_dig_tune(struct ad9361_rf_phy *phy, uint32_t max_freq, enum dig_tune_flags flags)
Definition ad9361_conv.c:512
ad9361_reg_read
int32_t ad9361_reg_read(struct ad9361_rf_phy *phy, uint32_t reg, uint32_t *val)
Definition ad9361.c:748
ad9361_bist_prbs
int32_t ad9361_bist_prbs(struct ad9361_rf_phy *phy, enum ad9361_bist_mode mode)
Definition ad9361.c:1177
ad9361_reg_write
int32_t ad9361_reg_write(struct ad9361_rf_phy *phy, uint32_t reg, uint32_t val)
Definition ad9361.c:837
ad9361_spi_readm
int32_t ad9361_spi_readm(struct no_os_spi_desc *spi, uint32_t reg, uint8_t *rbuf, uint32_t num)
Definition ad9361.c:688
dig_tune_flags
dig_tune_flags
Definition ad9361.h:3301
RESTORE_DEFAULT
@ RESTORE_DEFAULT
Definition ad9361.h:3307
DO_ODELAY
@ DO_ODELAY
Definition ad9361.h:3305
BE_VERBOSE
@ BE_VERBOSE
Definition ad9361.h:3302
SKIP_STORE_RESULT
@ SKIP_STORE_RESULT
Definition ad9361.h:3306
BE_MOREVERBOSE
@ BE_MOREVERBOSE
Definition ad9361.h:3303
DO_IDELAY
@ DO_IDELAY
Definition ad9361.h:3304
ad9361_ensm_restore_state
void ad9361_ensm_restore_state(struct ad9361_rf_phy *phy, uint8_t ensm_state)
Definition ad9361.c:2058
ad9361_pdata_tx_freq
ad9361_pdata_tx_freq
Definition ad9361.h:3135
DAC_FREQ
@ DAC_FREQ
Definition ad9361.h:3137
T1_FREQ
@ T1_FREQ
Definition ad9361.h:3139
IGNORE
@ IGNORE
Definition ad9361.h:3136
CLKTF_FREQ
@ CLKTF_FREQ
Definition ad9361.h:3140
T2_FREQ
@ T2_FREQ
Definition ad9361.h:3138
TX_SAMPL_FREQ
@ TX_SAMPL_FREQ
Definition ad9361.h:3141
NUM_TX_CLOCKS
@ NUM_TX_CLOCKS
Definition ad9361.h:3142
ad9361_do_calib_run
int32_t ad9361_do_calib_run(struct ad9361_rf_phy *phy, uint32_t cal, int32_t arg)
Definition ad9361.c:5664
rf_gain_ctrl_mode
rf_gain_ctrl_mode
Definition ad9361.h:2895
RF_GAIN_MGC
@ RF_GAIN_MGC
Definition ad9361.h:2896
RF_GAIN_SLOWATTACK_AGC
@ RF_GAIN_SLOWATTACK_AGC
Definition ad9361.h:2898
RF_GAIN_HYBRID_AGC
@ RF_GAIN_HYBRID_AGC
Definition ad9361.h:2899
RF_GAIN_FASTATTACK_AGC
@ RF_GAIN_FASTATTACK_AGC
Definition ad9361.h:2897
ad9361_calculate_rf_clock_chain
int32_t ad9361_calculate_rf_clock_chain(struct ad9361_rf_phy *phy, uint32_t tx_sample_rate, uint32_t rate_gov, uint32_t *rx_path_clks, uint32_t *tx_path_clks)
Definition ad9361.c:4754
ad9361_clkout
ad9361_clkout
Definition ad9361.h:3145
ADC_CLK_DIV_3
@ ADC_CLK_DIV_3
Definition ad9361.h:3149
ADC_CLK_DIV_16
@ ADC_CLK_DIV_16
Definition ad9361.h:3152
ADC_CLK_DIV_8
@ ADC_CLK_DIV_8
Definition ad9361.h:3151
ADC_CLK_DIV_2
@ ADC_CLK_DIV_2
Definition ad9361.h:3148
BUFFERED_XTALN_DCXO
@ BUFFERED_XTALN_DCXO
Definition ad9361.h:3147
ADC_CLK_DIV_4
@ ADC_CLK_DIV_4
Definition ad9361.h:3150
ad9361_unregister_clocks
int32_t ad9361_unregister_clocks(struct ad9361_rf_phy *phy)
Definition ad9361.c:7390
ad9361_set_trx_clock_chain_freq
int32_t ad9361_set_trx_clock_chain_freq(struct ad9361_rf_phy *phy, uint32_t freq)
Definition ad9361.c:4876
ad9361_rfpll_int_round_rate
int32_t ad9361_rfpll_int_round_rate(struct refclk_scale *clk_priv, uint32_t rate, uint32_t *prate)
Definition ad9361.c:6821
ad9361_rfpll_int_set_rate
int32_t ad9361_rfpll_int_set_rate(struct refclk_scale *clk_priv, uint32_t rate, uint32_t parent_rate)
Definition ad9361.c:6850
ad9361_ensm_set_state
int32_t ad9361_ensm_set_state(struct ad9361_rf_phy *phy, uint8_t ensm_state, bool pinctrl)
Definition ad9361.c:4422
ad9361_rfpll_dummy_recalc_rate
uint32_t ad9361_rfpll_dummy_recalc_rate(struct refclk_scale *clk_priv)
Definition ad9361.c:6969
ad9361_tx_mute
int32_t ad9361_tx_mute(struct ad9361_rf_phy *phy, uint32_t state)
Definition ad9361.c:1697
ad9361_spi_write
int32_t ad9361_spi_write(struct no_os_spi_desc *spi, uint32_t reg, uint32_t val)
Definition ad9361.c:805
ad9361_find_opt
int32_t ad9361_find_opt(uint8_t *field, uint32_t size, uint32_t *ret_start)
Definition ad9361.c:976
ad9361_register_clocks
int32_t ad9361_register_clocks(struct ad9361_rf_phy *phy)
Definition ad9361.c:7275
ad9361_gt
uint32_t ad9361_gt(struct ad9361_rf_phy *phy)
Definition ad9361.c:1367
ad9361_mcs
int32_t ad9361_mcs(struct ad9361_rf_phy *phy, int32_t step)
Definition ad9361.c:5237
ad9361_get_rx_gain
int32_t ad9361_get_rx_gain(struct ad9361_rf_phy *phy, uint32_t rx_id, struct rf_rx_gain *rx_gain)
Definition ad9361.c:1901
ad9361_clear_state
void ad9361_clear_state(struct ad9361_rf_phy *phy)
Definition ad9361.c:5291
ad9361_get_temp
int32_t ad9361_get_temp(struct ad9361_rf_phy *phy)
Definition ad9361.c:4202
ad9361_hdl_loopback
int32_t ad9361_hdl_loopback(struct ad9361_rf_phy *phy, bool enable)
Definition ad9361_conv.c:101
ad9361_rfpll_recalc_rate
uint32_t ad9361_rfpll_recalc_rate(struct refclk_scale *clk_priv)
Definition ad9361.c:6997
ad9361_post_setup
int32_t ad9361_post_setup(struct ad9361_rf_phy *phy)
Definition ad9361_conv.c:592
ad9361_get_tx_atten
int32_t ad9361_get_tx_atten(struct ad9361_rf_phy *phy, uint32_t tx_num)
Definition ad9361.c:1672
ad9361_get_trx_clock_chain
int32_t ad9361_get_trx_clock_chain(struct ad9361_rf_phy *phy, uint32_t *rx_path_clks, uint32_t *tx_path_clks)
Definition ad9361.c:4716
ad9361_get_bist_tone
void ad9361_get_bist_tone(struct ad9361_rf_phy *phy, enum ad9361_bist_mode *mode, uint32_t *freq_Hz, uint32_t *level_dB, uint32_t *mask)
Definition ad9361.c:1279
ad9361_update_rf_bandwidth
int32_t ad9361_update_rf_bandwidth(struct ad9361_rf_phy *phy, uint32_t rf_rx_bw, uint32_t rf_tx_bw)
Definition ad9361.c:5705
f_agc_target_gain_index_type
f_agc_target_gain_index_type
Definition ad9361.h:2902
SET_GAIN
@ SET_GAIN
Definition ad9361.h:2904
NO_GAIN_CHANGE
@ NO_GAIN_CHANGE
Definition ad9361.h:2906
OPTIMIZED_GAIN
@ OPTIMIZED_GAIN
Definition ad9361.h:2905
MAX_GAIN
@ MAX_GAIN
Definition ad9361.h:2903
ad9361_clk_factor_recalc_rate
uint32_t ad9361_clk_factor_recalc_rate(struct refclk_scale *clk_priv, uint32_t parent_rate)
Definition ad9361.c:6476
ad9361_fastlock_save
int32_t ad9361_fastlock_save(struct ad9361_rf_phy *phy, bool tx, uint32_t profile, uint8_t *values)
Definition ad9361.c:5217
ad9361_set_rx_gain
int32_t ad9361_set_rx_gain(struct ad9361_rf_phy *phy, uint32_t rx_id, struct rf_rx_gain *rx_gain)
Definition ad9361.c:2213
ad9361_bbpll_set_rate
int32_t ad9361_bbpll_set_rate(struct refclk_scale *clk_priv, uint32_t rate, uint32_t parent_rate)
Definition ad9361.c:6626
ad9361_validate_rf_bw
uint32_t ad9361_validate_rf_bw(struct ad9361_rf_phy *phy, uint32_t bw)
Definition ad9361.c:934
ad9361_get_bist_loopback
void ad9361_get_bist_loopback(struct ad9361_rf_phy *phy, int32_t *mode)
Definition ad9361.c:1166
rssi_restart_mode
rssi_restart_mode
Definition ad9361.h:3028
AGC_IN_FAST_ATTACK_MODE_LOCKS_THE_GAIN
@ AGC_IN_FAST_ATTACK_MODE_LOCKS_THE_GAIN
Definition ad9361.h:3029
ENTERS_RX_MODE
@ ENTERS_RX_MODE
Definition ad9361.h:3031
SPI_WRITE_TO_REGISTER
@ SPI_WRITE_TO_REGISTER
Definition ad9361.h:3033
GAIN_CHANGE_OCCURS_OR_EN_AGC_PIN_PULLED_HIGH
@ GAIN_CHANGE_OCCURS_OR_EN_AGC_PIN_PULLED_HIGH
Definition ad9361.h:3034
EN_AGC_PIN_IS_PULLED_HIGH
@ EN_AGC_PIN_IS_PULLED_HIGH
Definition ad9361.h:3030
GAIN_CHANGE_OCCURS
@ GAIN_CHANGE_OCCURS
Definition ad9361.h:3032
LUT_FTDD_40
@ LUT_FTDD_40
Definition ad9361.h:3248
LUT_FTDD_60
@ LUT_FTDD_60
Definition ad9361.h:3249
LUT_FTDD_80
@ LUT_FTDD_80
Definition ad9361.h:3250
LUT_FTDD_ENT
@ LUT_FTDD_ENT
Definition ad9361.h:3251
ad9361_clocks
ad9361_clocks
Definition ad9361.h:3254
RX_RFPLL
@ RX_RFPLL
Definition ad9361.h:3273
CLKTF_CLK
@ CLKTF_CLK
Definition ad9361.h:3267
T2_CLK
@ T2_CLK
Definition ad9361.h:3265
R1_CLK
@ R1_CLK
Definition ad9361.h:3261
RX_RFPLL_DUMMY
@ RX_RFPLL_DUMMY
Definition ad9361.h:3271
DAC_CLK
@ DAC_CLK
Definition ad9361.h:3264
TX_RFPLL_INT
@ TX_RFPLL_INT
Definition ad9361.h:3270
TX_RFPLL
@ TX_RFPLL
Definition ad9361.h:3274
TX_REFCLK
@ TX_REFCLK
Definition ad9361.h:3257
NUM_AD9361_CLKS
@ NUM_AD9361_CLKS
Definition ad9361.h:3275
R2_CLK
@ R2_CLK
Definition ad9361.h:3260
BB_REFCLK
@ BB_REFCLK
Definition ad9361.h:3255
RX_RFPLL_INT
@ RX_RFPLL_INT
Definition ad9361.h:3269
CLKRF_CLK
@ CLKRF_CLK
Definition ad9361.h:3262
T1_CLK
@ T1_CLK
Definition ad9361.h:3266
RX_SAMPL_CLK
@ RX_SAMPL_CLK
Definition ad9361.h:3263
EXT_REF_CLK
@ EXT_REF_CLK
Definition ad9361.h:3276
ADC_CLK
@ ADC_CLK
Definition ad9361.h:3259
BBPLL_CLK
@ BBPLL_CLK
Definition ad9361.h:3258
TX_SAMPL_CLK
@ TX_SAMPL_CLK
Definition ad9361.h:3268
TX_RFPLL_DUMMY
@ TX_RFPLL_DUMMY
Definition ad9361.h:3272
RX_REFCLK
@ RX_REFCLK
Definition ad9361.h:3256
ad9361_bbpll_recalc_rate
uint32_t ad9361_bbpll_recalc_rate(struct refclk_scale *clk_priv, uint32_t parent_rate)
Definition ad9361.c:6559
ad9361_clk_factor_round_rate
int32_t ad9361_clk_factor_round_rate(struct refclk_scale *clk_priv, uint32_t rate, uint32_t *prate)
Definition ad9361.c:6494
ad9361_load_fir_filter_coef
int32_t ad9361_load_fir_filter_coef(struct ad9361_rf_phy *phy, enum fir_dest dest, int32_t gain_dB, uint32_t ntaps, short *coef)
ad9361_to_clk
uint32_t ad9361_to_clk(uint64_t freq)
Definition ad9361.c:1383
ad9361_setup
int32_t ad9361_setup(struct ad9361_rf_phy *phy)
Definition ad9361.c:5350
rx_gain_table_type
rx_gain_table_type
Definition ad9361.h:2859
RXGAIN_SPLIT_TBL
@ RXGAIN_SPLIT_TBL
Definition ad9361.h:2861
RXGAIN_FULL_TBL
@ RXGAIN_FULL_TBL
Definition ad9361.h:2860
ad9361_rfpll_round_rate
int32_t ad9361_rfpll_round_rate(struct refclk_scale *clk_priv, uint32_t rate)
Definition ad9361.c:7039
ad9361_1rx1tx_channel_map
int32_t ad9361_1rx1tx_channel_map(struct ad9361_rf_phy *phy, bool tx, int32_t channel)
Definition ad9361.c:1012
ad9361_synth_lo_powerdown
int ad9361_synth_lo_powerdown(struct ad9361_rf_phy *phy, enum synth_pd_ctrl rx, enum synth_pd_ctrl tx)
Definition ad9361.c:3456
ad9361_ensm_restore_prev_state
void ad9361_ensm_restore_prev_state(struct ad9361_rf_phy *phy)
Definition ad9361.c:2112
ad9361_clk_mux_set_parent
int32_t ad9361_clk_mux_set_parent(struct refclk_scale *clk_priv, uint8_t index)
Definition ad9361.c:7138
ad9361_clk_factor_set_rate
int32_t ad9361_clk_factor_set_rate(struct refclk_scale *clk_priv, uint32_t rate, uint32_t parent_rate)
Definition ad9361.c:6528
ad9361_set_dcxo_tune
int32_t ad9361_set_dcxo_tune(struct ad9361_rf_phy *phy, uint32_t coarse, uint32_t fine)
Definition ad9361.c:3511
fir_dest
fir_dest
Definition ad9361.h:2880
FIR_IS_RX
@ FIR_IS_RX
Definition ad9361.h:2887
FIR_TX1
@ FIR_TX1
Definition ad9361.h:2881
FIR_TX2
@ FIR_TX2
Definition ad9361.h:2882
FIR_RX1_RX2
@ FIR_RX1_RX2
Definition ad9361.h:2886
FIR_TX1_TX2
@ FIR_TX1_TX2
Definition ad9361.h:2883
FIR_RX2
@ FIR_RX2
Definition ad9361.h:2885
FIR_RX1
@ FIR_RX1
Definition ad9361.h:2884
ad9361_fastlock_recall
int32_t ad9361_fastlock_recall(struct ad9361_rf_phy *phy, bool tx, uint32_t profile)
Definition ad9361.c:5161
ad9361_dig_interface_timing_analysis
int32_t ad9361_dig_interface_timing_analysis(struct ad9361_rf_phy *phy, char *buf, int32_t buflen)
Definition ad9361_conv.c:275
ad9361_en_dis_tx
int32_t ad9361_en_dis_tx(struct ad9361_rf_phy *phy, uint32_t tx_if, uint32_t enable)
Definition ad9361.c:1067
ad9361_set_ensm_mode
int32_t ad9361_set_ensm_mode(struct ad9361_rf_phy *phy, bool fdd, bool pinctrl)
Definition ad9361.c:4896
dev_id
dev_id
Definition ad9361.h:3322
ID_AD9364
@ ID_AD9364
Definition ad9361.h:3324
ID_AD9363A
@ ID_AD9363A
Definition ad9361.h:3325
ID_AD9361
@ ID_AD9361
Definition ad9361.h:3323
ad9361_set_gain_ctrl_mode
int32_t ad9361_set_gain_ctrl_mode(struct ad9361_rf_phy *phy, struct rf_gain_ctrl *gain_ctrl)
Definition ad9361.c:2366
ad9361_bist_loopback
int32_t ad9361_bist_loopback(struct ad9361_rf_phy *phy, int32_t mode)
Definition ad9361.c:1119
rx_gain_table_name
rx_gain_table_name
Definition ad9361.h:2864
TBL_1300_4000_MHZ
@ TBL_1300_4000_MHZ
Definition ad9361.h:2866
TBL_4000_6000_MHZ
@ TBL_4000_6000_MHZ
Definition ad9361.h:2867
RXGAIN_TBLS_END
@ RXGAIN_TBLS_END
Definition ad9361.h:2868
TBL_200_1300_MHZ
@ TBL_200_1300_MHZ
Definition ad9361.h:2865
ad9361_en_dis_rx
int32_t ad9361_en_dis_rx(struct ad9361_rf_phy *phy, uint32_t rx_if, uint32_t enable)
Definition ad9361.c:1084
ad9361_spi_read
int32_t ad9361_spi_read(struct no_os_spi_desc *spi, uint32_t reg)
Definition ad9361.c:729
ad9361_init_gain_tables
int32_t ad9361_init_gain_tables(struct ad9361_rf_phy *phy)
ad9361_set_trx_clock_chain
int32_t ad9361_set_trx_clock_chain(struct ad9361_rf_phy *phy, uint32_t *rx_path_clks, uint32_t *tx_path_clks)
Definition ad9361.c:4628
ad9361_rf_port_setup
int32_t ad9361_rf_port_setup(struct ad9361_rf_phy *phy, bool is_out, uint32_t rx_inputs, uint32_t txb)
Definition ad9361.c:3625
debugfs_cmd
debugfs_cmd
Definition ad9361.h:3417
DBGFS_BIST_PRBS
@ DBGFS_BIST_PRBS
Definition ad9361.h:3421
DBGFS_BIST_TONE
@ DBGFS_BIST_TONE
Definition ad9361.h:3422
DBGFS_BIST_DT_ANALYSIS
@ DBGFS_BIST_DT_ANALYSIS
Definition ad9361.h:3423
DBGFS_RXGAIN_1
@ DBGFS_RXGAIN_1
Definition ad9361.h:3424
DBGFS_LOOPBACK
@ DBGFS_LOOPBACK
Definition ad9361.h:3420
DBGFS_RXGAIN_2
@ DBGFS_RXGAIN_2
Definition ad9361.h:3425
DBGFS_NONE
@ DBGFS_NONE
Definition ad9361.h:3418
DBGFS_INIT
@ DBGFS_INIT
Definition ad9361.h:3419
ad9361_ensm_force_state
void ad9361_ensm_force_state(struct ad9361_rf_phy *phy, uint8_t ensm_state)
Definition ad9361.c:1979
ad9361_validate_enable_fir
int32_t ad9361_validate_enable_fir(struct ad9361_rf_phy *phy)
Definition ad9361.c:6072
ad9361_fastlock_store
int32_t ad9361_fastlock_store(struct ad9361_rf_phy *phy, bool tx, uint32_t profile)
Definition ad9361.c:5029
synth_pd_ctrl
synth_pd_ctrl
Definition ad9361.h:3316
LO_ON
@ LO_ON
Definition ad9361.h:3319
LO_DONTCARE
@ LO_DONTCARE
Definition ad9361.h:3317
LO_OFF
@ LO_OFF
Definition ad9361.h:3318
ad9361_bist_tone
int32_t ad9361_bist_tone(struct ad9361_rf_phy *phy, enum ad9361_bist_mode mode, uint32_t freq_Hz, uint32_t level_dB, uint32_t mask)
Definition ad9361.c:1222
profile
CUSTOM_FILE profile
Definition no_os_platform.c:29
spi
struct no_os_spi_desc * spi
Definition main.c:72
common.h
Header file of Common Driver.
no_os_gpio.h
Header file of GPIO Interface.
SynthLUT
Definition ad9361.h:3231
SynthLUT::VCO_Output_Level
uint8_t VCO_Output_Level
Definition ad9361.h:3233
SynthLUT::LF_R1
uint8_t LF_R1
Definition ad9361.h:3242
SynthLUT::VCO_Cal_Offset
uint8_t VCO_Cal_Offset
Definition ad9361.h:3237
SynthLUT::VCO_Bias_Ref
uint8_t VCO_Bias_Ref
Definition ad9361.h:3235
SynthLUT::LF_C3
uint8_t LF_C3
Definition ad9361.h:3243
SynthLUT::VCO_Bias_Tcf
uint8_t VCO_Bias_Tcf
Definition ad9361.h:3236
SynthLUT::VCO_MHz
uint16_t VCO_MHz
Definition ad9361.h:3232
SynthLUT::VCO_Varactor
uint8_t VCO_Varactor
Definition ad9361.h:3234
SynthLUT::LF_C2
uint8_t LF_C2
Definition ad9361.h:3240
SynthLUT::Charge_Pump_Current
uint8_t Charge_Pump_Current
Definition ad9361.h:3239
SynthLUT::LF_R3
uint8_t LF_R3
Definition ad9361.h:3244
SynthLUT::VCO_Varactor_Reference
uint8_t VCO_Varactor_Reference
Definition ad9361.h:3238
SynthLUT::LF_C1
uint8_t LF_C1
Definition ad9361.h:3241
ad9361_debugfs_entry
Definition ad9361.h:3279
ad9361_debugfs_entry::propname
const char * propname
Definition ad9361.h:3281
ad9361_debugfs_entry::cmd
uint8_t cmd
Definition ad9361.h:3285
ad9361_debugfs_entry::size
uint8_t size
Definition ad9361.h:3284
ad9361_debugfs_entry::val
uint32_t val
Definition ad9361.h:3283
ad9361_debugfs_entry::out_value
void * out_value
Definition ad9361.h:3282
ad9361_debugfs_entry::phy
struct ad9361_rf_phy * phy
Definition ad9361.h:3280
ad9361_fastlock_entry
Definition ad9361.h:3288
ad9361_fastlock_entry::flags
uint8_t flags
Definition ad9361.h:3290
ad9361_fastlock_entry::alc_written
uint8_t alc_written
Definition ad9361.h:3292
ad9361_fastlock_entry::alc_orig
uint8_t alc_orig
Definition ad9361.h:3291
ad9361_fastlock
Definition ad9361.h:3295
ad9361_fastlock::save_profile
uint8_t save_profile
Definition ad9361.h:3296
ad9361_fastlock::entry
struct ad9361_fastlock_entry entry[2][8]
Definition ad9361.h:3298
ad9361_fastlock::current_profile
uint8_t current_profile[2]
Definition ad9361.h:3297
ad9361_phy_platform_data
Definition ad9361.h:3155
ad9361_phy_platform_data::dig_interface_tune_skipmode
uint8_t dig_interface_tune_skipmode
Definition ad9361.h:3175
ad9361_phy_platform_data::qec_tracking_slow_mode_en
bool qec_tracking_slow_mode_en
Definition ad9361.h:3169
ad9361_phy_platform_data::tdd_use_dual_synth
bool tdd_use_dual_synth
Definition ad9361.h:3164
ad9361_phy_platform_data::tx_path_clks
uint32_t tx_path_clks[NUM_TX_CLOCKS]
Definition ad9361.h:3185
ad9361_phy_platform_data::fdd
bool fdd
Definition ad9361.h:3157
ad9361_phy_platform_data::gain_ctrl
struct gain_control gain_ctrl
Definition ad9361.h:3199
ad9361_phy_platform_data::tdd_skip_vco_cal
bool tdd_skip_vco_cal
Definition ad9361.h:3165
ad9361_phy_platform_data::rf_rx_bandwidth_Hz
uint32_t rf_rx_bandwidth_Hz
Definition ad9361.h:3189
ad9361_phy_platform_data::dig_interface_tune_fir_disable
uint8_t dig_interface_tune_fir_disable
Definition ad9361.h:3176
ad9361_phy_platform_data::rx_synth_freq
uint64_t rx_synth_freq
Definition ad9361.h:3187
ad9361_phy_platform_data::txmon_ctrl
struct tx_monitor_control txmon_ctrl
Definition ad9361.h:3207
ad9361_phy_platform_data::rx2tx2
bool rx2tx2
Definition ad9361.h:3156
ad9361_phy_platform_data::rf_tx_output_sel
uint32_t rf_tx_output_sel
Definition ad9361.h:3181
ad9361_phy_platform_data::rx1tx1_mode_use_tx_num
uint32_t rx1tx1_mode_use_tx_num
Definition ad9361.h:3183
ad9361_phy_platform_data::rf_tx_bandwidth_Hz
uint32_t rf_tx_bandwidth_Hz
Definition ad9361.h:3190
ad9361_phy_platform_data::use_extclk
bool use_extclk
Definition ad9361.h:3160
ad9361_phy_platform_data::rf_rx_input_sel
uint32_t rf_rx_input_sel
Definition ad9361.h:3180
ad9361_phy_platform_data::fdd_independent_mode
bool fdd_independent_mode
Definition ad9361.h:3158
ad9361_phy_platform_data::rx_path_clks
uint32_t rx_path_clks[NUM_RX_CLOCKS]
Definition ad9361.h:3184
ad9361_phy_platform_data::use_ext_rx_lo
bool use_ext_rx_lo
Definition ad9361.h:3166
ad9361_phy_platform_data::lo_powerdown_managed_en
uint8_t lo_powerdown_managed_en
Definition ad9361.h:3177
ad9361_phy_platform_data::rx_fastlock_delay_ns
uint32_t rx_fastlock_delay_ns
Definition ad9361.h:3193
ad9361_phy_platform_data::dcxo_fine
uint32_t dcxo_fine
Definition ad9361.h:3179
ad9361_phy_platform_data::tx_atten
int32_t tx_atten
Definition ad9361.h:3191
ad9361_phy_platform_data::tx_fastlock_delay_ns
uint32_t tx_fastlock_delay_ns
Definition ad9361.h:3194
ad9361_phy_platform_data::auxadc_ctrl
struct auxadc_control auxadc_ctrl
Definition ad9361.h:3204
ad9361_phy_platform_data::trx_fastlock_pinctrl_en
bool trx_fastlock_pinctrl_en[2]
Definition ad9361.h:3195
ad9361_phy_platform_data::split_gt
bool split_gt
Definition ad9361.h:3159
ad9361_phy_platform_data::rx1tx1_mode_use_rx_num
uint32_t rx1tx1_mode_use_rx_num
Definition ad9361.h:3182
ad9361_phy_platform_data::dc_offset_attenuation_high
uint8_t dc_offset_attenuation_high
Definition ad9361.h:3171
ad9361_phy_platform_data::ensm_pin_ctrl
bool ensm_pin_ctrl
Definition ad9361.h:3162
ad9361_phy_platform_data::rx1rx2_phase_inversion_en
bool rx1rx2_phase_inversion_en
Definition ad9361.h:3168
ad9361_phy_platform_data::dc_offset_attenuation_low
uint8_t dc_offset_attenuation_low
Definition ad9361.h:3172
ad9361_phy_platform_data::ctrl_outs_ctrl
struct ctrl_outs_control ctrl_outs_ctrl
Definition ad9361.h:3202
ad9361_phy_platform_data::ad9361_clkout_mode
enum ad9361_clkout ad9361_clkout_mode
Definition ad9361.h:3197
ad9361_phy_platform_data::trx_synth_max_fref
uint32_t trx_synth_max_fref
Definition ad9361.h:3186
ad9361_phy_platform_data::ensm_pin_pulse_mode
bool ensm_pin_pulse_mode
Definition ad9361.h:3161
ad9361_phy_platform_data::rf_dc_offset_count_low
uint8_t rf_dc_offset_count_low
Definition ad9361.h:3174
ad9361_phy_platform_data::elna_ctrl
struct elna_control elna_ctrl
Definition ad9361.h:3203
ad9361_phy_platform_data::rssi_ctrl
struct rssi_control rssi_ctrl
Definition ad9361.h:3200
ad9361_phy_platform_data::port_ctrl
struct port_control port_ctrl
Definition ad9361.h:3201
ad9361_phy_platform_data::debug_mode
bool debug_mode
Definition ad9361.h:3163
ad9361_phy_platform_data::auxdac_ctrl
struct auxdac_control auxdac_ctrl
Definition ad9361.h:3205
ad9361_phy_platform_data::gpo_ctrl
struct gpo_control gpo_ctrl
Definition ad9361.h:3206
ad9361_phy_platform_data::rf_dc_offset_count_high
uint8_t rf_dc_offset_count_high
Definition ad9361.h:3173
ad9361_phy_platform_data::tx_synth_freq
uint64_t tx_synth_freq
Definition ad9361.h:3188
ad9361_phy_platform_data::use_ext_tx_lo
bool use_ext_tx_lo
Definition ad9361.h:3167
ad9361_phy_platform_data::dc_offset_update_events
uint8_t dc_offset_update_events
Definition ad9361.h:3170
ad9361_phy_platform_data::update_tx_gain_via_alert
bool update_tx_gain_via_alert
Definition ad9361.h:3192
ad9361_phy_platform_data::dcxo_coarse
uint32_t dcxo_coarse
Definition ad9361.h:3178
ad9361_rf_phy
Definition ad9361.h:3328
ad9361_rf_phy::rfdc_track_en
bool rfdc_track_en
Definition ad9361.h:3387
ad9361_rf_phy::agc_mode
uint8_t agc_mode[2]
Definition ad9361.h:3386
ad9361_rf_phy::tx1_atten_cached
uint32_t tx1_atten_cached
Definition ad9361.h:3393
ad9361_rf_phy::current_tx_bw_Hz
uint32_t current_tx_bw_Hz
Definition ad9361.h:3371
ad9361_rf_phy::bist_tone_freq_Hz
uint32_t bist_tone_freq_Hz
Definition ad9361.h:3402
ad9361_rf_phy::bypass_tx_fir
bool bypass_tx_fir
Definition ad9361.h:3375
ad9361_rf_phy::dev_sel
enum dev_id dev_sel
Definition ad9361.h:3329
ad9361_rf_phy::gpio_desc_sync
struct no_os_gpio_desc * gpio_desc_sync
Definition ad9361.h:3332
ad9361_rf_phy::auto_cal_en
bool auto_cal_en
Definition ad9361.h:3358
ad9361_rf_phy::adc_state
struct axiadc_state * adc_state
Definition ad9361.h:3397
ad9361_rf_phy::bist_loopback_mode
int32_t bist_loopback_mode
Definition ad9361.h:3398
ad9361_rf_phy::pdata
struct ad9361_phy_platform_data * pdata
Definition ad9361.h:3347
ad9361_rf_phy::spi
struct no_os_spi_desc * spi
Definition ad9361.h:3330
ad9361_rf_phy::rxbbf_div
uint32_t rxbbf_div
Definition ad9361.h:3372
ad9361_rf_phy::rx_adc
struct axi_adc * rx_adc
Definition ad9361.h:3336
ad9361_rf_phy::ref_clk_scale
struct refclk_scale * ref_clk_scale[NUM_AD9361_CLKS]
Definition ad9361.h:3341
ad9361_rf_phy::gt_info
struct gain_table_info * gt_info
Definition ad9361.h:3355
ad9361_rf_phy::rate_governor
uint32_t rate_governor
Definition ad9361.h:3373
ad9361_rf_phy::bist_prbs_mode
enum ad9361_bist_mode bist_prbs_mode
Definition ad9361.h:3400
ad9361_rf_phy::ad9361_rfpll_ext_set_rate
int32_t(* ad9361_rfpll_ext_set_rate)(struct refclk_scale *clk_priv, uint32_t rate)
Definition ad9361.h:3345
ad9361_rf_phy::gpio_desc_cal_sw1
struct no_os_gpio_desc * gpio_desc_cal_sw1
Definition ad9361.h:3333
ad9361_rf_phy::current_rx_path_clks
uint32_t current_rx_path_clks[NUM_RX_CLOCKS]
Definition ad9361.h:3366
ad9361_rf_phy::cached_tx_rfpll_div
uint8_t cached_tx_rfpll_div
Definition ad9361.h:3351
ad9361_rf_phy::bist_tone_mode
enum ad9361_bist_mode bist_tone_mode
Definition ad9361.h:3401
ad9361_rf_phy::auxdac2_value
uint16_t auxdac2_value
Definition ad9361.h:3392
ad9361_rf_phy::bist_tone_level_dB
uint32_t bist_tone_level_dB
Definition ad9361.h:3403
ad9361_rf_phy::tx_dac
struct axi_dac * tx_dac
Definition ad9361.h:3337
ad9361_rf_phy::current_table
uint32_t current_table
Definition ad9361.h:3354
ad9361_rf_phy::clk_refin
struct no_os_clk * clk_refin
Definition ad9361.h:3339
ad9361_rf_phy::adc_conv
struct axiadc_converter * adc_conv
Definition ad9361.h:3396
ad9361_rf_phy::tx_fir_ntaps
uint8_t tx_fir_ntaps
Definition ad9361.h:3383
ad9361_rf_phy::current_rx_bw_Hz
uint32_t current_rx_bw_Hz
Definition ad9361.h:3370
ad9361_rf_phy::cached_rx_rfpll_div
uint8_t cached_rx_rfpll_div
Definition ad9361.h:3350
ad9361_rf_phy::current_rx_use_tdd_table
bool current_rx_use_tdd_table
Definition ad9361.h:3365
ad9361_rf_phy::bypass_rx_fir
bool bypass_rx_fir
Definition ad9361.h:3374
ad9361_rf_phy::tx_quad_lpf_tia_match
int32_t tx_quad_lpf_tia_match
Definition ad9361.h:3353
ad9361_rf_phy::filt_tx_bw_Hz
uint32_t filt_tx_bw_Hz
Definition ad9361.h:3381
ad9361_rf_phy::flags
uint32_t flags
Definition ad9361.h:3368
ad9361_rf_phy::current_rx_lo_freq
uint64_t current_rx_lo_freq
Definition ad9361.h:3363
ad9361_rf_phy::cached_synth_pd
uint8_t cached_synth_pd[2]
Definition ad9361.h:3352
ad9361_rf_phy::current_tx_use_tdd_table
bool current_tx_use_tdd_table
Definition ad9361.h:3364
ad9361_rf_phy::bist_tone_mask
uint32_t bist_tone_mask
Definition ad9361.h:3404
ad9361_rf_phy::txmon_tdd_en
bool txmon_tdd_en
Definition ad9361.h:3390
ad9361_rf_phy::last_tx_quad_cal_freq
uint64_t last_tx_quad_cal_freq
Definition ad9361.h:3360
ad9361_rf_phy::filt_tx_path_clks
uint32_t filt_tx_path_clks[NUM_TX_CLOCKS]
Definition ad9361.h:3379
ad9361_rf_phy::cal_threshold_freq
uint32_t cal_threshold_freq
Definition ad9361.h:3369
ad9361_rf_phy::rx_fir_ntaps
uint8_t rx_fir_ntaps
Definition ad9361.h:3385
ad9361_rf_phy::ensm_pin_ctl_en
bool ensm_pin_ctl_en
Definition ad9361.h:3356
ad9361_rf_phy::manual_tx_quad_cal_en
bool manual_tx_quad_cal_en
Definition ad9361.h:3359
ad9361_rf_phy::fastlock
struct ad9361_fastlock fastlock
Definition ad9361.h:3395
ad9361_rf_phy::rx_eq_2tx
bool rx_eq_2tx
Definition ad9361.h:3376
ad9361_rf_phy::ad9361_rfpll_ext_recalc_rate
uint32_t(* ad9361_rfpll_ext_recalc_rate)(struct refclk_scale *clk_priv)
Definition ad9361.h:3342
ad9361_rf_phy::filt_rx_path_clks
uint32_t filt_rx_path_clks[NUM_RX_CLOCKS]
Definition ad9361.h:3378
ad9361_rf_phy::filt_rx_bw_Hz
uint32_t filt_rx_bw_Hz
Definition ad9361.h:3380
ad9361_rf_phy::auxdac1_value
uint16_t auxdac1_value
Definition ad9361.h:3391
ad9361_rf_phy::gpio_desc_resetb
struct no_os_gpio_desc * gpio_desc_resetb
Definition ad9361.h:3331
ad9361_rf_phy::last_tx_quad_cal_phase
uint32_t last_tx_quad_cal_phase
Definition ad9361.h:3361
ad9361_rf_phy::tx_fir_int
uint8_t tx_fir_int
Definition ad9361.h:3382
ad9361_rf_phy::quad_track_en
bool quad_track_en
Definition ad9361.h:3389
ad9361_rf_phy::prev_ensm_state
uint8_t prev_ensm_state
Definition ad9361.h:3348
ad9361_rf_phy::bist_config
int32_t bist_config
Definition ad9361.h:3399
ad9361_rf_phy::bbdc_track_en
bool bbdc_track_en
Definition ad9361.h:3388
ad9361_rf_phy::filt_valid
bool filt_valid
Definition ad9361.h:3377
ad9361_rf_phy::tx2_atten_cached
uint32_t tx2_atten_cached
Definition ad9361.h:3394
ad9361_rf_phy::gpio_desc_cal_sw2
struct no_os_gpio_desc * gpio_desc_cal_sw2
Definition ad9361.h:3334
ad9361_rf_phy::clks
struct no_os_clk * clks[NUM_AD9361_CLKS]
Definition ad9361.h:3340
ad9361_rf_phy::current_tx_path_clks
uint32_t current_tx_path_clks[NUM_TX_CLOCKS]
Definition ad9361.h:3367
ad9361_rf_phy::rx_fir_dec
uint8_t rx_fir_dec
Definition ad9361.h:3384
ad9361_rf_phy::curr_ensm_state
uint8_t curr_ensm_state
Definition ad9361.h:3349
ad9361_rf_phy::bbpll_initialized
bool bbpll_initialized
Definition ad9361.h:3405
ad9361_rf_phy::current_tx_lo_freq
uint64_t current_tx_lo_freq
Definition ad9361.h:3362
ad9361_rf_phy::ad9361_rfpll_ext_round_rate
int32_t(* ad9361_rfpll_ext_round_rate)(struct refclk_scale *clk_priv, uint32_t rate)
Definition ad9361.h:3343
auxadc_control
Definition ad9361.h:3077
auxadc_control::offset
int8_t offset
Definition ad9361.h:3078
auxadc_control::auxadc_decimation
uint32_t auxadc_decimation
Definition ad9361.h:3083
auxadc_control::temp_sensor_decimation
uint32_t temp_sensor_decimation
Definition ad9361.h:3080
auxadc_control::auxadc_clock_rate
uint32_t auxadc_clock_rate
Definition ad9361.h:3082
auxadc_control::temp_time_inteval_ms
uint32_t temp_time_inteval_ms
Definition ad9361.h:3079
auxadc_control::periodic_temp_measuremnt
bool periodic_temp_measuremnt
Definition ad9361.h:3081
auxdac_control
Definition ad9361.h:3008
auxdac_control::dac2_in_alert_en
bool dac2_in_alert_en
Definition ad9361.h:3020
auxdac_control::dac2_rx_delay_us
uint8_t dac2_rx_delay_us
Definition ad9361.h:3024
auxdac_control::dac1_tx_delay_us
uint8_t dac1_tx_delay_us
Definition ad9361.h:3023
auxdac_control::dac1_in_rx_en
bool dac1_in_rx_en
Definition ad9361.h:3014
auxdac_control::dac2_in_tx_en
bool dac2_in_tx_en
Definition ad9361.h:3019
auxdac_control::dac1_in_tx_en
bool dac1_in_tx_en
Definition ad9361.h:3015
auxdac_control::dac2_default_value
uint16_t dac2_default_value
Definition ad9361.h:3010
auxdac_control::dac2_in_rx_en
bool dac2_in_rx_en
Definition ad9361.h:3018
auxdac_control::dac1_default_value
uint16_t dac1_default_value
Definition ad9361.h:3009
auxdac_control::dac1_in_alert_en
bool dac1_in_alert_en
Definition ad9361.h:3016
auxdac_control::dac2_tx_delay_us
uint8_t dac2_tx_delay_us
Definition ad9361.h:3025
auxdac_control::auxdac_manual_mode_en
bool auxdac_manual_mode_en
Definition ad9361.h:3012
auxdac_control::dac1_rx_delay_us
uint8_t dac1_rx_delay_us
Definition ad9361.h:3022
axi_adc
AXI ADC Device Descriptor.
Definition axi_adc_core.h:123
axi_dac
AXI DAC Device Descriptor.
Definition axi_dac_core.h:53
axiadc_converter
Definition ad9361_util.h:81
axiadc_state
Definition ad9361_util.h:71
ctrl_outs_control
Definition ad9361.h:3063
ctrl_outs_control::index
uint8_t index
Definition ad9361.h:3064
ctrl_outs_control::en_mask
uint8_t en_mask
Definition ad9361.h:3065
elna_control
Definition ad9361.h:3068
elna_control::bypass_loss_mdB
uint16_t bypass_loss_mdB
Definition ad9361.h:3070
elna_control::elna_2_control_en
bool elna_2_control_en
Definition ad9361.h:3073
elna_control::elna_in_gaintable_all_index_en
bool elna_in_gaintable_all_index_en
Definition ad9361.h:3074
elna_control::elna_1_control_en
bool elna_1_control_en
Definition ad9361.h:3072
elna_control::settling_delay_ns
uint32_t settling_delay_ns
Definition ad9361.h:3071
elna_control::gain_mdB
uint16_t gain_mdB
Definition ad9361.h:3069
gain_control
Definition ad9361.h:2909
gain_control::f_agc_final_overrange_count
uint8_t f_agc_final_overrange_count
Definition ad9361.h:2982
gain_control::agc_attack_delay_extra_margin_us
uint8_t agc_attack_delay_extra_margin_us
Definition ad9361.h:2936
gain_control::agc_inner_thresh_low_inc_steps
uint8_t agc_inner_thresh_low_inc_steps
Definition ad9361.h:2943
gain_control::f_agc_lock_level_gain_increase_upper_limit
uint8_t f_agc_lock_level_gain_increase_upper_limit
Definition ad9361.h:2978
gain_control::dig_gain_en
bool dig_gain_en
Definition ad9361.h:2924
gain_control::lmt_overload_small_exceed_counter
uint8_t lmt_overload_small_exceed_counter
Definition ad9361.h:2954
gain_control::immed_gain_change_if_large_adc_overload
bool immed_gain_change_if_large_adc_overload
Definition ad9361.h:2962
gain_control::agc_outer_thresh_high
uint8_t agc_outer_thresh_high
Definition ad9361.h:2938
gain_control::adc_small_overload_exceed_counter
uint8_t adc_small_overload_exceed_counter
Definition ad9361.h:2947
gain_control::adc_ovr_sample_size
uint8_t adc_ovr_sample_size
Definition ad9361.h:2914
gain_control::sync_for_gain_counter_en
bool sync_for_gain_counter_en
Definition ad9361.h:2959
gain_control::adc_large_overload_inc_steps
uint8_t adc_large_overload_inc_steps
Definition ad9361.h:2949
gain_control::adc_large_overload_thresh
uint8_t adc_large_overload_thresh
Definition ad9361.h:2916
gain_control::mgc_dec_gain_step
uint8_t mgc_dec_gain_step
Definition ad9361.h:2932
gain_control::f_agc_gain_increase_after_gain_lock_en
bool f_agc_gain_increase_after_gain_lock_en
Definition ad9361.h:2984
gain_control::f_agc_lp_thresh_increment_steps
uint8_t f_agc_lp_thresh_increment_steps
Definition ad9361.h:2973
gain_control::f_agc_optimized_gain_offset
uint8_t f_agc_optimized_gain_offset
Definition ad9361.h:2990
gain_control::f_agc_large_overload_inc_steps
uint8_t f_agc_large_overload_inc_steps
Definition ad9361.h:3005
gain_control::low_power_thresh
uint8_t low_power_thresh
Definition ad9361.h:2921
gain_control::f_agc_gain_index_type_after_exit_rx_mode
enum f_agc_target_gain_index_type f_agc_gain_index_type_after_exit_rx_mode
Definition ad9361.h:2987
gain_control::f_agc_rst_gla_if_en_agc_pulled_high_mode
enum f_agc_target_gain_index_type f_agc_rst_gla_if_en_agc_pulled_high_mode
Definition ad9361.h:3002
gain_control::f_agc_lmt_final_settling_steps
uint8_t f_agc_lmt_final_settling_steps
Definition ad9361.h:2981
gain_control::mgc_rx2_ctrl_inp_en
bool mgc_rx2_ctrl_inp_en
Definition ad9361.h:2929
gain_control::f_agc_lp_thresh_increment_time
uint8_t f_agc_lp_thresh_increment_time
Definition ad9361.h:2972
gain_control::f_agc_lock_level
uint8_t f_agc_lock_level
Definition ad9361.h:2976
gain_control::adc_small_overload_thresh
uint8_t adc_small_overload_thresh
Definition ad9361.h:2915
gain_control::rx2_mode
enum rf_gain_ctrl_mode rx2_mode
Definition ad9361.h:2911
gain_control::agc_inner_thresh_high
uint8_t agc_inner_thresh_high
Definition ad9361.h:2940
gain_control::f_agc_lpf_final_settling_steps
uint8_t f_agc_lpf_final_settling_steps
Definition ad9361.h:2980
gain_control::agc_outer_thresh_low
uint8_t agc_outer_thresh_low
Definition ad9361.h:2944
gain_control::f_agc_power_measurement_duration_in_state5
uint8_t f_agc_power_measurement_duration_in_state5
Definition ad9361.h:3004
gain_control::mgc_split_table_ctrl_inp_gain_mode
uint8_t mgc_split_table_ctrl_inp_gain_mode
Definition ad9361.h:2933
gain_control::f_agc_rst_gla_stronger_sig_thresh_exceeded_en
bool f_agc_rst_gla_stronger_sig_thresh_exceeded_en
Definition ad9361.h:2991
gain_control::f_agc_state_wait_time_ns
uint32_t f_agc_state_wait_time_ns
Definition ad9361.h:2969
gain_control::mgc_rx1_ctrl_inp_en
bool mgc_rx1_ctrl_inp_en
Definition ad9361.h:2928
gain_control::use_rx_fir_out_for_dec_pwr_meas
bool use_rx_fir_out_for_dec_pwr_meas
Definition ad9361.h:2922
gain_control::f_agc_rst_gla_engergy_lost_sig_thresh_exceeded_en
bool f_agc_rst_gla_engergy_lost_sig_thresh_exceeded_en
Definition ad9361.h:2993
gain_control::dig_gain_step_size
uint8_t dig_gain_step_size
Definition ad9361.h:2958
gain_control::f_agc_lock_level_lmt_gain_increase_en
bool f_agc_lock_level_lmt_gain_increase_en
Definition ad9361.h:2977
gain_control::f_agc_rst_gla_engergy_lost_sig_thresh_below_ll
uint8_t f_agc_rst_gla_engergy_lost_sig_thresh_below_ll
Definition ad9361.h:2995
gain_control::f_agc_dec_pow_measuremnt_duration
uint32_t f_agc_dec_pow_measuremnt_duration
Definition ad9361.h:2968
gain_control::dig_saturation_exceed_counter
uint8_t dig_saturation_exceed_counter
Definition ad9361.h:2957
gain_control::f_agc_rst_gla_large_lmt_overload_en
bool f_agc_rst_gla_large_lmt_overload_en
Definition ad9361.h:2998
gain_control::lmt_overload_low_thresh
uint16_t lmt_overload_low_thresh
Definition ad9361.h:2919
gain_control::mgc_inc_gain_step
uint8_t mgc_inc_gain_step
Definition ad9361.h:2931
gain_control::f_agc_energy_lost_stronger_sig_gain_lock_exit_cnt
uint8_t f_agc_energy_lost_stronger_sig_gain_lock_exit_cnt
Definition ad9361.h:2996
gain_control::agc_outer_thresh_low_inc_steps
uint8_t agc_outer_thresh_low_inc_steps
Definition ad9361.h:2945
gain_control::adc_large_overload_exceed_counter
uint8_t adc_large_overload_exceed_counter
Definition ad9361.h:2948
gain_control::f_agc_rst_gla_en_agc_pulled_high_en
bool f_agc_rst_gla_en_agc_pulled_high_en
Definition ad9361.h:2999
gain_control::lmt_overload_large_exceed_counter
uint8_t lmt_overload_large_exceed_counter
Definition ad9361.h:2953
gain_control::f_agc_rst_gla_stronger_sig_thresh_above_ll
uint8_t f_agc_rst_gla_stronger_sig_thresh_above_ll
Definition ad9361.h:2992
gain_control::dec_pow_measuremnt_duration
uint16_t dec_pow_measuremnt_duration
Definition ad9361.h:2920
gain_control::f_agc_rst_gla_large_adc_overload_en
bool f_agc_rst_gla_large_adc_overload_en
Definition ad9361.h:2997
gain_control::adc_lmt_small_overload_prevent_gain_inc
bool adc_lmt_small_overload_prevent_gain_inc
Definition ad9361.h:2951
gain_control::f_agc_use_last_lock_level_for_set_gain_en
bool f_agc_use_last_lock_level_for_set_gain_en
Definition ad9361.h:2989
gain_control::immed_gain_change_if_large_lmt_overload
bool immed_gain_change_if_large_lmt_overload
Definition ad9361.h:2963
gain_control::f_agc_allow_agc_gain_increase
bool f_agc_allow_agc_gain_increase
Definition ad9361.h:2971
gain_control::gain_update_interval_us
uint32_t gain_update_interval_us
Definition ad9361.h:2961
gain_control::agc_inner_thresh_high_dec_steps
uint8_t agc_inner_thresh_high_dec_steps
Definition ad9361.h:2941
gain_control::rx1_mode
enum rf_gain_ctrl_mode rx1_mode
Definition ad9361.h:2910
gain_control::agc_outer_thresh_high_dec_steps
uint8_t agc_outer_thresh_high_dec_steps
Definition ad9361.h:2939
gain_control::max_dig_gain
uint8_t max_dig_gain
Definition ad9361.h:2925
gain_control::agc_inner_thresh_low
uint8_t agc_inner_thresh_low
Definition ad9361.h:2942
gain_control::lmt_overload_high_thresh
uint16_t lmt_overload_high_thresh
Definition ad9361.h:2918
gain_control::f_agc_rst_gla_engergy_lost_goto_optim_gain_en
bool f_agc_rst_gla_engergy_lost_goto_optim_gain_en
Definition ad9361.h:2994
gain_control::lmt_overload_large_inc_steps
uint8_t lmt_overload_large_inc_steps
Definition ad9361.h:2955
gain_table_info
Definition ad9361.h:2871
gain_table_info::start
uint64_t start
Definition ad9361.h:2872
gain_table_info::end
uint64_t end
Definition ad9361.h:2873
gain_table_info::max_index
uint8_t max_index
Definition ad9361.h:2874
gain_table_info::split_table
uint8_t split_table
Definition ad9361.h:2875
gain_table_info::abs_gain_tbl
int8_t * abs_gain_tbl
Definition ad9361.h:2876
gain_table_info::tab
uint8_t(* tab)[3]
Definition ad9361.h:2877
gpo_control
Definition ad9361.h:3086
gpo_control::gpo3_slave_rx_en
bool gpo3_slave_rx_en
Definition ad9361.h:3099
gpo_control::gpo3_tx_delay_us
uint8_t gpo3_tx_delay_us
Definition ad9361.h:3108
gpo_control::gpo1_inactive_state_high_en
bool gpo1_inactive_state_high_en
Definition ad9361.h:3090
gpo_control::gpo3_slave_tx_en
bool gpo3_slave_tx_en
Definition ad9361.h:3100
gpo_control::gpo2_rx_delay_us
uint8_t gpo2_rx_delay_us
Definition ad9361.h:3105
gpo_control::gpo2_slave_rx_en
bool gpo2_slave_rx_en
Definition ad9361.h:3097
gpo_control::gpo3_rx_delay_us
uint8_t gpo3_rx_delay_us
Definition ad9361.h:3107
gpo_control::gpo0_slave_rx_en
bool gpo0_slave_rx_en
Definition ad9361.h:3093
gpo_control::gpo1_slave_rx_en
bool gpo1_slave_rx_en
Definition ad9361.h:3095
gpo_control::gpo1_slave_tx_en
bool gpo1_slave_tx_en
Definition ad9361.h:3096
gpo_control::gpo2_inactive_state_high_en
bool gpo2_inactive_state_high_en
Definition ad9361.h:3091
gpo_control::gpo0_tx_delay_us
uint8_t gpo0_tx_delay_us
Definition ad9361.h:3102
gpo_control::gpo_manual_mode_enable_mask
uint32_t gpo_manual_mode_enable_mask
Definition ad9361.h:3087
gpo_control::gpo2_slave_tx_en
bool gpo2_slave_tx_en
Definition ad9361.h:3098
gpo_control::gpo0_rx_delay_us
uint8_t gpo0_rx_delay_us
Definition ad9361.h:3101
gpo_control::gpo2_tx_delay_us
uint8_t gpo2_tx_delay_us
Definition ad9361.h:3106
gpo_control::gpo0_slave_tx_en
bool gpo0_slave_tx_en
Definition ad9361.h:3094
gpo_control::gpo1_tx_delay_us
uint8_t gpo1_tx_delay_us
Definition ad9361.h:3104
gpo_control::gpo1_rx_delay_us
uint8_t gpo1_rx_delay_us
Definition ad9361.h:3103
gpo_control::gpo3_inactive_state_high_en
bool gpo3_inactive_state_high_en
Definition ad9361.h:3092
gpo_control::gpo_manual_mode_en
bool gpo_manual_mode_en
Definition ad9361.h:3088
gpo_control::gpo0_inactive_state_high_en
bool gpo0_inactive_state_high_en
Definition ad9361.h:3089
no_os_clk
Definition no_os_clk.h:58
no_os_gpio_desc
Structure holding the GPIO descriptor.
Definition no_os_gpio.h:84
no_os_spi_desc
Structure holding SPI descriptor.
Definition no_os_spi.h:180
port_control
Definition ad9361.h:3054
port_control::lvds_invert
uint8_t lvds_invert[2]
Definition ad9361.h:3060
port_control::rx_clk_data_delay
uint8_t rx_clk_data_delay
Definition ad9361.h:3056
port_control::tx_clk_data_delay
uint8_t tx_clk_data_delay
Definition ad9361.h:3057
port_control::lvds_bias_ctrl
uint8_t lvds_bias_ctrl
Definition ad9361.h:3059
port_control::pp_conf
uint8_t pp_conf[3]
Definition ad9361.h:3055
port_control::digital_io_ctrl
uint8_t digital_io_ctrl
Definition ad9361.h:3058
refclk_scale
Definition ad9361.h:3408
refclk_scale::phy
struct ad9361_rf_phy * phy
Definition ad9361.h:3410
refclk_scale::mult
uint32_t mult
Definition ad9361.h:3411
refclk_scale::spi
struct no_os_spi_desc * spi
Definition ad9361.h:3409
refclk_scale::parent_source
enum ad9361_clocks parent_source
Definition ad9361.h:3414
refclk_scale::div
uint32_t div
Definition ad9361.h:3412
refclk_scale::source
enum ad9361_clocks source
Definition ad9361.h:3413
rf_gain_ctrl
Definition ad9361.h:2890
rf_gain_ctrl::ant
uint32_t ant
Definition ad9361.h:2891
rf_gain_ctrl::mode
uint8_t mode
Definition ad9361.h:2892
rf_rssi
Definition ad9361.h:3223
rf_rssi::duration
uint8_t duration
Definition ad9361.h:3228
rf_rssi::preamble
uint32_t preamble
Definition ad9361.h:3226
rf_rssi::ant
uint32_t ant
Definition ad9361.h:3224
rf_rssi::symbol
uint32_t symbol
Definition ad9361.h:3225
rf_rssi::multiplier
int32_t multiplier
Definition ad9361.h:3227
rf_rx_gain
Definition ad9361.h:3210
rf_rx_gain::lna_index
uint32_t lna_index
Definition ad9361.h:3218
rf_rx_gain::ant
uint32_t ant
Definition ad9361.h:3211
rf_rx_gain::mixer_index
uint32_t mixer_index
Definition ad9361.h:3220
rf_rx_gain::tia_index
uint32_t tia_index
Definition ad9361.h:3219
rf_rx_gain::fgt_lmt_index
uint32_t fgt_lmt_index
Definition ad9361.h:3213
rf_rx_gain::gain_db
int32_t gain_db
Definition ad9361.h:3212
rf_rx_gain::lpf_gain
uint32_t lpf_gain
Definition ad9361.h:3215
rf_rx_gain::digital_gain
uint32_t digital_gain
Definition ad9361.h:3216
rf_rx_gain::lmt_gain
uint32_t lmt_gain
Definition ad9361.h:3214
rssi_control
Definition ad9361.h:3037
rssi_control::rssi_delay
uint32_t rssi_delay
Definition ad9361.h:3040
rssi_control::restart_mode
enum rssi_restart_mode restart_mode
Definition ad9361.h:3038
rssi_control::rssi_unit_is_rx_samples
bool rssi_unit_is_rx_samples
Definition ad9361.h:3039
rssi_control::rssi_duration
uint32_t rssi_duration
Definition ad9361.h:3042
rssi_control::rssi_wait
uint32_t rssi_wait
Definition ad9361.h:3041
rx_gain_info
Definition ad9361.h:3045
rx_gain_info::idx_step_offset
int32_t idx_step_offset
Definition ad9361.h:3051
rx_gain_info::starting_gain_db
int32_t starting_gain_db
Definition ad9361.h:3047
rx_gain_info::max_gain_db
int32_t max_gain_db
Definition ad9361.h:3048
rx_gain_info::tbl_type
enum rx_gain_table_type tbl_type
Definition ad9361.h:3046
rx_gain_info::max_idx
int32_t max_idx
Definition ad9361.h:3050
rx_gain_info::gain_step_db
int32_t gain_step_db
Definition ad9361.h:3049
tx_monitor_control
Definition ad9361.h:3111
tx_monitor_control::low_gain_dB
uint8_t low_gain_dB
Definition ad9361.h:3115
tx_monitor_control::high_gain_dB
uint8_t high_gain_dB
Definition ad9361.h:3116
tx_monitor_control::low_high_gain_threshold_mdB
uint32_t low_high_gain_threshold_mdB
Definition ad9361.h:3114
tx_monitor_control::tx1_mon_lo_cm
uint8_t tx1_mon_lo_cm
Definition ad9361.h:3121
tx_monitor_control::tx2_mon_front_end_gain
uint8_t tx2_mon_front_end_gain
Definition ad9361.h:3120
tx_monitor_control::tx_mon_delay
uint16_t tx_mon_delay
Definition ad9361.h:3117
tx_monitor_control::tx_mon_duration
uint16_t tx_mon_duration
Definition ad9361.h:3118
tx_monitor_control::tx_mon_track_en
bool tx_mon_track_en
Definition ad9361.h:3112
tx_monitor_control::tx1_mon_front_end_gain
uint8_t tx1_mon_front_end_gain
Definition ad9361.h:3119
tx_monitor_control::one_shot_mode_en
bool one_shot_mode_en
Definition ad9361.h:3113
tx_monitor_control::tx2_mon_lo_cm
uint8_t tx2_mon_lo_cm
Definition ad9361.h:3122
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