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38 #ifndef IIO_FREQUENCY_AD9361_H_
39 #define IIO_FREQUENCY_AD9361_H_
51 #define REG_SPI_CONF 0x000
52 #define REG_MULTICHIP_SYNC_AND_TX_MON_CTRL 0x001
53 #define REG_TX_ENABLE_FILTER_CTRL 0x002
54 #define REG_RX_ENABLE_FILTER_CTRL 0x003
55 #define REG_INPUT_SELECT 0x004
56 #define REG_RFPLL_DIVIDERS 0x005
57 #define REG_RX_CLOCK_DATA_DELAY 0x006
58 #define REG_TX_CLOCK_DATA_DELAY 0x007
59 #define REG_CLOCK_ENABLE 0x009
60 #define REG_BBPLL 0x00A
61 #define REG_TEMP_OFFSET 0x00B
62 #define REG_START_TEMP_READING 0x00C
63 #define REG_TEMP_SENSE2 0x00D
64 #define REG_TEMPERATURE 0x00E
65 #define REG_TEMP_SENSOR_CONFIG 0x00F
66 #define REG_PARALLEL_PORT_CONF_1 0x010
67 #define REG_PARALLEL_PORT_CONF_2 0x011
68 #define REG_PARALLEL_PORT_CONF_3 0x012
69 #define REG_ENSM_MODE 0x013
70 #define REG_ENSM_CONFIG_1 0x014
71 #define REG_ENSM_CONFIG_2 0x015
72 #define REG_CALIBRATION_CTRL 0x016
73 #define REG_STATE 0x017
74 #define REG_AUXDAC_1_WORD 0x018
75 #define REG_AUXDAC_2_WORD 0x019
76 #define REG_AUXDAC_1_CONFIG 0x01A
77 #define REG_AUXDAC_2_CONFIG 0x01B
78 #define REG_AUXADC_CLOCK_DIVIDER 0x01C
79 #define REG_AUXADC_CONFIG 0x01D
80 #define REG_AUXADC_WORD_MSB 0x01E
81 #define REG_AUXADC_LSB 0x01F
82 #define REG_AUTO_GPO 0x020
83 #define REG_AGC_GAIN_LOCK_DELAY 0x021
84 #define REG_AGC_ATTACK_DELAY 0x022
85 #define REG_AUXDAC_ENABLE_CTRL 0x023
86 #define REG_RX_LOAD_SYNTH_DELAY 0x024
87 #define REG_TX_LOAD_SYNTH_DELAY 0x025
88 #define REG_EXTERNAL_LNA_CTRL 0x026
89 #define REG_GPO_FORCE_AND_INIT 0x027
90 #define REG_GPO0_RX_DELAY 0x028
91 #define REG_GPO1_RX_DELAY 0x029
92 #define REG_GPO2_RX_DELAY 0x02A
93 #define REG_GPO3_RX_DELAY 0x02B
94 #define REG_GPO0_TX_DELAY 0x02C
95 #define REG_GPO1_TX_DELAY 0x02D
96 #define REG_GPO2_TX_DELAY 0x02E
97 #define REG_GPO3_TX_DELAY 0x02F
98 #define REG_AUXDAC1_RX_DELAY 0x030
99 #define REG_AUXDAC1_TX_DELAY 0x031
100 #define REG_AUXDAC2_RX_DELAY 0x032
101 #define REG_AUXDAC2_TX_DELAY 0x033
102 #define REG_CTRL_OUTPUT_POINTER 0x035
103 #define REG_CTRL_OUTPUT_ENABLE 0x036
104 #define REG_PRODUCT_ID 0x037
105 #define REG_REFERENCE_CLOCK_CYCLES 0x03A
106 #define REG_DIGITAL_IO_CTRL 0x03B
107 #define REG_LVDS_BIAS_CTRL 0x03C
108 #define REG_LVDS_INVERT_CTRL1 0x03D
109 #define REG_LVDS_INVERT_CTRL2 0x03E
110 #define REG_SDM_CTRL_1 0x03F
111 #define REG_FRACT_BB_FREQ_WORD_1 0x041
112 #define REG_FRACT_BB_FREQ_WORD_2 0x042
113 #define REG_FRACT_BB_FREQ_WORD_3 0x043
114 #define REG_INTEGER_BB_FREQ_WORD 0x044
115 #define REG_CLOCK_CTRL 0x045
116 #define REG_CP_CURRENT 0x046
117 #define REG_CP_BLEED_CURRENT 0x047
118 #define REG_LOOP_FILTER_1 0x048
119 #define REG_LOOP_FILTER_2 0x049
120 #define REG_LOOP_FILTER_3 0x04A
121 #define REG_VCO_CTRL 0x04B
122 #define REG_VCO_PROGRAM_1 0x04C
123 #define REG_VCO_PROGRAM_2 0x04D
124 #define REG_SDM_CTRL 0x04E
125 #define REG_RX_SYNTH_POWER_DOWN_OVERRIDE 0x050
126 #define REG_TX_SYNTH_POWER_DOWN_OVERRIDE 0x051
127 #define REG_RX_ANALOG_POWER_DOWN_OVERRIDE_1 0x052
128 #define REG_RX_ANALOG_POWER_DOWN_OVERRIDE_2 0x053
129 #define REG_RX1_ADC_POWER_DOWN_OVERRIDE 0x054
130 #define REG_RX2_ADC_POWER_DOWN_OVERRIDE 0x055
131 #define REG_TX_ANALOG_POWER_DOWN_OVERRIDE_1 0x056
132 #define REG_ANALOG_POWER_DOWN_OVERRIDE 0x057
133 #define REG_MISC_POWER_DOWN_OVERRIDE 0x058
134 #define REG_CH_1_OVERFLOW 0x05E
135 #define REG_CH_2_OVERFLOW 0x05F
136 #define REG_TX_FILTER_COEF_ADDR 0x060
137 #define REG_TX_FILTER_COEF_WRITE_DATA_1 0x061
138 #define REG_TX_FILTER_COEF_WRITE_DATA_2 0x062
139 #define REG_TX_FILTER_COEF_READ_DATA_1 0x063
140 #define REG_TX_FILTER_COEF_READ_DATA_2 0x064
141 #define REG_TX_FILTER_CONF 0x065
142 #define REG_TX_MON_LOW_GAIN 0x067
143 #define REG_TX_MON_HIGH_GAIN 0x068
144 #define REG_TX_MON_DELAY 0x069
145 #define REG_TX_LEVEL_THRESH 0x06A
146 #define REG_TX_RSSI1 0x06B
147 #define REG_TX_RSSI2 0x06C
148 #define REG_TX_RSSI_LSB 0x06D
149 #define REG_TPM_MODE_ENABLE 0x06E
150 #define REG_TX_MON_TEMP_GAIN_COEF 0x06F
151 #define REG_TX_MON_1_CONFIG 0x070
152 #define REG_TX_MON_2_CONFIG 0x071
153 #define REG_TX1_ATTEN_0 0x073
154 #define REG_TX1_ATTEN_1 0x074
155 #define REG_TX2_ATTEN_0 0x075
156 #define REG_TX2_ATTEN_1 0x076
157 #define REG_TX_ATTEN_OFFSET 0x077
158 #define REG_TX_ATTEN_THRESH 0x078
159 #define REG_TX1_DIG_ATTEN 0x079
160 #define REG_TX2_DIG_ATTEN 0x07C
161 #define REG_TX1_SYMBOL_ATTEN 0x07F
162 #define REG_TX2_SYMBOL_ATTEN 0x080
163 #define REG_TX_SYMBOL_ATTEN_CONFIG 0x081
164 #define REG_TX1_OUT_1_PHASE_CORR 0x08E
165 #define REG_TX1_OUT_1_GAIN_CORR 0x08F
166 #define REG_TX2_OUT_1_PHASE_CORR 0x090
167 #define REG_TX2_OUT_1_GAIN_CORR 0x091
168 #define REG_TX1_OUT_1_OFFSET_I 0x092
169 #define REG_TX1_OUT_1_OFFSET_Q 0x093
170 #define REG_TX2_OUT_1_OFFSET_I 0x094
171 #define REG_TX2_OUT_1_OFFSET_Q 0x095
172 #define REG_TX1_OUT_2_PHASE_CORR 0x096
173 #define REG_TX1_OUT_2_GAIN_CORR 0x097
174 #define REG_TX2_OUT_2_PHASE_CORR 0x098
175 #define REG_TX2_OUT_2_GAIN_CORR 0x099
176 #define REG_TX1_OUT_2_OFFSET_I 0x09A
177 #define REG_TX1_OUT_2_OFFSET_Q 0x09B
178 #define REG_TX2_OUT_2_OFFSET_I 0x09C
179 #define REG_TX2_OUT_2_OFFSET_Q 0x09D
180 #define REG_TX_FORCE_BITS 0x09F
181 #define REG_QUAD_CAL_NCO_FREQ_PHASE_OFFSET 0x0A0
182 #define REG_QUAD_CAL_CTRL 0x0A1
183 #define REG_KEXP_1 0x0A2
184 #define REG_KEXP_2 0x0A3
185 #define REG_QUAD_SETTLE_COUNT 0x0A4
186 #define REG_MAG_FTEST_THRESH 0x0A5
187 #define REG_MAG_FTEST_THRESH_2 0x0A6
188 #define REG_QUAD_CAL_STATUS_TX1 0x0A7
189 #define REG_QUAD_CAL_STATUS_TX2 0x0A8
190 #define REG_QUAD_CAL_COUNT 0x0A9
191 #define REG_TX_QUAD_FULL_LMT_GAIN 0x0AA
192 #define REG_SQUARER_CONFIG 0x0AB
193 #define REG_TX_QUAD_CAL_ATTEN 0x0AC
194 #define REG_THRESH_ACCUM 0x0AD
195 #define REG_TX_QUAD_LPF_GAIN 0x0AE
196 #define REG_TXDAC_VDS_I 0x0B0
197 #define REG_TXDAC_VDS_Q 0x0B1
198 #define REG_TXDAC_GN_I 0x0B2
199 #define REG_TXDAC_GN_Q 0x0B3
200 #define REG_TXBBF_OPAMP_A 0x0C0
201 #define REG_TXBBF_OPAMP_B 0x0C1
202 #define REG_TX_BBF_R1 0x0C2
203 #define REG_TX_BBF_R2 0x0C3
204 #define REG_TX_BBF_R3 0x0C4
205 #define REG_TX_BBF_R4 0x0C5
206 #define REG_TX_BBF_RP 0x0C6
207 #define REG_TX_BBF_C1 0x0C7
208 #define REG_TX_BBF_C2 0x0C8
209 #define REG_TX_BBF_CP 0x0C9
210 #define REG_TX_TUNE_CTRL 0x0CA
211 #define REG_TX_BBF_R2B 0x0CB
212 #define REG_TX_BBF_TUNE 0x0CC
213 #define REG_CONFIG0 0x0D0
214 #define REG_RESISTOR 0x0D1
215 #define REG_CAPACITOR 0x0D2
216 #define REG_LO_CM 0x0D3
217 #define REG_TX_BBF_TUNE_DIVIDER 0x0D6
218 #define REG_TX_BBF_TUNE_MODE 0x0D7
219 #define REG_RX_FILTER_COEF_ADDR 0x0F0
220 #define REG_RX_FILTER_COEF_DATA_1 0x0F1
221 #define REG_RX_FILTER_COEF_DATA_2 0x0F2
222 #define REG_RX_FILTER_COEF_READ_DATA_1 0x0F3
223 #define REG_RX_FILTER_COEF_READ_DATA_2 0x0F4
224 #define REG_RX_FILTER_CONFIG 0x0F5
225 #define REG_RX_FILTER_GAIN 0x0F6
226 #define REG_AGC_CONFIG_1 0x0FA
227 #define REG_AGC_CONFIG_2 0x0FB
228 #define REG_AGC_CONFIG_3 0x0FC
229 #define REG_MAX_LMT_FULL_GAIN 0x0FD
230 #define REG_PEAK_WAIT_TIME 0x0FE
231 #define REG_DIGITAL_GAIN 0x100
232 #define REG_AGC_LOCK_LEVEL 0x101
233 #define REG_ADC_NOISE_CORRECTION_FACTOR 0x102
234 #define REG_GAIN_STP_CONFIG1 0x103
235 #define REG_ADC_SMALL_OVERLOAD_THRESH 0x104
236 #define REG_ADC_LARGE_OVERLOAD_THRESH 0x105
237 #define REG_GAIN_STP_CONFIG_2 0x106
238 #define REG_SMALL_LMT_OVERLOAD_THRESH 0x107
239 #define REG_LARGE_LMT_OVERLOAD_THRESH 0x108
240 #define REG_RX1_MANUAL_LMT_FULL_GAIN 0x109
241 #define REG_RX1_MANUAL_LPF_GAIN 0x10A
242 #define REG_RX1_MANUAL_DIGITALFORCED_GAIN 0x10B
243 #define REG_RX2_MANUAL_LMT_FULL_GAIN 0x10C
244 #define REG_RX2_MANUAL_LPF_GAIN 0x10D
245 #define REG_RX2_MANUAL_DIGITALFORCED_GAIN 0x10E
246 #define REG_FAST_CONFIG_1 0x110
247 #define REG_FAST_CONFIG_2_SETTLING_DELAY 0x111
248 #define REG_FAST_ENERGY_LOST_THRESH 0x112
249 #define REG_FAST_STRONGER_SIGNAL_THRESH 0x113
250 #define REG_FAST_LOW_POWER_THRESH 0x114
251 #define REG_FAST_STRONG_SIGNAL_FREEZE 0x115
252 #define REG_FAST_FINAL_OVER_RANGE_AND_OPT_GAIN 0x116
253 #define REG_FAST_ENERGY_DETECT_COUNT 0x117
254 #define REG_FAST_AGCLL_UPPER_LIMIT 0x118
255 #define REG_FAST_GAIN_LOCK_EXIT_COUNT 0x119
256 #define REG_FAST_INITIAL_LMT_GAIN_LIMIT 0x11A
257 #define REG_FAST_INCREMENT_TIME 0x11B
258 #define REG_AGC_INNER_LOW_THRESH 0x120
259 #define REG_LMT_OVERLOAD_COUNTERS 0x121
260 #define REG_ADC_OVERLOAD_COUNTERS 0x122
261 #define REG_GAIN_STP1 0x123
262 #define REG_GAIN_UPDATE_COUNTER1 0x124
263 #define REG_GAIN_UPDATE_COUNTER2 0x125
264 #define REG_DIGITAL_SAT_COUNTER 0x128
265 #define REG_OUTER_POWER_THRESHS 0x129
266 #define REG_GAIN_STP_2 0x12A
267 #define REG_EXT_LNA_HIGH_GAIN 0x12C
268 #define REG_EXT_LNA_LOW_GAIN 0x12D
269 #define REG_GAIN_TABLE_ADDRESS 0x130
270 #define REG_GAIN_TABLE_WRITE_DATA1 0x131
271 #define REG_GAIN_TABLE_WRITE_DATA2 0x132
272 #define REG_GAIN_TABLE_WRITE_DATA3 0x133
273 #define REG_GAIN_TABLE_READ_DATA1 0x134
274 #define REG_GAIN_TABLE_READ_DATA2 0x135
275 #define REG_GAIN_TABLE_READ_DATA3 0x136
276 #define REG_GAIN_TABLE_CONFIG 0x137
277 #define REG_GM_SUB_TABLE_ADDRESS 0x138
278 #define REG_GM_SUB_TABLE_GAIN_WRITE 0x139
279 #define REG_GM_SUB_TABLE_BIAS_WRITE 0x13A
280 #define REG_GM_SUB_TABLE_CTRL_WRITE 0x13B
281 #define REG_GM_SUB_TABLE_GAIN_READ 0x13C
282 #define REG_GM_SUB_TABLE_BIAS_READ 0x13D
283 #define REG_GM_SUB_TABLE_CTRL_READ 0x13E
284 #define REG_GM_SUB_TABLE_CONFIG 0x13F
285 #define REG_WORD_ADDRESS 0x140
286 #define REG_GAIN_DIFF_WORDERROR_WRITE 0x141
287 #define REG_GAIN_ERROR_READ 0x142
288 #define REG_CONFIG 0x143
289 #define REG_LNA_GAIN_DIFF_READ_BACK 0x144
290 #define REG_MAX_MIXER_CALIBRATION_GAIN_INDEX 0x145
291 #define REG_TEMP_GAIN_COEF 0x146
292 #define REG_SETTLE_TIME 0x147
293 #define REG_MEASURE_DURATION 0x148
294 #define REG_CAL_TEMP_SENSOR_WORD 0x149
295 #define REG_MEASURE_DURATION_01 0x150
296 #define REG_MEASURE_DURATION_23 0x151
297 #define REG_RSSI_WEIGHT_0 0x152
298 #define REG_RSSI_WEIGHT_1 0x153
299 #define REG_RSSI_WEIGHT_2 0x154
300 #define REG_RSSI_WEIGHT_3 0x155
301 #define REG_RSSI_DELAY 0x156
302 #define REG_RSSI_WAIT_TIME 0x157
303 #define REG_RSSI_CONFIG 0x158
304 #define REG_ADC_MEASURE_DURATION_01 0x159
305 #define REG_ADC_WEIGHT_0 0x15A
306 #define REG_ADC_WEIGHT_1 0x15B
307 #define REG_DEC_POWER_MEASURE_DURATION_0 0x15C
308 #define REG_LNA_GAIN 0x15D
309 #define REG_CH1_ADC_POWER 0x160
310 #define REG_CH1_RX_FILTER_POWER 0x161
311 #define REG_CH2_ADC_POWER 0x162
312 #define REG_CH2_RX_FILTER_POWER 0x163
313 #define REG_RX_QUAD_CAL_LEVEL 0x168
314 #define REG_CALIBRATION_CONFIG_1 0x169
315 #define REG_CALIBRATION_CONFIG_2 0x16A
316 #define REG_CALIBRATION_CONFIG_3 0x16B
317 #define REG_CALIB_COUNT 0x16C
318 #define REG_SETTLE_COUNT 0x16D
319 #define REG_RX_QUAD_GAIN1 0x16E
320 #define REG_RX_QUAD_GAIN2 0x16F
321 #define REG_RX1_INPUT_A_PHASE_CORR 0x170
322 #define REG_RX1_INPUT_A_GAIN_CORR 0x171
323 #define REG_RX2_INPUT_A_PHASE_CORR 0x172
324 #define REG_RX2_INPUT_A_GAIN_CORR 0x173
325 #define REG_RX1_INPUT_A_Q_OFFSET 0x174
326 #define REG_RX1_INPUT_A_OFFSETS 0x175
327 #define REG_INPUT_A_OFFSETS_1 0x176
328 #define REG_RX2_INPUT_A_OFFSETS 0x177
329 #define REG_RX2_INPUT_A_I_OFFSET 0x178
330 #define REG_RX1_INPUT_BC_PHASE_CORR 0x179
331 #define REG_RX1_INPUT_BC_GAIN_CORR 0x17A
332 #define REG_RX2_INPUT_BC_PHASE_CORR 0x17B
333 #define REG_RX2_INPUT_BC_GAIN_CORR 0x17C
334 #define REG_RX1_INPUT_BC_Q_OFFSET 0x17D
335 #define REG_RX1_INPUT_BC_OFFSETS 0x17E
336 #define REG_INPUT_BC_OFFSETS_1 0x17F
337 #define REG_RX2_INPUT_BC_OFFSETS 0x180
338 #define REG_RX2_INPUT_BC_I_OFFSET 0x181
339 #define REG_FORCE_BITS 0x182
340 #define REG_WAIT_COUNT 0x185
341 #define REG_RF_DC_OFFSET_COUNT 0x186
342 #define REG_RF_DC_OFFSET_CONFIG_1 0x187
343 #define REG_RF_DC_OFFSET_ATTEN 0x188
344 #define REG_INVERT_BITS 0x189
345 #define REG_DC_OFFSET_CONFIG2 0x18B
346 #define REG_RF_CAL_GAIN_INDEX 0x18C
347 #define REG_SOI_THRESH 0x18D
348 #define REG_BB_DC_OFFSET_SHIFT 0x190
349 #define REG_BB_DC_OFFSET_FAST_SETTLE_SHIFT 0x191
350 #define REG_BB_FAST_SETTLE_DUR 0x192
351 #define REG_BB_DC_OFFSET_COUNT 0x193
352 #define REG_BB_DC_OFFSET_ATTEN 0x194
353 #define REG_RX1_BB_DC_WORD_I_MSB 0x19A
354 #define REG_RX1_BB_DC_WORD_I_LSB 0x19B
355 #define REG_RX1_BB_DC_WORD_Q_MSB 0x19C
356 #define REG_RX1_BB_DC_WORD_Q_LSB 0x19D
357 #define REG_RX2_BB_DC_WORD_I_MSB 0x19E
358 #define REG_RX2_BB_DC_WORD_I_LSB 0x19F
359 #define REG_RX2_BB_DC_WORD_Q_MSB 0x1A0
360 #define REG_RX2_BB_DC_WORD_Q_LSB 0x1A1
361 #define REG_BB_TRACK_CORR_WORD_I_MSB 0x1A2
362 #define REG_BB_TRACK_CORR_WORD_I_LSB 0x1A3
363 #define REG_BB_TRACK_CORR_WORD_Q_MSB 0x1A4
364 #define REG_BB_TRACK_CORR_WORD_Q_LSB 0x1A5
365 #define REG_RX1_RSSI_SYMBOL 0x1A7
366 #define REG_RX1_RSSI_PREAMBLE 0x1A8
367 #define REG_RX2_RSSI_SYMBOL 0x1A9
368 #define REG_RX2_RSSI_PREAMBLE 0x1AA
369 #define REG_SYMBOL_LSB 0x1AB
370 #define REG_PREAMBLE_LSB 0x1AC
371 #define REG_RX_PATH_GAIN_MSB 0x1AD
372 #define REG_RX_PATH_GAIN_LSB 0x1AE
373 #define REG_RX_DIFF_LNA_FORCE 0x1B0
374 #define REG_RX_LNA_BIAS_COARSE 0x1B1
375 #define REG_RX_LNA_BIAS_FINE_0 0x1B2
376 #define REG_RX_LNA_BIAS_FINE_1 0x1B3
377 #define REG_RX_MIX_GM_CONFIG 0x1C0
378 #define REG_RX1_MIX_GM_FORCE 0x1C1
379 #define REG_RX1_MIX_GM_BIAS_FORCE 0x1C2
380 #define REG_RX2_MIX_GM_FORCE 0x1C3
381 #define REG_RX2_MIX_GM_BIAS_FORCE 0x1C4
382 #define REG_INPUT_A_MSBS 0x1C8
383 #define REG_INPUT_A_RX1_I 0x1C9
384 #define REG_INPUT_A_RX1_Q 0x1CA
385 #define REG_INPUT_A_RX2_I 0x1CB
386 #define REG_INPUT_A_RX2_Q 0x1CC
387 #define REG_INPUTS_BC_RX1_I 0x1CD
388 #define REG_BAND1_RX1_Q 0x1CE
389 #define REG_INPUTS_BC_RX2_I 0x1CF
390 #define REG_INPUTS_BC_RX2_Q 0x1D0
391 #define REG_INPUTS_BC_MSBS 0x1D1
392 #define REG_FORCE_OS_DAC 0x1D2
393 #define REG_RX_MIX_LO_CM 0x1D5
394 #define REG_RX_CGB_SEG_ENABLE 0x1D6
395 #define REG_RX_MIX_INPUTBIAS 0x1D7
396 #define REG_RX_TIA_CONFIG 0x1DB
397 #define REG_TIA1_C_LSB 0x1DC
398 #define REG_TIA1_C_MSB 0x1DD
399 #define REG_TIA2_C_LSB 0x1DE
400 #define REG_TIA2_C_MSB 0x1DF
401 #define REG_RX1_BBF_R1A 0x1E0
402 #define REG_RX2_BBF_R1A 0x1E1
403 #define REG_RX1_TUNE_CTRL 0x1E2
404 #define REG_RX2_TUNE_CTRL 0x1E3
405 #define REG_RX1_BBF_R5 0x1E4
406 #define REG_RX2_BBF_R5 0x1E5
407 #define REG_RX_BBF_R2346 0x1E6
408 #define REG_RX_BBF_C1_MSB 0x1E7
409 #define REG_RX_BBF_C1_LSB 0x1E8
410 #define REG_RX_BBF_C2_MSB 0x1E9
411 #define REG_RX_BBF_C2_LSB 0x1EA
412 #define REG_RX_BBF_C3_MSB 0x1EB
413 #define REG_RX_BBF_C3_LSB 0x1EC
414 #define REG_RX_BBF_CC1_CTR 0x1ED
415 #define REG_RX_BBF_POW_RZ_BYTE0 0x1EE
416 #define REG_RX_BBF_CC2_CTR 0x1EF
417 #define REG_RX_BBF_POW_RZ_BYTE1 0x1F0
418 #define REG_RX_BBF_CC3_CTR 0x1F1
419 #define REG_RX_BBF_R5_TUNE 0x1F2
420 #define REG_RX_BBF_TUNE 0x1F3
421 #define REG_RX1_BBF_MAN_GAIN 0x1F4
422 #define REG_RX2_BBF_MAN_GAIN 0x1F5
423 #define REG_RX_BBF_TUNE_DIVIDE 0x1F8
424 #define REG_RX_BBF_TUNE_CONFIG 0x1F9
425 #define REG_POLE_GAIN 0x1FA
426 #define REG_RX_BBBW_MHZ 0x1FB
427 #define REG_RX_BBBW_KHZ 0x1FC
428 #define REG_FB_DAC_CLK_DELAY1 0x201
429 #define REG_FB_DAC_CLK_DELAY2 0x202
430 #define REG_FLASH_SAMPLE_CLK_DELAY_3P 0x203
431 #define REG_FLASH_SAMPLE_CLK_DELAY_3N 0x204
432 #define REG_TEST_MUX_2I 0x205
433 #define REG_TEST_MUX_2Q 0x206
434 #define REG_INTEGRATOR_1_RESISTANCE 0x207
435 #define REG_INTEGRATOR_1_CAPACITANCE 0x208
436 #define REG_INTEGRATOR_23_RESISTANCE 0x209
437 #define REG_INTEGRATOR_2_RESISTANCE 0x20A
438 #define REG_INTEGRATOR_2_CAPACITANCE 0x20B
439 #define REG_INTEGRATOR_3_RESISTANCE 0x20C
440 #define REG_INTEGRATOR_3_CAPACITANCE 0x20D
441 #define REG_INTEGRATOR_AMP_CC 0x20E
442 #define REG_INT_1_FB_DAC_NMOS_CURRENT_SOURCE 0x20F
443 #define REG_INT_1_FB_DAC_NMOS_CASOADE_BIAS_CURRENT 0x210
444 #define REG_INT_1_FB_DAC_PMOS_CURRENT_SOURCE 0x211
445 #define REG_INT_2_FB_DAC_NMOS_CURRENT_SOURCE 0x212
446 #define REG_INT_2_FB_DAC_NMOS_CASCODE_BIAS_CURRENT 0x213
447 #define REG_INT_2_FB_DAC_PMOS_CURRENT_SOURCE 0x214
448 #define REG_INT_3_FB_DAC_NMOS_CURRENT_SOURCE 0x215
449 #define REG_INT_3_FB_DAC_NMOS_CASCODE_BIAS_CURRENT 0x216
450 #define REG_INT_3_FB_DAC_PMOS_CURRENT_SOURCE 0x217
451 #define REG_FB_DAC_BIAS_CURRENT 0x218
452 #define REG_INT_1_1ST_STAGE_CURRENT 0x219
453 #define REG_INT_1_1ST_STAGE_CASCODE_CURRENT 0x21A
454 #define REG_INT_1_2ND_STAGE_CURRENT 0x21B
455 #define REG_INTEGRATOR_2_1ST_STAGE_CURRENT 0x21C
456 #define REG_INT_2_1ST_STAGE_CASCODE_CURRENT 0x21D
457 #define REG_INT_2_2ND_STAGE_CURRENT 0x21E
458 #define REG_INT_3_1ST_STAGE_CURRENT 0x21F
459 #define REG_INT_3_1ST_STAGE_CASCODE_CURRENT 0x220
460 #define REG_INT_3_2ND_STAGE_CURRENT 0x221
461 #define REG_FLASH_BIAS_CURRENT 0x222
462 #define REG_FLASH_LADDER_BIAS 0x223
463 #define REG_FLASH_LADDER_CASCODE_CURRENT 0x224
464 #define REG_FLASH_LADDER_BIAS2 0x225
465 #define REG_RESET 0x226
466 #define REG_RX_PFD_CONFIG 0x230
467 #define REG_RX_INTEGER_BYTE_0 0x231
468 #define REG_RX_INTEGER_BYTE_1 0x232
469 #define REG_RX_FRACT_BYTE_0 0x233
470 #define REG_RX_FRACT_BYTE_1 0x234
471 #define REG_RX_FRACT_BYTE_2 0x235
472 #define REG_RX_FORCE_ALC 0x236
473 #define REG_RX_FORCE_VCO_TUNE_0 0x237
474 #define REG_RX_FORCE_VCO_TUNE_1 0x238
475 #define REG_RX_ALC_VARACTOR 0x239
476 #define REG_RX_VCO_OUTPUT 0x23A
477 #define REG_RX_CP_CURRENT 0x23B
478 #define REG_RX_CP_OFFSET 0x23C
479 #define REG_RX_CP_CONFIG 0x23D
480 #define REG_RX_LOOP_FILTER_1 0x23E
481 #define REG_RX_LOOP_FILTER_2 0x23F
482 #define REG_RX_LOOP_FILTER_3 0x240
483 #define REG_RX_DITHERCP_CAL 0x241
484 #define REG_RX_VCO_BIAS_1 0x242
485 #define REG_RX_CAL_STATUS 0x244
486 #define REG_RX_VCO_CAL_REF 0x245
487 #define REG_RX_VCO_PD_OVERRIDES 0x246
488 #define REG_RX_CP_OVERRANGE_VCO_LOCK 0x247
489 #define REG_RX_VCO_LDO 0x248
490 #define REG_RX_VCO_CAL 0x249
491 #define REG_RX_LOCK_DETECT_CONFIG 0x24A
492 #define REG_RX_CP_LEVEL_DETECT 0x24B
493 #define REG_RX_DSM_SETUP_0 0x24C
494 #define REG_RX_DSM_SETUP_1 0x24D
495 #define REG_RX_CORRECTION_WORD0 0x24E
496 #define REG_RX_CORRECTION_WORD1 0x24F
497 #define REG_RX_VCO_VARACTOR_CTRL_0 0x250
498 #define REG_RX_VCO_VARACTOR_CTRL_1 0x251
499 #define REG_RX_FAST_LOCK_SETUP 0x25A
500 #define REG_RX_FAST_LOCK_SETUP_INIT_DELAY 0x25B
501 #define REG_RX_FAST_LOCK_PROGRAM_ADDR 0x25C
502 #define REG_RX_FAST_LOCK_PROGRAM_DATA 0x25D
503 #define REG_RX_FAST_LOCK_PROGRAM_READ 0x25E
504 #define REG_RX_FAST_LOCK_PROGRAM_CTRL 0x25F
505 #define REG_RX_LO_GEN_POWER_MODE 0x261
506 #define REG_TX_PFD_CONFIG 0x270
507 #define REG_TX_INTEGER_BYTE_0 0x271
508 #define REG_TX_INTEGER_BYTE_1 0x272
509 #define REG_TX_FRACT_BYTE_0 0x273
510 #define REG_TX_FRACT_BYTE_1 0x274
511 #define REG_TX_FRACT_BYTE_2 0x275
512 #define REG_TX_FORCE_ALC 0x276
513 #define REG_TX_FORCE_VCO_TUNE_0 0x277
514 #define REG_TX_FORCE_VCO_TUNE_1 0x278
515 #define REG_TX_ALCVARACT_OR 0x279
516 #define REG_TX_VCO_OUTPUT 0x27A
517 #define REG_TX_CP_CURRENT 0x27B
518 #define REG_TX_CP_OFFSET 0x27C
519 #define REG_TX_CP_CONFIG 0x27D
520 #define REG_TX_LOOP_FILTER_1 0x27E
521 #define REG_TX_LOOP_FILTER_2 0x27F
522 #define REG_TX_LOOP_FILTER_3 0x280
523 #define REG_TX_DITHERCP_CAL 0x281
524 #define REG_TX_VCO_BIAS_1 0x282
525 #define REG_TX_VCO_BIAS_2 0x283
526 #define REG_TX_CAL_STATUS 0x284
527 #define REG_TX_VCO_CAL_REF 0x285
528 #define REG_TX_VCO_PD_OVERRIDES 0x286
529 #define REG_TX_CP_OVERRANGE_VCO_LOCK 0x287
530 #define REG_TX_VCO_LDO 0x288
531 #define REG_TX_VCO_CAL 0x289
532 #define REG_TX_LOCK_DETECT_CONFIG 0x28A
533 #define REG_TX_CP_LEVEL_DETECT 0x28B
534 #define REG_TX_DSM_SETUP_0 0x28C
535 #define REG_TX_DSM_SETUP_1 0x28D
536 #define REG_TX_CORRECTION_WORD0 0x28E
537 #define REG_TX_CORRECTION_WORD1 0x28F
538 #define REG_TX_VCO_VARACTOR_CTRL_0 0x290
539 #define REG_TX_VCO_VARACTOR_CTRL_1 0x291
540 #define REG_DCXO_COARSE_TUNE 0x292
541 #define REG_DCXO_FINE_TUNE_HIGH 0x293
542 #define REG_DCXO_FINE_TUNE_LOW 0x294
543 #define REG_DCXO_CONFIG 0x295
544 #define REG_DCXO_TEMPCO_WRITE 0x296
545 #define REG_DCXO_TEMPCO_READ 0x297
546 #define REG_DCXO_TEMPCO_ADDR 0x298
547 #define REG_DELTA_T_READ 0x299
548 #define REG_TX_FAST_LOCK_SETUP 0x29A
549 #define REG_TX_FAST_LOCK_SETUP_INIT_DELAY 0x29B
550 #define REG_TX_FAST_LOCK_PROGRAM_ADDR 0x29C
551 #define REG_TX_FAST_LOCK_PROGRAM_DATA 0x29D
552 #define REG_TX_FAST_LOCK_PROGRAM_READ 0x29E
553 #define REG_TX_FAST_LOCK_PROGRAM_CTRL 0x29F
554 #define REG_TX_LO_GEN_POWER_MODE 0x2A1
555 #define REG_BANDGAP_CONFIG0 0x2A6
556 #define REG_BANDGAP_CONFIG1 0x2A8
557 #define REG_REF_DIVIDE_CONFIG_1 0x2AB
558 #define REG_REF_DIVIDE_CONFIG_2 0x2AC
559 #define REG_GAIN_RX1 0x2B0
560 #define REG_LPF_GAIN_RX1 0x2B1
561 #define REG_DIG_GAIN_RX1 0x2B2
562 #define REG_FAST_ATTACK_STATE 0x2B3
563 #define REG_SLOW_LOOP_STATE 0x2B4
564 #define REG_GAIN_RX2 0x2B5
565 #define REG_LPF_GAIN_RX2 0x2B6
566 #define REG_DIG_GAIN_RX2 0x2B7
567 #define REG_OVRG_SIGS_RX1 0x2B8
568 #define REG_OVRG_SIGS_RX2 0x2B9
569 #define REG_CTRL 0x3DF
570 #define REG_BIST_CONFIG 0x3F4
571 #define REG_OBSERVE_CONFIG 0x3F5
572 #define REG_BIST_AND_DATA_PORT_TEST_CONFIG 0x3F6
573 #define REG_DAC_TEST_0 0x3FC
574 #define REG_DAC_TEST_1 0x3FD
575 #define REG_DAC_TEST_2 0x3FE
580 #define SOFT_RESET (1 << 7)
581 #define WIRE3_SPI (1 << 6)
582 #define LSB_FIRST (1 << 5)
583 #define _LSB_FIRST (1 << 2)
584 #define _WIRE3_SPI (1 << 1)
585 #define _SOFT_RESET (1 << 0)
590 #define TX2_MONITOR_ENABLE (1 << 6)
591 #define TX1_MONITOR_ENABLE (1 << 5)
592 #define MCS_RF_ENABLE (1 << 3)
593 #define MCS_BBPLL_ENABLE (1 << 2)
594 #define MCS_DIGITAL_CLK_ENABLE (1 << 1)
595 #define MCS_BB_ENABLE (1 << 0)
600 #define THB2_EN (1 << 3)
601 #define THB1_EN (1 << 2)
602 #define TX_CHANNEL_ENABLE(x) (((x) & 0x3) << 6)
603 #define THB3_ENABLE_INTERP(x) (((x) & 0x3) << 4)
604 #define TX_FIR_ENABLE_INTERPOLATION(x) (((x) & 0x3) << 0)
613 #define RHB2_EN (1 << 3)
614 #define RHB1_EN (1 << 2)
615 #define RX_CHANNEL_ENABLE(x) (((x) & 0x3) << 6)
616 #define DEC3_ENABLE_DECIMATION(x) (((x) & 0x3) << 4)
617 #define RX_FIR_ENABLE_DECIMATION(x) (((x) & 0x3) << 0)
626 #define TX_OUTPUT (1 << 6)
627 #define RX_INPUT(x) (((x) & 0x3F) << 0)
632 #define TX_VCO_DIVIDER(x) (((x) & 0xF) << 4)
633 #define RX_VCO_DIVIDER(x) (((x) & 0xF) << 0)
638 #define DATA_CLK_DELAY(x) (((x) & 0xF) << 4)
639 #define RX_DATA_DELAY(x) (((x) & 0xF) << 0)
644 #define FB_CLK_DELAY(x) (((x) & 0xF) << 4)
645 #define TX_DATA_DELAY(x) (((x) & 0xF) << 0)
650 #define XO_BYPASS (1 << 4)
651 #define DIGITAL_POWER_UP (1 << 2)
652 #define CLOCK_ENABLE_DFLT (1 << 1)
653 #define BBPLL_ENABLE (1 << 0)
658 #define CLKOUT_ENABLE (1 << 4)
659 #define DAC_CLK_DIV2 (1 << 3)
660 #define CLKOUT_SELECT(x) (((x) & 0x7) << 5)
661 #define BBPLL_DIVIDER(x) (((x) & 0x7) << 0)
666 #define START_TEMP_READING (1 << 0)
671 #define TEMP_SENSE_PERIODIC_ENABLE (1 << 0)
672 #define MEASUREMENT_TIME_INTERVAL(x) (((x) & 0x7F) << 1)
677 #define TEMP_SENSOR_DECIMATION(x) (((x) & 0x7) << 0)
682 #define PP_TX_SWAP_IQ (1 << 7)
683 #define PP_RX_SWAP_IQ (1 << 6)
684 #define TX_CHANNEL_SWAP (1 << 5)
685 #define RX_CHANNEL_SWAP (1 << 4)
686 #define RX_FRAME_PULSE_MODE (1 << 3)
687 #define R2T2_TIMING (1 << 2)
688 #define INVERT_DATA_BUS (1 << 1)
689 #define INVERT_DATA_CLK (1 << 0)
694 #define FDD_ALT_WORD_ORDER (1 << 7)
695 #define INVERT_RX1 (1 << 6)
696 #define INVERT_RX2 (1 << 5)
697 #define INVERT_TX1 (1 << 4)
698 #define INVERT_TX2 (1 << 3)
699 #define INVERT_RX_FRAME (1 << 2)
700 #define DELAY_RX_DATA(x) (((x) & 0x3) << 0)
705 #define FDD_RX_RATE_2TX_RATE (1 << 7)
706 #define SWAP_PORTS (1 << 6)
707 #define SINGLE_DATA_RATE (1 << 5)
708 #define LVDS_MODE (1 << 4)
709 #define HALF_DUPLEX_MODE (1 << 3)
710 #define SINGLE_PORT_MODE (1 << 2)
711 #define FULL_PORT (1 << 1)
712 #define FULL_DUPLEX_SWAP_BITS (1 << 0)
717 #define FDD_MODE (1 << 0)
722 #define ENABLE_RX_DATA_PORT_FOR_CAL (1 << 7)
723 #define FORCE_RX_ON (1 << 6)
724 #define FORCE_TX_ON (1 << 5)
725 #define ENABLE_ENSM_PIN_CTRL (1 << 4)
726 #define LEVEL_MODE (1 << 3)
727 #define FORCE_ALERT_STATE (1 << 2)
728 #define AUTO_GAIN_LOCK (1 << 1)
729 #define TO_ALERT (1 << 0)
734 #define FDD_EXTERNAL_CTRL_ENABLE (1 << 7)
735 #define POWER_DOWN_RX_SYNTH (1 << 6)
736 #define POWER_DOWN_TX_SYNTH (1 << 5)
737 #define TXNRX_SPI_CTRL (1 << 4)
738 #define SYNTH_ENABLE_PIN_CTRL_MODE (1 << 3)
739 #define DUAL_SYNTH_MODE (1 << 2)
740 #define RX_SYNTH_READY_MASK (1 << 1)
741 #define TX_SYNTH_READY_MASK (1 << 0)
746 #define RX_BB_TUNE_CAL (1 << 7)
747 #define TX_BB_TUNE_CAL (1 << 6)
748 #define RX_QUAD_CAL (1 << 5)
749 #define TX_QUAD_CAL (1 << 4)
750 #define RX_GAIN_STEP_CAL (1 << 3)
751 #define TXMON_CAL (1 << 2)
752 #define RFDC_CAL (1 << 1)
753 #define BBDC_CAL (1 << 0)
759 #define CALIBRATION_SEQUENCE_STATE(x) (((x) & 0xF) << 4)
760 #define ENSM_STATE(x) (((x) & 0xF) << 0)
761 #define ENSM_STATE_SLEEP_WAIT 0x0
762 #define ENSM_STATE_ALERT 0x5
763 #define ENSM_STATE_TX 0x6
764 #define ENSM_STATE_TX_FLUSH 0x7
765 #define ENSM_STATE_RX 0x8
766 #define ENSM_STATE_RX_FLUSH 0x9
767 #define ENSM_STATE_FDD 0xA
768 #define ENSM_STATE_FDD_FLUSH 0xB
769 #define ENSM_STATE_INVALID 0xFF
770 #define ENSM_STATE_SLEEP 0x80
775 #define AUXDAC_2_WORD_MSB(x) (((x) & 0x3F) << 2)
776 #define AUXDAC_1_WORD(x) (((x) & 0x3) << 0)
781 #define COMP_CTRL_1 (1 << 5)
782 #define AUXDAC1_STP_FACTOR (1 << 4)
783 #define AUXDAC_1_VREF(x) (((x) & 0x3) << 2)
784 #define AUXDAC_1_WORD_LSB(x) (((x) & 0x3) << 0)
789 #define COMP_CTRL_2 (1 << 5)
790 #define AUXDAC2_STP_FACTOR (1 << 4)
791 #define AUXDAC_2_VREF(x) (((x) & 0xF) << 2)
792 #define AUXDAC_2_WORD_LSB(x) (((x) & 0x3) << 0)
797 #define AUXADC_CLOCK_DIVIDER(x) (((x) & 0x3F) << 0)
802 #define AUXADC_POWER_DOWN (1 << 0)
803 #define AUX_ADC_DECIMATION(x) (((x) & 0x7) << 1)
808 #define AUXADC_WORD_LSB(x) (((x) & 0xF) << 0)
813 #define GPO_ENABLE_AUTO_RX(x) (((x) & 0xF) << 4)
814 #define GPO_ENABLE_AUTO_TX(x) (((x) & 0xF) << 0)
819 #define INVERT_BYPASSED_LNA_POLARITY (1 << 6)
820 #define AGC_ATTACK_DELAY(x) (((x) & 0x3F) << 0)
825 #define AUXDAC_MANUAL_BAR(x) (((x) & 0x3) << 6)
826 #define AUXDAC_AUTO_TX_BAR(x) (((x) & 0x3) << 4)
827 #define AUXDAC_AUTO_RX_BAR(x) (((x) & 0x3) << 2)
828 #define AUXDAC_INIT_BAR(x) (((x) & 0x3) << 0)
833 #define AUXDAC_MANUAL_SELECT (1 << 7)
834 #define EXTERNAL_LNA2_CTRL (1 << 6)
835 #define EXTERNAL_LNA1_CTRL (1 << 5)
836 #define GPO_MANUAL_SELECT (1 << 4)
837 #define OPEN(x) (((x) & 0xF) << 0)
842 #define GPO_MANUAL_CTRL(x) (((x) & 0xF) << 4)
843 #define GPO_INIT_STATE(x) (((x) & 0xF) << 0)
848 #define EN_CTRL7 (1 << 7)
849 #define EN_CTRL6 (1 << 6)
850 #define EN_CTRL5 (1 << 5)
851 #define EN_CTRL4 (1 << 4)
852 #define EN_CTRL3 (1 << 3)
853 #define EN_CTRL2 (1 << 2)
854 #define EN_CTRL1 (1 << 1)
855 #define EN_CTRL0 (1 << 0)
860 #define PRODUCT_ID_MASK 0xF8
861 #define PRODUCT_ID_9361 0x08
862 #define REV_MASK 0x07
867 #define REFERENCE_CLOCK_CYCLES_PER_US(x) (((x) & 0x7F) << 0)
872 #define CLK_OUT_DRIVE (1 << 7)
873 #define DATACLK_DRIVE (1 << 6)
874 #define DATA_PORT_DRIVE (1 << 2)
875 #define DATACLK_SLEW(x) (((x) & 0x3) << 4)
876 #define DATA_PORT_SLEW(x) (((x) & 0x3) << 0)
881 #define RX_ON_CHIP_TERM (1 << 5)
882 #define LVDS_BYPASS_BIAS_R (1 << 4)
883 #define LVDS_TX_LO_VCM (1 << 3)
884 #define CLK_OUT_SLEW(x) (((x) & 0x3) << 6)
885 #define LVDS_BIAS(x) (((x) & 0x7) << 0)
890 #define INIT_BB_FO_CAL (1 << 2)
891 #define BBPLL_RESET_BAR (1 << 0)
896 #define REF_FREQ_SCALER(x) (((x) & 0x3) << 0)
901 #define CHARGE_PUMP_CURRENT(x) (((x) & 0x3F) << 0)
906 #define MCS_REFCLK_SCALE_EN (1 << 7)
911 #define C1_WORD(x) (((x) & 0x7) << 5)
912 #define R1_WORD(x) (((x) & 0x1F) << 0)
917 #define R2_WORD (1 << 7)
918 #define C2_WORD(x) (((x) & 0x1F) << 2)
919 #define C1_WORD_LSB(x) (((x) & 0x3) << 0)
924 #define BYPASS_C3 (1 << 7)
925 #define BYPASS_R2 (1 << 6)
926 #define C3_WORD(x) (((x) & 0xF) << 2)
927 #define R2_WORD_LSB(x) (((x) & 0x3) << 0)
932 #define FREQ_CAL_ENABLE (1 << 7)
933 #define FREQ_CAL_RESET (1 << 4)
934 #define FREQ_CAL_COUNT_LENGTH(x) (((x) & 0x3) << 5)
939 #define CAL_CLOCK_DIV_4 (1 << 4)
944 #define RX_LO_POWER_DOWN (1 << 4)
945 #define RX_SYNTH_VCO_ALC_POWER_DOWN (1 << 3)
946 #define RX_SYNTH_PTAT_POWER_DOWN (1 << 2)
947 #define RX_SYNTH_VCO_POWER_DOWN (1 << 1)
948 #define RX_SYNTH_VCO_LDO_POWER_DOWN (1 << 0)
953 #define TX_LO_POWER_DOWN (1 << 4)
954 #define TX_SYNTH_VCO_ALC_POWER_DOWN (1 << 3)
955 #define TX_SYNTH_PTAT_POWER_DOWN (1 << 2)
956 #define TX_SYNTH_VCO_POWER_DOWN (1 << 1)
957 #define TX_SYNTH_VCO_LDO_POWER_DOWN (1 << 0)
962 #define RX_OFFSET_DAC_CGIN_POWER_DOWN(x) (((x) & 0x3) << 6)
963 #define RX_LMT_OVERLOAD_POWER_DOWN(x) (((x) & 0x3) << 4)
964 #define RX_MIXER_GM_POWER_DOWN(x) (((x) & 0x3) << 2)
965 #define RX_CGB_POWER_DOWN(x) (((x) & 0x3) << 0)
970 #define RX_BBF_POWER_DOWN(x) (((x) & 0x3) << 6)
971 #define RX_TIA_POWER_DOWN(x) (((x) & 0x3) << 4)
972 #define RX_MIXER_POWER_DOWN(x) (((x) & 0x3) << 2)
973 #define RX_OFFSET_DAC_CGOUT_POWER_DOWN(x) (((x) & 0x3) << 0)
978 #define TX_SECONDARY_FILTER_POWER_DOWN(x) (((x) & 0x3) << 6)
979 #define TX_BBF_POWER_DOWN(x) (((x) & 0x3) << 4)
980 #define TX_DAC_POWER_DOWN(x) (((x) & 0x3) << 2)
981 #define TX_DAC_BIAS_POWER_DOWN(x) (((x) & 0x3) << 0)
986 #define RX_EXT_VCO_BUFFER_POWER_DOWN (1 << 5)
987 #define TX_EXT_VCO_BUFFER_POWER_DOWN (1 << 4)
988 #define TX_MONITOR_POWER_DOWN(x) (((x) & 0x3) << 2)
989 #define TX_UPCONVERTER_POWER_DOWN(x) (((x) & 0x3) << 0)
994 #define RX_LNA_POWER_DOWN (1 << 6)
995 #define DCXO_POWER_DOWN (1 << 1)
996 #define MASTER_BIAS_POWER_DOWN (1 << 0)
997 #define RX_CALIBRATION_POWER_DOWN(x) (((x) & 0x3) << 2)
1002 #define BBPLL_LOCK (1 << 7)
1003 #define CH_1_INT3 (1 << 6)
1004 #define CH1_HB3 (1 << 5)
1005 #define CH1_HB2 (1 << 4)
1006 #define CH1_QEC (1 << 3)
1007 #define CH1_HB1 (1 << 2)
1008 #define CH1_TFIR (1 << 1)
1009 #define CH1_RFIR (1 << 0)
1014 #define CH2_INT3 (1 << 6)
1015 #define CH2_HB3 (1 << 5)
1016 #define CH2_HB2 (1 << 4)
1017 #define CH2_QEC (1 << 3)
1018 #define CH2_HB1 (1 << 2)
1019 #define CH2_TFIR (1 << 1)
1020 #define CH2_RFIR (1 << 0)
1025 #define TX_FIR_GAIN_6DB (1 << 0)
1026 #define FIR_START_CLK (1 << 1)
1027 #define FIR_WRITE (1 << 2)
1028 #define FIR_SELECT(x) (((x) & 0x3) << 3)
1029 #define FIR_NUM_TAPS(x) (((x) & 0x7) << 5)
1034 #define TX_MON_TRACK (1 << 5)
1035 #define TX_MON_LOW_GAIN(x) (((x) & 0x1F) << 0)
1040 #define TX_MON_HIGH_GAIN(x) (((x) & 0x1F) << 0)
1045 #define TX_LEVEL_THRESH(x) (((x) & 0x3F) << 2)
1046 #define TX_MON_DELAY_COUNTER(x) (((x) & 0x3) << 0)
1051 #define TX_RSSI_2 (1 << 1)
1052 #define TX_RSSI_1 (1 << 0)
1057 #define TX2_MON_ENABLE (1 << 7)
1058 #define TX1_MON_ENABLE (1 << 5)
1059 #define ONE_SHOT_MODE (1 << 6)
1060 #define TX_MON_DURATION(x) (((x) & 0xF) << 0)
1065 #define TX_MON_1_LO_CM(x) (((x) & 0x3F) << 2)
1066 #define TX_MON_1_GAIN(x) (((x) & 0x3) << 0)
1071 #define TX_MON_2_LO_CM(x) (((x) & 0x3F) << 2)
1072 #define TX_MON_2_GAIN(x) (((x) & 0x3) << 0)
1077 #define TX_1_ATTEN (1 << 0)
1082 #define TX_2_ATTEN (1 << 0)
1087 #define MASK_CLR_ATTEN_UPDATE (1 << 6)
1088 #define TX_ATTEN_OFFSET(x) (((x) & 0x3F) << 0)
1093 #define SEL_TX1_TX2 (1 << 6)
1098 #define IMMEDIATELY_UPDATE_TPC_ATTEN (1 << 6)
1103 #define TX_1_SYMBOL_ATTEN(x) (((x) & 0x7F) << 0)
1108 #define TX_2_SYMBOL_ATTEN(x) (((x) & 0x7F) << 0)
1113 #define USE_TX1_PIN_SYMBOL_ATTEN (1 << 3)
1114 #define USE_CTRL_IN_FOR_SYMBOL_ATTEN (1 << 1)
1115 #define ENABLE_SYMBOL_ATTEN (1 << 0)
1120 #define FORCE_OUT_2_TX2_OFFSET (1 << 7)
1121 #define FORCE_OUT_2_TX1_OFFSET (1 << 6)
1122 #define FORCE_OUT_2_TX2_PHASE_GAIN (1 << 5)
1123 #define FORCE_OUT_2_TX1_PHASE_GAIN (1 << 4)
1124 #define FORCE_OUT_1_TX2_OFFSET (1 << 3)
1125 #define FORCE_OUT_1_TX1_OFFSET (1 << 2)
1126 #define FORCE_OUT_1_TX2_PHASE_GAIN (1 << 1)
1127 #define FORCE_OUT_1_TX1_PHASE_GAIN (1 << 0)
1132 #define RX_NCO_FREQ(x) (((x) & 0x3) << 5)
1133 #define RX_NCO_PHASE_OFFSET(x) (((x) & 0x1F) << 0)
1138 #define FREE_RUN_ENABLE (1 << 7)
1139 #define SETTLE_MAIN_ENABLE (1 << 6)
1140 #define DC_OFFSET_ENABLE (1 << 5)
1141 #define GAIN_ENABLE (1 << 4)
1142 #define PHASE_ENABLE (1 << 3)
1143 #define QUAD_CAL_SOFT_RESET (1 << 2)
1144 #define M_DECIM(x) (((x) & 0x3) << 0)
1149 #define KEXP_TX(x) (((x) & 0x3) << 6)
1150 #define KEXP_TX_COMP(x) (((x) & 0x3) << 4)
1151 #define KEXP_DC_I(x) (((x) & 0x3) << 2)
1152 #define KEXP_DC_Q(x) (((x) & 0x3) << 0)
1157 #define INVERT_I_DATA (1 << 5)
1158 #define INVERT_Q_DATA (1 << 4)
1159 #define TX_NCO_FREQ(x) (((x) & 0x3) << 6)
1160 #define KEXP_PHASE(x) (((x) & 0x3) << 2)
1161 #define KEXP_AMP(x) (((x) & 0x3) << 0)
1166 #define TX1_LO_CONV (1 << 1)
1167 #define TX1_SSB_CONV (1 << 0)
1168 #define TX1_CONVERGENCE_COUNT(x) (((x) & 0x3F) << 2)
1173 #define TX2_LO_CONV (1 << 1)
1174 #define TX2_SSB_CONV (1 << 0)
1175 #define TX2_CONVERGENCE_COUNT(x) (((x) & 0x3F) << 2)
1180 #define RX_FULL_TABLELMT_TABLE_GAIN(x) (((x) & 0x7F) << 0)
1185 #define GM_STAGE_TIME_CON_OVERRIDE (1 << 5)
1186 #define GM_STAGE_MV_HP_POLE (1 << 4)
1187 #define GM_STAGE_LOWER_CM (1 << 3)
1188 #define BYPASS_BIAS_R (1 << 0)
1189 #define VBIAS_CTRL(x) (((x) & 0x3) << 1)
1194 #define THRESH_ACCUMULATOR(x) (((x) & 0xF) << 0)
1199 #define RX_LPF_GAIN(x) (((x) & 0x1F) << 0)
1204 #define TXDAC_VDS_I(x) (((x) & 0x3F) << 0)
1209 #define TXDAC_VDS_Q(x) (((x) & 0x3F) << 0)
1214 #define TXDAC_GN_I(x) (((x) & 0x3F) << 0)
1219 #define TXDAC_GN_Q(x) (((x) & 0x3F) << 0)
1224 #define OPAMPA_OUTPUT_BIAS(x) (((x) & 0x3) << 5)
1225 #define OPAMPA_RZ(x) (((x) & 0x3) << 3)
1226 #define OPAMP_A_CC(x) (((x) & 0x7) << 0)
1231 #define OPAMPB_OUTPUT_BIAS(x) (((x) & 0x3) << 5)
1232 #define OPAMPB_RZ(x) (((x) & 0x3) << 3)
1233 #define OPAMP_B_CC(x) (((x) & 0x7) << 0)
1238 #define OVERRIDE_ENABLE (1 << 7)
1239 #define R1(x) (((x) & 0x1F) << 0)
1244 #define R2(x) (((x) & 0x1F) << 0)
1249 #define R3(x) (((x) & 0x1F) << 0)
1254 #define R4(x) (((x) & 0x1F) << 0)
1259 #define RP(x) (((x) & 0x1F) << 0)
1264 #define C1(x) (((x) & 0x3F) << 0)
1269 #define C2(x) (((x) & 0x3F) << 0)
1274 #define CP(x) (((x) & 0x3F) << 0)
1279 #define PD_TUNE (1 << 2)
1280 #define TUNER_RESAMPLE (1 << 1)
1281 #define TUNER_RESAMPLE_PHASE (1 << 0)
1282 #define TUNE_CTRL(x) (((x) & 0x3) << 5)
1287 #define TX_BBF_BYPASS_BIAS_R (1 << 7)
1288 #define R2B_OVR (1 << 5)
1289 #define R2B(x) (((x) & 0x1F) << 0)
1294 #define BBF1_COMP_I (1 << 3)
1295 #define BBF1_COMP_Q (1 << 2)
1296 #define BBF2_COMP_I (1 << 1)
1297 #define BBF2_COMP_Q (1 << 0)
1302 #define BIAS(x) (((x) & 0x3) << 6)
1303 #define RGM(x) (((x) & 0x3) << 4)
1304 #define CC(x) (((x) & 0x3) << 2)
1305 #define AMPBIAS(x) (((x) & 0x3) << 0)
1310 #define RESISTOR(x) (((x) & 0xF) << 0)
1315 #define CAPACITOR(x) (((x) & 0x3F) << 0)
1320 #define LO_COMMON_MODE(x) (((x) & 0x3) << 5)
1325 #define EVALTIME (1 << 4)
1326 #define TX_BBF_TUNE_DIVIDER (1 << 0)
1327 #define TUNE_COMP_MASK(x) (((x) & 0x3) << 5)
1328 #define TUNER_MODE(x) (((x) & 0x7) << 1)
1333 #define WRITE_RX (1 << 2)
1334 #define START_RX_CLOCK (1 << 1)
1335 #define NUMBER_OF_TAPS(x) (((x) & 0x7) << 5)
1336 #define SELECT_RX_CH(x) (((x) & 0x3) << 3)
1341 #define FILTER_GAIN(x) (((x) & 0x3) << 0)
1346 #define DEC_PWR_FOR_LOW_PWR (1 << 7)
1347 #define DEC_PWR_FOR_LOCK_LEVEL (1 << 6)
1348 #define DEC_PWR_FOR_GAIN_LOCK_EXIT (1 << 5)
1349 #define SLOW_ATTACK_HYBRID_MODE (1 << 4)
1350 #define RX2_GAIN_CTRL_SETUP(x) (((x) & 0x3) << 2)
1351 #define RX1_GAIN_CTRL_SETUP(x) (((x) & 0x3) << 0)
1352 #define RX_GAIN_CTL_MASK 0x03
1353 #define RX2_GAIN_CTRL_SHIFT 2
1354 #define RX1_GAIN_CTRL_SHIFT 0
1355 #define RX_GAIN_CTL_MGC 0x00
1356 #define RX_GAIN_CTL_AGC_FAST_ATK 0x01
1357 #define RX_GAIN_CTL_AGC_SLOW_ATK 0x02
1358 #define RX_GAIN_CTL_AGC_SLOW_ATK_HYBD 0x03
1363 #define AGC_SOFT_RESET (1 << 7)
1364 #define AGC_GAIN_UNLOCK_CTRL (1 << 6)
1365 #define AGC_USE_FULL_GAIN_TABLE (1 << 3)
1366 #define DIG_GAIN_EN (1 << 2)
1367 #define MAN_GAIN_CTRL_RX2 (1 << 1)
1368 #define MAN_GAIN_CTRL_RX1 (1 << 0)
1373 #define INCDEC_LMT_GAIN (1 << 4)
1374 #define USE_AGC_FOR_LMTLPF_GAIN (1 << 3)
1375 #define MANUAL_INCR_STEP_SIZE(x) (((x) & 0x7) << 5)
1376 #define ADC_OVERRANGE_SAMPLE_SIZE(x) (((x) & 0x7) << 0)
1381 #define MAXIMUM_FULL_TABLELMT_TABLE_INDEX(x) (((x) & 0x7F) << 0)
1386 #define MANUAL_CTRL_IN_DECR_GAIN_STP_SIZE(x) (((x) & 0x7) << 5)
1387 #define PEAK_OVERLOAD_WAIT_TIME(x) (((x) & 0x1F) << 0)
1392 #define DIG_GAIN_STP_SIZE(x) (((x) & 0x7) << 5)
1393 #define MAXIMUM_DIGITAL_GAIN(x) (((x) & 0x1F) << 0)
1398 #define ENABLE_DIG_SAT_OVRG (1 << 7)
1399 #define AGC_LOCK_LEVEL_FAST_AGC_INNER_HIGH_THRESH_SLOW(x) (((x) & 0x7F) << 0)
1404 #define LMT_DETECTOR_SETTLING_TIME(x) (((x) & 0x7) << 5)
1405 #define DEC_STP_SIZE_FOR_LARGE_LMT_OVERLOAD(x) (((x) & 0x7) << 2)
1406 #define ADC_NOISE_CORRECTION_FACTOR(x) (((x) & 0x3) << 0)
1411 #define DECREMENT_STP_SIZE_FOR_SMALL_LPF_GAIN_CHANGE(x) (((x) & 0x7) << 4)
1412 #define LARGE_LPF_GAIN_STEP(x) (((x) & 0xF) << 0)
1417 #define FORCE_PD_RESET_RX2 (1 << 7)
1418 #define FORCE_PD_RESET_RX1 (1 << 6)
1419 #define SMALL_LMT_OVERLOAD_THRESH(x) (((x) & 0x3F) << 0)
1424 #define LARGE_LMT_OVERLOAD_THRESH(x) (((x) & 0x3F) << 0)
1429 #define POWER_MEAS_IN_STATE_5_MSB (1 << 7)
1430 #define RX1_MANUAL_FULL_TABLE_LMT_TABLE_GAIN_INDEX(x) (((x) & 0x7F) << 0)
1431 #define RX_FULL_TBL_IDX_MASK RX1_MANUAL_FULL_TABLE_LMT_TABLE_GAIN_INDEX(~0)
1436 #define POWER_MEAS_IN_STATE_5(x) (((x) & 0x7) << 5)
1437 #define RX1_MANUAL_LPF_GAIN(x) (((x) & 0x1F) << 0)
1438 #define RX_LPF_IDX_MASK RX1_MANUAL_LPF_GAIN(~0)
1443 #define FORCE_RX1_DIGITAL_GAIN (1 << 5)
1444 #define RX1_MANUALFORCED_DIGITAL_GAIN(x) (((x) & 0x1F) << 0)
1445 #define RX_DIGITAL_IDX_MASK RX1_MANUALFORCED_DIGITAL_GAIN(~0)
1449 #define RX2_MANUAL_FULL_TABLE_LMT_TABLE_GAIN_INDEX(x) (((x) & 0x7F) << 0)
1454 #define RX2_MANUAL_LPF_GAIN(x) (((x) & 0x1F) << 0)
1459 #define FORCE_RX2_DIGITAL_GAIN (1 << 5)
1460 #define RX2_MANUALFORCED_DIGITAL_GAIN(x) (((x) & 0x1F) << 0)
1465 #define ENABLE_GAIN_INC_AFTER_GAIN_LOCK (1 << 7)
1466 #define GOTO_OPT_GAIN_IF_ENERGY_LOST_OR_EN_AGC_HIGH (1 << 6)
1467 #define GOTO_SET_GAIN_IF_EN_AGC_HIGH (1 << 5)
1468 #define GOTO_SET_GAIN_IF_EXIT_RX_STATE (1 << 4)
1469 #define DONT_UNLOCK_GAIN_IF_ENERGY_LOST (1 << 3)
1470 #define GOTO_OPTIMIZED_GAIN_IF_EXIT_RX_STATE (1 << 2)
1471 #define DONT_UNLOCK_GAIN_IF_LG_ADC_OR_LMT_OVRG (1 << 1)
1472 #define ENABLE_INCR_GAIN (1 << 0)
1477 #define USE_LAST_LOCK_LEVEL_FOR_SET_GAIN (1 << 7)
1478 #define ENABLE_LMT_GAIN_INC_FOR_LOCK_LEVEL (1 << 6)
1479 #define GOTO_MAX_GAIN_OR_OPT_GAIN_IF_EN_AGC_HIGH (1 << 5)
1480 #define SETTLING_DELAY(x) (((x) & 0x1F) << 0)
1485 #define POST_LOCK_LEVEL_STP_SIZE_FOR_LPF_TABLE_FULL_TABLE(x) (((x) & 0x3) << 6)
1486 #define ENERGY_LOST_THRESH(x) (((x) & 0x3F) << 0)
1491 #define POST_LOCK_LEVEL_STP_FOR_LMT_TABLE(x) (((x) & 0x3) << 6)
1492 #define STRONGER_SIGNAL_THRESH(x) (((x) & 0x3F) << 0)
1497 #define DONT_UNLOCK_GAIN_IF_ADC_OVRG (1 << 7)
1498 #define LOW_POWER_THRESH(x) (((x) & 0x7F) << 0)
1503 #define DONT_UNLOCK_GAIN_IF_STRONGER_SIGNAL (1 << 7)
1508 #define FINAL_OVER_RANGE_COUNT(x) (((x) & 0x7) << 5)
1509 #define OPTIMIZE_GAIN_OFFSET(x) (((x) & 0xF) << 0)
1514 #define INCREMENT_GAIN_STP_LPFLMT(x) (((x) & 0x7) << 5)
1515 #define ENERGY_DETECT_COUNT(x) (((x) & 0x1F) << 0)
1520 #define AGCLL_MAX_INCREASE(x) (((x) & 0x3F) << 0)
1525 #define GAIN_LOCK_EXIT_COUNT(x) (((x) & 0x3F) << 0)
1530 #define INITIAL_LMT_GAIN_LIMIT(x) (((x) & 0x7F) << 0)
1535 #define PREVENT_GAIN_INC (1 << 7)
1536 #define AGC_INNER_LOW_THRESH(x) (((x) & 0x7F) << 0)
1541 #define LARGE_LMT_OVERLOAD_EXED_COUNTER(x) (((x) & 0xF) << 4)
1542 #define SMALL_LMT_OVERLOAD_EXED_COUNTER(x) (((x) & 0xF) << 0)
1547 #define LARGE_ADC_OVERLOAD_EXED_COUNTER(x) (((x) & 0xF) << 4)
1548 #define SMALL_ADC_OVERLOAD_EXED_COUNTER(x) (((x) & 0xF) << 0)
1553 #define IMMED_GAIN_CHANGE_IF_LG_LMT_OVERLOAD (1 << 7)
1554 #define IMMED_GAIN_CHANGE_IF_LG_ADC_OVERLOAD (1 << 3)
1555 #define AGC_INNER_HIGH_THRESH_EXED_STP_SIZE(x) (((x) & 0x7) << 4)
1556 #define AGC_INNER_LOW_THRESH_EXED_STP_SIZE(x) (((x) & 0x7) << 0)
1561 #define DOUBLE_GAIN_COUNTER (1 << 5)
1562 #define ENABLE_SYNC_FOR_GAIN_COUNTER (1 << 4)
1563 #define DIG_SATURATION_EXED_COUNTER(x) (((x) & 0xF) << 0)
1568 #define AGC_OUTER_HIGH_THRESH(x) (((x) & 0xF) << 4)
1569 #define AGC_OUTER_LOW_THRESH(x) (((x) & 0xF) << 0)
1574 #define AGC_OUTER_HIGH_THRESH_EXED_STP_SIZE(x) (((x) & 0xF) << 4)
1575 #define AGC_OUTER_LOW_THRESH_EXED_STP_SIZE(x) (((x) & 0xF) << 0)
1580 #define EXT_LNA_HIGH_GAIN(x) (((x) & 0x3F) << 0)
1585 #define EXT_LNA_LOW_GAIN(x) (((x) & 0x3F) << 0)
1590 #define GAIN_TABLE_ADDRESS(x) (((x) & 0x7F) << 0)
1595 #define EXT_LNA_CTRL (1 << 7)
1596 #define LNA_GAIN(x) (((x) & 0x3) << 5)
1597 #define MIXER_GM_GAIN(x) (((x) & 0x1F) << 0)
1602 #define TIA_GAIN (1 << 5)
1603 #define LPF_GAIN(x) (((x) & 0x1F) << 0)
1608 #define RF_DC_CAL (1 << 5)
1609 #define DIGITAL_GAIN(x) (((x) & 0x1F) << 0)
1614 #define TO_LNA_GAIN(x) (((x) >> 5) & 0x3)
1615 #define TO_MIXER_GM_GAIN(x) (((x) >> 0) & 0x1F)
1620 #define TO_LPF_GAIN(x) (((x) >> 0) & 0x1F)
1625 #define TO_DIGITAL_GAIN(x) (((x) >> 0) & 0x1F)
1630 #define WRITE_GAIN_TABLE (1 << 2)
1631 #define START_GAIN_TABLE_CLOCK (1 << 1)
1632 #define RECEIVER_SELECT(x) (((x) & 0x3) << 3)
1640 #define GM_SUB_TABLE_GAIN_WRITE(x) (((x) & 0x7F) << 0)
1645 #define GM_SUB_TABLE_BIAS_WRITE(x) (((x) & 0x1F) << 0)
1650 #define GM_SUB_TABLE_CTRL_WRITE(x) (((x) & 0x3F) << 0)
1655 #define GM_SUB_TABLE_GAIN_READ(x) (((x) & 0x7F) << 0)
1660 #define GM_SUB_TABLE_BIAS_READ(x) (((x) & 0x1F) << 0)
1665 #define GM_SUB_TABLE_CTRL_READ(x) (((x) & 0x3F) << 0)
1670 #define WRITE_GM_SUB_TABLE (1 << 2)
1671 #define START_GM_SUB_TABLE_CLOCK (1 << 1)
1676 #define CALIB_TABLE_GAIN_DIFFERROR_WORD(x) (((x) & 0x3F) << 0)
1681 #define CALIB_TABLE_GAIN_ERROR(x) (((x) & 0x1F) << 0)
1686 #define READ_SELECT (1 << 4)
1687 #define WRITE_MIXER_ERROR_TABLE (1 << 3)
1688 #define WRITE_LNA_ERROR_TABLE (1 << 2)
1689 #define WRITE_LNA_GAIN_DIFF (1 << 1)
1690 #define START_CALIB_TABLE_CLOCK (1 << 0)
1691 #define CALIB_TABLE_SELECT(x) (((x) & 0x3) << 5)
1696 #define LNA_CALIB_TABLE_GAIN_DIFFERENCE_WORD(x) (((x) & 0x3F) << 0)
1701 #define MAX_MIXER_CALIBRATION_GAIN_INDEX(x) (((x) & 0x1F) << 0)
1706 #define ENABLE_DIG_GAIN_CORR (1 << 7)
1707 #define FORCE_TEMP_SENSOR_FOR_CAL (1 << 6)
1708 #define SETTLE_TIME(x) (((x) & 0x3F) << 0)
1713 #define GAIN_CAL_MEAS_DURATION(x) (((x) & 0xF) << 0)
1718 #define MEASUREMENT_DURATION_1(x) (((x) & 0xF) << 4)
1719 #define MEASUREMENT_DURATION_0(x) (((x) & 0xF) << 0)
1724 #define MEASUREMENT_DURATION_3(x) (((x) & 0xF) << 4)
1725 #define MEASUREMENT_DURATION_2(x) (((x) & 0xF) << 0)
1730 #define START_RSSI_MEAS (1 << 5)
1731 #define ENABLE_ADC_POWER_MEAS (1 << 1)
1732 #define DEFAULT_RSSI_MEAS_MODE (1 << 0)
1733 #define RFIR_FOR_RSSI_MEASUREMENT(x) (((x) & 0x3) << 6)
1734 #define RSSI_MODE_SELECT(x) (((x) & 0x7) << 2)
1739 #define ADC_POWER_MEASUREMENT_DURATION_1(x) (((x) & 0xF) << 4)
1740 #define ADC_POWER_MEASUREMENT_DURATION_0(x) (((x) & 0xF) << 0)
1745 #define USE_HB3_OUT_FOR_ADC_PWR_MEAS (1 << 7)
1746 #define USE_HB1_OUT_FOR_DEC_PWR_MEAS (1 << 6)
1747 #define ENABLE_DEC_PWR_MEAS (1 << 5)
1748 #define DEFAULT_MODE_ADC_POWER (1 << 4)
1749 #define DEC_POWER_MEASUREMENT_DURATION(x) (((x) & 0xF) << 0)
1754 #define DB_GAIN_READBACK_CHANNEL (1 << 0)
1755 #define MAX_LNA_GAIN(x) (((x) & 0x7F) << 1)
1760 #define RX_QUAD_CAL_LEVEL(x) (((x) & 0xF) << 0)
1765 #define ENABLE_PHASE_CORR (1 << 7)
1766 #define ENABLE_GAIN_CORR (1 << 6)
1767 #define USE_SETTLE_COUNT_FOR_DC_CAL_WAIT (1 << 5)
1768 #define FIXED_DC_CAL_WAIT_TIME (1 << 4)
1769 #define FREE_RUN_MODE (1 << 3)
1770 #define ENABLE_CORR_WORD_DECIMATION (1 << 2)
1771 #define ENABLE_TRACKING_MODE_CH2 (1 << 1)
1772 #define ENABLE_TRACKING_MODE_CH1 (1 << 0)
1777 #define SOFT_RESET (1 << 7)
1778 #define CALIBRATION_CONFIG2_DFLT (0x3 << 5)
1779 #define K_EXP_PHASE(x) (((x) & 0x1F) << 0)
1784 #define PREVENT_POS_LOOP_GAIN (1 << 7)
1785 #define K_EXP_AMPLITUDE(x) (((x) & 0x1F) << 0)
1790 #define RX_FULL_TABLELMT_TABLE_GAIN(x) (((x) & 0x7F) << 0)
1795 #define CORRECTION_WORD_DECIMATION_M(x) (((x) & 0x7) << 5)
1796 #define RX_LPF_GAIN(x) (((x) & 0x1F) << 0)
1801 #define RX1_INPUT_A_I_DC_OFFSET_LSB(x) (((x) & 0x3F) << 2)
1802 #define RX1_INPUT_A_Q_DC_OFFSET(x) (((x) & 0x3) << 0)
1807 #define RX2_INPUT_A_Q_DC_OFFSET_LSB(x) (((x) & 0xF) << 4)
1808 #define RX1_INPUT_A_I_DC_OFFSET_MSB(x) (((x) & 0xF) << 0)
1813 #define RX2_INPUT_A_I_DC_OFFSET(x) (((x) & 0x3) << 6)
1814 #define RX2_INPUT_A_Q_DC_OFFSET_MSB(x) (((x) & 0x3F) << 0)
1819 #define RX1_INPUT_BC_I_DC_OFFSET_LSB(x) (((x) & 0x3F) << 2)
1820 #define RX1_INPUT_BC_Q_DC_OFFSET(x) (((x) & 0x3) << 0)
1825 #define RX2_INPUT_BC_Q_DC_OFFSET_LSB(x) (((x) & 0xF) << 4)
1826 #define RX1_INPUT_BC_I_DC_OFFSET_MSB(x) (((x) & 0xF) << 0)
1831 #define RX2_INPUT_BC_I_DC_OFFSET(x) (((x) & 0x3) << 6)
1832 #define RX2_INPUT_BC_Q_DC_OFFSET_MSB(x) (((x) & 0x3F) << 0)
1837 #define RX2_INPUT_BC_FORCE_OFFSET (1 << 7)
1838 #define RX1_INPUT_BC_FORCE_OFFSET (1 << 6)
1839 #define RX2_INPUT_BC_FORCE_PHGAIN (1 << 5)
1840 #define RX1_INPUT_BC_FORCE_PHGAIN (1 << 4)
1841 #define RX2_INPUT_A_FORCE_OFFSET (1 << 3)
1842 #define RX1_INPUT_A_FORCE_OFFSET (1 << 2)
1843 #define RX2_INPUT_A_FORCE_PHGAIN (1 << 1)
1844 #define RX1_INPUT_A_FORCE_PHGAIN (1 << 0)
1849 #define DAC_FS(x) (((x) & 0x3) << 4)
1850 #define RF_DC_CALIBRATION_COUNT(x) (((x) & 0xF) << 0)
1855 #define RF_DC_OFFSET_TABLE_UPDATE_COUNT(x) (((x) & 0x7) << 5)
1856 #define RF_DC_OFFSET_ATTEN(x) (((x) & 0x1F) << 0)
1861 #define INVERT_RX2_RF_DC_CGIN_WORD (1 << 7)
1862 #define INVERT_RX1_RF_DC_CGIN_WORD (1 << 6)
1863 #define INVERT_RX2_RF_DC_CGOUT_WORD (1 << 5)
1864 #define INVERT_RX1_RF_DC_CGOUT_WORD (1 << 4)
1869 #define USE_WAIT_COUNTER_FOR_RF_DC_INIT_CAL (1 << 7)
1870 #define ENABLE_FAST_SETTLE_MODE (1 << 6)
1871 #define ENABLE_BB_DC_OFFSET_TRACKING (1 << 5)
1872 #define RESET_ACC_ON_GAIN_CHANGE (1 << 4)
1873 #define ENABLE_RF_OFFSET_TRACKING (1 << 3)
1874 #define DC_OFFSET_UPDATE(x) (((x) & 0x7) << 0)
1879 #define RF_MINIMUM_CALIBRATION_GAIN_INDEX(x) (((x) & 0x7F) << 0)
1884 #define RF_SOI_THRESH(x) (((x) & 0x7F) << 0)
1889 #define INCREASE_COUNT_DURATION (1 << 7)
1890 #define BB_TRACKING_DECIMATE(x) (((x) & 0x3) << 5)
1891 #define BB_DC_M_SHIFT(x) (((x) & 0x1F) << 0)
1896 #define READ_BACK_CH_SEL (1 << 7)
1897 #define UPDATE_TRACKING_WORD (1 << 6)
1898 #define FORCE_RX_NULL (1 << 5)
1899 #define BB_DC_TRACKING_FAST_SETTLE_M_SHIFT(x) (((x) & 0x1F) << 0)
1904 #define BB_DC_OFFSET_ATTEN(x) (((x) & 0xF) << 0)
1909 #define RX1_BB_DC_OFFSET_CORRECTION_WORD_I(x) (((x) & 0x7F) << 0)
1914 #define RX1_BB_DC_OFFSET_CORRECTION_WORD_Q(x) (((x) & 0x7F) << 0)
1919 #define RX2_BB_DC_OFFSET_CORRECTION_WORD_I(x) (((x) & 0x7F) << 0)
1924 #define RX2_BB_DC_OFFSET_CORRECTION_WORD_Q(x) (((x) & 0x7F) << 0)
1929 #define RX1RX2_BB_DC_OFFSET_TRACKING_CORRECTION_WORD_I(x) (((x) & 0x7F) << 0)
1934 #define RX1RX2_BB_DC_OFFSET_TRACKING_CORRECTION_WORD_Q(x) (((x) & 0x7F) << 0)
1939 #define RX2_RSSI_SYMBOL (1 << 1)
1940 #define RX1_RSSI_SYMBOL (1 << 0)
1945 #define RX2_RSSI_PREAMBLE (1 << 1)
1946 #define RX1_RSSI_PREAMBLE (1 << 0)
1952 #define RSSI_LSB_SHIFT 1
1953 #define RSSI_LSB_MASK1 0x01
1954 #define RSSI_LSB_MASK2 0x02
1959 #define RX_PATH_GAIN (1 << 0)
1964 #define FORCE_RX2_LNA_GAIN (1 << 7)
1965 #define RX2_LNA_BYPASS (1 << 6)
1966 #define FORCE_RX1_LNA_GAIN (1 << 3)
1967 #define RX1_LNA_BYPASS (1 << 2)
1968 #define RX2_LNA_GAIN(x) (((x) & 0x3) << 4)
1969 #define RX1_LNA_GAIN(x) (((x) & 0x3) << 0)
1974 #define RX_LNA_BIAS_COARSE(x) (((x) & 0xF) << 0)
1979 #define RX_LNA_PCASCODE_BIAS(x) (((x) & 0x7) << 5)
1980 #define RX_LNA_BIAS(x) (((x) & 0x1F) << 0)
1985 #define RX_LNA_P_CASCODE_BIAS_FINE(x) (((x) & 0x3) << 0)
1990 #define RX_MIX_GM_CM_OUT(x) (((x) & 0x7) << 5)
1991 #define RX_MIX_GM_PLOAD(x) (((x) & 0x3) << 0)
1996 #define FORCE_RX1_MIX_GM (1 << 6)
1997 #define RX1_MIX_GM_GAIN(x) (((x) & 0x3F) << 0)
2002 #define RX1_MIX_GM_BIAS(x) (((x) & 0x1F) << 0)
2007 #define FORCE_RX2_MIX_GM (1 << 6)
2008 #define RX2_MIX_GM_GAIN(x) (((x) & 0x3F) << 0)
2013 #define RX2_MIX_GM_BIAS(x) (((x) & 0x1F) << 0)
2018 #define INPUT_A_RX1_Q(x) (((x) & 0x3) << 6)
2019 #define INPUT_A_RX1_I(x) (((x) & 0x3) << 4)
2020 #define INPUT_A_RX2_I(x) (((x) & 0x3) << 2)
2021 #define INPUT_A_RX2_Q(x) (((x) & 0x3) << 0)
2026 #define INPUTS_BC_RX1_Q(x) (((x) & 0x3) << 6)
2027 #define INPUTS_BC_RX1_I(x) (((x) & 0x3) << 4)
2028 #define INPUTS_BC_RX2_I(x) (((x) & 0x3) << 2)
2029 #define INPUTS_BC_RX2_Q(x) (((x) & 0x3) << 0)
2034 #define FORCE_CGIN_DAC (1 << 2)
2039 #define RX_MIX_LO_CM(x) (((x) & 0x3F) << 0)
2044 #define RX_CGB_SEG_ENABLE(x) (((x) & 0x3F) << 0)
2049 #define RX_CGB_INPUT_CM_SEL(x) (((x) & 0x3) << 4)
2050 #define RX_CGB_BIAS(x) (((x) & 0xF) << 0)
2055 #define TIA2_OVERRIDE_C (1 << 3)
2056 #define TIA2_OVERRIDE_R (1 << 2)
2057 #define TIA1_OVERRIDE_C (1 << 1)
2058 #define TIA1_OVERRIDE_R (1 << 0)
2059 #define TIA_SEL_CC(x) (((x) & 0x7) << 5)
2064 #define TIA1_RF(x) (((x) & 0x3) << 6)
2065 #define TIA1_C_LSB(x) (((x) & 0x3F) << 0)
2070 #define TIA1_C_MSB(x) (((x) & 0x7F) << 0)
2075 #define TIA2_RF(x) (((x) & 0x3) << 6)
2076 #define TIA2_C_LSB(x) (((x) & 0x3F) << 0)
2081 #define TIA2_C_MSB(x) (((x) & 0x7F) << 0)
2086 #define FORCE_RX1_RESISTORS (1 << 7)
2087 #define RX1_BBF_R1A(x) (((x) & 0x3F) << 0)
2092 #define FORCE_RX2_RESISTORS (1 << 7)
2093 #define RX2_BBF_R1A(x) (((x) & 0x3F) << 0)
2098 #define RX1_TUNE_RESAMPLE_PHASE (1 << 2)
2099 #define RX1_TUNE_RESAMPLE (1 << 1)
2100 #define RX1_PD_TUNE (1 << 0)
2105 #define RX2_TUNE_RESAMPLE_PHASE (1 << 2)
2106 #define RX2_TUNE_RESAMPLE (1 << 1)
2107 #define RX2_PD_TUNE (1 << 0)
2112 #define TUNE_OVERRIDE (1 << 7)
2113 #define RX_BBF_R2346(x) (((x) & 0x7) << 0)
2118 #define RX_BBF_C1_MSB(x) (((x) & 0x3F) << 0)
2123 #define RX_BBF_C1_LSB(x) (((x) & 0x7F) << 0)
2128 #define RX_BBF_C2_MSB(x) (((x) & 0x3F) << 0)
2133 #define RX_BBF_C2_LSB(x) (((x) & 0x7F) << 0)
2138 #define RX_BBF_C3_MSB(x) (((x) & 0x3F) << 0)
2143 #define RX_BBF_C3_LSB(x) (((x) & 0x7F) << 0)
2148 #define RX_BBF_CC1_CTR(x) (((x) & 0x7F) << 0)
2153 #define MUST_BE_ZERO (1 << 7)
2154 #define RX1_BBF_POW_CTR(x) (((x) & 0x3) << 5)
2155 #define RX_BBF_RZ1_CTR(x) (((x) & 0x3) << 3)
2160 #define RX_BBF_CC2_CTR(x) (((x) & 0x7F) << 0)
2165 #define RX_BBF_POW3_CTR(x) (((x) & 0x3) << 6)
2166 #define RX_BBF_RZ3_CTR(x) (((x) & 0x3) << 4)
2167 #define RX_BBF_POW2_CTR(x) (((x) & 0x3) << 2)
2168 #define RX_BBF_RZ2_CTR(x) (((x) & 0x3) << 0)
2173 #define RX_BBF_CC3_CTR(x) (((x) & 0x7F) << 0)
2178 #define RXBBF_BYPASS_BIAS_R (1 << 7)
2179 #define RX_BBF_R5_TUNE (1 << 4)
2180 #define RX1_BBF_TUNE_COMP_I (1 << 3)
2181 #define RX1_BBF_TUNE_COMP_Q (1 << 2)
2182 #define RX2_BBF_TUNE_COMP_I (1 << 1)
2183 #define RX2_BBF_TUNE_COMP_Q (1 << 0)
2184 #define RX_BBF_TUNE_CTR(x) (((x) & 0x3) << 5)
2189 #define RX1_BBF_FORCE_GAIN (1 << 5)
2190 #define RX1_BBF_BQ_GAIN(x) (((x) & 0x3) << 3)
2191 #define RX1_BBF_POLE_GAIN(x) (((x) & 0x7) << 0)
2196 #define RX2_BBF_FORCE_GAIN (1 << 5)
2197 #define RX2_BBF_BQ_GAIN(x) (((x) & 0x3) << 3)
2198 #define RX2_BBF_POLE_GAIN(x) (((x) & 0x7) << 0)
2203 #define RX_TUNE_EVALTIME (1 << 4)
2204 #define RX_BBF_TUNE_DIVIDE (1 << 0)
2205 #define TUNE_COMP_MASK(x) (((x) & 0x3) << 5)
2206 #define RX_TUNE_MODE(x) (((x) & 0x7) << 1)
2211 #define POLE_GAIN_TUNE(x) (((x) & 0x3) << 0)
2216 #define RX_TUNE_BBBW_MHZ(x) (((x) & 0x1F) << 0)
2221 #define RX_TUNE_BBBW_KHZ(x) (((x) & 0x7F) << 0)
2226 #define BYPASS_LD_SYNTH (1 << 0)
2231 #define SYNTH_INTEGER_WORD(x) (((x) & 0x7) << 0)
2236 #define SYNTH_FRACT_WORD(x) (((x) & 0x7F) << 0)
2241 #define VCO_CAL_OFFSET(x) (((x) & 0xF) << 3)
2246 #define INIT_ALC_VALUE(x) (((x) & 0xF) << 4)
2247 #define VCO_VARACTOR(x) (((x) & 0xF) << 0)
2252 #define PORB_VCO_LOGIC (1 << 6)
2253 #define VCO_OUTPUT_LEVEL(x) (((x) & 0xF) << 0)
2258 #define CHARGE_PUMP_CURRENT(x) (((x) & 0x3F) << 0)
2263 #define SYNTH_RECAL (1 << 7)
2268 #define HALF_VCO_CAL_CLK (1 << 7)
2269 #define CP_OFFSET_OFF (1 << 4)
2270 #define F_CPCAL (1 << 3)
2271 #define CP_CAL_ENABLE (1 << 2)
2276 #define LOOP_FILTER_C2(x) (((x) & 0xF) << 4)
2277 #define LOOP_FILTER_C1(x) (((x) & 0xF) << 0)
2282 #define LOOP_FILTER_R1(x) (((x) & 0xF) << 4)
2283 #define LOOP_FILTER_C3(x) (((x) & 0xF) << 0)
2288 #define LOOP_FILTER_BYPASS_R3 (1 << 7)
2289 #define LOOP_FILTER_BYPASS_R1 (1 << 6)
2290 #define LOOP_FILTER_BYPASS_C2 (1 << 5)
2291 #define LOOP_FILTER_BYPASS_C1 (1 << 4)
2292 #define LOOP_FILTER_R3(x) (((x) & 0xF) << 0)
2297 #define FORCED_CP_CAL_WORD(x) (((x) & 0xF) << 0)
2302 #define VCO_BIAS_TCF(x) (((x) & 0x3) << 3)
2303 #define VCO_BIAS_REF(x) (((x) & 0x7) << 0)
2308 #define CP_CAL_VALID (1 << 7)
2309 #define CP_CAL_DONE (1 << 5)
2310 #define VCO_CAL_BUSY (1 << 4)
2311 #define CP_CAL_WORD(x) (((x) & 0xF) << 0)
2316 #define VCO_CAL_REF_TCF(x) (((x) & 0x7) << 0)
2321 #define POWER_DOWN_VARACTOR_REF (1 << 3)
2322 #define PWR_DOWN_VARACT_REF_TCF (1 << 2)
2323 #define POWER_DOWN_CAL_TCF (1 << 1)
2324 #define POWER_DOWN_VCO_BUFFFER (1 << 0)
2329 #define CP_OVRG_HIGH (1 << 7)
2330 #define CP_OVRG_LOW (1 << 6)
2331 #define VCO_LOCK (1 << 1)
2336 #define VCO_LDO_BYPASS (1 << 7)
2337 #define VCO_LDO_INRUSH(x) (((x) & 0x3) << 5)
2338 #define VCO_LDO_SEL(x) (((x) & 0x7) << 2)
2339 #define VCO_LDO_VDROP_SEL(x) (((x) & 0x3) << 0)
2344 #define VCO_CAL_EN (1 << 7)
2345 #define VCO_CAL_ALC_WAIT(x) (((x) & 0x7) << 4)
2346 #define VCO_CAL_COUNT(x) (((x) & 0x3) << 2)
2351 #define LOCK_DETECT_COUNT(x) (((x) & 0x3) << 2)
2352 #define LOCK_DETECT_MODE(x) (((x) & 0x3) << 0)
2357 #define CP_LEVEL_DETECT_POWER_DOWN (1 << 6)
2358 #define CP_LEVEL_THRESH_LOW(x) (((x) & 0x7) << 3)
2359 #define CP_LEVEL_THRESH_HIGH(x) (((x) & 0x7) << 0)
2364 #define DSM_PROG(x) (((x) & 0xF) << 0)
2369 #define SIF_CLOCK (1 << 6)
2370 #define SIF_RESET_BAR (1 << 5)
2371 #define SIF_ADDR(x) (((x) & 0x1F) << 0)
2376 #define UPDATE_FREQ_WORD (1 << 7)
2377 #define READ_EFFECTIVE_TUNING_WORD (1 << 5)
2378 #define FREQ_CORRECTION_WORD_MSB(x) (((x) & 0x1F) << 0)
2383 #define UPDATE_FREQ_WORD (1 << 7)
2384 #define FREQ_CORRECTION_WORD_LSB(x) (((x) & 0x7F) << 0)
2389 #define VCO_VARACTOR_REFERENCE_TCF(x) (((x) & 0x7) << 4)
2390 #define VCO_VARACTOR_OFFSET(x) (((x) & 0xF) << 0)
2395 #define VCO_VARACTOR_REFERENCE(x) (((x) & 0xF) << 0)
2400 #define RX_FAST_LOCK_LOAD_SYNTH (1 << 3)
2401 #define RX_FAST_LOCK_PROFILE_INIT (1 << 2)
2402 #define RX_FAST_LOCK_PROFILE_PIN_SELECT (1 << 1)
2403 #define RX_FAST_LOCK_MODE_ENABLE (1 << 0)
2404 #define RX_FAST_LOCK_PROFILE(x) (((x) & 0x7) << 5)
2409 #define RX_FAST_LOCK_PROFILE_ADDR(x) (((x) & 0x7) << 4)
2410 #define RX_FAST_LOCK_PROFILE_WORD(x) (((x) & 0xF) << 0)
2416 #define RX_FAST_LOCK_PROGRAM_WRITE (1 << 1)
2417 #define RX_FAST_LOCK_PROGRAM_CLOCK_ENABLE (1 << 0)
2419 #define RX_FAST_LOCK_CONFIG_WORD_NUM 16
2424 #define RX_LO_GEN_POWER_MODE(x) (((x) & 0x3) << 4)
2429 #define DIV_TEST_EN (1 << 5)
2430 #define PFD_CLK_EDGE (1 << 1)
2431 #define BYPASS_LD_SYNTH (1 << 0)
2432 #define PFD_WIDTH(x) (((x) & 0x3) << 2)
2437 #define SDM_BYPASS (1 << 7)
2438 #define SDM_POWER_DOWN (1 << 6)
2439 #define SYNTH_INTEGER_WORD(x) (((x) & 0x7) << 0)
2444 #define SYNTH_FRACT_WORD(x) (((x) & 0x7F) << 0)
2449 #define FORCE_ALC_ENABLE (1 << 7)
2450 #define FORCE_ALC_WORD(x) (((x) & 0x7F) << 0)
2455 #define BYPASS_LOAD_DELAY (1 << 7)
2456 #define FORCE_VCO_TUNE_ENABLE (1 << 1)
2457 #define FORCE_VCO_TUNE (1 << 0)
2458 #define VCO_CAL_OFFSET(x) (((x) & 0xF) << 3)
2463 #define INIT_ALC_VALUE(x) (((x) & 0xF) << 4)
2464 #define VCO_VARACTOR(x) (((x) & 0xF) << 0)
2469 #define PORB_VCO_LOGIC (1 << 6)
2470 #define VCO_OUTPUT_LEVEL(x) (((x) & 0xF) << 0)
2475 #define TX_CP_CURRENT_DFLT (1 << 7)
2476 #define VTUNE_FORCE (1 << 6)
2477 #define CHARGE_PUMP_CURRENT(x) (((x) & 0x3F) << 0)
2482 #define SYNTH_RECAL (1 << 7)
2483 #define CHARGE_PUMP_OFFSET(x) (((x) & 0x3F) << 0)
2488 #define HALF_VCO_CAL_CLK (1 << 7)
2489 #define DITHER_MODE (1 << 6)
2490 #define CP_OFFSET_OFF (1 << 4)
2491 #define F_CPCAL (1 << 3)
2492 #define CP_CAL_ENABLE (1 << 2)
2493 #define CP_TEST(x) (((x) & 0x3) << 0)
2498 #define LOOP_FILTER_C2(x) (((x) & 0xF) << 4)
2499 #define LOOP_FILTER_C1(x) (((x) & 0xF) << 0)
2504 #define LOOP_FILTER_R1(x) (((x) & 0xF) << 4)
2505 #define LOOP_FILTER_C3(x) (((x) & 0xF) << 0)
2510 #define LOOP_FILTER_BYPASS_R3 (1 << 7)
2511 #define LOOP_FILTER_BYPASS_R1 (1 << 6)
2512 #define LOOP_FILTER_BYPASS_C2 (1 << 5)
2513 #define LOOP_FILTER_BYPASS_C1 (1 << 4)
2514 #define LOOP_FILTER_R3(x) (((x) & 0xF) << 0)
2519 #define NUMBER_SDM_DITHER_BITS(x) (((x) & 0xF) << 4)
2520 #define FORCED_CP_CAL_WORD(x) (((x) & 0xF) << 0)
2525 #define MUST_BE_ZEROS(x) (((x) & 0x3) << 5)
2526 #define VCO_BIAS_TCF(x) (((x) & 0x3) << 3)
2527 #define VCO_BIAS_REF(x) (((x) & 0x7) << 0)
2532 #define VCO_BYPASS_BIAS_DAC_R (1 << 7)
2533 #define VCO_COMP_BYPASS_BIAS_R (1 << 4)
2534 #define BYPASS_PRESCALE_R (1 << 3)
2535 #define LAST_ALC_ENABLE (1 << 2)
2536 #define PRESCALE_BIAS(x) (((x) & 0x3) << 0)
2541 #define CP_CAL_VALID (1 << 7)
2542 #define COMP_OUT (1 << 6)
2543 #define CP_CAL_DONE (1 << 5)
2544 #define VCO_CAL_BUSY (1 << 4)
2545 #define CP_CAL_WORD(x) (((x) & 0xF) << 0)
2550 #define VCO_CAL_REF_MONITOR (1 << 3)
2551 #define VCO_CAL_REF_TCF(x) (((x) & 0x7) << 0)
2556 #define POWER_DOWN_VARACTOR_REF (1 << 3)
2557 #define POWER_DOWN_VARACT_REF_TCF (1 << 2)
2558 #define POWER_DOWN_CAL_TCF (1 << 1)
2559 #define POWER_DOWN_VCO_BUFFFER (1 << 0)
2564 #define CP_OVRG_HIGH (1 << 7)
2565 #define CP_OVRG_LOW (1 << 6)
2566 #define VCO_LOCK (1 << 1)
2571 #define VCO_LDO_BYPASS (1 << 7)
2572 #define VCO_LDO_INRUSH(x) (((x) & 0x3) << 5)
2573 #define VCO_LDO_VOUT_SEL(x) (((x) & 0x7) << 2)
2574 #define VCO_LDO_VDROP_SEL(x) (((x) & 0x3) << 0)
2579 #define VCO_CAL_EN (1 << 7)
2580 #define VCO_CAL_ALC_WAIT(x) (((x) & 0x7) << 4)
2581 #define VCO_CAL_COUNT(x) (((x) & 0x3) << 2)
2582 #define FB_CLOCK_ADV(x) (((x) & 0x3) << 0)
2587 #define LOCK_DETECT_COUNT(x) (((x) & 0x3) << 2)
2588 #define LOCK_DETECT_MODE(x) (((x) & 0x3) << 0)
2593 #define CP_LEVEL_DETECT_POWER_DOWN (1 << 6)
2594 #define CP_LEVEL_DETECT_THRESH_LOW(x) (((x) & 0x7) << 3)
2595 #define CP_LEVEL_DETECT_THRESH_HIGH(x) (((x) & 0x7) << 0)
2600 #define DSM_PROG(x) (((x) & 0xF) << 0)
2605 #define SIF_CLOCK (1 << 6)
2606 #define SIF_RESET_BAR (1 << 5)
2607 #define SIF_ADDR(x) (((x) & 0x1F) << 0)
2612 #define UPDATE_FREQ_WORD (1 << 7)
2613 #define READ_EFFECTIVE_TUNING_WORD (1 << 5)
2614 #define FREQ_CORRECTION_WORD_MSB(x) (((x) & 0x1F) << 0)
2619 #define UPDATE_FREQ_WORD (1 << 7)
2620 #define FREQ_CORRECTION_WORD_LSB(x) (((x) & 0x7F) << 0)
2625 #define VCO_VARACTOR_REFERENCE_TCF(x) (((x) & 0x7) << 4)
2626 #define VCO_VARACTOR_OFFSET(x) (((x) & 0xF) << 0)
2631 #define VCO_VARACTOR_REFERENCE(x) (((x) & 0xF) << 0)
2636 #define DCXO_TUNE_COARSE(x) (((x) & 0x3F) << 0)
2641 #define DCXO_TUNE_FINE_LOW(x) (((x) & 0x1F) << 3)
2646 #define DCXO_TUNE_FINE_HIGH(x) ((x) >> 5)
2651 #define MUST_BE_ZERO (1 << 7)
2652 #define DCXO_RTAIL(x) (((x) & 0x7) << 4)
2653 #define DCXO_RD(x) (((x) & 0x3) << 2)
2658 #define DCXO_TEMPCO_EN (1 << 7)
2659 #define DCXO_TEMPCO_CLK (1 << 6)
2660 #define DCXO_TEMPERATURE_COEF_ADDRESS(x) (((x) & 0x3F) << 0)
2665 #define TX_FAST_LOCK_LOAD_SYNTH (1 << 3)
2666 #define TX_FAST_LOCK_PROFILE_INIT (1 << 2)
2667 #define TX_FAST_LOCK_PROFILE_PIN_SELECT (1 << 1)
2668 #define TX_FAST_LOCK_MODE_ENABLE (1 << 0)
2669 #define TX_FAST_LOCK_PROFILE(x) (((x) & 0x7) << 5)
2674 #define TX_FAST_LOCK_PROGRAM_WRITE (1 << 1)
2675 #define TX_FAST_LOCK_PROGRAM_CLOCK_ENABLE (1 << 0)
2680 #define TX_LO_GEN_POWER_MODE(x) (((x) & 0xF) << 4)
2685 #define POWER_DOWN_BANDGAP_REF (1 << 7)
2686 #define MASTER_BIAS_FILTER_BYPASS (1 << 6)
2687 #define MASTER_BIAS_REF_SEL (1 << 5)
2688 #define MASTER_BIAS_TRIM(x) (((x) & 0x1F) << 0)
2693 #define VCO_LDO_FILTER_BYPASS (1 << 7)
2694 #define VCO_LDO_REF_SEL (1 << 6)
2695 #define BANDGAP_REF_RESET (1 << 5)
2696 #define BANDGAP_TEMP_TRIM(x) (((x) & 0x1F) << 0)
2701 #define REF_DIVIDE_CONFIG_1_DFLT (1 << 2)
2702 #define RX_REF_RESET_BAR (1 << 1)
2703 #define RX_REF_DIVIDER_MSB (1 << 0)
2708 #define RX_REF_DIVIDER_LSB (1 << 7)
2709 #define TX_REF_RESET_BAR (1 << 4)
2710 #define RX_REF_DOUBLER_FB_DELAY(x) (((x) & 0x3) << 5)
2711 #define TX_REF_DIVIDER(x) (((x) & 0x3) << 2)
2712 #define TX_REF_DOUBLER_FB_DELAY(x) (((x) & 0x3) << 0)
2717 #define FULL_TABLE_GAIN_INDEX(x) (((x) & 0x7F) << 0)
2722 #define LPF_GAIN_RX(x) (((x) & 0x1F) << 0)
2727 #define DIGITAL_GAIN_RX(x) (((x) & 0x1F) << 0)
2732 #define FAST_ATTACK_STATE_RX2(x) (((x) & 0x7) << 4)
2733 #define FAST_ATTACK_STATE_RX1(x) (((x) & 0x7) << 0)
2734 #define FAST_ATK_MASK 0x7
2735 #define RX1_FAST_ATK_SHIFT 0
2736 #define RX2_FAST_ATK_SHIFT 4
2737 #define FAST_ATK_RESET 0
2738 #define FAST_ATK_PEAK_DETECT 1
2739 #define FAST_ATK_PWR_MEASURE 2
2740 #define FAST_ATK_FINAL_SETTELING 3
2741 #define FAST_ATK_FINAL_OVER 4
2742 #define FAST_ATK_GAIN_LOCKED 5
2747 #define SLOW_LOOP_STATE_RX2(x) (((x) & 0x7) << 4)
2748 #define SLOW_LOOP_STATE_RX1(x) (((x) & 0x7) << 0)
2754 #define GAIN_LOCK_1 (1 << 6)
2755 #define LOW_POWER_1 (1 << 5)
2756 #define LARGE_LMT_OL (1 << 4)
2757 #define SMALL_LMT_OL (1 << 3)
2758 #define LARGE_ADC_OL (1 << 2)
2759 #define SMALL_ADC_OL (1 << 1)
2760 #define DIG_SAT (1 << 0)
2764 #define CTRL_ENABLE (1 << 0)
2769 #define TONE_PRBS (1 << 1)
2770 #define BIST_ENABLE (1 << 0)
2771 #define TONE_FREQ(x) (((x) & 0x3) << 6)
2772 #define TONE_LEVEL(x) (((x) & 0x3) << 4)
2773 #define BIST_CTRL_POINT(x) (((x) & 0x3) << 2)
2778 #define DATA_PORT_SP_HD_LOOP_TEST_OE (1 << 7)
2779 #define RX_MASK (1 << 6)
2780 #define CHANNEL (1 << 5)
2781 #define DATA_PORT_LOOP_TEST_ENABLE (1 << 0)
2782 #define OBSERVATION_POINT(x) (((x) & 0xF) << 1)
2787 #define BIST_MASK_CHANNEL_2_Q_DATA (1 << 5)
2788 #define BIST_MASK_CHANNEL_2_I_DATA (1 << 4)
2789 #define BIST_MASK_CHANNEL_1_Q_DATA (1 << 3)
2790 #define BIST_MASK_CHANNEL_1_I_DATA (1 << 2)
2791 #define DATA_PORT_HILOW (1 << 1)
2792 #define USE_DATA_PORT (1 << 0)
2793 #define TEMP_SENSE_VBE_TEST(x) (((x) & 0x3) << 6)
2798 #define DAC_TEST_ENABLE (1 << 7)
2799 #define DAC_TEST_WORD(x) (((x) & 0x7F) << 0)
2804 #define AD_READ (0 << 15)
2805 #define AD_WRITE (1 << 15)
2806 #define AD_CNT(x) ((((x) - 1) & 0x7) << 12)
2807 #define AD_ADDR(x) ((x) & 0x3FF)
2814 #define RSSI_MULTIPLIER 100
2815 #define RSSI_RESOLUTION ((int) (0.25 * RSSI_MULTIPLIER))
2816 #define RSSI_MAX_WEIGHT 255
2818 #define MAX_LMT_INDEX 40
2819 #define MAX_LPF_GAIN 24
2820 #define MAX_DIG_GAIN 31
2822 #define MAX_BBPLL_FREF 70007000UL
2823 #define MIN_BBPLL_FREQ 714928500UL
2824 #define MAX_BBPLL_FREQ 1430143000UL
2825 #define MAX_BBPLL_DIV 64
2826 #define MIN_BBPLL_DIV 2
2834 #define MIN_ADC_CLK 25000000U
2836 #define MAX_ADC_CLK 640000000U
2837 #define MAX_DAC_CLK (MAX_ADC_CLK / 2)
2840 #define MAX_RX_HB1 245760000UL
2841 #define MAX_RX_HB2 320000000UL
2842 #define MAX_RX_HB3 640000000UL
2844 #define MAX_TX_HB1 160000000UL
2845 #define MAX_TX_HB2 320000000UL
2846 #define MAX_TX_HB3 320000000UL
2848 #define MAX_BASEBAND_RATE 61440000UL
2850 #define MAX_MBYTE_SPI 8
2852 #define RFPLL_MODULUS 8388593UL
2853 #define BBPLL_MODULUS 2088960UL
2855 #define MAX_SYNTH_FREF 80008000UL
2856 #define MIN_SYNTH_FREF 9999000UL
2857 #define MIN_VCO_FREQ_HZ 6000000000ULL
2858 #define MAX_CARRIER_FREQ_HZ 6000000000ULL
2859 #define MIN_RX_CARRIER_FREQ_HZ 70000000ULL
2860 #define MIN_TX_CARRIER_FREQ_HZ 46875001ULL
2862 #define AD9363A_MAX_CARRIER_FREQ_HZ 3800000000ULL
2863 #define AD9363A_MIN_CARRIER_FREQ_HZ 325000000ULL
2865 #define MAX_TX_ATTENUATION_DB 89750
3301 #define FASTLOOK_INIT 1
3347 #ifndef AXI_ADC_NOT_PRESENT
3444 uint8_t *rbuf, uint32_t num);
3447 uint32_t reg, uint32_t *val);
3449 uint32_t reg, uint32_t val);
3451 uint32_t reg, uint32_t val);
3467 uint32_t rf_rx_bw, uint32_t rf_tx_bw);
3469 uint32_t tx_sample_rate,
3471 uint32_t *rx_path_clks,
3472 uint32_t *tx_path_clks);
3474 uint32_t *rx_path_clks,
3475 uint32_t *tx_path_clks);
3477 uint32_t *rx_path_clks,
3478 uint32_t *tx_path_clks);
3485 enum fir_dest dest, int32_t gain_dB,
3486 uint32_t ntaps,
short *coef);
3489 bool tx1,
bool tx2,
bool immed);
3492 uint32_t parent_rate);
3497 uint32_t parent_rate);
3499 uint32_t parent_rate);
3503 uint32_t parent_rate);
3505 uint32_t parent_rate);
3510 uint32_t parent_rate);
3519 bool rfdc_track,
bool rxquad_track);
3527 uint32_t level_dB, uint32_t mask);
3530 uint32_t *level_dB, uint32_t *mask);
3532 uint32_t rx_inputs, uint32_t txb);
3541 uint32_t
profile, uint8_t *values);
3543 uint32_t
profile, uint8_t *values);
3550 int32_t
ad9361_find_opt(uint8_t *field, uint32_t size, uint32_t *ret_start);
3553 char *buf, int32_t buflen);
3564 uint32_t coarse, uint32_t fine);
#define REG_GAIN_UPDATE_COUNTER2
Definition: ad9361.h:263
#define REG_PREAMBLE_LSB
Definition: ad9361.h:370
int32_t ad9361_spi_read(struct no_os_spi_desc *spi, uint32_t reg)
Definition: ad9361.c:741
#define REG_GPO1_RX_DELAY
Definition: ad9361.h:91
#define ENABLE_BB_DC_OFFSET_TRACKING
Definition: ad9361.h:1871
uint8_t agc_inner_thresh_low
Definition: ad9361.h:2954
#define RX_MIX_GM_PLOAD(x)
Definition: ad9361.h:1991
#define REG_AGC_INNER_LOW_THRESH
Definition: ad9361.h:258
#define REG_DIGITAL_SAT_COUNTER
Definition: ad9361.h:264
#define TX2_MON_ENABLE
Definition: ad9361.h:1057
#define RSSI_MULTIPLIER
Definition: ad9361.h:2814
int32_t ad9361_rf_port_setup(struct ad9361_rf_phy *phy, bool is_out, uint32_t rx_inputs, uint32_t txb)
Definition: ad9361.c:3643
uint8_t lvds_bias_ctrl
Definition: ad9361.h:3071
bool gpo3_slave_rx_en
Definition: ad9361.h:3111
#define REG_GM_SUB_TABLE_CTRL_WRITE
Definition: ad9361.h:280
#define AD_ADDR(x)
Definition: ad9361.h:2807
#define REG_TX_FILTER_COEF_READ_DATA_1
Definition: ad9361.h:139
#define DIG_GAIN_EN
Definition: ad9361.h:1366
#define REG_GPO_FORCE_AND_INIT
Definition: ad9361.h:89
uint8_t lmt_overload_large_inc_steps
Definition: ad9361.h:2967
@ LUT_FTDD_80
Definition: ad9361.h:3262
#define MAX_DIG_GAIN
Definition: ad9361.h:2820
#define REG_RX_ENABLE_FILTER_CTRL
Definition: ad9361.h:54
@ RF_GAIN_HYBRID_AGC
Definition: ad9361.h:2911
enum rx_gain_table_type tbl_type
Definition: ad9361.h:3058
#define ENSM_STATE_SLEEP
Definition: ad9361.h:770
#define REG_CTRL_OUTPUT_ENABLE
Definition: ad9361.h:103
#define LOOP_FILTER_R1(x)
Definition: ad9361.h:2504
int32_t ad9361_validate_enable_fir(struct ad9361_rf_phy *phy)
Definition: ad9361.c:6091
bool f_agc_rst_gla_large_lmt_overload_en
Definition: ad9361.h:3010
uint64_t start
Definition: ad9361.h:2884
#define REG_MAG_FTEST_THRESH
Definition: ad9361.h:186
uint8_t pp_conf[3]
Definition: ad9361.h:3067
#define REG_AUXDAC_2_CONFIG
Definition: ad9361.h:77
#define XO_BYPASS
Definition: ad9361.h:650
uint32_t div
Definition: ad9361.h:3424
#define REG_QUAD_CAL_STATUS_TX1
Definition: ad9361.h:188
#define MIN_VCO_FREQ_HZ
Definition: ad9361.h:2857
uint32_t fgt_lmt_index
Definition: ad9361.h:3225
bool bbdc_track_en
Definition: ad9361.h:3400
#define POWER_DOWN_RX_SYNTH
Definition: ad9361.h:735
#define REG_RSSI_CONFIG
Definition: ad9361.h:303
#define TX_REF_DIVIDER(x)
Definition: ad9361.h:2711
@ BB_REFCLK
Definition: ad9361.h:3267
#define AUXDAC_INIT_BAR(x)
Definition: ad9361.h:828
#define AGC_GAIN_UNLOCK_CTRL
Definition: ad9361.h:1364
uint32_t timeout
Definition: ad413x.c:55
#define REG_RX_TIA_CONFIG
Definition: ad9361.h:396
#define REG_TX_ATTEN_OFFSET
Definition: ad9361.h:157
int32_t ad9361_fastlock_load(struct ad9361_rf_phy *phy, bool tx, uint32_t profile, uint8_t *values)
Definition: ad9361.c:5004
#define ENABLE_ENSM_PIN_CTRL
Definition: ad9361.h:725
#define RX_REF_DIVIDER_LSB
Definition: ad9361.h:2708
Definition: ad9361_util.h:93
#define DUAL_SYNTH_MODE
Definition: ad9361.h:739
#define TX_LO_GEN_POWER_MODE(x)
Definition: ad9361.h:2680
#define ENABLE_CORR_WORD_DECIMATION
Definition: ad9361.h:1770
#define MANUAL_INCR_STEP_SIZE(x)
Definition: ad9361.h:1375
@ DBGFS_BIST_DT_ANALYSIS
Definition: ad9361.h:3435
#define no_os_min_t(type, x, y)
Definition: no_os_util.h:65
#define RX2_GAIN_CTRL_SETUP(x)
Definition: ad9361.h:1350
#define REG_RX_BBF_C3_MSB
Definition: ad9361.h:412
#define MAN_GAIN_CTRL_RX1
Definition: ad9361.h:1368
#define REG_VCO_PROGRAM_2
Definition: ad9361.h:123
Definition: ad9361.h:3307
Definition: ad9361.h:3291
#define REG_RX_CAL_STATUS
Definition: ad9361.h:485
void ad9361_get_bist_prbs(struct ad9361_rf_phy *phy, enum ad9361_bist_mode *mode)
Definition: ad9361.c:1221
bool elna_2_control_en
Definition: ad9361.h:3085
rx_gain_table_type
Definition: ad9361.h:2871
#define REG_EXT_LNA_HIGH_GAIN
Definition: ad9361.h:267
#define REG_RX_CP_OVERRANGE_VCO_LOCK
Definition: ad9361.h:488
#define REG_FAST_LOW_POWER_THRESH
Definition: ad9361.h:250
#define GPO_MANUAL_SELECT
Definition: ad9361.h:836
uint32_t ad9361_rfpll_int_recalc_rate(struct refclk_scale *clk_priv, uint32_t parent_rate)
Definition: ad9361.c:6784
#define FAST_ATK_MASK
Definition: ad9361.h:2734
int32_t ad9361_get_rx_gain(struct ad9361_rf_phy *phy, uint32_t rx_id, struct rf_rx_gain *rx_gain)
Definition: ad9361.c:1916
#define BIST_MASK_CHANNEL_1_I_DATA
Definition: ad9361.h:2790
int32_t ad9361_dig_tune(struct ad9361_rf_phy *phy, uint32_t max_freq, enum dig_tune_flags flags)
Definition: ad9361_conv.c:525
#define DOUBLE_GAIN_COUNTER
Definition: ad9361.h:1561
#define RX_FAST_LOCK_PROFILE_WORD(x)
Definition: ad9361.h:2410
#define REG_RX_BBF_TUNE_DIVIDE
Definition: ad9361.h:423
#define GOTO_OPTIMIZED_GAIN_IF_EXIT_RX_STATE
Definition: ad9361.h:1470
int32_t ad9361_fastlock_recall(struct ad9361_rf_phy *phy, bool tx, uint32_t profile)
Definition: ad9361.c:5179
bool immed_gain_change_if_large_lmt_overload
Definition: ad9361.h:2975
#define TO_MIXER_GM_GAIN(x)
Definition: ad9361.h:1615
int32_t ad9361_reg_write(struct ad9361_rf_phy *phy, uint32_t reg, uint32_t val)
Definition: ad9361.c:849
#define dev_err(dev, format,...)
Definition: ad9361_util.h:69
uint8_t LF_R1
Definition: ad9361.h:3254
uint8_t agc_inner_thresh_low_inc_steps
Definition: ad9361.h:2955
#define REG_MULTICHIP_SYNC_AND_TX_MON_CTRL
Definition: ad9361.h:52
#define FORCE_VCO_TUNE
Definition: ad9361.h:2457
#define RX_FAST_LOCK_PROGRAM_CLOCK_ENABLE
Definition: ad9361.h:2417
#define TEMP_SENSOR_DECIMATION(x)
Definition: ad9361.h:677
#define CLKOUT_SELECT(x)
Definition: ad9361.h:660
struct no_os_gpio_desc * gpio_desc_cal_sw2
Definition: ad9361.h:3346
int32_t ad9361_clk_factor_round_rate(struct refclk_scale *clk_priv, uint32_t rate, uint32_t *prate)
Definition: ad9361.c:6513
#define AUX_ADC_DECIMATION(x)
Definition: ad9361.h:803
#define TX_BBF_TUNE_DIVIDER
Definition: ad9361.h:1326
#define VCO_LOCK
Definition: ad9361.h:2566
#define REG_GAIN_STP_CONFIG1
Definition: ad9361.h:234
@ LO_DONTCARE
Definition: ad9361.h:3329
#define REG_CALIBRATION_CONFIG_1
Definition: ad9361.h:314
#define SYNTH_ENABLE_PIN_CTRL_MODE
Definition: ad9361.h:738
#define POWER_MEAS_IN_STATE_5_MSB
Definition: ad9361.h:1429
uint8_t adc_large_overload_inc_steps
Definition: ad9361.h:2961
int32_t ad9361_rfpll_int_round_rate(struct refclk_scale *clk_priv, uint32_t rate, uint32_t *prate)
Definition: ad9361.c:6840
bool gpo0_inactive_state_high_en
Definition: ad9361.h:3101
#define TX_SYNTH_VCO_ALC_POWER_DOWN
Definition: ad9361.h:954
struct no_os_clk * clks[NUM_AD9361_CLKS]
Definition: ad9361.h:3352
int32_t ad9361_fastlock_save(struct ad9361_rf_phy *phy, bool tx, uint32_t profile, uint8_t *values)
Definition: ad9361.c:5235
@ BE_VERBOSE
Definition: ad9361.h:3314
#define TX_MONITOR_POWER_DOWN(x)
Definition: ad9361.h:988
#define CP_CAL_VALID
Definition: ad9144.h:670
#define REG_RF_DC_OFFSET_COUNT
Definition: ad9361.h:341
bool gpo3_inactive_state_high_en
Definition: ad9361.h:3104
Definition: ad9361.h:3222
#define DEC3_ENABLE_DECIMATION(x)
Definition: ad9361.h:616
#define MIN_BBPLL_DIV
Definition: ad9361.h:2826
#define REG_FAST_INITIAL_LMT_GAIN_LIMIT
Definition: ad9361.h:256
#define SIZE_FULL_TABLE
Definition: ad9361.c:401
uint8_t dac1_rx_delay_us
Definition: ad9361.h:3034
#define CHARGE_PUMP_CURRENT(x)
Definition: ad9361.h:2477
bool adc_lmt_small_overload_prevent_gain_inc
Definition: ad9361.h:2963
int32_t no_os_spi_write_and_read(struct no_os_spi_desc *desc, uint8_t *data, uint16_t bytes_number)
Write and read data to/from SPI.
Definition: no_os_spi.c:165
#define FIR_START_CLK
Definition: ad9361.h:1026
#define REG_TIA1_C_MSB
Definition: ad9361.h:398
#define REG_AUXDAC_1_CONFIG
Definition: ad9361.h:76
#define REG_RX_LOOP_FILTER_3
Definition: ad9361.h:482
#define FREQ_CAL_COUNT_LENGTH(x)
Definition: ad9361.h:934
#define FORCE_ALC_ENABLE
Definition: ad9361.h:2449
struct axiadc_state * adc_state
Definition: ad9361.h:3409
#define REG_BIST_AND_DATA_PORT_TEST_CONFIG
Definition: ad9361.h:572
#define RX_ENABLE
Definition: ad9361.h:620
#define REG_FRACT_BB_FREQ_WORD_1
Definition: ad9361.h:111
@ SPI_WRITE_TO_REGISTER
Definition: ad9361.h:3045
uint8_t rx_fir_ntaps
Definition: ad9361.h:3397
#define REFERENCE_CLOCK_CYCLES_PER_US(x)
Definition: ad9361.h:867
@ NUM_RX_CLOCKS
Definition: ad9361.h:3144
#define RX_DISABLE
Definition: ad9361.h:621
#define AGC_ATTACK_DELAY(x)
Definition: ad9361.h:820
Definition: ad9361.h:3300
#define MAX_LMT_INDEX
Definition: ad9361.h:2818
#define REG_TX_TUNE_CTRL
Definition: ad9361.h:210
#define REF_FREQ_SCALER(x)
Definition: ad9361.h:896
#define REG_CALIBRATION_CONFIG_2
Definition: ad9361.h:315
#define REG_TPM_MODE_ENABLE
Definition: ad9361.h:149
#define REG_RX2_TUNE_CTRL
Definition: ad9361.h:404
#define SYNTH_INTEGER_WORD(x)
Definition: ad9361.h:2439
int32_t ad9361_en_dis_rx(struct ad9361_rf_phy *phy, uint32_t rx_if, uint32_t enable)
Definition: ad9361.c:1096
int32_t ad9361_reset(struct ad9361_rf_phy *phy)
Definition: ad9361.c:1048
Header file of SPI Interface.
int32_t ad9361_register_clocks(struct ad9361_rf_phy *phy)
Definition: ad9361.c:7294
#define REG_GM_SUB_TABLE_CONFIG
Definition: ad9361.h:284
@ DBGFS_BIST_PRBS
Definition: ad9361.h:3433
bool manual_tx_quad_cal_en
Definition: ad9361.h:3371
#define MAX_ADC_CLK
Definition: ad9361.h:2836
#define REG_RX_VCO_CAL_REF
Definition: ad9361.h:486
#define REG_FAST_ATTACK_STATE
Definition: ad9361.h:562
#define FB_CLOCK_ADV(x)
Definition: ad9361.h:2582
uint8_t index
Definition: ad9361.h:3076
struct ad9361_rf_phy * phy
Definition: ad9361.h:3292
fir_dest
Definition: ad9361.h:2892
#define TONE_FREQ(x)
Definition: ad9361.h:2771
bool dac2_in_rx_en
Definition: ad9361.h:3030
@ ADC_CLK_DIV_4
Definition: ad9361.h:3162
uint8_t f_agc_rst_gla_engergy_lost_sig_thresh_below_ll
Definition: ad9361.h:3007
#define MEASUREMENT_TIME_INTERVAL(x)
Definition: ad9361.h:672
#define TX_MON_TRACK
Definition: ad9361.h:1034
#define REG_QUAD_CAL_COUNT
Definition: ad9361.h:190
uint8_t lmt_overload_small_exceed_counter
Definition: ad9361.h:2966
#define PHASE_ENABLE
Definition: ad9361.h:1142
#define MAX_TX_HB3
Definition: ad9361.h:2846
bool elna_in_gaintable_all_index_en
Definition: ad9361.h:3086
uint8_t adc_ovr_sample_size
Definition: ad9361.h:2926
#define REG_TIA2_C_MSB
Definition: ad9361.h:400
uint8_t current_profile[2]
Definition: ad9361.h:3309
#define REG_AUXADC_CONFIG
Definition: ad9361.h:79
void ad9361_ensm_restore_state(struct ad9361_rf_phy *phy, uint8_t ensm_state)
Definition: ad9361.c:2075
Definition: ad9361.h:3057
#define FDD_MODE
Definition: ad9361.h:717
@ MAX_GAIN
Definition: ad9361.h:2915
#define MAX_CARRIER_FREQ_HZ
Definition: ad9361.h:2858
#define REG_RX_SYNTH_POWER_DOWN_OVERRIDE
Definition: ad9361.h:125
#define REG_TEMP_OFFSET
Definition: ad9361.h:61
#define ENABLE_TRACKING_MODE_CH2
Definition: ad9361.h:1771
@ T1_CLK
Definition: ad9361.h:3278
@ AGC_IN_FAST_ATTACK_MODE_LOCKS_THE_GAIN
Definition: ad9361.h:3041
#define REG_TX_QUAD_FULL_LMT_GAIN
Definition: ad9361.h:191
void ad9361_clear_state(struct ad9361_rf_phy *phy)
Definition: ad9361.c:5310
#define RX_GAIN_CTL_AGC_FAST_ATK
Definition: ad9361.h:1356
#define DCXO_TUNE_COARSE(x)
Definition: ad9361.h:2636
bool gpo_manual_mode_en
Definition: ad9361.h:3100
#define ENABLE_INCR_GAIN
Definition: ad9361.h:1472
#define REG_TEMP_SENSE2
Definition: ad9361.h:63
#define REG_QUAD_CAL_NCO_FREQ_PHASE_OFFSET
Definition: ad9361.h:181
#define REG_BBPLL
Definition: ad9361.h:60
bool rfdc_track_en
Definition: ad9361.h:3399
#define POST_LOCK_LEVEL_STP_FOR_LMT_TABLE(x)
Definition: ad9361.h:1491
#define REG_RFPLL_DIVIDERS
Definition: ad9361.h:56
#define RX_SYNTH_PTAT_POWER_DOWN
Definition: ad9361.h:946
#define MAN_GAIN_CTRL_RX2
Definition: ad9361.h:1367
int32_t ad9361_spi_readm(struct no_os_spi_desc *spi, uint32_t reg, uint8_t *rbuf, uint32_t num)
Definition: ad9361.c:700
bool elna_1_control_en
Definition: ad9361.h:3084
#define printk(format,...)
Definition: ad9361_util.h:72
#define MAX_LPF_GAIN
Definition: ad9361.h:2819
void ad9361_ensm_force_state(struct ad9361_rf_phy *phy, uint8_t ensm_state)
Definition: ad9361.c:1995
#define REG_RX_VCO_LDO
Definition: ad9361.h:489
#define TONE_LEVEL(x)
Definition: ad9361.h:2772
bool f_agc_rst_gla_engergy_lost_goto_optim_gain_en
Definition: ad9361.h:3006
uint8_t VCO_Cal_Offset
Definition: ad9361.h:3249
int32_t ad9361_fastlock_load(struct ad9361_rf_phy *phy, bool tx, uint32_t profile, uint8_t *values)
Definition: ad9361.c:5004
uint8_t VCO_Bias_Tcf
Definition: ad9361.h:3248
uint8_t gpo3_tx_delay_us
Definition: ad9361.h:3120
#define FORCE_RX_ON
Definition: ad9361.h:723
int32_t ad9361_en_dis_rx(struct ad9361_rf_phy *phy, uint32_t rx_if, uint32_t enable)
Definition: ad9361.c:1096
int32_t ad9361_reset(struct ad9361_rf_phy *phy)
Definition: ad9361.c:1048
#define TX_SYNTH_PTAT_POWER_DOWN
Definition: ad9361.h:955
#define FIR_WRITE
Definition: ad9361.h:1027
#define RX_FAST_LOCK_PROFILE_ADDR(x)
Definition: ad9361.h:2409
int32_t ad9361_set_trx_clock_chain(struct ad9361_rf_phy *phy, uint32_t *rx_path_clks, uint32_t *tx_path_clks)
Definition: ad9361.c:4646
int32_t ad9361_get_temp(struct ad9361_rf_phy *phy)
Definition: ad9361.c:4220
#define HAVE_TDD_SYNTH_TABLE
Definition: app_config.h:43
void ad9361_get_bist_loopback(struct ad9361_rf_phy *phy, int32_t *mode)
Definition: ad9361.c:1179
#define RX_BBF_R2346(x)
Definition: ad9361.h:2113
@ EXT_REF_CLK
Definition: ad9361.h:3288
int8_t offset
Definition: ad9361.h:3090
#define RX_LO_POWER_DOWN
Definition: ad9361.h:944
#define AD9363A_MAX_CARRIER_FREQ_HZ
Definition: ad9361.h:2862
int32_t ad9361_get_tx_atten(struct ad9361_rf_phy *phy, uint32_t tx_num)
Definition: ad9361.c:1687
#define REG_MEASURE_DURATION_23
Definition: ad9361.h:296
struct gain_table_info ad9361_adi_gt_info[]
Definition: ad9361.c:605
#define CALIBRATION_CONFIG2_DFLT
Definition: ad9361.h:1778
#define DEC_PWR_FOR_LOCK_LEVEL
Definition: ad9361.h:1347
#define FORCE_PD_RESET_RX2
Definition: ad9361.h:1417
#define REG_GM_SUB_TABLE_GAIN_READ
Definition: ad9361.h:281
@ ID_AD9364
Definition: ad9361.h:3336
#define REG_TIA2_C_LSB
Definition: ad9361.h:399
#define REG_RX1_MANUAL_DIGITALFORCED_GAIN
Definition: ad9361.h:242
Definition: ad9361.h:3420
#define GPO_ENABLE_AUTO_RX(x)
Definition: ad9361.h:813
uint16_t dac2_default_value
Definition: ad9361.h:3022
#define MAX_RX_HB3
Definition: ad9361.h:2842
#define GOTO_MAX_GAIN_OR_OPT_GAIN_IF_EN_AGC_HIGH
Definition: ad9361.h:1479
Header file of Delay functions.
#define AD_READ
Definition: ad9361.h:2804
#define FORCE_VCO_TUNE_ENABLE
Definition: ad9361.h:2456
int32_t gain_step_db
Definition: ad9361.h:3061
#define ENSM_STATE_INVALID
Definition: ad9361.h:769
uint8_t LF_R3
Definition: ad9361.h:3256
@ TX_SAMPL_FREQ
Definition: ad9361.h:3153
#define RX_1
Definition: ad9361.h:618
#define FDD_EXTERNAL_CTRL_ENABLE
Definition: ad9361.h:734
#define AGC_INNER_HIGH_THRESH_EXED_STP_SIZE(x)
Definition: ad9361.h:1555
#define START_GM_SUB_TABLE_CLOCK
Definition: ad9361.h:1671
Definition: ad9361.h:2921
uint64_t end
Definition: ad9361.h:2885
@ NO_GAIN_CHANGE
Definition: ad9361.h:2918
#define LEVEL_MODE
Definition: ad9361.h:726
#define RX_FAST_LOCK_PROFILE(x)
Definition: ad9361.h:2404
#define PORB_VCO_LOGIC
Definition: ad9361.h:2469
#define REG_TX_CLOCK_DATA_DELAY
Definition: ad9361.h:58
#define REG_TX_MON_HIGH_GAIN
Definition: ad9361.h:143
#define PREVENT_GAIN_INC
Definition: ad9361.h:1535
#define REG_GAIN_STP1
Definition: ad9361.h:261
#define REG_AUXADC_LSB
Definition: ad9361.h:81
#define REG_RX_FAST_LOCK_PROGRAM_CTRL
Definition: ad9361.h:504
#define REG_TEMPERATURE
Definition: ad9361.h:64
AXI ADC Device Descriptor.
Definition: axi_adc_core.h:128
#define REG_FRACT_BB_FREQ_WORD_3
Definition: ad9361.h:113
#define KEXP_DC_Q(x)
Definition: ad9361.h:1152
#define REG_RX_BBF_C3_LSB
Definition: ad9361.h:413
#define ad9361_spi_writef(spi, reg, mask, val)
Definition: ad9361.c:891
int32_t ad9361_tx_mute(struct ad9361_rf_phy *phy, uint32_t state)
Definition: ad9361.c:1712
#define TX_SYNTH_READY_MASK
Definition: ad9361.h:741
#define REG_GAIN_UPDATE_COUNTER1
Definition: ad9361.h:262
#define FREQ_CAL_ENABLE
Definition: ad9361.h:932
uint8_t agc_mode[2]
Definition: ad9361.h:3398
uint8_t gpo0_tx_delay_us
Definition: ad9361.h:3114
int8_t * abs_gain_tbl
Definition: ad9361.h:2888
Definition: no_os_clk.h:70
#define REG_AUXDAC_2_WORD
Definition: ad9361.h:75
#define TO_ALERT
Definition: ad9361.h:729
#define REG_RX_FRACT_BYTE_0
Definition: ad9361.h:469
#define TX_MON_2_GAIN(x)
Definition: ad9361.h:1072
bool gpo3_slave_tx_en
Definition: ad9361.h:3112
#define MAX_SYNTH_FREF
Definition: ad9361.h:2855
#define SMALL_LMT_OVERLOAD_THRESH(x)
Definition: ad9361.h:1419
#define BBPLL_LOCK
Definition: ad9361.h:1002
uint32_t gpo_manual_mode_enable_mask
Definition: ad9361.h:3099
#define REG_TX_VCO_OUTPUT
Definition: ad9361.h:516
@ TBL_1300_4000_MHZ
Definition: ad9361.h:2878
#define FORCE_ALC_WORD(x)
Definition: ad9361.h:2450
struct no_os_spi_desc * spi
Definition: ad9361.h:3342
#define LVDS_MODE
Definition: ad9361.h:708
#define RX_NCO_FREQ(x)
Definition: ad9361.h:1132
@ CLKOUT_ENABLE
Definition: ad5758.h:294
#define TX_REF_RESET_BAR
Definition: ad9361.h:2709
#define REG_DCXO_FINE_TUNE_LOW
Definition: ad9361.h:542
#define ENSM_STATE_SLEEP_WAIT
Definition: ad9361.h:761
#define REG_CALIBRATION_CTRL
Definition: ad9361.h:72
#define GT_RX1
Definition: ad9361.h:1633
uint8_t f_agc_optimized_gain_offset
Definition: ad9361.h:3002
@ TBL_4000_6000_MHZ
Definition: ad9361.h:2879
#define DONT_UNLOCK_GAIN_IF_ENERGY_LOST
Definition: ad9361.h:1469
#define DIG_GAIN_STP_SIZE(x)
Definition: ad9361.h:1392
#define REG_LARGE_LMT_OVERLOAD_THRESH
Definition: ad9361.h:239
int32_t ad9361_rf_port_setup(struct ad9361_rf_phy *phy, bool is_out, uint32_t rx_inputs, uint32_t txb)
Definition: ad9361.c:3643
#define ENABLE_RF_OFFSET_TRACKING
Definition: ad9361.h:1873
#define REG_RX_BBF_R2346
Definition: ad9361.h:407
#define REG_AGC_LOCK_LEVEL
Definition: ad9361.h:232
#define FINAL_OVER_RANGE_COUNT(x)
Definition: ad9361.h:1508
uint8_t rx_clk_data_delay
Definition: ad9361.h:3068
#define TX_OUTPUT
Definition: ad9361.h:626
void * ERR_PTR(long error)
ERR_PTR.
Definition: ad9361_util.c:314
#define REG_FAST_AGCLL_UPPER_LIMIT
Definition: ad9361.h:254
int32_t ilog2(int32_t x)
ilog2
Definition: ad9361_util.c:255
uint8_t cmd
Definition: ad9361.h:3297
#define REG_FAST_FINAL_OVER_RANGE_AND_OPT_GAIN
Definition: ad9361.h:252
int32_t ad9361_reg_read(struct ad9361_rf_phy *phy, uint32_t reg, uint32_t *val)
Definition: ad9361.c:760
#define REG_TX_MON_LOW_GAIN
Definition: ad9361.h:142
#define REG_GAIN_ERROR_READ
Definition: ad9361.h:287
#define DONT_UNLOCK_GAIN_IF_LG_ADC_OR_LMT_OVRG
Definition: ad9361.h:1471
bool current_tx_use_tdd_table
Definition: ad9361.h:3376
uint8_t VCO_Output_Level
Definition: ad9361.h:3245
@ DBGFS_NONE
Definition: ad9361.h:3430
int32_t ad9361_rfpll_int_set_rate(struct refclk_scale *clk_priv, uint32_t rate, uint32_t parent_rate)
Definition: ad9361.c:6869
uint8_t gpo2_rx_delay_us
Definition: ad9361.h:3117
uint8_t cached_rx_rfpll_div
Definition: ad9361.h:3362
#define TX_MON_DELAY_COUNTER(x)
Definition: ad9361.h:1046
uint32_t ant
Definition: ad9361.h:3223
#define REG_RX_BBBW_MHZ
Definition: ad9361.h:426
#define _SOFT_RESET
Definition: ad9361.h:585
#define REG_CTRL
Definition: ad9361.h:569
AD9361 Header file of Util driver.
#define RX2_FAST_ATK_SHIFT
Definition: ad9361.h:2736
enum ad9361_clocks parent_source
Definition: ad9361.h:3426
#define ONE_SHOT_MODE
Definition: ad9361.h:1059
#define RHB1_EN
Definition: ad9361.h:614
int32_t ad9361_set_dcxo_tune(struct ad9361_rf_phy *phy, uint32_t coarse, uint32_t fine)
Definition: ad9361.c:3529
uint32_t lmt_gain
Definition: ad9361.h:3226
@ FIR_RX1
Definition: ad9361.h:2896
int32_t ad9361_set_gain_ctrl_mode(struct ad9361_rf_phy *phy, struct rf_gain_ctrl *gain_ctrl)
Definition: ad9361.c:2384
uint8_t tx1_mon_lo_cm
Definition: ad9361.h:3133
@ DAC_FREQ
Definition: ad9361.h:3149
#define REG_GPO0_TX_DELAY
Definition: ad9361.h:94
#define REG_DCXO_COARSE_TUNE
Definition: ad9361.h:540
int32_t ad9361_rfpll_round_rate(struct refclk_scale *clk_priv, uint32_t rate)
Definition: ad9361.c:7058
int32_t ad9361_clk_mux_set_parent(struct refclk_scale *clk_priv, uint8_t index)
Definition: ad9361.c:7157
@ RX_RFPLL_DUMMY
Definition: ad9361.h:3283
#define LOOP_FILTER_R3(x)
Definition: ad9361.h:2514
#define ENABLE_GAIN_CORR
Definition: ad9361.h:1766
#define TX_QUAD_CAL
Definition: ad9361.h:749
uint8_t save_profile
Definition: ad9361.h:3308
struct no_os_clk * clk_refin
Definition: ad9361.h:3351
#define REG_TX_MON_2_CONFIG
Definition: ad9361.h:152
uint8_t mgc_inc_gain_step
Definition: ad9361.h:2943
#define REG_CLOCK_CTRL
Definition: ad9361.h:115
int32_t ad9361_1rx1tx_channel_map(struct ad9361_rf_phy *phy, bool tx, int32_t channel)
Definition: ad9361.c:1024
#define REG_PEAK_WAIT_TIME
Definition: ad9361.h:230
#define NO_OS_ARRAY_SIZE(x)
Definition: no_os_util.h:53
#define TX_EXT_VCO_BUFFER_POWER_DOWN
Definition: ad9361.h:987
#define REG_GAIN_TABLE_WRITE_DATA3
Definition: ad9361.h:272
#define REG_MEASURE_DURATION_01
Definition: ad9361.h:295
uint32_t filt_tx_path_clks[NUM_TX_CLOCKS]
Definition: ad9361.h:3391
#define REG_RSSI_WEIGHT_0
Definition: ad9361.h:297
uint32_t ad9361_rfpll_recalc_rate(struct refclk_scale *clk_priv)
Definition: ad9361.c:7016
#define BIST_MASK_CHANNEL_1_Q_DATA
Definition: ad9361.h:2789
#define MIN_TX_CARRIER_FREQ_HZ
Definition: ad9361.h:2860
#define CLK_IGNORE_UNUSED
Definition: ad9361_util.h:56
#define K_EXP_AMPLITUDE(x)
Definition: ad9361.h:1785
#define ENSM_STATE_TX
Definition: ad9361.h:763
struct ad9361_rf_phy * phy
Definition: ad9361.h:3422
#define REG_FAST_INCREMENT_TIME
Definition: ad9361.h:257
#define POWER_MEAS_IN_STATE_5(x)
Definition: ad9361.h:1436
#define REG_AUXDAC1_TX_DELAY
Definition: ad9361.h:99
#define TEMP_SENSE_PERIODIC_ENABLE
Definition: ad9361.h:671
uint8_t VCO_Varactor_Reference
Definition: ad9361.h:3250
#define RX_NCO_PHASE_OFFSET(x)
Definition: ad9361.h:1133
#define RX1_TUNE_RESAMPLE
Definition: ad9361.h:2099
bool f_agc_allow_agc_gain_increase
Definition: ad9361.h:2983
const char * ad9361_ensm_states[]
Definition: ad9361.c:687
#define DC_OFFSET_UPDATE(x)
Definition: ad9361.h:1874
@ T1_FREQ
Definition: ad9361.h:3151
const char * name
Definition: no_os_clk.h:73
uint32_t current_rx_path_clks[NUM_RX_CLOCKS]
Definition: ad9361.h:3378
#define REG_TX_SYMBOL_ATTEN_CONFIG
Definition: ad9361.h:163
#define REG_AUXDAC2_TX_DELAY
Definition: ad9361.h:101
#define REG_TX_FILTER_COEF_WRITE_DATA_2
Definition: ad9361.h:138
#define RSSI_RESOLUTION
Definition: ad9361.h:2815
uint8_t adc_large_overload_exceed_counter
Definition: ad9361.h:2960
#define REG_TX_FILTER_COEF_WRITE_DATA_1
Definition: ad9361.h:137
@ BIST_DISABLE
Definition: ad9361.h:3323
uint8_t Charge_Pump_Current
Definition: ad9361.h:3251
#define REG_GPO2_RX_DELAY
Definition: ad9361.h:92
int32_t ad9361_rfpll_dummy_set_rate(struct refclk_scale *clk_priv, uint32_t rate)
Definition: ad9361.c:7001
int32_t ad9361_set_trx_clock_chain(struct ad9361_rf_phy *phy, uint32_t *rx_path_clks, uint32_t *tx_path_clks)
Definition: ad9361.c:4646
uint8_t tx_clk_data_delay
Definition: ad9361.h:3069
#define REG_BB_DC_OFFSET_SHIFT
Definition: ad9361.h:348
uint16_t tx_mon_delay
Definition: ad9361.h:3129
#define REG_ADC_LARGE_OVERLOAD_THRESH
Definition: ad9361.h:236
int32_t tx_quad_lpf_tia_match
Definition: ad9361.h:3365
#define REG_RX_MIX_LO_CM
Definition: ad9361.h:393
#define AD_WRITE
Definition: ad9361.h:2805
uint8_t adc_large_overload_thresh
Definition: ad9361.h:2928
uint8_t ad9361_ensm_get_state(struct ad9361_rf_phy *phy)
Definition: ad9361.c:1982
#define REG_RX_FRACT_BYTE_1
Definition: ad9361.h:470
int32_t max_gain_db
Definition: ad9361.h:3060
int32_t ad9361_rfpll_round_rate(struct refclk_scale *clk_priv, uint32_t rate)
Definition: ad9361.c:7058
#define REG_TX_LO_GEN_POWER_MODE
Definition: ad9361.h:554
ad9361_pdata_tx_freq
Definition: ad9361.h:3147
#define RF_DC_OFFSET_ATTEN(x)
Definition: ad9361.h:1856
@ DO_IDELAY
Definition: ad9361.h:3316
uint16_t auxdac1_value
Definition: ad9361.h:3403
#define MCS_DIGITAL_CLK_ENABLE
Definition: ad9361.h:594
#define REG_STATE
Definition: ad9361.h:73
#define RX_REF_DOUBLER_FB_DELAY(x)
Definition: ad9361.h:2710
#define WRITE_MIXER_ERROR_TABLE
Definition: ad9361.h:1687
int32_t ad9361_hdl_loopback(struct ad9361_rf_phy *phy, bool enable)
Definition: ad9361_conv.c:113
#define ENSM_STATE_FDD
Definition: ad9361.h:767
#define TX_REF_DOUBLER_FB_DELAY(x)
Definition: ad9361.h:2712
#define RHB2_EN
Definition: ad9361.h:613
#define REG_GAIN_TABLE_READ_DATA2
Definition: ad9361.h:274
@ RX_SAMPL_CLK
Definition: ad9361.h:3275
int32_t ad9361_set_rx_gain(struct ad9361_rf_phy *phy, uint32_t rx_id, struct rf_rx_gain *rx_gain)
Definition: ad9361.c:2231
@ ADC_CLK_DIV_8
Definition: ad9361.h:3163
@ BIST_INJ_RX
Definition: ad9361.h:3325
#define THB2_EN
Definition: ad9361.h:600
enum ad9361_bist_mode bist_prbs_mode
Definition: ad9361.h:3412
uint32_t ad9361_gt(struct ad9361_rf_phy *phy)
Definition: ad9361.c:1382
#define INIT_BB_FO_CAL
Definition: ad9361.h:890
uint8_t agc_outer_thresh_high
Definition: ad9361.h:2950
uint64_t current_tx_lo_freq
Definition: ad9361.h:3374
uint8_t f_agc_lmt_final_settling_steps
Definition: ad9361.h:2993
#define TX1_LO_CONV
Definition: ad9361.h:1166
#define MAX_TX_HB1
Definition: ad9361.h:2844
bool mgc_rx1_ctrl_inp_en
Definition: ad9361.h:2940
Definition: ad9361.h:3123
#define PD_TUNE
Definition: ad9361.h:1279
#define REG_WAIT_COUNT
Definition: ad9361.h:340
#define REG_AUXDAC1_RX_DELAY
Definition: ad9361.h:98
#define RSSI_MODE_SELECT(x)
Definition: ad9361.h:1734
@ CLKRF_FREQ
Definition: ad9361.h:3142
#define RX2_GAIN_CTRL_SHIFT
Definition: ad9361.h:1353
#define RX_SYNTH_READY_MASK
Definition: ad9361.h:740
uint8_t curr_ensm_state
Definition: ad9361.h:3361
#define SYNTH_FRACT_WORD(x)
Definition: ad9361.h:2444
int32_t ad9361_spi_write(struct no_os_spi_desc *spi, uint32_t reg, uint32_t val)
Definition: ad9361.c:817
int32_t ad9361_find_opt(uint8_t *field, uint32_t size, uint32_t *ret_start)
Definition: ad9361.c:988
#define AGC_OUTER_LOW_THRESH(x)
Definition: ad9361.h:1569
#define IMMEDIATELY_UPDATE_TPC_ATTEN
Definition: ad9361.h:1098
#define MANUAL_CTRL_IN_DECR_GAIN_STP_SIZE(x)
Definition: ad9361.h:1386
uint8_t split_table
Definition: ad9361.h:2887
#define dev_warn(dev, format,...)
Definition: ad9361_util.h:70
#define REG_GPO3_RX_DELAY
Definition: ad9361.h:93
#define ENERGY_DETECT_COUNT(x)
Definition: ad9361.h:1515
enum f_agc_target_gain_index_type f_agc_gain_index_type_after_exit_rx_mode
Definition: ad9361.h:2999
bool f_agc_rst_gla_stronger_sig_thresh_exceeded_en
Definition: ad9361.h:3003
@ TX_RFPLL
Definition: ad9361.h:3286
uint64_t no_os_do_div(uint64_t *n, uint64_t base)
int32_t ad9361_rssi_gain_step_calib(struct ad9361_rf_phy *phy)
Definition: ad9361.c:7429
#define VCO_VARACTOR(x)
Definition: ad9361.h:2464
#define REG_TX_ATTEN_THRESH
Definition: ad9361.h:158
#define MAX_MIXER_CALIBRATION_GAIN_INDEX(x)
Definition: ad9361.h:1701
#define ENERGY_LOST_THRESH(x)
Definition: ad9361.h:1486
bool f_agc_rst_gla_engergy_lost_sig_thresh_exceeded_en
Definition: ad9361.h:3005
#define TUNE_CTRL(x)
Definition: ad9361.h:1282
bool dig_gain_en
Definition: ad9361.h:2936
void no_os_mdelay(uint32_t msecs)
Wait until msecs milliseconds passed.
Definition: aducm3029_delay.c:132
uint8_t ad9361_ensm_get_state(struct ad9361_rf_phy *phy)
Definition: ad9361.c:1982
#define REG_GAIN_RX1
Definition: ad9361.h:559
@ R1_FREQ
Definition: ad9361.h:3141
#define DIGITAL_GAIN_RX(x)
Definition: ad9361.h:2727
int32_t ad9361_set_trx_clock_chain_freq(struct ad9361_rf_phy *phy, uint32_t freq)
Definition: ad9361.c:4894
#define AGC_OUTER_HIGH_THRESH_EXED_STP_SIZE(x)
Definition: ad9361.h:1574
#define REG_FAST_ENERGY_DETECT_COUNT
Definition: ad9361.h:253
void * out_value
Definition: ad9361.h:3294
bool gpo0_slave_tx_en
Definition: ad9361.h:3106
#define START_GAIN_TABLE_CLOCK
Definition: ad9361.h:1631
int32_t ad9361_post_setup(struct ad9361_rf_phy *phy)
Definition: ad9361_conv.c:605
#define ENABLE_LMT_GAIN_INC_FOR_LOCK_LEVEL
Definition: ad9361.h:1478
#define no_os_min(x, y)
Definition: no_os_util.h:63
int32_t ad9361_do_calib_run(struct ad9361_rf_phy *phy, uint32_t cal, int32_t arg)
Definition: ad9361.c:5683
#define REG_REFERENCE_CLOCK_CYCLES
Definition: ad9361.h:105
int32_t ad9361_set_ensm_mode(struct ad9361_rf_phy *phy, bool fdd, bool pinctrl)
Definition: ad9361.c:4914
void ad9361_ensm_restore_state(struct ad9361_rf_phy *phy, uint8_t ensm_state)
Definition: ad9361.c:2075
#define GPO_MANUAL_CTRL(x)
Definition: ad9361.h:842
int32_t ad9361_set_rx_gain(struct ad9361_rf_phy *phy, uint32_t rx_id, struct rf_rx_gain *rx_gain)
Definition: ad9361.c:2231
@ NUM_TX_CLOCKS
Definition: ad9361.h:3154
uint16_t dac1_default_value
Definition: ad9361.h:3021
#define RX1_GAIN_CTRL_SETUP(x)
Definition: ad9361.h:1351
#define USE_HB1_OUT_FOR_DEC_PWR_MEAS
Definition: ad9361.h:1746
@ RESTORE_DEFAULT
Definition: ad9361.h:3319
#define AGCLL_MAX_INCREASE(x)
Definition: ad9361.h:1520
#define REG_CLOCK_ENABLE
Definition: ad9361.h:59
uint32_t ad9361_gt(struct ad9361_rf_phy *phy)
Definition: ad9361.c:1382
int32_t ad9361_reg_read(struct ad9361_rf_phy *phy, uint32_t reg, uint32_t *val)
Definition: ad9361.c:760
int32_t ad9361_tracking_control(struct ad9361_rf_phy *phy, bool bbdc_track, bool rfdc_track, bool rxquad_track)
Definition: ad9361.c:3323
#define REG_QUAD_CAL_CTRL
Definition: ad9361.h:182
@ LUT_FTDD_40
Definition: ad9361.h:3260
#define RSSI_LSB_MASK2
Definition: ad9361.h:1954
#define REG_RX_VCO_VARACTOR_CTRL_0
Definition: ad9361.h:497
int32_t ad9361_rfpll_set_rate(struct refclk_scale *clk_priv, uint32_t rate)
Definition: ad9361.c:7100
#define GPO_INIT_STATE(x)
Definition: ad9361.h:843
Header file of AD9361 Driver.
#define REG_GAIN_STP_2
Definition: ad9361.h:266
#define REG_RX_CP_LEVEL_DETECT
Definition: ad9361.h:492
#define VCO_BIAS_TCF(x)
Definition: ad9361.h:2526
#define NO_OS_DIV_ROUND_UP(x, y)
Definition: no_os_util.h:56
#define MCS_BBPLL_ENABLE
Definition: ad9361.h:593
#define REG_INPUT_SELECT
Definition: ad9361.h:55
@ DBGFS_RXGAIN_1
Definition: ad9361.h:3436
#define SETTLING_DELAY(x)
Definition: ad9361.h:1480
#define REG_CAPACITOR
Definition: ad9361.h:215
uint8_t prev_ensm_state
Definition: ad9361.h:3360
@ ID_AD9363A
Definition: ad9361.h:3337
#define REG_SMALL_LMT_OVERLOAD_THRESH
Definition: ad9361.h:238
@ FIR_RX2
Definition: ad9361.h:2897
#define REG_TX_FILTER_COEF_ADDR
Definition: ad9361.h:136
#define REG_GAIN_DIFF_WORDERROR_WRITE
Definition: ad9361.h:286
@ RX_REFCLK
Definition: ad9361.h:3268
#define VCO_VARACTOR_REFERENCE(x)
Definition: ad9361.h:2631
#define AUXDAC_AUTO_RX_BAR(x)
Definition: ad9361.h:827
@ SOFT_RESET
Definition: ad738x.h:141
#define RX_FAST_LOCK_PROFILE_PIN_SELECT
Definition: ad9361.h:2402
#define MAX_RX_HB1
Definition: ad9361.h:2840
#define REG_RX_FILTER_COEF_ADDR
Definition: ad9361.h:219
#define REG_RX_INTEGER_BYTE_1
Definition: ad9361.h:468
int32_t ad9361_get_auxadc(struct ad9361_rf_phy *phy)
Definition: ad9361.c:4236
uint32_t filt_rx_path_clks[NUM_RX_CLOCKS]
Definition: ad9361.h:3390
int32_t ad9361_calculate_rf_clock_chain(struct ad9361_rf_phy *phy, uint32_t tx_sample_rate, uint32_t rate_gov, uint32_t *rx_path_clks, uint32_t *tx_path_clks)
Definition: ad9361.c:4772
#define TX_MON_1_GAIN(x)
Definition: ad9361.h:1066
rf_gain_ctrl_mode
Definition: ad9361.h:2907
#define REG_TX_FRACT_BYTE_2
Definition: ad9361.h:511
void ad9361_get_bist_loopback(struct ad9361_rf_phy *phy, int32_t *mode)
Definition: ad9361.c:1179
#define CALIB_TABLE_SELECT(x)
Definition: ad9361.h:1691
Definition: ad9361_util.h:83
#define REG_AGC_ATTACK_DELAY
Definition: ad9361.h:84
@ ADC_CLK_DIV_3
Definition: ad9361.h:3161
#define TXNRX_SPI_CTRL
Definition: ad9361.h:737
@ IGNORE
Definition: ad9361.h:3148
#define REG_DEC_POWER_MEASURE_DURATION_0
Definition: ad9361.h:307
@ SKIP_STORE_RESULT
Definition: ad9361.h:3318
bool gpo1_slave_rx_en
Definition: ad9361.h:3107
#define DEC_STP_SIZE_FOR_LARGE_LMT_OVERLOAD(x)
Definition: ad9361.h:1405
#define REG_RF_DC_OFFSET_CONFIG_1
Definition: ad9361.h:342
#define REG_REF_DIVIDE_CONFIG_1
Definition: ad9361.h:557
@ BUFFERED_XTALN_DCXO
Definition: ad9361.h:3159
#define TX_MON_LOW_GAIN(x)
Definition: ad9361.h:1035
#define REG_LVDS_INVERT_CTRL1
Definition: ad9361.h:108
#define REG_GAIN_TABLE_WRITE_DATA2
Definition: ad9361.h:271
#define REG_TX_FILTER_COEF_READ_DATA_2
Definition: ad9361.h:140
int32_t ad9361_set_tx_atten(struct ad9361_rf_phy *phy, uint32_t atten_mdb, bool tx1, bool tx2, bool immed)
Definition: ad9361.c:1648
@ GAIN_CHANGE_OCCURS
Definition: ad9361.h:3044
struct no_os_gpio_desc * gpio_desc_cal_sw1
Definition: ad9361.h:3345
@ TX_REFCLK
Definition: ad9361.h:3269
int32_t ad9361_set_ensm_mode(struct ad9361_rf_phy *phy, bool fdd, bool pinctrl)
Definition: ad9361.c:4914
uint32_t f_agc_state_wait_time_ns
Definition: ad9361.h:2981
#define DCXO_TUNE_FINE_LOW(x)
Definition: ad9361.h:2641
#define REG_OUTER_POWER_THRESHS
Definition: ad9361.h:265
bool bypass_rx_fir
Definition: ad9361.h:3386
const bool have_tdd_tables
Definition: ad9361.c:63
int32_t ad9361_clk_factor_set_rate(struct refclk_scale *clk_priv, uint32_t rate, uint32_t parent_rate)
Definition: ad9361.c:6547
#define REG_RX_VCO_BIAS_1
Definition: ad9361.h:484
void ad9361_ensm_restore_prev_state(struct ad9361_rf_phy *phy)
Definition: ad9361.c:2130
@ RF_GAIN_MGC
Definition: ad9361.h:2908
bool f_agc_lock_level_lmt_gain_increase_en
Definition: ad9361.h:2989
@ ENTERS_RX_MODE
Definition: ad9361.h:3043
#define VCO_CAL_OFFSET(x)
Definition: ad9361.h:2458
#define ENSM_STATE_RX
Definition: ad9361.h:765
#define REG_ANALOG_POWER_DOWN_OVERRIDE
Definition: ad9361.h:132
#define RX_BB_TUNE_CAL
Definition: ad9361.h:746
#define ENABLE_DEC_PWR_MEAS
Definition: ad9361.h:1747
#define BIST_CTRL_POINT(x)
Definition: ad9361.h:2773
#define REG_RX_LO_GEN_POWER_MODE
Definition: ad9361.h:505
#define MAX_BBPLL_FREQ
Definition: ad9361.h:2824
int ad9361_synth_lo_powerdown(struct ad9361_rf_phy *phy, enum synth_pd_ctrl rx, enum synth_pd_ctrl tx)
Definition: ad9361.c:3474
int32_t ad9361_tx_mute(struct ad9361_rf_phy *phy, uint32_t state)
Definition: ad9361.c:1712
#define DEFAULT_RSSI_MEAS_MODE
Definition: ad9361.h:1732
uint8_t dig_saturation_exceed_counter
Definition: ad9361.h:2969
uint32_t ad9361_validate_rf_bw(struct ad9361_rf_phy *phy, uint32_t bw)
Definition: ad9361.c:946
#define REG_GPO3_TX_DELAY
Definition: ad9361.h:97
#define SETTLE_MAIN_ENABLE
Definition: ad9361.h:1139
int32_t ad9361_update_rf_bandwidth(struct ad9361_rf_phy *phy, uint32_t rf_rx_bw, uint32_t rf_tx_bw)
Definition: ad9361.c:5724
uint32_t bist_tone_level_dB
Definition: ad9361.h:3415
#define REG_GAIN_STP_CONFIG_2
Definition: ad9361.h:237
int32_t ad9361_bist_prbs(struct ad9361_rf_phy *phy, enum ad9361_bist_mode mode)
Definition: ad9361.c:1190
#define READ_SELECT
Definition: ad9361.h:1686
uint32_t ad9361_clk_factor_recalc_rate(struct refclk_scale *clk_priv, uint32_t parent_rate)
Definition: ad9361.c:6495
int32_t ad9361_rfpll_dummy_set_rate(struct refclk_scale *clk_priv, uint32_t rate)
Definition: ad9361.c:7001
#define ENABLE_TRACKING_MODE_CH1
Definition: ad9361.h:1772
#define FORCE_TX_ON
Definition: ad9361.h:724
uint8_t agc_outer_thresh_low
Definition: ad9361.h:2956
#define VCO_CAL_REF_TCF(x)
Definition: ad9144.h:947
enum ad9361_clocks source
Definition: ad9361.h:3425
int32_t ad9361_setup(struct ad9361_rf_phy *phy)
Definition: ad9361.c:5369
#define REG_RX_FORCE_ALC
Definition: ad9361.h:472
#define FORCE_PD_RESET_RX1
Definition: ad9361.h:1418
#define REG_RX1_MANUAL_LMT_FULL_GAIN
Definition: ad9361.h:240
uint16_t lmt_overload_low_thresh
Definition: ad9361.h:2931
#define FORCE_ALERT_STATE
Definition: ad9361.h:727
#define TX_LO_POWER_DOWN
Definition: ad9361.h:953
struct no_os_spi_desc * spi
Definition: ad9361.h:3421
#define CORRECTION_WORD_DECIMATION_M(x)
Definition: ad9361.h:1795
#define TX_MON_DURATION(x)
Definition: ad9361.h:1060
#define RX_REF_DIVIDER_MSB
Definition: ad9361.h:2703
#define REG_RSSI_WEIGHT_1
Definition: ad9361.h:298
uint8_t rx_fir_dec
Definition: ad9361.h:3396
void ad9361_get_bist_prbs(struct ad9361_rf_phy *phy, enum ad9361_bist_mode *mode)
Definition: ad9361.c:1221
struct ad9361_fastlock_entry entry[2][8]
Definition: ad9361.h:3310
#define TX_NCO_FREQ(x)
Definition: ad9361.h:1159
uint32_t ad9361_rfpll_int_recalc_rate(struct refclk_scale *clk_priv, uint32_t parent_rate)
Definition: ad9361.c:6784
void ad9361_get_bist_tone(struct ad9361_rf_phy *phy, enum ad9361_bist_mode *mode, uint32_t *freq_Hz, uint32_t *level_dB, uint32_t *mask)
Definition: ad9361.c:1294
#define REG_MAX_LMT_FULL_GAIN
Definition: ad9361.h:229
int32_t ad9361_fastlock_recall(struct ad9361_rf_phy *phy, bool tx, uint32_t profile)
Definition: ad9361.c:5179
uint8_t VCO_Varactor
Definition: ad9361.h:3246
struct no_os_gpio_desc * gpio_desc_resetb
Definition: ad9361.h:3343
#define REG_GAIN_TABLE_CONFIG
Definition: ad9361.h:276
bool auto_cal_en
Definition: ad9361.h:3370
ad9361_clkout
Definition: ad9361.h:3157
uint32_t mixer_index
Definition: ad9361.h:3232
#define REG_BB_DC_OFFSET_ATTEN
Definition: ad9361.h:352
@ T2_CLK
Definition: ad9361.h:3277
#define TX_BB_TUNE_CAL
Definition: ad9361.h:747
int32_t ad9361_bist_loopback(struct ad9361_rf_phy *phy, int32_t mode)
Definition: ad9361.c:1131
int32_t ad9361_load_fir_filter_coef(struct ad9361_rf_phy *phy, enum fir_dest dest, int32_t gain_dB, uint32_t ntaps, int16_t *coef)
Definition: ad9361.c:5835
uint16_t tx_mon_duration
Definition: ad9361.h:3130
#define ENSM_STATE_ALERT
Definition: ad9361.h:762
#define RX_FIR_ENABLE_DECIMATION(x)
Definition: ad9361.h:617
uint8_t agc_attack_delay_extra_margin_us
Definition: ad9361.h:2948
#define REG_RX_BBF_TUNE_CONFIG
Definition: ad9361.h:424
uint32_t digital_gain
Definition: ad9361.h:3228
uint8_t mgc_split_table_ctrl_inp_gain_mode
Definition: ad9361.h:2945
int32_t no_os_clk_set_rate(struct no_os_clk_desc *desc, uint64_t rate)
#define THB1_EN
Definition: ad9361.h:601
#define REG_SETTLE_TIME
Definition: ad9361.h:292
#define RX2_TUNE_RESAMPLE
Definition: ad9361.h:2106
#define REG_AUXDAC2_RX_DELAY
Definition: ad9361.h:100
#define AD_CNT(x)
Definition: ad9361.h:2806
#define SINGLE_DATA_RATE
Definition: ad9361.h:707
#define REG_PARALLEL_PORT_CONF_2
Definition: ad9361.h:67
#define RX_VCO_DIVIDER(x)
Definition: ad9361.h:633
@ FIR_TX1_TX2
Definition: ad9361.h:2895
#define REG_QUAD_SETTLE_COUNT
Definition: ad9361.h:185
int32_t ad9361_rssi_gain_step_calib(struct ad9361_rf_phy *phy)
Definition: ad9361.c:7429
uint32_t mult
Definition: ad9361.h:3423
struct axi_adc * rx_adc
Definition: ad9361.h:3348
#define REG_TX_SYNTH_POWER_DOWN_OVERRIDE
Definition: ad9361.h:126
#define MASTER_BIAS_TRIM(x)
Definition: ad9361.h:2688
bool tx_mon_track_en
Definition: ad9361.h:3124
int32_t ad9361_set_gain_ctrl_mode(struct ad9361_rf_phy *phy, struct rf_gain_ctrl *gain_ctrl)
Definition: ad9361.c:2384
#define REG_RSSI_DELAY
Definition: ad9361.h:301
uint32_t clk_get_rate(struct ad9361_rf_phy *phy, struct refclk_scale *clk_priv)
clk_get_rate
Definition: ad9361_util.c:67
int32_t starting_gain_db
Definition: ad9361.h:3059
#define DCXO_TUNE_FINE_HIGH(x)
Definition: ad9361.h:2646
int32_t ad9361_set_trx_clock_chain_freq(struct ad9361_rf_phy *phy, uint32_t freq)
Definition: ad9361.c:4894
#define REG_RX_VCO_OUTPUT
Definition: ad9361.h:476
enum dev_id dev_sel
Definition: ad9361.h:3341
#define REG_CALIBRATION_CONFIG_3
Definition: ad9361.h:316
@ RXGAIN_FULL_TBL
Definition: ad9361.h:2872
#define RX_GAIN_CTL_AGC_SLOW_ATK
Definition: ad9361.h:1357
int32_t ad9361_1rx1tx_channel_map(struct ad9361_rf_phy *phy, bool tx, int32_t channel)
Definition: ad9361.c:1024
#define REG_CP_BLEED_CURRENT
Definition: ad9361.h:117
#define EXTERNAL_LNA2_CTRL
Definition: ad9361.h:834
#define BIST_MASK_CHANNEL_2_I_DATA
Definition: ad9361.h:2788
#define ad9361_spi_readf(spi, reg, mask)
Definition: ad9361.c:807
#define RX1_GAIN_CTRL_SHIFT
Definition: ad9361.h:1354
struct ad9361_fastlock fastlock
Definition: ad9361.h:3407
uint8_t flags
Definition: ad9361.h:3302
#define REG_RX_FAST_LOCK_SETUP
Definition: ad9361.h:499
#define REG_RX_FAST_LOCK_PROGRAM_DATA
Definition: ad9361.h:502
#define REG_VCO_PROGRAM_1
Definition: ad9361.h:122
uint8_t f_agc_lpf_final_settling_steps
Definition: ad9361.h:2992
#define ENABLE_SYNC_FOR_GAIN_COUNTER
Definition: ad9361.h:1562
uint32_t ad9361_rfpll_recalc_rate(struct refclk_scale *clk_priv)
Definition: ad9361.c:7016
uint32_t filt_rx_bw_Hz
Definition: ad9361.h:3392
#define TX_VCO_DIVIDER(x)
Definition: ad9361.h:632
#define EXTERNAL_LNA1_CTRL
Definition: ad9361.h:835
uint8_t agc_inner_thresh_high
Definition: ad9361.h:2952
#define DEC_PWR_FOR_LOW_PWR
Definition: ad9361.h:1346
#define AGC_INNER_LOW_THRESH_EXED_STP_SIZE(x)
Definition: ad9361.h:1556
#define VCO_BIAS_REF(x)
Definition: ad9144.h:941
@ CLKOUT_DISABLE
Definition: ad5758.h:293
#define REG_RX2_MANUAL_LPF_GAIN
Definition: ad9361.h:244
#define EXT_LNA_HIGH_GAIN(x)
Definition: ad9361.h:1580
int32_t ad9361_ensm_set_state(struct ad9361_rf_phy *phy, uint8_t ensm_state, bool pinctrl)
Definition: ad9361.c:4440
enum ad9361_bist_mode bist_tone_mode
Definition: ad9361.h:3413
#define RX_MIX_LO_CM(x)
Definition: ad9361.h:2039
@ LO_OFF
Definition: ad9361.h:3330
#define REG_RX_INTEGER_BYTE_0
Definition: ad9361.h:467
#define OPTIMIZE_GAIN_OFFSET(x)
Definition: ad9361.h:1509
@ R2_CLK
Definition: ad9361.h:3272
#define ENABLE_PHASE_CORR
Definition: ad9361.h:1765
#define AUXADC_POWER_DOWN
Definition: ad9361.h:802
int32_t ad9361_bbpll_set_rate(struct refclk_scale *clk_priv, uint32_t rate, uint32_t parent_rate)
Definition: ad9361.c:6645
#define ENABLE_RX_DATA_PORT_FOR_CAL
Definition: ad9361.h:722
uint8_t agc_inner_thresh_high_dec_steps
Definition: ad9361.h:2953
#define REG_SDM_CTRL_1
Definition: ad9361.h:110
int32_t ad9361_fastlock_store(struct ad9361_rf_phy *phy, bool tx, uint32_t profile)
Definition: ad9361.c:5047
#define REG_RX_MIX_GM_CONFIG
Definition: ad9361.h:377
#define GAIN_ENABLE
Definition: ad9361.h:1141
#define REG_RX_ALC_VARACTOR
Definition: ad9361.h:475
#define REG_RSSI_WAIT_TIME
Definition: ad9361.h:302
uint64_t last_tx_quad_cal_freq
Definition: ad9361.h:3372
int32_t gain_db
Definition: ad9361.h:3224
@ LO_ON
Definition: ad9361.h:3331
#define RX_SYNTH_VCO_POWER_DOWN
Definition: ad9361.h:947
#define REG_OBSERVE_CONFIG
Definition: ad9361.h:571
uint32_t tx1_atten_cached
Definition: ad9361.h:3405
Structure holding SPI descriptor.
Definition: no_os_spi.h:177
#define IMMED_GAIN_CHANGE_IF_LG_LMT_OVERLOAD
Definition: ad9361.h:1553
#define REG_RX1_MANUAL_LPF_GAIN
Definition: ad9361.h:241
uint8_t size
Definition: ad9361.h:3296
#define RX_LPF_IDX_MASK
Definition: ad9361.h:1438
uint8_t dac2_rx_delay_us
Definition: ad9361.h:3036
rssi_restart_mode
Definition: ad9361.h:3040
#define REG_LVDS_BIAS_CTRL
Definition: ad9361.h:107
uint16_t lmt_overload_high_thresh
Definition: ad9361.h:2930
#define RX_FAST_LOCK_MODE_ENABLE
Definition: ad9361.h:2403
#define CLOCK_ENABLE_DFLT
Definition: ad9361.h:652
int32_t(* ad9361_rfpll_ext_round_rate)(struct refclk_scale *clk_priv, uint32_t rate)
Definition: ad9361.h:3355
#define no_os_clamp(val, min_val, max_val)
Definition: no_os_util.h:73
#define REG_LNA_GAIN
Definition: ad9361.h:308
void ad9361_clear_state(struct ad9361_rf_phy *phy)
Definition: ad9361.c:5310
@ RXGAIN_SPLIT_TBL
Definition: ad9361.h:2873
@ T2_FREQ
Definition: ad9361.h:3150
#define REG_MEASURE_DURATION
Definition: ad9361.h:293
int32_t ad9361_ensm_set_state(struct ad9361_rf_phy *phy, uint8_t ensm_state, bool pinctrl)
Definition: ad9361.c:4440
uint8_t f_agc_lock_level_gain_increase_upper_limit
Definition: ad9361.h:2990
#define TX_MON_1_LO_CM(x)
Definition: ad9361.h:1065
AXI DAC Device Descriptor.
Definition: axi_dac_core.h:54
uint32_t temp_sensor_decimation
Definition: ad9361.h:3092
bool dac1_in_alert_en
Definition: ad9361.h:3028
#define MIN_RX_CARRIER_FREQ_HZ
Definition: ad9361.h:2859
#define DIGITAL_POWER_UP
Definition: ad9361.h:651
#define AGC_USE_FULL_GAIN_TABLE
Definition: ad9361.h:1365
#define MAX_DAC_CLK
Definition: ad9361.h:2837
int32_t ad9361_spi_write(struct no_os_spi_desc *spi, uint32_t reg, uint32_t val)
Definition: ad9361.c:817
#define DONT_UNLOCK_GAIN_IF_STRONGER_SIGNAL
Definition: ad9361.h:1503
#define REG_FRACT_BB_FREQ_WORD_2
Definition: ad9361.h:112
bool f_agc_rst_gla_large_adc_overload_en
Definition: ad9361.h:3009
uint32_t ad9361_clk_factor_recalc_rate(struct refclk_scale *clk_priv, uint32_t parent_rate)
Definition: ad9361.c:6495
#define REG_ENSM_CONFIG_2
Definition: ad9361.h:71
#define MAX_BBPLL_DIV
Definition: ad9361.h:2825
ad9361_clocks
Definition: ad9361.h:3266
Definition: ad9361.h:3340
uint8_t f_agc_lp_thresh_increment_time
Definition: ad9361.h:2984
#define RX_GAIN_CTL_MASK
Definition: ad9361.h:1352
@ FIR_IS_RX
Definition: ad9361.h:2899
bool gpo2_slave_tx_en
Definition: ad9361.h:3110
int32_t ad9361_setup(struct ad9361_rf_phy *phy)
Definition: ad9361.c:5369
#define HAVE_SPLIT_GAIN_TABLE
Definition: app_config.h:42
#define REG_CP_CURRENT
Definition: ad9361.h:116
bool dac2_in_alert_en
Definition: ad9361.h:3032
int32_t ad9361_get_temp(struct ad9361_rf_phy *phy)
Definition: ad9361.c:4220
#define PREVENT_POS_LOOP_GAIN
Definition: ad9361.h:1784
Definition: ad9361.h:2902
debugfs_cmd
Definition: ad9361.h:3429
#define INCREMENT_GAIN_STP_LPFLMT(x)
Definition: ad9361.h:1514
uint8_t LF_C1
Definition: ad9361.h:3253
uint8_t f_agc_energy_lost_stronger_sig_gain_lock_exit_cnt
Definition: ad9361.h:3008
#define REG_RX_VCO_VARACTOR_CTRL_1
Definition: ad9361.h:498
uint8_t f_agc_power_measurement_duration_in_state5
Definition: ad9361.h:3016
#define REG_RX_FORCE_VCO_TUNE_0
Definition: ad9361.h:473
#define WRITE_GM_SUB_TABLE
Definition: ad9361.h:1670
#define TX_CHANNEL_ENABLE(x)
Definition: ad9361.h:602
int32_t ad9361_spi_read(struct no_os_spi_desc *spi, uint32_t reg)
Definition: ad9361.c:741
#define DONT_UNLOCK_GAIN_IF_ADC_OVRG
Definition: ad9361.h:1497
Structure holding the GPIO descriptor.
Definition: no_os_gpio.h:102
uint16_t auxdac2_value
Definition: ad9361.h:3404
#define FAST_ATK_GAIN_LOCKED
Definition: ad9361.h:2742
#define MCS_RF_ENABLE
Definition: ad9361.h:592
#define CLK_GET_RATE_NOCACHE
Definition: ad9361_util.h:57
int32_t ad9361_unregister_clocks(struct ad9361_rf_phy *phy)
Definition: ad9361.c:7409
uint8_t cached_synth_pd[2]
Definition: ad9361.h:3364
#define REG_LMT_OVERLOAD_COUNTERS
Definition: ad9361.h:259
#define AD9363A_MIN_CARRIER_FREQ_HZ
Definition: ad9361.h:2863
#define REG_CONFIG0
Definition: ad9361.h:213
uint8_t VCO_Bias_Ref
Definition: ad9361.h:3247
uint32_t(* ad9361_rfpll_ext_recalc_rate)(struct refclk_scale *clk_priv)
Definition: ad9361.h:3354
#define REG_ADC_SMALL_OVERLOAD_THRESH
Definition: ad9361.h:235
const bool has_split_gt
Definition: ad9361.c:62
#define BB_DC_M_SHIFT(x)
Definition: ad9361.h:1891
#define REG_VCO_CTRL
Definition: ad9361.h:121
#define REG_GAIN_TABLE_ADDRESS
Definition: ad9361.h:269
Definition: ad9361.h:3089
uint32_t current_rx_bw_Hz
Definition: ad9361.h:3382
int32_t ad9361_validate_enable_fir(struct ad9361_rf_phy *phy)
Definition: ad9361.c:6091
int32_t ad9361_bist_loopback(struct ad9361_rf_phy *phy, int32_t mode)
Definition: ad9361.c:1131
uint16_t gain_mdB
Definition: ad9361.h:3081
#define REG_AUTO_GPO
Definition: ad9361.h:82
uint8_t max_index
Definition: ad9361.h:2886
uint32_t val
Definition: ad9361.h:3295
#define REG_BANDGAP_CONFIG0
Definition: ad9361.h:555
uint32_t auxadc_clock_rate
Definition: ad9361.h:3094
#define AUXDAC_MANUAL_BAR(x)
Definition: ad9361.h:825
uint32_t lpf_gain
Definition: ad9361.h:3227
bool quad_track_en
Definition: ad9361.h:3401
int32_t ad9361_parse_fir(struct ad9361_rf_phy *phy, char *data, uint32_t size)
Definition: ad9361.c:5920
bool bbpll_initialized
Definition: ad9361.h:3417
uint8_t tx_fir_int
Definition: ad9361.h:3394
#define AUXDAC_MANUAL_SELECT
Definition: ad9361.h:833
Definition: ad9361.h:2883
uint32_t temp_time_inteval_ms
Definition: ad9361.h:3091
#define MAX_MBYTE_SPI
Definition: ad9361.h:2850
uint8_t mgc_dec_gain_step
Definition: ad9361.h:2944
int32_t ad9361_read_rssi(struct ad9361_rf_phy *phy, struct rf_rssi *rssi)
Definition: ad9361.c:2459
uint16_t VCO_MHz
Definition: ad9361.h:3244
#define MEASUREMENT_DURATION_0(x)
Definition: ad9361.h:1719
#define REG_DCXO_FINE_TUNE_HIGH
Definition: ad9361.h:541
#define REG_KEXP_2
Definition: ad9361.h:184
@ CLKTF_CLK
Definition: ad9361.h:3279
#define KEXP_TX(x)
Definition: ad9361.h:1149
uint32_t low_high_gain_threshold_mdB
Definition: ad9361.h:3126
#define REG_RX_FORCE_VCO_TUNE_1
Definition: ad9361.h:474
uint32_t last_tx_quad_cal_phase
Definition: ad9361.h:3373
@ CLKTF_FREQ
Definition: ad9361.h:3152
#define MAX_TX_HB2
Definition: ad9361.h:2845
struct refclk_scale * ref_clk_scale[NUM_AD9361_CLKS]
Definition: ad9361.h:3353
uint32_t ad9361_to_clk(uint64_t freq)
Definition: ad9361.c:1398
int32_t ad9361_validate_rfpll(struct ad9361_rf_phy *phy, bool is_tx, uint64_t freq)
Definition: ad9361.c:963
@ CLKOUT_DISABLE
Definition: ad9361.h:3158
#define CP_OFFSET_OFF
Definition: ad9361.h:2490
int32_t ad9361_set_tx_atten(struct ad9361_rf_phy *phy, uint32_t atten_mdb, bool tx1, bool tx2, bool immed)
Definition: ad9361.c:1648
#define WRITE_GAIN_TABLE
Definition: ad9361.h:1630
#define IMMED_GAIN_CHANGE_IF_LG_ADC_OVERLOAD
Definition: ad9361.h:1554
#define REG_GPO2_TX_DELAY
Definition: ad9361.h:96
#define REG_TX_ENABLE_FILTER_CTRL
Definition: ad9361.h:53
#define REG_TX_BBF_TUNE_DIVIDER
Definition: ad9361.h:217
#define BB_DC_OFFSET_ATTEN(x)
Definition: ad9361.h:1904
@ RX_RFPLL
Definition: ad9361.h:3285
int32_t ad9361_clk_factor_set_rate(struct refclk_scale *clk_priv, uint32_t rate, uint32_t parent_rate)
Definition: ad9361.c:6547
#define REG_TX1_ATTEN_1
Definition: ad9361.h:154
void * no_os_malloc(size_t size)
Allocate memory and return a pointer to it.
Definition: chibios_alloc.c:49
#define TUNER_RESAMPLE
Definition: ad9361.h:1280
#define REG_GAIN_RX2
Definition: ad9361.h:564
#define no_os_clamp_t(type, val, min_val, max_val)
Definition: no_os_util.h:75
@ DAC_CLK
Definition: ad9361.h:3276
uint8_t max_dig_gain
Definition: ad9361.h:2937
int32_t idx_step_offset
Definition: ad9361.h:3063
#define RX_EXT_VCO_BUFFER_POWER_DOWN
Definition: ad9361.h:986
bool f_agc_rst_gla_en_agc_pulled_high_en
Definition: ad9361.h:3011
uint8_t tx2_mon_lo_cm
Definition: ad9361.h:3134
#define BBPLL_ENABLE
Definition: ad9361.h:653
#define BYPASS_LD_SYNTH
Definition: ad9361.h:2431
uint8_t LF_C2
Definition: ad9361.h:3252
#define AD9364_DEVICE
Definition: app_config.h:46
#define EXT_LNA_CTRL
Definition: ad9361.h:1595
int32_t ad9361_rfpll_int_set_rate(struct refclk_scale *clk_priv, uint32_t rate, uint32_t parent_rate)
Definition: ad9361.c:6869
int ad9361_synth_lo_powerdown(struct ad9361_rf_phy *phy, enum synth_pd_ctrl rx, enum synth_pd_ctrl tx)
Definition: ad9361.c:3474
#define SETTLE_TIME(x)
Definition: ad9361.h:1708
uint8_t alc_written
Definition: ad9361.h:3304
uint8_t en_mask
Definition: ad9361.h:3077
int32_t ad9361_bist_prbs(struct ad9361_rf_phy *phy, enum ad9361_bist_mode mode)
Definition: ad9361.c:1190
uint8_t mode
Definition: ad9361.h:2904
int32_t ad9361_get_trx_clock_chain(struct ad9361_rf_phy *phy, uint32_t *rx_path_clks, uint32_t *tx_path_clks)
Definition: ad9361.c:4734
#define DIG_SATURATION_EXED_COUNTER(x)
Definition: ad9361.h:1563
bool auxdac_manual_mode_en
Definition: ad9361.h:3024
#define REG_MAG_FTEST_THRESH_2
Definition: ad9361.h:187
int32_t ad9361_bbpll_set_rate(struct refclk_scale *clk_priv, uint32_t rate, uint32_t parent_rate)
Definition: ad9361.c:6645
bool dac2_in_tx_en
Definition: ad9361.h:3031
int32_t ad9361_mcs(struct ad9361_rf_phy *phy, int32_t step)
Definition: ad9361.c:5255
#define FULL_TABLE_GAIN_INDEX(x)
Definition: ad9361.h:2717
Definition: ad9361.h:3243
dig_tune_flags
Definition: ad9361.h:3313
#define RX_2
Definition: ad9361.h:619
#define RX_GAIN_CTL_AGC_SLOW_ATK_HYBD
Definition: ad9361.h:1358
#define REG_AUXADC_CLOCK_DIVIDER
Definition: ad9361.h:78
int32_t ad9361_set_dcxo_tune(struct ad9361_rf_phy *phy, uint32_t coarse, uint32_t fine)
Definition: ad9361.c:3529
bool dac1_in_rx_en
Definition: ad9361.h:3026
#define FDD_RX_RATE_2TX_RATE
Definition: ad9361.h:705
uint8_t gpo1_rx_delay_us
Definition: ad9361.h:3115
#define REG_GM_SUB_TABLE_ADDRESS
Definition: ad9361.h:277
@ TX_RFPLL_INT
Definition: ad9361.h:3282
uint32_t bist_tone_mask
Definition: ad9361.h:3416
#define no_os_max_t(type, x, y)
Definition: no_os_util.h:70
uint32_t flags
Definition: ad9361.h:3380
int32_t ad9361_fastlock_save(struct ad9361_rf_phy *phy, bool tx, uint32_t profile, uint8_t *values)
Definition: ad9361.c:5235
const char * propname
Definition: ad9361.h:3293
bool rx_eq_2tx
Definition: ad9361.h:3388
#define FIR_NUM_TAPS(x)
Definition: ad9361.h:1029
#define REG_GM_SUB_TABLE_GAIN_WRITE
Definition: ad9361.h:278
#define MAXIMUM_DIGITAL_GAIN(x)
Definition: ad9361.h:1393
#define LARGE_LMT_OVERLOAD_EXED_COUNTER(x)
Definition: ad9361.h:1541
#define REG_DIGITAL_GAIN
Definition: ad9361.h:231
#define REG_RX_VCO_PD_OVERRIDES
Definition: ad9361.h:487
uint8_t f_agc_lock_level
Definition: ad9361.h:2988
#define FIR_SELECT(x)
Definition: ad9361.h:1028
#define REG_BB_DC_OFFSET_COUNT
Definition: ad9361.h:351
#define RX_FULL_TBL_IDX_MASK
Definition: ad9361.h:1431
#define DC_OFFSET_ENABLE
Definition: ad9361.h:1140
#define M_DECIM(x)
Definition: ad9361.h:1144
#define TX_MON_HIGH_GAIN(x)
Definition: ad9361.h:1040
#define REG_GPO0_RX_DELAY
Definition: ad9361.h:90
#define REG_AUXDAC_ENABLE_CTRL
Definition: ad9361.h:85
#define NO_OS_BIT(x)
Definition: no_os_util.h:51
#define AUXDAC_2_WORD_LSB(x)
Definition: ad9361.h:792
@ FIR_TX2
Definition: ad9361.h:2894
@ OPTIMIZED_GAIN
Definition: ad9361.h:2917
@ RX_SAMPL_FREQ
Definition: ad9361.h:3143
void no_os_free(void *ptr)
Deallocate memory previously allocated by a call to no_os_calloc or no_os_malloc.
Definition: chibios_alloc.c:75
#define DECREMENT_STP_SIZE_FOR_SMALL_LPF_GAIN_CHANGE(x)
Definition: ad9361.h:1411
#define HALF_DUPLEX_MODE
Definition: ad9361.h:709
uint64_t current_rx_lo_freq
Definition: ad9361.h:3375
#define REG_TX_BBF_TUNE_MODE
Definition: ad9361.h:218
#define REG_CTRL_OUTPUT_POINTER
Definition: ad9361.h:102
uint32_t rxbbf_div
Definition: ad9361.h:3384
uint32_t rate_governor
Definition: ad9361.h:3385
#define REG_PARALLEL_PORT_CONF_3
Definition: ad9361.h:68
#define FREE_RUN_MODE
Definition: ad9361.h:1769
@ DBGFS_LOOPBACK
Definition: ad9361.h:3432
#define RF_DC_CALIBRATION_COUNT(x)
Definition: ad9361.h:1850
int32_t ad9361_load_fir_filter_coef(struct ad9361_rf_phy *phy, enum fir_dest dest, int32_t gain_dB, uint32_t ntaps, short *coef)
int32_t ad9361_register_clocks(struct ad9361_rf_phy *phy)
Definition: ad9361.c:7294
#define SLOW_ATTACK_HYBRID_MODE
Definition: ad9361.h:1349
#define AUXDAC_1_VREF(x)
Definition: ad9361.h:783
#define CP_CAL_ENABLE
Definition: ad9361.h:2492
#define VCO_VARACTOR_REFERENCE_TCF(x)
Definition: ad9361.h:2625
int32_t ad9361_mcs(struct ad9361_rf_phy *phy, int32_t step)
Definition: ad9361.c:5255
uint8_t gpo3_rx_delay_us
Definition: ad9361.h:3119
int32_t ad9361_en_dis_tx(struct ad9361_rf_phy *phy, uint32_t tx_if, uint32_t enable)
Definition: ad9361.c:1079
@ DO_ODELAY
Definition: ad9361.h:3317
bool gpo1_slave_tx_en
Definition: ad9361.h:3108
bool gpo1_inactive_state_high_en
Definition: ad9361.h:3102
#define RX_DIGITAL_IDX_MASK
Definition: ad9361.h:1445
#define REG_RX_LOOP_FILTER_1
Definition: ad9361.h:480
#define REG_MAX_MIXER_CALIBRATION_GAIN_INDEX
Definition: ad9361.h:290
#define RFPLL_MODULUS
Definition: ad9361.h:2852
@ LUT_FTDD_ENT
Definition: ad9361.h:3263
uint8_t alc_orig
Definition: ad9361.h:3303
#define GT_RX2
Definition: ad9361.h:1634
#define TX_FIR_GAIN_6DB
Definition: ad9361.h:1025
#define CTRL_ENABLE
Definition: ad9361.h:2764
@ TX_RFPLL_DUMMY
Definition: ad9361.h:3284
uint8_t lvds_invert[2]
Definition: ad9361.h:3072
uint64_t ad9361_from_clk(uint32_t freq)
Definition: ad9361.c:1409
#define BANDGAP_TEMP_TRIM(x)
Definition: ad9361.h:2696
#define TX1_MON_ENABLE
Definition: ad9361.h:1058
bool gpo2_slave_rx_en
Definition: ad9361.h:3109
void no_os_udelay(uint32_t usecs)
Wait until usecs microseconds passed.
Definition: aducm3029_delay.c:120
#define REG_TIA1_C_LSB
Definition: ad9361.h:397
#define REG_AGC_CONFIG_3
Definition: ad9361.h:228
#define REG_TX_CP_OVERRANGE_VCO_LOCK
Definition: ad9361.h:529
#define REG_QUAD_CAL_STATUS_TX2
Definition: ad9361.h:189
#define REG_RX_CP_CURRENT
Definition: ad9361.h:477
#define USE_WAIT_COUNTER_FOR_RF_DC_INIT_CAL
Definition: ad9361.h:1869
uint8_t f_agc_large_overload_inc_steps
Definition: ad9361.h:3017
int32_t ad9361_init_gain_tables(struct ad9361_rf_phy *phy)
#define REG_REF_DIVIDE_CONFIG_2
Definition: ad9361.h:558
#define NULL
Definition: wrapper.h:64
#define MAX_RX_HB2
Definition: ad9361.h:2841
bool gpo2_inactive_state_high_en
Definition: ad9361.h:3103
int32_t ad9361_dig_interface_timing_analysis(struct ad9361_rf_phy *phy, char *buf, int32_t buflen)
Definition: ad9361_conv.c:288
#define REG_SPI_CONF
Definition: ad9361.h:51
@ ADC_CLK_DIV_2
Definition: ad9361.h:3160
#define TX2_SSB_CONV
Definition: ad9361.h:1174
int32_t(* ad9361_rfpll_ext_set_rate)(struct refclk_scale *clk_priv, uint32_t rate)
Definition: ad9361.h:3357
#define REG_RX_FILTER_GAIN
Definition: ad9361.h:225
uint32_t auxadc_decimation
Definition: ad9361.h:3095
#define SIZE_SPLIT_TABLE
Definition: ad9361.c:526
int32_t ad9361_spi_readm(struct no_os_spi_desc *spi, uint32_t reg, uint8_t *rbuf, uint32_t num)
Definition: ad9361.c:700
uint8_t f_agc_rst_gla_stronger_sig_thresh_above_ll
Definition: ad9361.h:3004
#define REG_AUXDAC_1_WORD
Definition: ad9361.h:74
#define REG_PARALLEL_PORT_CONF_1
Definition: ad9361.h:66
#define NO_GAIN_TABLE
Definition: ad9361.c:59
#define diff_abs(x, y)
Definition: ad9361.c:57
#define REG_GPO1_TX_DELAY
Definition: ad9361.h:95
uint8_t dac2_tx_delay_us
Definition: ad9361.h:3037
struct axi_dac * tx_dac
Definition: ad9361.h:3349
#define INVERT_RX2
Definition: ad9361.h:696
#define REG_GAIN_TABLE_WRITE_DATA1
Definition: ad9361.h:270
bool mgc_rx2_ctrl_inp_en
Definition: ad9361.h:2941
int32_t no_os_gpio_set_value(struct no_os_gpio_desc *desc, uint8_t value)
Set the value of the specified GPIO.
Definition: no_os_gpio.c:203
#define INCDEC_LMT_GAIN
Definition: ad9361.h:1373
@ ADC_FREQ
Definition: ad9361.h:3139
#define QUAD_CAL_SOFT_RESET
Definition: ad9361.h:1143
#define GAIN_LOCK_EXIT_COUNT(x)
Definition: ad9361.h:1525
#define WRITE_LNA_GAIN_DIFF
Definition: ad9361.h:1689
int32_t ad9361_read_rssi(struct ad9361_rf_phy *phy, struct rf_rssi *rssi)
Definition: ad9361.c:2459
#define VCO_CAL_EN
Definition: ad9361.h:2579
#define TX_2
Definition: ad9361.h:606
int32_t ad9361_en_dis_tx(struct ad9361_rf_phy *phy, uint32_t tx_if, uint32_t enable)
Definition: ad9361.c:1079
#define RX_GAIN_CTL_MGC
Definition: ad9361.h:1355
Definition: ad9361.h:3075
#define REG_RESISTOR
Definition: ad9361.h:214
@ ADC_CLK_DIV_16
Definition: ad9361.h:3164
uint8_t low_gain_dB
Definition: ad9361.h:3127
@ DBGFS_RXGAIN_2
Definition: ad9361.h:3437
#define TO_LNA_GAIN(x)
Definition: ad9361.h:1614
@ LUT_FTDD_60
Definition: ad9361.h:3261
#define WRITE_LNA_ERROR_TABLE
Definition: ad9361.h:1688
@ R1_CLK
Definition: ad9361.h:3273
uint8_t digital_io_ctrl
Definition: ad9361.h:3070
uint8_t adc_small_overload_thresh
Definition: ad9361.h:2927
#define RX_REF_RESET_BAR
Definition: ad9361.h:2702
uint32_t ad9361_to_clk(uint64_t freq)
Definition: ad9361.c:1398
int32_t ad9361_do_calib_run(struct ad9361_rf_phy *phy, uint32_t cal, int32_t arg)
Definition: ad9361.c:5683
uint32_t tia_index
Definition: ad9361.h:3231
#define MAX_BBPLL_FREF
Definition: ad9361.h:2822
#define REG_CONFIG
Definition: ad9361.h:288
uint8_t agc_outer_thresh_low_inc_steps
Definition: ad9361.h:2957
#define REG_START_TEMP_READING
Definition: ad9361.h:62
@ BIST_INJ_TX
Definition: ad9361.h:3324
#define MAX_BASEBAND_RATE
Definition: ad9361.h:2848
uint32_t ant
Definition: ad9361.h:2903
#define GPO_ENABLE_AUTO_TX(x)
Definition: ad9361.h:814
#define REG_RSSI_WEIGHT_3
Definition: ad9361.h:300
bool ensm_pin_ctl_en
Definition: ad9361.h:3368
#define RSSI_MAX_WEIGHT
Definition: ad9361.h:2816
#define MCS_REFCLK_SCALE_EN
Definition: ad9361.h:906
uint32_t filt_tx_bw_Hz
Definition: ad9361.h:3393
#define dev_dbg(dev, format,...)
Definition: ad9361_util.h:71
#define DAC_FS(x)
Definition: ad9361.h:1849
#define REG_AGC_CONFIG_1
Definition: ad9361.h:226
#define BBPLL_RESET_BAR
Definition: ad9361.h:891
uint32_t current_table
Definition: ad9361.h:3366
#define TIA_GAIN
Definition: ad9361.h:1602
#define VCO_VARACTOR_OFFSET(x)
Definition: ad9361.h:2626
#define SMALL_LMT_OVERLOAD_EXED_COUNTER(x)
Definition: ad9361.h:1542
#define RX1_PD_TUNE
Definition: ad9361.h:2100
#define REG_TX_FAST_LOCK_SETUP
Definition: ad9361.h:548
int32_t max_idx
Definition: ad9361.h:3062
#define USE_AGC_FOR_LMTLPF_GAIN
Definition: ad9361.h:1374
#define K_EXP_PHASE(x)
Definition: ad9361.h:1779
#define TX_FIR_ENABLE_INTERPOLATION(x)
Definition: ad9361.h:604
int32_t ad9361_rfpll_set_rate(struct refclk_scale *clk_priv, uint32_t rate)
Definition: ad9361.c:7100
bool txmon_tdd_en
Definition: ad9361.h:3402
#define REG_RX_BBBW_KHZ
Definition: ad9361.h:427
uint8_t f_agc_lp_thresh_increment_steps
Definition: ad9361.h:2985
int32_t ad9361_auxdac_get(struct ad9361_rf_phy *phy, int32_t dac)
Definition: ad9361.c:4126
#define RX1_FAST_ATK_SHIFT
Definition: ad9361.h:2735
uint8_t LF_C3
Definition: ad9361.h:3255
uint32_t settling_delay_ns
Definition: ad9361.h:3083
#define AGC_OUTER_HIGH_THRESH(x)
Definition: ad9361.h:1568
uint32_t f_agc_dec_pow_measuremnt_duration
Definition: ad9361.h:2980
#define REG_FAST_STRONG_SIGNAL_FREEZE
Definition: ad9361.h:251
#define REG_RX2_MANUAL_DIGITALFORCED_GAIN
Definition: ad9361.h:245
#define REG_FAST_ENERGY_LOST_THRESH
Definition: ad9361.h:248
@ EN_AGC_PIN_IS_PULLED_HIGH
Definition: ad9361.h:3042
#define RX_LO_GEN_POWER_MODE(x)
Definition: ad9361.h:2424
#define REG_FAST_CONFIG_2_SETTLING_DELAY
Definition: ad9361.h:247
#define REG_ENSM_CONFIG_1
Definition: ad9361.h:70
#define MASK_CLR_ATTEN_UPDATE
Definition: ad9361.h:1087
#define REG_LOOP_FILTER_3
Definition: ad9361.h:120
bool f_agc_use_last_lock_level_for_set_gain_en
Definition: ad9361.h:3001
#define REG_RX2_MANUAL_LMT_FULL_GAIN
Definition: ad9361.h:243
uint32_t current_tx_bw_Hz
Definition: ad9361.h:3383
#define VCO_OUTPUT_LEVEL(x)
Definition: ad9361.h:2470
uint8_t gpo1_tx_delay_us
Definition: ad9361.h:3116
#define REG_RX_LOOP_FILTER_2
Definition: ad9361.h:481
@ ADC_CLK
Definition: ad9361.h:3271
#define GAIN_CAL_MEAS_DURATION(x)
Definition: ad9361.h:1713
#define REG_FAST_STRONGER_SIGNAL_THRESH
Definition: ad9361.h:249
@ RX_RFPLL_INT
Definition: ad9361.h:3281
#define REG_RX_CLOCK_DATA_DELAY
Definition: ad9361.h:57
#define REG_RF_DC_OFFSET_ATTEN
Definition: ad9361.h:343
int32_t ad9361_unregister_clocks(struct ad9361_rf_phy *phy)
Definition: ad9361.c:7409
uint8_t f_agc_final_overrange_count
Definition: ad9361.h:2994
#define ENSM_STATE(x)
Definition: ad9361.h:760
#define AGC_LOCK_LEVEL_FAST_AGC_INNER_HIGH_THRESH_SLOW(x)
Definition: ad9361.h:1399
#define LOOP_FILTER_C3(x)
Definition: ad9361.h:2505
uint8_t gpo0_rx_delay_us
Definition: ad9361.h:3113
int32_t ad9361_get_rx_gain(struct ad9361_rf_phy *phy, uint32_t rx_id, struct rf_rx_gain *rx_gain)
Definition: ad9361.c:1916
uint8_t cached_tx_rfpll_div
Definition: ad9361.h:3363
#define AUXDAC_AUTO_TX_BAR(x)
Definition: ad9361.h:826
#define GOTO_SET_GAIN_IF_EXIT_RX_STATE
Definition: ad9361.h:1468
void ad9361_ensm_restore_prev_state(struct ad9361_rf_phy *phy)
Definition: ad9361.c:2130
uint8_t lmt_overload_large_exceed_counter
Definition: ad9361.h:2965
@ BBPLL_FREQ
Definition: ad9361.h:3138
#define REG_GM_SUB_TABLE_BIAS_WRITE
Definition: ad9361.h:279
Header file of GPIO Interface.
@ TBL_200_1300_MHZ
Definition: ad9361.h:2877
int32_t ad9361_bbpll_round_rate(struct refclk_scale *clk_priv, uint32_t rate, uint32_t *prate)
Definition: ad9361.c:6605
uint32_t ad9361_bbpll_recalc_rate(struct refclk_scale *clk_priv, uint32_t parent_rate)
Definition: ad9361.c:6578
struct no_os_gpio_desc * gpio_desc_sync
Definition: ad9361.h:3344
bool f_agc_gain_increase_after_gain_lock_en
Definition: ad9361.h:2996
rx_gain_table_name
Definition: ad9361.h:2876
int32_t bist_config
Definition: ad9361.h:3411
#define REG_EXT_LNA_LOW_GAIN
Definition: ad9361.h:268
#define POST_LOCK_LEVEL_STP_SIZE_FOR_LPF_TABLE_FULL_TABLE(x)
Definition: ad9361.h:1485
ad9361_pdata_rx_freq
Definition: ad9361.h:3137
#define REG_RX_FAST_LOCK_SETUP_INIT_DELAY
Definition: ad9361.h:500
#define REG_RX_FRACT_BYTE_2
Definition: ad9361.h:471
#define DEC_PWR_FOR_GAIN_LOCK_EXIT
Definition: ad9361.h:1348
uint32_t ad9361_validate_rf_bw(struct ad9361_rf_phy *phy, uint32_t bw)
Definition: ad9361.c:946
@ RF_GAIN_SLOWATTACK_AGC
Definition: ad9361.h:2910
#define AUXADC_WORD_LSB(x)
Definition: ad9361.h:808
int32_t ad9361_update_rf_bandwidth(struct ad9361_rf_phy *phy, uint32_t rf_rx_bw, uint32_t rf_tx_bw)
Definition: ad9361.c:5724
int32_t ad9361_clk_factor_round_rate(struct refclk_scale *clk_priv, uint32_t rate, uint32_t *prate)
Definition: ad9361.c:6513
enum f_agc_target_gain_index_type f_agc_rst_gla_if_en_agc_pulled_high_mode
Definition: ad9361.h:3014
#define REG_TX_PFD_CONFIG
Definition: ad9361.h:506
@ FIR_RX1_RX2
Definition: ad9361.h:2898
#define ENABLE_GAIN_INC_AFTER_GAIN_LOCK
Definition: ad9361.h:1465
#define DATA_PORT_LOOP_TEST_ENABLE
Definition: ad9361.h:2781
uint8_t tx2_mon_front_end_gain
Definition: ad9361.h:3132
@ RXGAIN_TBLS_END
Definition: ad9361.h:2880
int32_t ad9361_rfpll_int_round_rate(struct refclk_scale *clk_priv, uint32_t rate, uint32_t *prate)
Definition: ad9361.c:6840
#define BIST_ENABLE
Definition: ad9361.h:2770
#define REG_RX_PFD_CONFIG
Definition: ad9361.h:466
bool use_rx_fir_out_for_dec_pwr_meas
Definition: ad9361.h:2934
#define LARGE_ADC_OVERLOAD_EXED_COUNTER(x)
Definition: ad9361.h:1547
uint32_t ad9361_rfpll_dummy_recalc_rate(struct refclk_scale *clk_priv)
Definition: ad9361.c:6988
int32_t clk_prepare_enable(struct no_os_clk *clk)
clk_prepare_enable
Definition: ad9361_util.c:55
ad9361_bist_mode
Definition: ad9361.h:3322
#define REG_RX_FAST_LOCK_PROGRAM_READ
Definition: ad9361.h:503
Definition: ad9361.h:3080
#define RSSI_LSB_SHIFT
Definition: ad9361.h:1952
uint32_t current_tx_path_clks[NUM_TX_CLOCKS]
Definition: ad9361.h:3379
int32_t ad9361_clk_mux_set_parent(struct refclk_scale *clk_priv, uint8_t index)
Definition: ad9361.c:7157
@ BBPLL_CLK
Definition: ad9361.h:3270
uint64_t ad9361_from_clk(uint32_t freq)
Definition: ad9361.c:1409
#define REG_BANDGAP_CONFIG1
Definition: ad9361.h:556
#define SMALL_ADC_OVERLOAD_EXED_COUNTER(x)
Definition: ad9361.h:1548
struct gain_table_info * gt_info
Definition: ad9361.h:3367
@ FIR_TX1
Definition: ad9361.h:2893
#define REG_TX_QUAD_LPF_GAIN
Definition: ad9361.h:195
#define VCO_CAL_COUNT(x)
Definition: ad9361.h:2581
#define REG_TX2_DIG_ATTEN
Definition: ad9361.h:160
Definition: ad9361.h:3020
@ DBGFS_INIT
Definition: ad9361.h:3431
#define SYNTH_LUT_SIZE
Definition: ad9361.c:65
#define TX2_LO_CONV
Definition: ad9361.h:1173
#define EXT_LNA_LOW_GAIN(x)
Definition: ad9361.h:1585
bool filt_valid
Definition: ad9361.h:3389
Definition: ad9361.h:3066
#define REG_TX_LEVEL_THRESH
Definition: ad9361.h:145
uint8_t(* tab)[3]
Definition: ad9361.h:2889
void ad9361_get_bist_tone(struct ad9361_rf_phy *phy, enum ad9361_bist_mode *mode, uint32_t *freq_Hz, uint32_t *level_dB, uint32_t *mask)
Definition: ad9361.c:1294
#define REG_TX_FILTER_CONF
Definition: ad9361.h:141
#define BBDC_CAL
Definition: ad9361.h:753
uint8_t tx1_mon_front_end_gain
Definition: ad9361.h:3131
#define REG_RX_FAST_LOCK_PROGRAM_ADDR
Definition: ad9361.h:501
#define REG_SDM_CTRL
Definition: ad9361.h:124
struct no_os_spi_desc * spi
Definition: main.c:78
#define REG_FAST_CONFIG_1
Definition: ad9361.h:246
uint32_t ad9361_bbpll_recalc_rate(struct refclk_scale *clk_priv, uint32_t parent_rate)
Definition: ad9361.c:6578
#define REG_INVERT_BITS
Definition: ad9361.h:344
#define REG_RX1_TUNE_CTRL
Definition: ad9361.h:403
uint8_t dig_gain_step_size
Definition: ad9361.h:2970
Header file of utility functions.
#define REG_TX_MON_DELAY
Definition: ad9361.h:144
#define REG_GAIN_TABLE_READ_DATA1
Definition: ad9361.h:273
int32_t ad9361_get_trx_clock_chain(struct ad9361_rf_phy *phy, uint32_t *rx_path_clks, uint32_t *tx_path_clks)
Definition: ad9361.c:4734
#define TX_1
Definition: ad9361.h:605
uint32_t cal_threshold_freq
Definition: ad9361.h:3381
#define TX1_SSB_CONV
Definition: ad9361.h:1167
struct ad9361_phy_platform_data * pdata
Definition: ad9361.h:3359
#define KEXP_DC_I(x)
Definition: ad9361.h:1151
#define REG_BIST_CONFIG
Definition: ad9361.h:570
uint16_t bypass_loss_mdB
Definition: ad9361.h:3082
@ CLKRF_CLK
Definition: ad9361.h:3274
#define REG_RX_QUAD_GAIN2
Definition: ad9361.h:320
#define BIST_MASK_CHANNEL_2_Q_DATA
Definition: ad9361.h:2787
@ R2_FREQ
Definition: ad9361.h:3140
#define AGC_OUTER_LOW_THRESH_EXED_STP_SIZE(x)
Definition: ad9361.h:1575
@ GAIN_CHANGE_OCCURS_OR_EN_AGC_PIN_PULLED_HIGH
Definition: ad9361.h:3046
#define THB3_ENABLE_INTERP(x)
Definition: ad9361.h:603
uint32_t ad9361_rfpll_dummy_recalc_rate(struct refclk_scale *clk_priv)
Definition: ad9361.c:6988
#define FASTLOOK_INIT
Definition: ad9361.h:3301
#define MIN_BBPLL_FREQ
Definition: ad9361.h:2823
#define RX_CHANNEL_ENABLE(x)
Definition: ad9361.h:615
#define ADC_OVERRANGE_SAMPLE_SIZE(x)
Definition: ad9361.h:1376
uint8_t dac1_tx_delay_us
Definition: ad9361.h:3035
#define RX_FAST_LOCK_CONFIG_WORD_NUM
Definition: ad9361.h:2419
#define REG_EXTERNAL_LNA_CTRL
Definition: ad9361.h:88
#define REG_TX2_ATTEN_1
Definition: ad9361.h:156
#define TX_MON_2_LO_CM(x)
Definition: ad9361.h:1071
#define REG_RX_CP_CONFIG
Definition: ad9361.h:479
#define BBPLL_MODULUS
Definition: ad9361.h:2853
@ SET_GAIN
Definition: ad9361.h:2916
#define SINGLE_PORT_MODE
Definition: ad9361.h:710
#define AUXDAC_1_WORD_LSB(x)
Definition: ad9361.h:784
Header file of Common Driver.
#define LOOP_FILTER_C1(x)
Definition: ad9361.h:2499
bool immed_gain_change_if_large_adc_overload
Definition: ad9361.h:2974
enum rf_gain_ctrl_mode rx1_mode
Definition: ad9361.h:2922
int32_t bist_loopback_mode
Definition: ad9361.h:3410
#define REG_INTEGER_BB_FREQ_WORD
Definition: ad9361.h:114
uint8_t high_gain_dB
Definition: ad9361.h:3128
enum no_os_spi_mode mode
Definition: no_os_spi.h:187
#define DEC_POWER_MEASUREMENT_DURATION(x)
Definition: ad9361.h:1749
#define RSSI_LSB_MASK1
Definition: ad9361.h:1953
uint8_t gpo2_tx_delay_us
Definition: ad9361.h:3118
#define START_RSSI_MEAS
Definition: ad9361.h:1730
uint8_t agc_outer_thresh_high_dec_steps
Definition: ad9361.h:2951
#define USE_LAST_LOCK_LEVEL_FOR_SET_GAIN
Definition: ad9361.h:1477
#define LPF_GAIN_RX(x)
Definition: ad9361.h:2722
@ BE_MOREVERBOSE
Definition: ad9361.h:3315
int32_t ad9361_reg_write(struct ad9361_rf_phy *phy, uint32_t reg, uint32_t val)
Definition: ad9361.c:849
dev_id
Definition: ad9361.h:3334
uint16_t dec_pow_measuremnt_duration
Definition: ad9361.h:2932
#define RX_SYNTH_VCO_ALC_POWER_DOWN
Definition: ad9361.h:945
uint32_t rate
Definition: common.h:59
uint32_t tx2_atten_cached
Definition: ad9361.h:3406
#define REG_RX_VCO_CAL
Definition: ad9361.h:490
int32_t ad9361_bist_tone(struct ad9361_rf_phy *phy, enum ad9361_bist_mode mode, uint32_t freq_Hz, uint32_t level_dB, uint32_t mask)
Definition: ad9361.c:1236
#define RFDC_CAL
Definition: ad9361.h:752
int32_t ad9361_find_opt(uint8_t *field, uint32_t size, uint32_t *ret_start)
Definition: ad9361.c:988
bool gpo0_slave_rx_en
Definition: ad9361.h:3105
#define REG_CH_1_OVERFLOW
Definition: ad9361.h:134
#define POWER_DOWN_TX_SYNTH
Definition: ad9361.h:736
#define DATA_PORT_SP_HD_LOOP_TEST_OE
Definition: ad9361.h:2778
uint32_t int_sqrt(uint32_t x)
int_sqrt
Definition: ad9361_util.c:230
#define REG_RSSI_WEIGHT_2
Definition: ad9361.h:299
#define REG_ENSM_MODE
Definition: ad9361.h:69
#define REG_ADC_OVERLOAD_COUNTERS
Definition: ad9361.h:260
void ad9361_ensm_force_state(struct ad9361_rf_phy *phy, uint8_t ensm_state)
Definition: ad9361.c:1995
#define START_CALIB_TABLE_CLOCK
Definition: ad9361.h:1690
#define LARGE_LPF_GAIN_STEP(x)
Definition: ad9361.h:1412
@ NUM_AD9361_CLKS
Definition: ad9361.h:3287
uint32_t bist_tone_freq_Hz
Definition: ad9361.h:3414
#define MCS_BB_ENABLE
Definition: ad9361.h:595
#define REG_AGC_CONFIG_2
Definition: ad9361.h:227
#define PEAK_OVERLOAD_WAIT_TIME(x)
Definition: ad9361.h:1387
int32_t ad9361_fastlock_store(struct ad9361_rf_phy *phy, bool tx, uint32_t profile)
Definition: ad9361.c:5047
#define FULL_PORT
Definition: ad9361.h:711
#define STRONGER_SIGNAL_THRESH(x)
Definition: ad9361.h:1492
int32_t ad9361_get_tx_atten(struct ad9361_rf_phy *phy, uint32_t tx_num)
Definition: ad9361.c:1687
#define GOTO_SET_GAIN_IF_EN_AGC_HIGH
Definition: ad9361.h:1467
#define REG_RX_DSM_SETUP_1
Definition: ad9361.h:494
#define REG_TEMP_SENSOR_CONFIG
Definition: ad9361.h:65
#define TX_SYNTH_VCO_POWER_DOWN
Definition: ad9361.h:956
#define MIN_SYNTH_FREF
Definition: ad9361.h:2856
#define MAX_TX_ATTENUATION_DB
Definition: ad9361.h:2865
enum rf_gain_ctrl_mode rx2_mode
Definition: ad9361.h:2923
#define KEXP_TX_COMP(x)
Definition: ad9361.h:1150
uint8_t adc_small_overload_exceed_counter
Definition: ad9361.h:2959
#define REG_KEXP_1
Definition: ad9361.h:183
bool current_rx_use_tdd_table
Definition: ad9361.h:3377
#define TONE_PRBS
Definition: ad9361.h:2769
#define REG_LVDS_INVERT_CTRL2
Definition: ad9361.h:109
#define INVERT_RX2_RF_DC_CGOUT_WORD
Definition: ad9361.h:1863
f_agc_target_gain_index_type
Definition: ad9361.h:2914
#define RX_FAST_LOCK_PROGRAM_WRITE
Definition: ad9361.h:2416
int32_t ad9361_bbpll_round_rate(struct refclk_scale *clk_priv, uint32_t rate, uint32_t *prate)
Definition: ad9361.c:6605
int32_t ad9361_tracking_control(struct ad9361_rf_phy *phy, bool bbdc_track, bool rfdc_track, bool rxquad_track)
Definition: ad9361.c:3323
bool dac1_in_tx_en
Definition: ad9361.h:3027
@ RF_GAIN_FASTATTACK_AGC
Definition: ad9361.h:2909
#define RX_GAIN_STEP_CAL
Definition: ad9361.h:750
uint32_t gain_update_interval_us
Definition: ad9361.h:2973
#define NO_OS_DIV_ROUND_CLOSEST(x, y)
Definition: no_os_util.h:58
int32_t ad9361_bist_tone(struct ad9361_rf_phy *phy, enum ad9361_bist_mode mode, uint32_t freq_Hz, uint32_t level_dB, uint32_t mask)
Definition: ad9361.c:1236
#define REG_WORD_ADDRESS
Definition: ad9361.h:285
@ ID_AD9361
Definition: ad9361.h:3335
#define REG_FAST_GAIN_LOCK_EXIT_COUNT
Definition: ad9361.h:255
#define REG_DC_OFFSET_CONFIG2
Definition: ad9361.h:345
#define REG_TX_MON_1_CONFIG
Definition: ad9361.h:151
bool one_shot_mode_en
Definition: ad9361.h:3125
Definition: ad9361.h:3098
bool sync_for_gain_counter_en
Definition: ad9361.h:2971
#define RECEIVER_SELECT(x)
Definition: ad9361.h:1632
#define GOTO_OPT_GAIN_IF_ENERGY_LOST_OR_EN_AGC_HIGH
Definition: ad9361.h:1466
#define INVERT_RX1_RF_DC_CGOUT_WORD
Definition: ad9361.h:1864
struct axiadc_converter * adc_conv
Definition: ad9361.h:3408
bool periodic_temp_measuremnt
Definition: ad9361.h:3093
uint32_t lna_index
Definition: ad9361.h:3230
int32_t ad9361_calculate_rf_clock_chain(struct ad9361_rf_phy *phy, uint32_t tx_sample_rate, uint32_t rate_gov, uint32_t *rx_path_clks, uint32_t *tx_path_clks)
Definition: ad9361.c:4772
@ DBGFS_BIST_TONE
Definition: ad9361.h:3434
bool bypass_tx_fir
Definition: ad9361.h:3387
uint8_t tx_fir_ntaps
Definition: ad9361.h:3395
uint8_t low_power_thresh
Definition: ad9361.h:2933
#define RX2_PD_TUNE
Definition: ad9361.h:2107
synth_pd_ctrl
Definition: ad9361.h:3328
#define MIN_ADC_CLK
Definition: ad9361.h:2834
#define LOOP_FILTER_C2(x)
Definition: ad9361.h:2498
@ TX_SAMPL_CLK
Definition: ad9361.h:3280