#include <ad9361.h>
◆ ad9361_clkout_mode
◆ auxadc_ctrl
◆ auxdac_ctrl
◆ axi_half_dac_rate_en
| bool ad9361_phy_platform_data::axi_half_dac_rate_en |
◆ bb_clk_change_dig_tune_en
| bool ad9361_phy_platform_data::bb_clk_change_dig_tune_en |
◆ ctrl_outs_ctrl
◆ dc_offset_attenuation_high
| uint8_t ad9361_phy_platform_data::dc_offset_attenuation_high |
◆ dc_offset_attenuation_low
| uint8_t ad9361_phy_platform_data::dc_offset_attenuation_low |
◆ dc_offset_update_events
| uint8_t ad9361_phy_platform_data::dc_offset_update_events |
◆ dcxo_coarse
| uint32_t ad9361_phy_platform_data::dcxo_coarse |
◆ dcxo_fine
| uint32_t ad9361_phy_platform_data::dcxo_fine |
◆ debug_mode
| bool ad9361_phy_platform_data::debug_mode |
◆ dig_interface_tune_fir_disable
| bool ad9361_phy_platform_data::dig_interface_tune_fir_disable |
◆ dig_interface_tune_skipmode
| uint8_t ad9361_phy_platform_data::dig_interface_tune_skipmode |
◆ elna_ctrl
◆ ensm_pin_ctrl
| bool ad9361_phy_platform_data::ensm_pin_ctrl |
◆ ensm_pin_pulse_mode
| bool ad9361_phy_platform_data::ensm_pin_pulse_mode |
◆ fdd
| bool ad9361_phy_platform_data::fdd |
◆ fdd_independent_mode
| bool ad9361_phy_platform_data::fdd_independent_mode |
◆ gain_ctrl
◆ gpo_ctrl
◆ lo_powerdown_managed_en
| uint8_t ad9361_phy_platform_data::lo_powerdown_managed_en |
◆ port_ctrl
◆ qec_tracking_slow_mode_en
| bool ad9361_phy_platform_data::qec_tracking_slow_mode_en |
◆ rf_dc_offset_count_high
| uint8_t ad9361_phy_platform_data::rf_dc_offset_count_high |
◆ rf_dc_offset_count_low
| uint8_t ad9361_phy_platform_data::rf_dc_offset_count_low |
◆ rf_rx_bandwidth_Hz
| uint32_t ad9361_phy_platform_data::rf_rx_bandwidth_Hz |
◆ rf_rx_input_sel
| uint32_t ad9361_phy_platform_data::rf_rx_input_sel |
◆ rf_rx_input_sel_lock
| bool ad9361_phy_platform_data::rf_rx_input_sel_lock |
◆ rf_tx_bandwidth_Hz
| uint32_t ad9361_phy_platform_data::rf_tx_bandwidth_Hz |
◆ rf_tx_output_sel
| uint32_t ad9361_phy_platform_data::rf_tx_output_sel |
◆ rf_tx_output_sel_lock
| bool ad9361_phy_platform_data::rf_tx_output_sel_lock |
◆ rssi_ctrl
◆ rssi_gain_step_calib_reg_val
| uint32_t ad9361_phy_platform_data::rssi_gain_step_calib_reg_val[5] |
◆ rssi_lna_err_tbl
| uint32_t ad9361_phy_platform_data::rssi_lna_err_tbl[4] |
◆ rssi_mixer_err_tbl
| uint32_t ad9361_phy_platform_data::rssi_mixer_err_tbl[16] |
◆ rssi_skip_calib
| bool ad9361_phy_platform_data::rssi_skip_calib |
◆ rx1rx2_phase_inversion_en
| bool ad9361_phy_platform_data::rx1rx2_phase_inversion_en |
◆ rx1tx1_mode_use_rx_num
| uint32_t ad9361_phy_platform_data::rx1tx1_mode_use_rx_num |
◆ rx1tx1_mode_use_tx_num
| uint32_t ad9361_phy_platform_data::rx1tx1_mode_use_tx_num |
◆ rx2tx2
| bool ad9361_phy_platform_data::rx2tx2 |
◆ rx_fastlock_delay_ns
| uint32_t ad9361_phy_platform_data::rx_fastlock_delay_ns |
◆ rx_path_clks
◆ rx_synth_freq
| uint64_t ad9361_phy_platform_data::rx_synth_freq |
◆ split_gt
| bool ad9361_phy_platform_data::split_gt |
◆ tdd_skip_vco_cal
| bool ad9361_phy_platform_data::tdd_skip_vco_cal |
◆ tdd_use_dual_synth
| bool ad9361_phy_platform_data::tdd_use_dual_synth |
◆ trx_fastlock_pinctrl_en
| bool ad9361_phy_platform_data::trx_fastlock_pinctrl_en[2] |
◆ trx_synth_max_fref
| uint32_t ad9361_phy_platform_data::trx_synth_max_fref |
◆ tx_atten
| int32_t ad9361_phy_platform_data::tx_atten |
◆ tx_fastlock_delay_ns
| uint32_t ad9361_phy_platform_data::tx_fastlock_delay_ns |
◆ tx_path_clks
◆ tx_synth_freq
| uint64_t ad9361_phy_platform_data::tx_synth_freq |
◆ txmon_ctrl
◆ update_tx_gain_via_alert
| bool ad9361_phy_platform_data::update_tx_gain_via_alert |
◆ use_ext_rx_lo
| bool ad9361_phy_platform_data::use_ext_rx_lo |
◆ use_ext_tx_lo
| bool ad9361_phy_platform_data::use_ext_tx_lo |
◆ use_extclk
| bool ad9361_phy_platform_data::use_extclk |
The documentation for this struct was generated from the following file:
- /home/runner/work/no-OS/no-OS/drivers/rf-transceiver/ad9361/ad9361.h