Header file of AD9523 Driver. More...

#include <stdint.h>
#include "no_os_delay.h"
#include "no_os_spi.h"

Include dependency graph for ad9523.h:

Classes
struct	ad9523_channel_spec
	Output channel configuration. More...

struct	ad9523_platform_data
	platform specific information More...

struct	ad9523_state

struct	ad9523_dev

struct	ad9523_init_param

Macros
#define	AD9523_READ (1 << 15)

#define	AD9523_WRITE (0 << 15)

#define	AD9523_CNT(x)

#define	AD9523_ADDR(x)

#define	AD9523_R1B (1 << 16)

#define	AD9523_R2B (2 << 16)

#define	AD9523_R3B (3 << 16)

#define	AD9523_TRANSF_LEN(x)

#define	AD9523_SERIAL_PORT_CONFIG (AD9523_R1B \| 0x0)

#define	AD9523_VERSION_REGISTER (AD9523_R1B \| 0x2)

#define	AD9523_PART_REGISTER (AD9523_R1B \| 0x3)

#define	AD9523_READBACK_CTRL (AD9523_R1B \| 0x4)

#define	AD9523_EEPROM_CUSTOMER_VERSION_ID (AD9523_R2B \| 0x6)

#define	AD9523_PLL1_REF_A_DIVIDER (AD9523_R2B \| 0x11)

#define	AD9523_PLL1_REF_B_DIVIDER (AD9523_R2B \| 0x13)

#define	AD9523_PLL1_REF_TEST_DIVIDER (AD9523_R1B \| 0x14)

#define	AD9523_PLL1_FEEDBACK_DIVIDER (AD9523_R2B \| 0x17)

#define	AD9523_PLL1_CHARGE_PUMP_CTRL (AD9523_R2B \| 0x19)

#define	AD9523_PLL1_INPUT_RECEIVERS_CTRL (AD9523_R1B \| 0x1A)

#define	AD9523_PLL1_REF_CTRL (AD9523_R1B \| 0x1B)

#define	AD9523_PLL1_MISC_CTRL (AD9523_R1B \| 0x1C)

#define	AD9523_PLL1_LOOP_FILTER_CTRL (AD9523_R1B \| 0x1D)

#define	AD9523_PLL2_CHARGE_PUMP (AD9523_R1B \| 0xF0)

#define	AD9523_PLL2_FEEDBACK_DIVIDER_AB (AD9523_R1B \| 0xF1)

#define	AD9523_PLL2_CTRL (AD9523_R1B \| 0xF2)

#define	AD9523_PLL2_VCO_CTRL (AD9523_R1B \| 0xF3)

#define	AD9523_PLL2_VCO_DIVIDER (AD9523_R1B \| 0xF4)

#define	AD9523_PLL2_LOOP_FILTER_CTRL (AD9523_R2B \| 0xF6)

#define	AD9523_PLL2_R2_DIVIDER (AD9523_R1B \| 0xF7)

#define	AD9523_CHANNEL_CLOCK_DIST(ch)

#define	AD9523_PLL1_OUTPUT_CTRL (AD9523_R1B \| 0x1BA)

#define	AD9523_PLL1_OUTPUT_CHANNEL_CTRL (AD9523_R1B \| 0x1BB)

#define	AD9523_READBACK_0 (AD9523_R1B \| 0x22C)

#define	AD9523_READBACK_1 (AD9523_R1B \| 0x22D)

#define	AD9523_STATUS_SIGNALS (AD9523_R3B \| 0x232)

#define	AD9523_POWER_DOWN_CTRL (AD9523_R1B \| 0x233)

#define	AD9523_IO_UPDATE (AD9523_R1B \| 0x234)

#define	AD9523_EEPROM_DATA_XFER_STATUS (AD9523_R1B \| 0xB00)

#define	AD9523_EEPROM_ERROR_READBACK (AD9523_R1B \| 0xB01)

#define	AD9523_EEPROM_CTRL1 (AD9523_R1B \| 0xB02)

#define	AD9523_EEPROM_CTRL2 (AD9523_R1B \| 0xB03)

#define	AD9523_SER_CONF_SDO_ACTIVE ((1 << 7) \| (1 << 0))

#define	AD9523_SER_CONF_SOFT_RESET ((1 << 5) \| (1 << 2))

#define	AD9523_READBACK_CTRL_READ_BUFFERED (1 << 0)

#define	AD9523_PLL1_CHARGE_PUMP_CURRENT_nA(x)

#define	AD9523_PLL1_CHARGE_PUMP_TRISTATE (1 << 7)

#define	AD9523_PLL1_CHARGE_PUMP_MODE_NORMAL (3 << 8)

#define	AD9523_PLL1_CHARGE_PUMP_MODE_PUMP_DOWN (2 << 8)

#define	AD9523_PLL1_CHARGE_PUMP_MODE_PUMP_UP (1 << 8)

#define	AD9523_PLL1_CHARGE_PUMP_MODE_TRISTATE (0 << 8)

#define	AD9523_PLL1_BACKLASH_PW_MIN (0 << 10)

#define	AD9523_PLL1_BACKLASH_PW_LOW (1 << 10)

#define	AD9523_PLL1_BACKLASH_PW_HIGH (2 << 10)

#define	AD9523_PLL1_BACKLASH_PW_MAX (3 << 10)

#define	AD9523_PLL1_REF_TEST_RCV_EN (1 << 7)

#define	AD9523_PLL1_REFB_DIFF_RCV_EN (1 << 6)

#define	AD9523_PLL1_REFA_DIFF_RCV_EN (1 << 5)

#define	AD9523_PLL1_REFB_RCV_EN (1 << 4)

#define	AD9523_PLL1_REFA_RCV_EN (1 << 3)

#define	AD9523_PLL1_REFA_REFB_PWR_CTRL_EN (1 << 2)

#define	AD9523_PLL1_OSC_IN_CMOS_NEG_INP_EN (1 << 1)

#define	AD9523_PLL1_OSC_IN_DIFF_EN (1 << 0)

#define	AD9523_PLL1_BYPASS_REF_TEST_DIV_EN (1 << 7)

#define	AD9523_PLL1_BYPASS_FEEDBACK_DIV_EN (1 << 6)

#define	AD9523_PLL1_ZERO_DELAY_MODE_INT (1 << 5)

#define	AD9523_PLL1_ZERO_DELAY_MODE_EXT (0 << 5)

#define	AD9523_PLL1_OSC_IN_PLL_FEEDBACK_EN (1 << 4)

#define	AD9523_PLL1_ZD_IN_CMOS_NEG_INP_EN (1 << 3)

#define	AD9523_PLL1_ZD_IN_DIFF_EN (1 << 2)

#define	AD9523_PLL1_REFB_CMOS_NEG_INP_EN (1 << 1)

#define	AD9523_PLL1_REFA_CMOS_NEG_INP_EN (1 << 0)

#define	AD9523_PLL1_REFB_INDEP_DIV_CTRL_EN (1 << 7)

#define	AD9523_PLL1_OSC_CTRL_FAIL_VCC_BY2_EN (1 << 6)

#define	AD9523_PLL1_REF_MODE(x)

#define	AD9523_PLL1_BYPASS_REFB_DIV (1 << 1)

#define	AD9523_PLL1_BYPASS_REFA_DIV (1 << 0)

#define	AD9523_PLL1_LOOP_FILTER_RZERO(x)

#define	AD9523_PLL2_CHARGE_PUMP_CURRENT_nA(x)

#define	AD9523_PLL2_FB_NDIV_A_CNT(x)

#define	AD9523_PLL2_FB_NDIV_B_CNT(x)

#define	AD9523_PLL2_FB_NDIV(a, b)

#define	AD9523_PLL2_CHARGE_PUMP_MODE_NORMAL (3 << 0)

#define	AD9523_PLL2_CHARGE_PUMP_MODE_PUMP_DOWN (2 << 0)

#define	AD9523_PLL2_CHARGE_PUMP_MODE_PUMP_UP (1 << 0)

#define	AD9523_PLL2_CHARGE_PUMP_MODE_TRISTATE (0 << 0)

#define	AD9523_PLL2_BACKLASH_PW_MIN (0 << 2)

#define	AD9523_PLL2_BACKLASH_PW_LOW (1 << 2)

#define	AD9523_PLL2_BACKLASH_PW_HIGH (2 << 2)

#define	AD9523_PLL2_BACKLASH_PW_MAX (3 << 1)

#define	AD9523_PLL2_BACKLASH_CTRL_EN (1 << 4)

#define	AD9523_PLL2_FREQ_DOUBLER_EN (1 << 5)

#define	AD9523_PLL2_LOCK_DETECT_PWR_DOWN_EN (1 << 7)

#define	AD9523_PLL2_VCO_CALIBRATE (1 << 1)

#define	AD9523_PLL2_FORCE_VCO_MIDSCALE (1 << 2)

#define	AD9523_PLL2_FORCE_REFERENCE_VALID (1 << 3)

#define	AD9523_PLL2_FORCE_RELEASE_SYNC (1 << 4)

#define	AD9523_PLL2_VCO_DIV_M1(x)

#define	AD9523_PLL2_VCO_DIV_M2(x)

#define	AD9523_PLL2_VCO_DIV_M1_PWR_DOWN_EN (1 << 2)

#define	AD9523_PLL2_VCO_DIV_M2_PWR_DOWN_EN (1 << 6)

#define	AD9523_PLL2_LOOP_FILTER_CPOLE1(x)

#define	AD9523_PLL2_LOOP_FILTER_RZERO(x)

#define	AD9523_PLL2_LOOP_FILTER_RPOLE2(x)

#define	AD9523_PLL2_LOOP_FILTER_RZERO_BYPASS_EN (1 << 8)

#define	AD9523_PLL2_R2_DIVIDER_VAL(x)

#define	AD9523_CLK_DIST_DIV_PHASE(x)

#define	AD9523_CLK_DIST_DIV_PHASE_REV(x)

#define	AD9523_CLK_DIST_DIV(x)

#define	AD9523_CLK_DIST_DIV_REV(x)

#define	AD9523_CLK_DIST_INV_DIV_OUTPUT_EN (1 << 7)

#define	AD9523_CLK_DIST_IGNORE_SYNC_EN (1 << 6)

#define	AD9523_CLK_DIST_PWR_DOWN_EN (1 << 5)

#define	AD9523_CLK_DIST_LOW_PWR_MODE_EN (1 << 4)

#define	AD9523_CLK_DIST_DRIVER_MODE(x)

#define	AD9523_PLL1_OUTP_CTRL_VCO_DIV_SEL_CH6_M2 (1 << 7)

#define	AD9523_PLL1_OUTP_CTRL_VCO_DIV_SEL_CH5_M2 (1 << 6)

#define	AD9523_PLL1_OUTP_CTRL_VCO_DIV_SEL_CH4_M2 (1 << 5)

#define	AD9523_PLL1_OUTP_CTRL_CMOS_DRV_WEAK (1 << 4)

#define	AD9523_PLL1_OUTP_CTRL_OUTPUT_DIV_1 (0 << 0)

#define	AD9523_PLL1_OUTP_CTRL_OUTPUT_DIV_2 (1 << 0)

#define	AD9523_PLL1_OUTP_CTRL_OUTPUT_DIV_4 (2 << 0)

#define	AD9523_PLL1_OUTP_CTRL_OUTPUT_DIV_8 (4 << 0)

#define	AD9523_PLL1_OUTP_CTRL_OUTPUT_DIV_16 (8 << 0)

#define	AD9523_PLL1_OUTP_CH_CTRL_OUTPUT_PWR_DOWN_EN (1 << 7)

#define	AD9523_PLL1_OUTP_CH_CTRL_VCO_DIV_SEL_CH9_M2 (1 << 6)

#define	AD9523_PLL1_OUTP_CH_CTRL_VCO_DIV_SEL_CH8_M2 (1 << 5)

#define	AD9523_PLL1_OUTP_CH_CTRL_VCO_DIV_SEL_CH7_M2 (1 << 4)

#define	AD9523_PLL1_OUTP_CH_CTRL_VCXO_SRC_SEL_CH3 (1 << 3)

#define	AD9523_PLL1_OUTP_CH_CTRL_VCXO_SRC_SEL_CH2 (1 << 2)

#define	AD9523_PLL1_OUTP_CH_CTRL_VCXO_SRC_SEL_CH1 (1 << 1)

#define	AD9523_PLL1_OUTP_CH_CTRL_VCXO_SRC_SEL_CH0 (1 << 0)

#define	AD9523_READBACK_0_STAT_PLL2_REF_CLK (1 << 7)

#define	AD9523_READBACK_0_STAT_PLL2_FB_CLK (1 << 6)

#define	AD9523_READBACK_0_STAT_VCXO (1 << 5)

#define	AD9523_READBACK_0_STAT_REF_TEST (1 << 4)

#define	AD9523_READBACK_0_STAT_REFB (1 << 3)

#define	AD9523_READBACK_0_STAT_REFA (1 << 2)

#define	AD9523_READBACK_0_STAT_PLL2_LD (1 << 1)

#define	AD9523_READBACK_0_STAT_PLL1_LD (1 << 0)

#define	AD9523_READBACK_1_HOLDOVER_ACTIVE (1 << 3)

#define	AD9523_READBACK_1_AUTOMODE_SEL_REFB (1 << 2)

#define	AD9523_READBACK_1_VCO_CALIB_IN_PROGRESS (1 << 0)

#define	AD9523_STATUS_SIGNALS_SYNC_MAN_CTRL (1 << 16)

#define	AD9523_STATUS_MONITOR_01_PLL12_LOCKED (0x302)

#define	AD9523_POWER_DOWN_CTRL_PLL1_PWR_DOWN (1 << 2)

#define	AD9523_POWER_DOWN_CTRL_PLL2_PWR_DOWN (1 << 1)

#define	AD9523_POWER_DOWN_CTRL_DIST_PWR_DOWN (1 << 0)

#define	AD9523_IO_UPDATE_EN (1 << 0)

#define	AD9523_EEPROM_DATA_XFER_IN_PROGRESS (1 << 0)

#define	AD9523_EEPROM_ERROR_READBACK_FAIL (1 << 0)

#define	AD9523_EEPROM_CTRL1_SOFT_EEPROM (1 << 1)

#define	AD9523_EEPROM_CTRL1_EEPROM_WRITE_PROT_DIS (1 << 0)

#define	AD9523_EEPROM_CTRL2_REG2EEPROM (1 << 0)

#define	AD9523_NUM_CHAN 14

#define	AD9523_NUM_CHAN_ALT_CLK_SRC 10

Enumerations
enum	outp_drv_mode { TRISTATE , LVPECL_8mA , LVDS_4mA , LVDS_7mA , HSTL0_16mA , HSTL1_8mA , CMOS_CONF1 , CMOS_CONF2 , CMOS_CONF3 , CMOS_CONF4 , CMOS_CONF5 , CMOS_CONF6 , CMOS_CONF7 , CMOS_CONF8 , CMOS_CONF9 }

enum	ref_sel_mode { NONEREVERTIVE_STAY_ON_REFB , REVERT_TO_REFA , SELECT_REFA , SELECT_REFB , EXT_REF_SEL }

enum	pll1_rzero_resistor { RZERO_883_OHM , RZERO_677_OHM , RZERO_341_OHM , RZERO_135_OHM , RZERO_10_OHM , RZERO_USE_EXT_RES = 8 }

enum	rpole2_resistor { RPOLE2_900_OHM , RPOLE2_450_OHM , RPOLE2_300_OHM , RPOLE2_225_OHM }

enum	rzero_resistor { RZERO_3250_OHM , RZERO_2750_OHM , RZERO_2250_OHM , RZERO_2100_OHM , RZERO_3000_OHM , RZERO_2500_OHM , RZERO_2000_OHM , RZERO_1850_OHM }

enum	cpole1_capacitor { CPOLE1_0_PF , CPOLE1_8_PF , CPOLE1_16_PF , CPOLE1_24_PF , _CPOLE1_24_PF , CPOLE1_32_PF , CPOLE1_40_PF , CPOLE1_48_PF }

enum	ad9523_out_frequencies { AD9523_VCO1 , AD9523_VCO2 , AD9523_VCXO , AD9523_NUM_CLK_SRC }

Functions
int32_t	ad9523_spi_read (struct ad9523_dev dev, uint32_t reg_addr, uint32_t reg_data)
	Reads the value of the selected register.

int32_t	ad9523_spi_write (struct ad9523_dev *dev, uint32_t reg_addr, uint32_t reg_data)
	Writes a value to the selected register.

int32_t	ad9523_io_update (struct ad9523_dev *dev)
	Updates the AD9523 configuration.

int32_t	ad9523_vco_out_map (struct ad9523_dev *dev, uint32_t ch, uint32_t out)
	Sets the clock provider for selected channel.

int32_t	ad9523_sync (struct ad9523_dev *dev)
	Updates the AD9523 configuration.

int32_t	ad9523_init (struct ad9523_init_param *init_param)
	Initialize the AD9523 data structure with the default register values.

int32_t	ad9523_setup (struct ad9523_dev *device, const struct ad9523_init_param init_param)
	Setup the AD9523 device.

int32_t	ad9523_remove (struct ad9523_dev *dev)
	Free the resources allocated by ad9523_setup().

int32_t	ad9523_status (struct ad9523_dev *dev)
	Updates the AD9523 configuration.

Detailed Description

Header file of AD9523 Driver.

Author: DBogdan (drago.nosp@m.s.bo.nosp@m.gdan@.nosp@m.anal.nosp@m.og.co.nosp@m.m)

SPDX-License-Identifier: BSD-3-Clause

Macro Definition Documentation

◆ AD9523_ADDR

#define AD9523_ADDR ( x )

Value:

((x) & 0xFFF)

◆ AD9523_CHANNEL_CLOCK_DIST

#define AD9523_CHANNEL_CLOCK_DIST ( ch )

Value:

(AD9523_R3B | (0x192 + 3 * ch))

AD9523_R3B

#define AD9523_R3B

Definition ad9523.h:27

◆ AD9523_CLK_DIST_DIV

#define AD9523_CLK_DIST_DIV ( x )

Value:

((((x) - 1) & 0x3FF) << 8)

◆ AD9523_CLK_DIST_DIV_PHASE

#define AD9523_CLK_DIST_DIV_PHASE ( x )

Value:

(((x) & 0x3F) << 18)

◆ AD9523_CLK_DIST_DIV_PHASE_REV

#define AD9523_CLK_DIST_DIV_PHASE_REV ( x )

Value:

((ret >> 18) & 0x3F)

◆ AD9523_CLK_DIST_DIV_REV

#define AD9523_CLK_DIST_DIV_REV ( x )

Value:

(((ret >> 8) & 0x3FF) + 1)

◆ AD9523_CLK_DIST_DRIVER_MODE

#define AD9523_CLK_DIST_DRIVER_MODE ( x )

Value:

(((x) & 0xF) << 0)

◆ AD9523_CLK_DIST_IGNORE_SYNC_EN

#define AD9523_CLK_DIST_IGNORE_SYNC_EN (1 << 6)

◆ AD9523_CLK_DIST_INV_DIV_OUTPUT_EN

#define AD9523_CLK_DIST_INV_DIV_OUTPUT_EN (1 << 7)

◆ AD9523_CLK_DIST_LOW_PWR_MODE_EN

#define AD9523_CLK_DIST_LOW_PWR_MODE_EN (1 << 4)

◆ AD9523_CLK_DIST_PWR_DOWN_EN

#define AD9523_CLK_DIST_PWR_DOWN_EN (1 << 5)

◆ AD9523_CNT

#define AD9523_CNT ( x )

Value:

(((x) - 1) << 13)

◆ AD9523_EEPROM_CTRL1

#define AD9523_EEPROM_CTRL1 (AD9523_R1B | 0xB02)

◆ AD9523_EEPROM_CTRL1_EEPROM_WRITE_PROT_DIS

#define AD9523_EEPROM_CTRL1_EEPROM_WRITE_PROT_DIS (1 << 0)

◆ AD9523_EEPROM_CTRL1_SOFT_EEPROM

#define AD9523_EEPROM_CTRL1_SOFT_EEPROM (1 << 1)

◆ AD9523_EEPROM_CTRL2

#define AD9523_EEPROM_CTRL2 (AD9523_R1B | 0xB03)

◆ AD9523_EEPROM_CTRL2_REG2EEPROM

#define AD9523_EEPROM_CTRL2_REG2EEPROM (1 << 0)

◆ AD9523_EEPROM_CUSTOMER_VERSION_ID

#define AD9523_EEPROM_CUSTOMER_VERSION_ID (AD9523_R2B | 0x6)

◆ AD9523_EEPROM_DATA_XFER_IN_PROGRESS

#define AD9523_EEPROM_DATA_XFER_IN_PROGRESS (1 << 0)

◆ AD9523_EEPROM_DATA_XFER_STATUS

#define AD9523_EEPROM_DATA_XFER_STATUS (AD9523_R1B | 0xB00)

◆ AD9523_EEPROM_ERROR_READBACK

#define AD9523_EEPROM_ERROR_READBACK (AD9523_R1B | 0xB01)

◆ AD9523_EEPROM_ERROR_READBACK_FAIL

#define AD9523_EEPROM_ERROR_READBACK_FAIL (1 << 0)

◆ AD9523_IO_UPDATE

#define AD9523_IO_UPDATE (AD9523_R1B | 0x234)

◆ AD9523_IO_UPDATE_EN

#define AD9523_IO_UPDATE_EN (1 << 0)

◆ AD9523_NUM_CHAN

#define AD9523_NUM_CHAN 14

◆ AD9523_NUM_CHAN_ALT_CLK_SRC

#define AD9523_NUM_CHAN_ALT_CLK_SRC 10

◆ AD9523_PART_REGISTER

#define AD9523_PART_REGISTER (AD9523_R1B | 0x3)

◆ AD9523_PLL1_BACKLASH_PW_HIGH

#define AD9523_PLL1_BACKLASH_PW_HIGH (2 << 10)

◆ AD9523_PLL1_BACKLASH_PW_LOW

#define AD9523_PLL1_BACKLASH_PW_LOW (1 << 10)

◆ AD9523_PLL1_BACKLASH_PW_MAX

#define AD9523_PLL1_BACKLASH_PW_MAX (3 << 10)

◆ AD9523_PLL1_BACKLASH_PW_MIN

#define AD9523_PLL1_BACKLASH_PW_MIN (0 << 10)

◆ AD9523_PLL1_BYPASS_FEEDBACK_DIV_EN

#define AD9523_PLL1_BYPASS_FEEDBACK_DIV_EN (1 << 6)

◆ AD9523_PLL1_BYPASS_REF_TEST_DIV_EN

#define AD9523_PLL1_BYPASS_REF_TEST_DIV_EN (1 << 7)

◆ AD9523_PLL1_BYPASS_REFA_DIV

#define AD9523_PLL1_BYPASS_REFA_DIV (1 << 0)

◆ AD9523_PLL1_BYPASS_REFB_DIV

#define AD9523_PLL1_BYPASS_REFB_DIV (1 << 1)

◆ AD9523_PLL1_CHARGE_PUMP_CTRL

#define AD9523_PLL1_CHARGE_PUMP_CTRL (AD9523_R2B | 0x19)

◆ AD9523_PLL1_CHARGE_PUMP_CURRENT_nA

#define AD9523_PLL1_CHARGE_PUMP_CURRENT_nA ( x )

Value:

(((x) / 500) & 0x7F)

◆ AD9523_PLL1_CHARGE_PUMP_MODE_NORMAL

#define AD9523_PLL1_CHARGE_PUMP_MODE_NORMAL (3 << 8)

◆ AD9523_PLL1_CHARGE_PUMP_MODE_PUMP_DOWN

#define AD9523_PLL1_CHARGE_PUMP_MODE_PUMP_DOWN (2 << 8)

◆ AD9523_PLL1_CHARGE_PUMP_MODE_PUMP_UP

#define AD9523_PLL1_CHARGE_PUMP_MODE_PUMP_UP (1 << 8)

◆ AD9523_PLL1_CHARGE_PUMP_MODE_TRISTATE

#define AD9523_PLL1_CHARGE_PUMP_MODE_TRISTATE (0 << 8)

◆ AD9523_PLL1_CHARGE_PUMP_TRISTATE

#define AD9523_PLL1_CHARGE_PUMP_TRISTATE (1 << 7)

◆ AD9523_PLL1_FEEDBACK_DIVIDER

#define AD9523_PLL1_FEEDBACK_DIVIDER (AD9523_R2B | 0x17)

◆ AD9523_PLL1_INPUT_RECEIVERS_CTRL

#define AD9523_PLL1_INPUT_RECEIVERS_CTRL (AD9523_R1B | 0x1A)

◆ AD9523_PLL1_LOOP_FILTER_CTRL

#define AD9523_PLL1_LOOP_FILTER_CTRL (AD9523_R1B | 0x1D)

◆ AD9523_PLL1_LOOP_FILTER_RZERO

#define AD9523_PLL1_LOOP_FILTER_RZERO ( x )

Value:

((x) & 0xF)

◆ AD9523_PLL1_MISC_CTRL

#define AD9523_PLL1_MISC_CTRL (AD9523_R1B | 0x1C)

◆ AD9523_PLL1_OSC_CTRL_FAIL_VCC_BY2_EN

#define AD9523_PLL1_OSC_CTRL_FAIL_VCC_BY2_EN (1 << 6)

◆ AD9523_PLL1_OSC_IN_CMOS_NEG_INP_EN

#define AD9523_PLL1_OSC_IN_CMOS_NEG_INP_EN (1 << 1)

◆ AD9523_PLL1_OSC_IN_DIFF_EN

#define AD9523_PLL1_OSC_IN_DIFF_EN (1 << 0)

◆ AD9523_PLL1_OSC_IN_PLL_FEEDBACK_EN

#define AD9523_PLL1_OSC_IN_PLL_FEEDBACK_EN (1 << 4)

◆ AD9523_PLL1_OUTP_CH_CTRL_OUTPUT_PWR_DOWN_EN

#define AD9523_PLL1_OUTP_CH_CTRL_OUTPUT_PWR_DOWN_EN (1 << 7)

◆ AD9523_PLL1_OUTP_CH_CTRL_VCO_DIV_SEL_CH7_M2

#define AD9523_PLL1_OUTP_CH_CTRL_VCO_DIV_SEL_CH7_M2 (1 << 4)

◆ AD9523_PLL1_OUTP_CH_CTRL_VCO_DIV_SEL_CH8_M2

#define AD9523_PLL1_OUTP_CH_CTRL_VCO_DIV_SEL_CH8_M2 (1 << 5)

◆ AD9523_PLL1_OUTP_CH_CTRL_VCO_DIV_SEL_CH9_M2

#define AD9523_PLL1_OUTP_CH_CTRL_VCO_DIV_SEL_CH9_M2 (1 << 6)

◆ AD9523_PLL1_OUTP_CH_CTRL_VCXO_SRC_SEL_CH0

#define AD9523_PLL1_OUTP_CH_CTRL_VCXO_SRC_SEL_CH0 (1 << 0)

◆ AD9523_PLL1_OUTP_CH_CTRL_VCXO_SRC_SEL_CH1

#define AD9523_PLL1_OUTP_CH_CTRL_VCXO_SRC_SEL_CH1 (1 << 1)

◆ AD9523_PLL1_OUTP_CH_CTRL_VCXO_SRC_SEL_CH2

#define AD9523_PLL1_OUTP_CH_CTRL_VCXO_SRC_SEL_CH2 (1 << 2)

◆ AD9523_PLL1_OUTP_CH_CTRL_VCXO_SRC_SEL_CH3

#define AD9523_PLL1_OUTP_CH_CTRL_VCXO_SRC_SEL_CH3 (1 << 3)

◆ AD9523_PLL1_OUTP_CTRL_CMOS_DRV_WEAK

#define AD9523_PLL1_OUTP_CTRL_CMOS_DRV_WEAK (1 << 4)

◆ AD9523_PLL1_OUTP_CTRL_OUTPUT_DIV_1

#define AD9523_PLL1_OUTP_CTRL_OUTPUT_DIV_1 (0 << 0)

◆ AD9523_PLL1_OUTP_CTRL_OUTPUT_DIV_16

#define AD9523_PLL1_OUTP_CTRL_OUTPUT_DIV_16 (8 << 0)

◆ AD9523_PLL1_OUTP_CTRL_OUTPUT_DIV_2

#define AD9523_PLL1_OUTP_CTRL_OUTPUT_DIV_2 (1 << 0)

◆ AD9523_PLL1_OUTP_CTRL_OUTPUT_DIV_4

#define AD9523_PLL1_OUTP_CTRL_OUTPUT_DIV_4 (2 << 0)

◆ AD9523_PLL1_OUTP_CTRL_OUTPUT_DIV_8

#define AD9523_PLL1_OUTP_CTRL_OUTPUT_DIV_8 (4 << 0)

◆ AD9523_PLL1_OUTP_CTRL_VCO_DIV_SEL_CH4_M2

#define AD9523_PLL1_OUTP_CTRL_VCO_DIV_SEL_CH4_M2 (1 << 5)

◆ AD9523_PLL1_OUTP_CTRL_VCO_DIV_SEL_CH5_M2

#define AD9523_PLL1_OUTP_CTRL_VCO_DIV_SEL_CH5_M2 (1 << 6)

◆ AD9523_PLL1_OUTP_CTRL_VCO_DIV_SEL_CH6_M2

#define AD9523_PLL1_OUTP_CTRL_VCO_DIV_SEL_CH6_M2 (1 << 7)

◆ AD9523_PLL1_OUTPUT_CHANNEL_CTRL

#define AD9523_PLL1_OUTPUT_CHANNEL_CTRL (AD9523_R1B | 0x1BB)

◆ AD9523_PLL1_OUTPUT_CTRL

#define AD9523_PLL1_OUTPUT_CTRL (AD9523_R1B | 0x1BA)

◆ AD9523_PLL1_REF_A_DIVIDER

#define AD9523_PLL1_REF_A_DIVIDER (AD9523_R2B | 0x11)

◆ AD9523_PLL1_REF_B_DIVIDER

#define AD9523_PLL1_REF_B_DIVIDER (AD9523_R2B | 0x13)

◆ AD9523_PLL1_REF_CTRL

#define AD9523_PLL1_REF_CTRL (AD9523_R1B | 0x1B)

◆ AD9523_PLL1_REF_MODE

#define AD9523_PLL1_REF_MODE ( x )

Value:

((x) << 2)

◆ AD9523_PLL1_REF_TEST_DIVIDER

#define AD9523_PLL1_REF_TEST_DIVIDER (AD9523_R1B | 0x14)

◆ AD9523_PLL1_REF_TEST_RCV_EN

#define AD9523_PLL1_REF_TEST_RCV_EN (1 << 7)

◆ AD9523_PLL1_REFA_CMOS_NEG_INP_EN

#define AD9523_PLL1_REFA_CMOS_NEG_INP_EN (1 << 0)

◆ AD9523_PLL1_REFA_DIFF_RCV_EN

#define AD9523_PLL1_REFA_DIFF_RCV_EN (1 << 5)

◆ AD9523_PLL1_REFA_RCV_EN

#define AD9523_PLL1_REFA_RCV_EN (1 << 3)

◆ AD9523_PLL1_REFA_REFB_PWR_CTRL_EN

#define AD9523_PLL1_REFA_REFB_PWR_CTRL_EN (1 << 2)

◆ AD9523_PLL1_REFB_CMOS_NEG_INP_EN

#define AD9523_PLL1_REFB_CMOS_NEG_INP_EN (1 << 1)

◆ AD9523_PLL1_REFB_DIFF_RCV_EN

#define AD9523_PLL1_REFB_DIFF_RCV_EN (1 << 6)

◆ AD9523_PLL1_REFB_INDEP_DIV_CTRL_EN

#define AD9523_PLL1_REFB_INDEP_DIV_CTRL_EN (1 << 7)

◆ AD9523_PLL1_REFB_RCV_EN

#define AD9523_PLL1_REFB_RCV_EN (1 << 4)

◆ AD9523_PLL1_ZD_IN_CMOS_NEG_INP_EN

#define AD9523_PLL1_ZD_IN_CMOS_NEG_INP_EN (1 << 3)

◆ AD9523_PLL1_ZD_IN_DIFF_EN

#define AD9523_PLL1_ZD_IN_DIFF_EN (1 << 2)

◆ AD9523_PLL1_ZERO_DELAY_MODE_EXT

#define AD9523_PLL1_ZERO_DELAY_MODE_EXT (0 << 5)

◆ AD9523_PLL1_ZERO_DELAY_MODE_INT

#define AD9523_PLL1_ZERO_DELAY_MODE_INT (1 << 5)

◆ AD9523_PLL2_BACKLASH_CTRL_EN

#define AD9523_PLL2_BACKLASH_CTRL_EN (1 << 4)

◆ AD9523_PLL2_BACKLASH_PW_HIGH

#define AD9523_PLL2_BACKLASH_PW_HIGH (2 << 2)

◆ AD9523_PLL2_BACKLASH_PW_LOW

#define AD9523_PLL2_BACKLASH_PW_LOW (1 << 2)

◆ AD9523_PLL2_BACKLASH_PW_MAX

#define AD9523_PLL2_BACKLASH_PW_MAX (3 << 1)

◆ AD9523_PLL2_BACKLASH_PW_MIN

#define AD9523_PLL2_BACKLASH_PW_MIN (0 << 2)

◆ AD9523_PLL2_CHARGE_PUMP

#define AD9523_PLL2_CHARGE_PUMP (AD9523_R1B | 0xF0)

◆ AD9523_PLL2_CHARGE_PUMP_CURRENT_nA

#define AD9523_PLL2_CHARGE_PUMP_CURRENT_nA ( x )

Value:

((x) / 3500)

◆ AD9523_PLL2_CHARGE_PUMP_MODE_NORMAL

#define AD9523_PLL2_CHARGE_PUMP_MODE_NORMAL (3 << 0)

◆ AD9523_PLL2_CHARGE_PUMP_MODE_PUMP_DOWN

#define AD9523_PLL2_CHARGE_PUMP_MODE_PUMP_DOWN (2 << 0)

◆ AD9523_PLL2_CHARGE_PUMP_MODE_PUMP_UP

#define AD9523_PLL2_CHARGE_PUMP_MODE_PUMP_UP (1 << 0)

◆ AD9523_PLL2_CHARGE_PUMP_MODE_TRISTATE

#define AD9523_PLL2_CHARGE_PUMP_MODE_TRISTATE (0 << 0)

◆ AD9523_PLL2_CTRL

#define AD9523_PLL2_CTRL (AD9523_R1B | 0xF2)

◆ AD9523_PLL2_FB_NDIV

#define AD9523_PLL2_FB_NDIV	(		a,
			b )

Value:

(4 * (b) + (a))

◆ AD9523_PLL2_FB_NDIV_A_CNT

#define AD9523_PLL2_FB_NDIV_A_CNT ( x )

Value:

(((x) & 0x3) << 6)

◆ AD9523_PLL2_FB_NDIV_B_CNT

#define AD9523_PLL2_FB_NDIV_B_CNT ( x )

Value:

(((x) & 0x3F) << 0)

◆ AD9523_PLL2_FEEDBACK_DIVIDER_AB

#define AD9523_PLL2_FEEDBACK_DIVIDER_AB (AD9523_R1B | 0xF1)

◆ AD9523_PLL2_FORCE_REFERENCE_VALID

#define AD9523_PLL2_FORCE_REFERENCE_VALID (1 << 3)

◆ AD9523_PLL2_FORCE_RELEASE_SYNC

#define AD9523_PLL2_FORCE_RELEASE_SYNC (1 << 4)

◆ AD9523_PLL2_FORCE_VCO_MIDSCALE

#define AD9523_PLL2_FORCE_VCO_MIDSCALE (1 << 2)

◆ AD9523_PLL2_FREQ_DOUBLER_EN

#define AD9523_PLL2_FREQ_DOUBLER_EN (1 << 5)

◆ AD9523_PLL2_LOCK_DETECT_PWR_DOWN_EN

#define AD9523_PLL2_LOCK_DETECT_PWR_DOWN_EN (1 << 7)

◆ AD9523_PLL2_LOOP_FILTER_CPOLE1

#define AD9523_PLL2_LOOP_FILTER_CPOLE1 ( x )

Value:

(((x) & 0x7) << 0)

◆ AD9523_PLL2_LOOP_FILTER_CTRL

#define AD9523_PLL2_LOOP_FILTER_CTRL (AD9523_R2B | 0xF6)

◆ AD9523_PLL2_LOOP_FILTER_RPOLE2

#define AD9523_PLL2_LOOP_FILTER_RPOLE2 ( x )

Value:

(((x) & 0x7) << 6)

◆ AD9523_PLL2_LOOP_FILTER_RZERO

#define AD9523_PLL2_LOOP_FILTER_RZERO ( x )

Value:

(((x) & 0x7) << 3)

◆ AD9523_PLL2_LOOP_FILTER_RZERO_BYPASS_EN

#define AD9523_PLL2_LOOP_FILTER_RZERO_BYPASS_EN (1 << 8)

◆ AD9523_PLL2_R2_DIVIDER

#define AD9523_PLL2_R2_DIVIDER (AD9523_R1B | 0xF7)

◆ AD9523_PLL2_R2_DIVIDER_VAL

#define AD9523_PLL2_R2_DIVIDER_VAL ( x )

Value:

(((x) & 0x1F) << 0)

◆ AD9523_PLL2_VCO_CALIBRATE

#define AD9523_PLL2_VCO_CALIBRATE (1 << 1)

◆ AD9523_PLL2_VCO_CTRL

#define AD9523_PLL2_VCO_CTRL (AD9523_R1B | 0xF3)

◆ AD9523_PLL2_VCO_DIV_M1

#define AD9523_PLL2_VCO_DIV_M1 ( x )

Value:

((((x) - 3) & 0x3) << 0)

◆ AD9523_PLL2_VCO_DIV_M1_PWR_DOWN_EN

#define AD9523_PLL2_VCO_DIV_M1_PWR_DOWN_EN (1 << 2)

◆ AD9523_PLL2_VCO_DIV_M2

#define AD9523_PLL2_VCO_DIV_M2 ( x )

Value:

((((x) - 3) & 0x3) << 4)

◆ AD9523_PLL2_VCO_DIV_M2_PWR_DOWN_EN

#define AD9523_PLL2_VCO_DIV_M2_PWR_DOWN_EN (1 << 6)

◆ AD9523_PLL2_VCO_DIVIDER

#define AD9523_PLL2_VCO_DIVIDER (AD9523_R1B | 0xF4)

◆ AD9523_POWER_DOWN_CTRL

#define AD9523_POWER_DOWN_CTRL (AD9523_R1B | 0x233)

◆ AD9523_POWER_DOWN_CTRL_DIST_PWR_DOWN

#define AD9523_POWER_DOWN_CTRL_DIST_PWR_DOWN (1 << 0)

◆ AD9523_POWER_DOWN_CTRL_PLL1_PWR_DOWN

#define AD9523_POWER_DOWN_CTRL_PLL1_PWR_DOWN (1 << 2)

◆ AD9523_POWER_DOWN_CTRL_PLL2_PWR_DOWN

#define AD9523_POWER_DOWN_CTRL_PLL2_PWR_DOWN (1 << 1)

◆ AD9523_R1B

#define AD9523_R1B (1 << 16)

◆ AD9523_R2B

#define AD9523_R2B (2 << 16)

◆ AD9523_R3B

#define AD9523_R3B (3 << 16)

◆ AD9523_READ

#define AD9523_READ (1 << 15)

◆ AD9523_READBACK_0

#define AD9523_READBACK_0 (AD9523_R1B | 0x22C)

◆ AD9523_READBACK_0_STAT_PLL1_LD

#define AD9523_READBACK_0_STAT_PLL1_LD (1 << 0)

◆ AD9523_READBACK_0_STAT_PLL2_FB_CLK

#define AD9523_READBACK_0_STAT_PLL2_FB_CLK (1 << 6)

◆ AD9523_READBACK_0_STAT_PLL2_LD

#define AD9523_READBACK_0_STAT_PLL2_LD (1 << 1)

◆ AD9523_READBACK_0_STAT_PLL2_REF_CLK

#define AD9523_READBACK_0_STAT_PLL2_REF_CLK (1 << 7)

◆ AD9523_READBACK_0_STAT_REF_TEST

#define AD9523_READBACK_0_STAT_REF_TEST (1 << 4)

◆ AD9523_READBACK_0_STAT_REFA

#define AD9523_READBACK_0_STAT_REFA (1 << 2)

◆ AD9523_READBACK_0_STAT_REFB

#define AD9523_READBACK_0_STAT_REFB (1 << 3)

◆ AD9523_READBACK_0_STAT_VCXO

#define AD9523_READBACK_0_STAT_VCXO (1 << 5)

◆ AD9523_READBACK_1

#define AD9523_READBACK_1 (AD9523_R1B | 0x22D)

◆ AD9523_READBACK_1_AUTOMODE_SEL_REFB

#define AD9523_READBACK_1_AUTOMODE_SEL_REFB (1 << 2)

◆ AD9523_READBACK_1_HOLDOVER_ACTIVE

#define AD9523_READBACK_1_HOLDOVER_ACTIVE (1 << 3)

◆ AD9523_READBACK_1_VCO_CALIB_IN_PROGRESS

#define AD9523_READBACK_1_VCO_CALIB_IN_PROGRESS (1 << 0)

◆ AD9523_READBACK_CTRL

#define AD9523_READBACK_CTRL (AD9523_R1B | 0x4)

◆ AD9523_READBACK_CTRL_READ_BUFFERED

#define AD9523_READBACK_CTRL_READ_BUFFERED (1 << 0)

◆ AD9523_SER_CONF_SDO_ACTIVE

#define AD9523_SER_CONF_SDO_ACTIVE ((1 << 7) | (1 << 0))

◆ AD9523_SER_CONF_SOFT_RESET

#define AD9523_SER_CONF_SOFT_RESET ((1 << 5) | (1 << 2))

◆ AD9523_SERIAL_PORT_CONFIG

#define AD9523_SERIAL_PORT_CONFIG (AD9523_R1B | 0x0)

◆ AD9523_STATUS_MONITOR_01_PLL12_LOCKED

#define AD9523_STATUS_MONITOR_01_PLL12_LOCKED (0x302)

◆ AD9523_STATUS_SIGNALS

#define AD9523_STATUS_SIGNALS (AD9523_R3B | 0x232)

◆ AD9523_STATUS_SIGNALS_SYNC_MAN_CTRL

#define AD9523_STATUS_SIGNALS_SYNC_MAN_CTRL (1 << 16)

◆ AD9523_TRANSF_LEN

#define AD9523_TRANSF_LEN ( x )

Value:

((x) >> 16)

◆ AD9523_VERSION_REGISTER

#define AD9523_VERSION_REGISTER (AD9523_R1B | 0x2)

◆ AD9523_WRITE

#define AD9523_WRITE (0 << 15)

Enumeration Type Documentation

◆ ad9523_out_frequencies

enum ad9523_out_frequencies

Enumerator
AD9523_VCO1
AD9523_VCO2
AD9523_VCXO
AD9523_NUM_CLK_SRC

◆ cpole1_capacitor

enum cpole1_capacitor

Enumerator
CPOLE1_0_PF
CPOLE1_8_PF
CPOLE1_16_PF
CPOLE1_24_PF
_CPOLE1_24_PF
CPOLE1_32_PF
CPOLE1_40_PF
CPOLE1_48_PF

◆ outp_drv_mode

enum outp_drv_mode

Enumerator
TRISTATE
LVPECL_8mA
LVDS_4mA
LVDS_7mA
HSTL0_16mA
HSTL1_8mA
CMOS_CONF1
CMOS_CONF2
CMOS_CONF3
CMOS_CONF4
CMOS_CONF5
CMOS_CONF6
CMOS_CONF7
CMOS_CONF8
CMOS_CONF9

◆ pll1_rzero_resistor

enum pll1_rzero_resistor

Enumerator
RZERO_883_OHM
RZERO_677_OHM
RZERO_341_OHM
RZERO_135_OHM
RZERO_10_OHM
RZERO_USE_EXT_RES

◆ ref_sel_mode

enum ref_sel_mode

Enumerator
NONEREVERTIVE_STAY_ON_REFB
REVERT_TO_REFA
SELECT_REFA
SELECT_REFB
EXT_REF_SEL

◆ rpole2_resistor

enum rpole2_resistor

Enumerator
RPOLE2_900_OHM
RPOLE2_450_OHM
RPOLE2_300_OHM
RPOLE2_225_OHM

◆ rzero_resistor

enum rzero_resistor

Enumerator
RZERO_3250_OHM
RZERO_2750_OHM
RZERO_2250_OHM
RZERO_2100_OHM
RZERO_3000_OHM
RZERO_2500_OHM
RZERO_2000_OHM
RZERO_1850_OHM

Function Documentation

◆ ad9523_init()

int32_t ad9523_init ( struct ad9523_init_param * init_param )

Initialize the AD9523 data structure with the default register values.

Parameters

init_param - The device initial parameters.

Returns: Always return 0.

◆ ad9523_io_update()

int32_t ad9523_io_update ( struct ad9523_dev * dev )

Updates the AD9523 configuration.

Parameters

dev	- The device structure.

Returns: Returns 0 in case of success or negative error code.

◆ ad9523_remove()

int32_t ad9523_remove ( struct ad9523_dev * dev )

Free the resources allocated by ad9523_setup().

Parameters

dev	- The device structure.

Returns: 0 in case of success, negative error code otherwise.

◆ ad9523_setup()

int32_t ad9523_setup	(	struct ad9523_dev **	device,
		const struct ad9523_init_param *	init_param )

Setup the AD9523 device.

Parameters

device	- The device structure.
init_param	- The structure holding the device initial parameters.

Returns: Returns 0 in case of success or negative error code.

◆ ad9523_spi_read()

int32_t ad9523_spi_read	(	struct ad9523_dev *	dev,
		uint32_t	reg_addr,
		uint32_t *	reg_data )

Reads the value of the selected register.

Parameters

dev	- The device structure.
reg_addr	- The address of the register to read.
reg_data	- Pointer to the read value.

Returns: Returns 0 in case of success or negative error code.

◆ ad9523_spi_write()

int32_t ad9523_spi_write	(	struct ad9523_dev *	dev,
		uint32_t	reg_addr,
		uint32_t	reg_data )

Writes a value to the selected register.

Parameters

dev	- The device structure.
reg_addr	- The address of the register to write to.
reg_data	- The value to write to the register.

Returns: Returns 0 in case of success or negative error code.

◆ ad9523_status()

int32_t ad9523_status ( struct ad9523_dev * dev )

Updates the AD9523 configuration.

Parameters

dev	- The device structure.

Returns: Returns 0 in case of success or negative error code.

◆ ad9523_sync()

int32_t ad9523_sync ( struct ad9523_dev * dev )

Updates the AD9523 configuration.

Parameters

dev	- The device structure.

Returns: Returns 0 in case of success or negative error code.

◆ ad9523_vco_out_map()

int32_t ad9523_vco_out_map	(	struct ad9523_dev *	dev,
		uint32_t	ch,
		uint32_t	out )

Sets the clock provider for selected channel.

Parameters

dev	- The device structure.
ch	- Selected channel.
out	- Selected clock provider.

Returns: Returns 0 in case of success or negative error code.

Classes

Macros

Enumerations

Functions

Detailed Description

Macro Definition Documentation

◆ AD9523_ADDR

◆ AD9523_CHANNEL_CLOCK_DIST

◆ AD9523_CLK_DIST_DIV

◆ AD9523_CLK_DIST_DIV_PHASE

◆ AD9523_CLK_DIST_DIV_PHASE_REV

◆ AD9523_CLK_DIST_DIV_REV

◆ AD9523_CLK_DIST_DRIVER_MODE

◆ AD9523_CLK_DIST_IGNORE_SYNC_EN

◆ AD9523_CLK_DIST_INV_DIV_OUTPUT_EN

◆ AD9523_CLK_DIST_LOW_PWR_MODE_EN

◆ AD9523_CLK_DIST_PWR_DOWN_EN

◆ AD9523_CNT

◆ AD9523_EEPROM_CTRL1

◆ AD9523_EEPROM_CTRL1_EEPROM_WRITE_PROT_DIS

◆ AD9523_EEPROM_CTRL1_SOFT_EEPROM

◆ AD9523_EEPROM_CTRL2

◆ AD9523_EEPROM_CTRL2_REG2EEPROM

◆ AD9523_EEPROM_CUSTOMER_VERSION_ID

◆ AD9523_EEPROM_DATA_XFER_IN_PROGRESS

◆ AD9523_EEPROM_DATA_XFER_STATUS

◆ AD9523_EEPROM_ERROR_READBACK

◆ AD9523_EEPROM_ERROR_READBACK_FAIL

◆ AD9523_IO_UPDATE

◆ AD9523_IO_UPDATE_EN

◆ AD9523_NUM_CHAN

◆ AD9523_NUM_CHAN_ALT_CLK_SRC

◆ AD9523_PART_REGISTER

◆ AD9523_PLL1_BACKLASH_PW_HIGH

◆ AD9523_PLL1_BACKLASH_PW_LOW

◆ AD9523_PLL1_BACKLASH_PW_MAX

◆ AD9523_PLL1_BACKLASH_PW_MIN

◆ AD9523_PLL1_BYPASS_FEEDBACK_DIV_EN

◆ AD9523_PLL1_BYPASS_REF_TEST_DIV_EN

◆ AD9523_PLL1_BYPASS_REFA_DIV

◆ AD9523_PLL1_BYPASS_REFB_DIV

◆ AD9523_PLL1_CHARGE_PUMP_CTRL

◆ AD9523_PLL1_CHARGE_PUMP_CURRENT_nA

◆ AD9523_PLL1_CHARGE_PUMP_MODE_NORMAL

◆ AD9523_PLL1_CHARGE_PUMP_MODE_PUMP_DOWN

◆ AD9523_PLL1_CHARGE_PUMP_MODE_PUMP_UP

◆ AD9523_PLL1_CHARGE_PUMP_MODE_TRISTATE

◆ AD9523_PLL1_CHARGE_PUMP_TRISTATE

◆ AD9523_PLL1_FEEDBACK_DIVIDER

◆ AD9523_PLL1_INPUT_RECEIVERS_CTRL

◆ AD9523_PLL1_LOOP_FILTER_CTRL

◆ AD9523_PLL1_LOOP_FILTER_RZERO

◆ AD9523_PLL1_MISC_CTRL

◆ AD9523_PLL1_OSC_CTRL_FAIL_VCC_BY2_EN

◆ AD9523_PLL1_OSC_IN_CMOS_NEG_INP_EN

◆ AD9523_PLL1_OSC_IN_DIFF_EN

◆ AD9523_PLL1_OSC_IN_PLL_FEEDBACK_EN

◆ AD9523_PLL1_OUTP_CH_CTRL_OUTPUT_PWR_DOWN_EN

◆ AD9523_PLL1_OUTP_CH_CTRL_VCO_DIV_SEL_CH7_M2

◆ AD9523_PLL1_OUTP_CH_CTRL_VCO_DIV_SEL_CH8_M2

◆ AD9523_PLL1_OUTP_CH_CTRL_VCO_DIV_SEL_CH9_M2

◆ AD9523_PLL1_OUTP_CH_CTRL_VCXO_SRC_SEL_CH0

◆ AD9523_PLL1_OUTP_CH_CTRL_VCXO_SRC_SEL_CH1

◆ AD9523_PLL1_OUTP_CH_CTRL_VCXO_SRC_SEL_CH2

◆ AD9523_PLL1_OUTP_CH_CTRL_VCXO_SRC_SEL_CH3

◆ AD9523_PLL1_OUTP_CTRL_CMOS_DRV_WEAK

◆ AD9523_PLL1_OUTP_CTRL_OUTPUT_DIV_1

◆ AD9523_PLL1_OUTP_CTRL_OUTPUT_DIV_16

◆ AD9523_PLL1_OUTP_CTRL_OUTPUT_DIV_2

◆ AD9523_PLL1_OUTP_CTRL_OUTPUT_DIV_4

◆ AD9523_PLL1_OUTP_CTRL_OUTPUT_DIV_8

◆ AD9523_PLL1_OUTP_CTRL_VCO_DIV_SEL_CH4_M2

◆ AD9523_PLL1_OUTP_CTRL_VCO_DIV_SEL_CH5_M2

◆ AD9523_PLL1_OUTP_CTRL_VCO_DIV_SEL_CH6_M2

◆ AD9523_PLL1_OUTPUT_CHANNEL_CTRL

◆ AD9523_PLL1_OUTPUT_CTRL

◆ AD9523_PLL1_REF_A_DIVIDER

◆ AD9523_PLL1_REF_B_DIVIDER

◆ AD9523_PLL1_REF_CTRL

◆ AD9523_PLL1_REF_MODE