ad9523.h

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/***************************************************************************/
#ifndef _AD9523_H_
#define _AD9523_H_
 
#include <stdint.h>
#include "no_os_delay.h"
#include "no_os_spi.h"
 
/* Registers */
 
#define AD9523_READ                     (1 << 15)
#define AD9523_WRITE                        (0 << 15)
#define AD9523_CNT(x)                       (((x) - 1) << 13)
#define AD9523_ADDR(x)                      ((x) & 0xFFF)
 
#define AD9523_R1B                      (1 << 16)
#define AD9523_R2B                      (2 << 16)
#define AD9523_R3B                      (3 << 16)
#define AD9523_TRANSF_LEN(x)                    ((x) >> 16)
 
#define AD9523_SERIAL_PORT_CONFIG               (AD9523_R1B | 0x0)
#define AD9523_VERSION_REGISTER                 (AD9523_R1B | 0x2)
#define AD9523_PART_REGISTER                    (AD9523_R1B | 0x3)
#define AD9523_READBACK_CTRL                    (AD9523_R1B | 0x4)
 
#define AD9523_EEPROM_CUSTOMER_VERSION_ID           (AD9523_R2B | 0x6)
 
#define AD9523_PLL1_REF_A_DIVIDER               (AD9523_R2B | 0x11)
#define AD9523_PLL1_REF_B_DIVIDER               (AD9523_R2B | 0x13)
#define AD9523_PLL1_REF_TEST_DIVIDER                (AD9523_R1B | 0x14)
#define AD9523_PLL1_FEEDBACK_DIVIDER                (AD9523_R2B | 0x17)
#define AD9523_PLL1_CHARGE_PUMP_CTRL                (AD9523_R2B | 0x19)
#define AD9523_PLL1_INPUT_RECEIVERS_CTRL            (AD9523_R1B | 0x1A)
#define AD9523_PLL1_REF_CTRL                    (AD9523_R1B | 0x1B)
#define AD9523_PLL1_MISC_CTRL                   (AD9523_R1B | 0x1C)
#define AD9523_PLL1_LOOP_FILTER_CTRL                (AD9523_R1B | 0x1D)
 
#define AD9523_PLL2_CHARGE_PUMP                 (AD9523_R1B | 0xF0)
#define AD9523_PLL2_FEEDBACK_DIVIDER_AB             (AD9523_R1B | 0xF1)
#define AD9523_PLL2_CTRL                    (AD9523_R1B | 0xF2)
#define AD9523_PLL2_VCO_CTRL                    (AD9523_R1B | 0xF3)
#define AD9523_PLL2_VCO_DIVIDER                 (AD9523_R1B | 0xF4)
#define AD9523_PLL2_LOOP_FILTER_CTRL                (AD9523_R2B | 0xF6)
#define AD9523_PLL2_R2_DIVIDER                  (AD9523_R1B | 0xF7)
 
#define AD9523_CHANNEL_CLOCK_DIST(ch)               (AD9523_R3B | (0x192 + 3 * ch))
 
#define AD9523_PLL1_OUTPUT_CTRL                 (AD9523_R1B | 0x1BA)
#define AD9523_PLL1_OUTPUT_CHANNEL_CTRL             (AD9523_R1B | 0x1BB)
 
#define AD9523_READBACK_0                   (AD9523_R1B | 0x22C)
#define AD9523_READBACK_1                   (AD9523_R1B | 0x22D)
 
#define AD9523_STATUS_SIGNALS                   (AD9523_R3B | 0x232)
#define AD9523_POWER_DOWN_CTRL                  (AD9523_R1B | 0x233)
#define AD9523_IO_UPDATE                    (AD9523_R1B | 0x234)
 
#define AD9523_EEPROM_DATA_XFER_STATUS              (AD9523_R1B | 0xB00)
#define AD9523_EEPROM_ERROR_READBACK                (AD9523_R1B | 0xB01)
#define AD9523_EEPROM_CTRL1                 (AD9523_R1B | 0xB02)
#define AD9523_EEPROM_CTRL2                 (AD9523_R1B | 0xB03)
 
/* AD9523_SERIAL_PORT_CONFIG */
 
#define AD9523_SER_CONF_SDO_ACTIVE              ((1 << 7) | (1 << 0))
#define AD9523_SER_CONF_SOFT_RESET              ((1 << 5) | (1 << 2))
 
/* AD9523_READBACK_CTRL */
#define AD9523_READBACK_CTRL_READ_BUFFERED          (1 << 0)
 
/* AD9523_PLL1_CHARGE_PUMP_CTRL */
#define AD9523_PLL1_CHARGE_PUMP_CURRENT_nA(x)           (((x) / 500) & 0x7F)
#define AD9523_PLL1_CHARGE_PUMP_TRISTATE            (1 << 7)
#define AD9523_PLL1_CHARGE_PUMP_MODE_NORMAL         (3 << 8)
#define AD9523_PLL1_CHARGE_PUMP_MODE_PUMP_DOWN          (2 << 8)
#define AD9523_PLL1_CHARGE_PUMP_MODE_PUMP_UP            (1 << 8)
#define AD9523_PLL1_CHARGE_PUMP_MODE_TRISTATE           (0 << 8)
#define AD9523_PLL1_BACKLASH_PW_MIN             (0 << 10)
#define AD9523_PLL1_BACKLASH_PW_LOW             (1 << 10)
#define AD9523_PLL1_BACKLASH_PW_HIGH                (2 << 10)
#define AD9523_PLL1_BACKLASH_PW_MAX             (3 << 10)
 
/* AD9523_PLL1_INPUT_RECEIVERS_CTRL */
#define AD9523_PLL1_REF_TEST_RCV_EN             (1 << 7)
#define AD9523_PLL1_REFB_DIFF_RCV_EN                (1 << 6)
#define AD9523_PLL1_REFA_DIFF_RCV_EN                (1 << 5)
#define AD9523_PLL1_REFB_RCV_EN                 (1 << 4)
#define AD9523_PLL1_REFA_RCV_EN                 (1 << 3)
#define AD9523_PLL1_REFA_REFB_PWR_CTRL_EN           (1 << 2)
#define AD9523_PLL1_OSC_IN_CMOS_NEG_INP_EN          (1 << 1)
#define AD9523_PLL1_OSC_IN_DIFF_EN              (1 << 0)
 
/* AD9523_PLL1_REF_CTRL */
#define AD9523_PLL1_BYPASS_REF_TEST_DIV_EN          (1 << 7)
#define AD9523_PLL1_BYPASS_FEEDBACK_DIV_EN          (1 << 6)
#define AD9523_PLL1_ZERO_DELAY_MODE_INT             (1 << 5)
#define AD9523_PLL1_ZERO_DELAY_MODE_EXT             (0 << 5)
#define AD9523_PLL1_OSC_IN_PLL_FEEDBACK_EN          (1 << 4)
#define AD9523_PLL1_ZD_IN_CMOS_NEG_INP_EN           (1 << 3)
#define AD9523_PLL1_ZD_IN_DIFF_EN               (1 << 2)
#define AD9523_PLL1_REFB_CMOS_NEG_INP_EN            (1 << 1)
#define AD9523_PLL1_REFA_CMOS_NEG_INP_EN            (1 << 0)
 
/* AD9523_PLL1_MISC_CTRL */
#define AD9523_PLL1_REFB_INDEP_DIV_CTRL_EN          (1 << 7)
#define AD9523_PLL1_OSC_CTRL_FAIL_VCC_BY2_EN            (1 << 6)
#define AD9523_PLL1_REF_MODE(x)                 ((x) << 2)
#define AD9523_PLL1_BYPASS_REFB_DIV             (1 << 1)
#define AD9523_PLL1_BYPASS_REFA_DIV             (1 << 0)
 
/* AD9523_PLL1_LOOP_FILTER_CTRL */
#define AD9523_PLL1_LOOP_FILTER_RZERO(x)            ((x) & 0xF)
 
/* AD9523_PLL2_CHARGE_PUMP */
#define AD9523_PLL2_CHARGE_PUMP_CURRENT_nA(x)           ((x) / 3500)
 
/* AD9523_PLL2_FEEDBACK_DIVIDER_AB */
#define AD9523_PLL2_FB_NDIV_A_CNT(x)                (((x) & 0x3) << 6)
#define AD9523_PLL2_FB_NDIV_B_CNT(x)                (((x) & 0x3F) << 0)
#define AD9523_PLL2_FB_NDIV(a, b)               (4 * (b) + (a))
 
/* AD9523_PLL2_CTRL */
#define AD9523_PLL2_CHARGE_PUMP_MODE_NORMAL         (3 << 0)
#define AD9523_PLL2_CHARGE_PUMP_MODE_PUMP_DOWN          (2 << 0)
#define AD9523_PLL2_CHARGE_PUMP_MODE_PUMP_UP            (1 << 0)
#define AD9523_PLL2_CHARGE_PUMP_MODE_TRISTATE           (0 << 0)
#define AD9523_PLL2_BACKLASH_PW_MIN             (0 << 2)
#define AD9523_PLL2_BACKLASH_PW_LOW             (1 << 2)
#define AD9523_PLL2_BACKLASH_PW_HIGH                (2 << 2)
#define AD9523_PLL2_BACKLASH_PW_MAX             (3 << 1)
#define AD9523_PLL2_BACKLASH_CTRL_EN                (1 << 4)
#define AD9523_PLL2_FREQ_DOUBLER_EN             (1 << 5)
#define AD9523_PLL2_LOCK_DETECT_PWR_DOWN_EN         (1 << 7)
 
/* AD9523_PLL2_VCO_CTRL */
#define AD9523_PLL2_VCO_CALIBRATE               (1 << 1)
#define AD9523_PLL2_FORCE_VCO_MIDSCALE              (1 << 2)
#define AD9523_PLL2_FORCE_REFERENCE_VALID           (1 << 3)
#define AD9523_PLL2_FORCE_RELEASE_SYNC              (1 << 4)
 
/* AD9523_PLL2_VCO_DIVIDER */
#define AD9523_PLL2_VCO_DIV_M1(x)               ((((x) - 3) & 0x3) << 0)
#define AD9523_PLL2_VCO_DIV_M2(x)               ((((x) - 3) & 0x3) << 4)
#define AD9523_PLL2_VCO_DIV_M1_PWR_DOWN_EN          (1 << 2)
#define AD9523_PLL2_VCO_DIV_M2_PWR_DOWN_EN          (1 << 6)
 
/* AD9523_PLL2_LOOP_FILTER_CTRL */
#define AD9523_PLL2_LOOP_FILTER_CPOLE1(x)           (((x) & 0x7) << 0)
#define AD9523_PLL2_LOOP_FILTER_RZERO(x)            (((x) & 0x7) << 3)
#define AD9523_PLL2_LOOP_FILTER_RPOLE2(x)           (((x) & 0x7) << 6)
#define AD9523_PLL2_LOOP_FILTER_RZERO_BYPASS_EN         (1 << 8)
 
/* AD9523_PLL2_R2_DIVIDER */
#define AD9523_PLL2_R2_DIVIDER_VAL(x)               (((x) & 0x1F) << 0)
 
/* AD9523_CHANNEL_CLOCK_DIST */
#define AD9523_CLK_DIST_DIV_PHASE(x)                (((x) & 0x3F) << 18)
#define AD9523_CLK_DIST_DIV_PHASE_REV(x)            ((ret >> 18) & 0x3F)
#define AD9523_CLK_DIST_DIV(x)                  ((((x) - 1) & 0x3FF) << 8)
#define AD9523_CLK_DIST_DIV_REV(x)              (((ret >> 8) & 0x3FF) + 1)
#define AD9523_CLK_DIST_INV_DIV_OUTPUT_EN           (1 << 7)
#define AD9523_CLK_DIST_IGNORE_SYNC_EN              (1 << 6)
#define AD9523_CLK_DIST_PWR_DOWN_EN             (1 << 5)
#define AD9523_CLK_DIST_LOW_PWR_MODE_EN             (1 << 4)
#define AD9523_CLK_DIST_DRIVER_MODE(x)              (((x) & 0xF) << 0)
 
/* AD9523_PLL1_OUTPUT_CTRL */
#define AD9523_PLL1_OUTP_CTRL_VCO_DIV_SEL_CH6_M2        (1 << 7)
#define AD9523_PLL1_OUTP_CTRL_VCO_DIV_SEL_CH5_M2        (1 << 6)
#define AD9523_PLL1_OUTP_CTRL_VCO_DIV_SEL_CH4_M2        (1 << 5)
#define AD9523_PLL1_OUTP_CTRL_CMOS_DRV_WEAK         (1 << 4)
#define AD9523_PLL1_OUTP_CTRL_OUTPUT_DIV_1          (0 << 0)
#define AD9523_PLL1_OUTP_CTRL_OUTPUT_DIV_2          (1 << 0)
#define AD9523_PLL1_OUTP_CTRL_OUTPUT_DIV_4          (2 << 0)
#define AD9523_PLL1_OUTP_CTRL_OUTPUT_DIV_8          (4 << 0)
#define AD9523_PLL1_OUTP_CTRL_OUTPUT_DIV_16         (8 << 0)
 
/* AD9523_PLL1_OUTPUT_CHANNEL_CTRL */
#define AD9523_PLL1_OUTP_CH_CTRL_OUTPUT_PWR_DOWN_EN     (1 << 7)
#define AD9523_PLL1_OUTP_CH_CTRL_VCO_DIV_SEL_CH9_M2     (1 << 6)
#define AD9523_PLL1_OUTP_CH_CTRL_VCO_DIV_SEL_CH8_M2     (1 << 5)
#define AD9523_PLL1_OUTP_CH_CTRL_VCO_DIV_SEL_CH7_M2     (1 << 4)
#define AD9523_PLL1_OUTP_CH_CTRL_VCXO_SRC_SEL_CH3       (1 << 3)
#define AD9523_PLL1_OUTP_CH_CTRL_VCXO_SRC_SEL_CH2       (1 << 2)
#define AD9523_PLL1_OUTP_CH_CTRL_VCXO_SRC_SEL_CH1       (1 << 1)
#define AD9523_PLL1_OUTP_CH_CTRL_VCXO_SRC_SEL_CH0       (1 << 0)
 
/* AD9523_READBACK_0 */
#define AD9523_READBACK_0_STAT_PLL2_REF_CLK         (1 << 7)
#define AD9523_READBACK_0_STAT_PLL2_FB_CLK          (1 << 6)
#define AD9523_READBACK_0_STAT_VCXO             (1 << 5)
#define AD9523_READBACK_0_STAT_REF_TEST             (1 << 4)
#define AD9523_READBACK_0_STAT_REFB             (1 << 3)
#define AD9523_READBACK_0_STAT_REFA             (1 << 2)
#define AD9523_READBACK_0_STAT_PLL2_LD              (1 << 1)
#define AD9523_READBACK_0_STAT_PLL1_LD              (1 << 0)
 
/* AD9523_READBACK_1 */
#define AD9523_READBACK_1_HOLDOVER_ACTIVE           (1 << 3)
#define AD9523_READBACK_1_AUTOMODE_SEL_REFB         (1 << 2)
#define AD9523_READBACK_1_VCO_CALIB_IN_PROGRESS         (1 << 0)
 
/* AD9523_STATUS_SIGNALS */
#define AD9523_STATUS_SIGNALS_SYNC_MAN_CTRL         (1 << 16)
#define AD9523_STATUS_MONITOR_01_PLL12_LOCKED           (0x302)
/* AD9523_POWER_DOWN_CTRL */
#define AD9523_POWER_DOWN_CTRL_PLL1_PWR_DOWN            (1 << 2)
#define AD9523_POWER_DOWN_CTRL_PLL2_PWR_DOWN            (1 << 1)
#define AD9523_POWER_DOWN_CTRL_DIST_PWR_DOWN            (1 << 0)
 
/* AD9523_IO_UPDATE */
#define AD9523_IO_UPDATE_EN                 (1 << 0)
 
/* AD9523_EEPROM_DATA_XFER_STATUS */
#define AD9523_EEPROM_DATA_XFER_IN_PROGRESS         (1 << 0)
 
/* AD9523_EEPROM_ERROR_READBACK */
#define AD9523_EEPROM_ERROR_READBACK_FAIL           (1 << 0)
 
/* AD9523_EEPROM_CTRL1 */
#define AD9523_EEPROM_CTRL1_SOFT_EEPROM             (1 << 1)
#define AD9523_EEPROM_CTRL1_EEPROM_WRITE_PROT_DIS       (1 << 0)
 
/* AD9523_EEPROM_CTRL2 */
#define AD9523_EEPROM_CTRL2_REG2EEPROM              (1 << 0)
 
#define AD9523_NUM_CHAN                     14
#define AD9523_NUM_CHAN_ALT_CLK_SRC             10
 
enum outp_drv_mode {
    TRISTATE,
    LVPECL_8mA,
    LVDS_4mA,
    LVDS_7mA,
    HSTL0_16mA,
    HSTL1_8mA,
    CMOS_CONF1,
    CMOS_CONF2,
    CMOS_CONF3,
    CMOS_CONF4,
    CMOS_CONF5,
    CMOS_CONF6,
    CMOS_CONF7,
    CMOS_CONF8,
    CMOS_CONF9
};
enum outp_drv_mode {…};
 
enum ref_sel_mode {
    NONEREVERTIVE_STAY_ON_REFB,
    REVERT_TO_REFA,
    SELECT_REFA,
    SELECT_REFB,
    EXT_REF_SEL
};
enum ref_sel_mode {…};

struct ad9523_channel_spec {
    uint8_t channel_num;
    uint8_t divider_output_invert_en;
    uint8_t sync_ignore_en;
    uint8_t low_power_mode_en;
    uint8_t use_alt_clock_src;
    uint8_t output_dis;
    uint8_t driver_mode;
    uint8_t divider_phase;
    uint16_t channel_divider;
    int8_t extended_name[16];
};
struct ad9523_channel_spec {…};
 
enum pll1_rzero_resistor {
    RZERO_883_OHM,
    RZERO_677_OHM,
    RZERO_341_OHM,
    RZERO_135_OHM,
    RZERO_10_OHM,
    RZERO_USE_EXT_RES = 8,
};
enum pll1_rzero_resistor {…};
 
enum rpole2_resistor {
    RPOLE2_900_OHM,
    RPOLE2_450_OHM,
    RPOLE2_300_OHM,
    RPOLE2_225_OHM,
};
enum rpole2_resistor {…};
 
enum rzero_resistor {
    RZERO_3250_OHM,
    RZERO_2750_OHM,
    RZERO_2250_OHM,
    RZERO_2100_OHM,
    RZERO_3000_OHM,
    RZERO_2500_OHM,
    RZERO_2000_OHM,
    RZERO_1850_OHM,
};
enum rzero_resistor {…};
 
enum cpole1_capacitor {
    CPOLE1_0_PF,
    CPOLE1_8_PF,
    CPOLE1_16_PF,
    CPOLE1_24_PF,
    _CPOLE1_24_PF, /* place holder */
    CPOLE1_32_PF,
    CPOLE1_40_PF,
    CPOLE1_48_PF,
};
enum cpole1_capacitor {…};

struct ad9523_platform_data {
    uint32_t vcxo_freq;
    uint8_t spi3wire;

    uint8_t refa_diff_rcv_en;
    uint8_t refb_diff_rcv_en;
    uint8_t zd_in_diff_en;
    uint8_t osc_in_diff_en;
 
    /*
     * Valid if differential input disabled
     * if not true defaults to pos input
     */
    uint8_t refa_cmos_neg_inp_en;
    /* REFB single-ended neg./pos. input enable. */
    uint8_t refb_cmos_neg_inp_en;
    uint8_t zd_in_cmos_neg_inp_en;
    uint8_t osc_in_cmos_neg_inp_en;
 
    /* PLL1 Setting */
    uint16_t refa_r_div;
    uint16_t refb_r_div;
    uint16_t pll1_feedback_div;
    uint16_t pll1_charge_pump_current_nA;
    uint8_t zero_delay_mode_internal_en;
    uint8_t osc_in_feedback_en;

    uint8_t pll1_bypass_en;
    uint8_t pll1_loop_filter_rzero;

    uint8_t ref_mode;
 
    /* PLL2 Setting */
    uint32_t pll2_charge_pump_current_nA;
    uint8_t pll2_ndiv_a_cnt;
    uint8_t pll2_ndiv_b_cnt;
    uint8_t pll2_freq_doubler_en;
    uint8_t pll2_r2_div;
    uint8_t pll2_vco_diff_m1;
    uint8_t pll2_vco_diff_m2;
 
    /* Loop Filter PLL2 */
    uint8_t rpole2;
    uint8_t rzero;
    uint8_t cpole1;
    uint8_t rzero_bypass_en;
 
    /* Output Channel Configuration */
    int32_t num_channels;
    struct ad9523_channel_spec *channels;

    int8_t name[16];
};
struct ad9523_platform_data {…};
 
struct ad9523_state {
    struct ad9523_platform_data *pdata;
    uint32_t vcxo_freq;
    uint32_t vco_freq;
    uint32_t vco_out_freq[3];
    uint8_t vco_out_map[14];
};
struct ad9523_state {…};
 
enum ad9523_out_frequencies {
    AD9523_VCO1,
    AD9523_VCO2,
    AD9523_VCXO,
    AD9523_NUM_CLK_SRC,
};
enum ad9523_out_frequencies {…};
 
struct ad9523_dev {
    /* SPI */
    struct no_os_spi_desc     *spi_desc;
    /* Device Settings */
    struct ad9523_state     ad9523_st;
    struct ad9523_platform_data *pdata;
};
struct ad9523_dev {…};
 
struct ad9523_init_param {
    /* SPI */
    struct no_os_spi_init_param spi_init;
    /* Device Settings */
    struct ad9523_platform_data *pdata;
};
struct ad9523_init_param {…};
 
/* Reads the value of the selected register. */
int32_t ad9523_spi_read(struct ad9523_dev *dev,
            uint32_t reg_addr,
            uint32_t *reg_data);
 
/* Writes a value to the selected register. */
int32_t ad9523_spi_write(struct ad9523_dev *dev,
             uint32_t reg_addr,
             uint32_t reg_data);
 
/* Updates the AD9523 configuration */
int32_t ad9523_io_update(struct ad9523_dev *dev);
 
/* Sets the clock provider for selected channel. */
int32_t ad9523_vco_out_map(struct ad9523_dev *dev,
               uint32_t ch,
               uint32_t out);
 
/* Updates the AD9523 configuration. */
int32_t ad9523_sync(struct ad9523_dev *dev);
 
/* Initialize the AD9523 data structure*/
int32_t ad9523_init(struct ad9523_init_param *init_param);
 
/* Configure the AD9523. */
int32_t ad9523_setup(struct ad9523_dev **device,
             const struct ad9523_init_param *init_param);
 
/* Free the resources allocated by ad9523_setup(). */
int32_t ad9523_remove(struct ad9523_dev *dev);
 
int32_t ad9523_status(struct ad9523_dev *dev);
#endif // __AD9523_H__