Header file of ADE9039 Driver. More...

#include <stdbool.h>
#include <stdint.h>
#include <string.h>
#include "no_os_util.h"
#include "no_os_spi.h"
#include "no_os_gpio.h"
#include "no_os_print_log.h"

Include dependency graph for ade9039.h:

Classes
struct	ade9039_init_param
	ADE9039 Device initialization parameters. More...

struct	ade9039_dev
	ADE9039 Device structure. More...

Macros
#define	ADE9039_SPI_READ NO_OS_BIT(3)

#define	ENABLE 0x0001

#define	DISABLE 0x0000

#define	ADE9039_REG_AIGAIN 0x000 /* Phase A current gain adjust. */

#define	ADE9039_REG_AIGAIN0

#define	ADE9039_REG_AIGAIN1 0x002 /* See the AIGAIN0 description. */

#define	ADE9039_REG_AIGAIN2 0x003 /* See the AIGAIN0 description. */

#define	ADE9039_REG_AIGAIN3 0x004 /* See the AIGAIN0 description. */

#define	ADE9039_REG_AIGAIN4 0x005 /* See the AIGAIN0 description. */

#define	ADE9039_REG_APHCAL0

#define	ADE9039_REG_APHCAL1 0x007 /* See the APHCAL0 description. */

#define	ADE9039_REG_APHCAL2 0x008 /* See the APHCAL0 description. */

#define	ADE9039_REG_APHCAL3 0x009 /* See the APHCAL0 description. */

#define	ADE9039_REG_APHCAL4 0x00A /* See the APHCAL0 description. */

#define	ADE9039_REG_AVGAIN 0x00B /* Phase A voltage gain adjust. */

#define	ADE9039_REG_AIRMSOS 0x00C /* Phase A current RMS offset for the filter-based AIRMS calculation. */

#define	ADE9039_REG_AVRMSOS 0x00D /* Phase A voltage RMS offset for the filter-based AVRMS calculation. */

#define	ADE9039_REG_APGAIN 0x00E /* Phase A power gain adjust for the AWATT, AVA, AFWATT, AFVA, and */

#define	ADE9039_REG_AWATTOS 0x00F /* Phase A total active power offset correction for the AWATT calculation. */

#define	ADE9039_REG_AFWATTOS 0x011 /* Phase A fundamental active power offset correction for the AFWATT */

#define	ADE9039_REG_AFVAROS 0x012 /* Phase A fundamental reactive power offset correction for the AFVAR */

#define	ADE9039_REG_AIFRMSOS 0x013 /* Phase A current RMS offset for the fundamental current RMS, AIFRMS */

#define	ADE9039_REG_AVFRMSOS 0x014 /* Phase A voltage RMS offset for the fundamental voltage RMS, AVFRMS */

#define	ADE9039_REG_AVRMSONEOS 0x015 /* Phase A voltage RMS offset for the fast AVRMSONE calculation. */

#define	ADE9039_REG_AIRMSONEOS 0x016 /* Phase A current RMS offset for the fast AIRMSONE calculation. */

#define	ADE9039_REG_AECCOEF 0x019 /* Phase A coupling coefficient used to compensate for the electrostatic the Analog Devices PCB-based di/dt sensor. Format is 5.27. */

#define	ADE9039_REG_BIGAIN 0x020 /* Phase B current gain adjust. */

#define	ADE9039_REG_BIGAIN0

#define	ADE9039_REG_BIGAIN1 0x022 /* See the BIGAIN0 description. */

#define	ADE9039_REG_BIGAIN2 0x023 /* See the BIGAIN0 description. */

#define	ADE9039_REG_BIGAIN3 0x024 /* See the BIGAIN0 description. */

#define	ADE9039_REG_BIGAIN4 0x025 /* See the BIGAIN0 description. */

#define	ADE9039_REG_BPHCAL0 0x026 /* Phase B multipoint phase correction factor. If multipoint phase and gain disabled, with MTEN = 0 in the CONFIG0 register, the */

#define	ADE9039_REG_BPHCAL1 0x027 /* See the BPHCAL0 description. */

#define	ADE9039_REG_BPHCAL2 0x028 /* See the BPHCAL0 description. */

#define	ADE9039_REG_BPHCAL3 0x029 /* See the BPHCAL0 description. */

#define	ADE9039_REG_BPHCAL4 0x02A /* See the BPHCAL0 description. */

#define	ADE9039_REG_BVGAIN 0x02B /* Phase B voltage gain adjust. */

#define	ADE9039_REG_BIRMSOS 0x02C /* Phase B current RMS offset for the BIRMS calculation. */

#define	ADE9039_REG_BVRMSOS 0x02D /* Phase B voltage RMS offset for the BVRMS calculation. */

#define	ADE9039_REG_BPGAIN 0x02E /* Phase B power gain adjust for the BWATT, BVA, BFWATT, BFVA, and */

#define	ADE9039_REG_BWATTOS 0x02F /* Phase B total active power offset correction for the BWATT calculation. */

#define	ADE9039_REG_BFWATTOS 0x031 /* Phase B fundamental active power offset correction for the BFWATT */

#define	ADE9039_REG_BFVAROS 0x032 /* Phase B fundamental reactive power offset correction for the BFVAR */

#define	ADE9039_REG_BIFRMSOS 0x033 /* Phase B current RMS offset for the fundamental current RMS, BIFRMS */

#define	ADE9039_REG_BVFRMSOS 0x034 /* Phase B voltage RMS offset for the fundamental voltage RMS, BVFRMS */

#define	ADE9039_REG_BVRMSONEOS 0x035 /* Phase B voltage RMS offset for the fast BVRMSONE calculation. */

#define	ADE9039_REG_BIRMSONEOS 0x036 /* Phase B current RMS offset for the fast BIRMSONE calculation. */

#define	ADE9039_REG_BECCOEF 0x039 /* Phase B coupling coefficient used to compensate for the electrostatic the Analog Devices PCB-based di/dt sensor. Format is 5.27. */

#define	ADE9039_REG_CIGAIN 0x040 /* Phase C current gain adjust. */

#define	ADE9039_REG_CIGAIN0

#define	ADE9039_REG_CIGAIN1 0x042 /* See the CIGAIN0 description. */

#define	ADE9039_REG_CIGAIN2 0x043 /* See the CIGAIN0 description. */

#define	ADE9039_REG_CIGAIN3 0x044 /* See the CIGAIN0 description. */

#define	ADE9039_REG_CIGAIN4 0x045 /* See the CIGAIN0 description. */

#define	ADE9039_REG_CPHCAL0

#define	ADE9039_REG_CPHCAL1 0x047 /* See the CPHCAL0 description. */

#define	ADE9039_REG_CPHCAL2 0x048 /* See the CPHCAL0 description. */

#define	ADE9039_REG_CPHCAL3 0x049 /* See the CPHCAL0 description. */

#define	ADE9039_REG_CPHCAL4 0x04A /* See the CPHCAL0 description. */

#define	ADE9039_REG_CVGAIN 0x04B /* Phase C voltage gain adjust. */

#define	ADE9039_REG_CIRMSOS 0x04C /* Phase C current RMS offset for the CIRMS calculation. */

#define	ADE9039_REG_CVRMSOS 0x04D /* Phase C voltage RMS offset for the CVRMS calculation. */

#define	ADE9039_REG_CPGAIN 0x04E /* Phase C power gain adjust for the CWATT, CVA, CFWATT, CFVA, and */

#define	ADE9039_REG_CWATTOS 0x04F /* Phase C total active power offset correction for the CWATT calculation. */

#define	ADE9039_REG_CFWATTOS 0x051 /* Phase C fundamental active power offset correction for the CFWATT */

#define	ADE9039_REG_CFVAROS 0x052 /* Phase C fundamental reactive power offset correction for the CFVAR */

#define	ADE9039_REG_CIFRMSOS 0x053 /* Phase C current RMS offset for the fundamental current RMS, CIFRMS */

#define	ADE9039_REG_CVFRMSOS 0x054 /* Phase C voltage RMS offset for the fundamental voltage RMS, CVFRMS */

#define	ADE9039_REG_CVRMSONEOS 0x055 /* Phase C voltage RMS offset for the fast CVRMSONE calculation. */

#define	ADE9039_REG_CIRMSONEOS 0x056 /* Phase C current RMS offset for the fast CIRMSONE calculation. */

#define	ADE9039_REG_CECCOEF 0x059 /* Phase C coupling coefficient used to compensate for the electrostatic the Analog Devices PCB-based di/dt sensor. Format is 5.27. */

#define	ADE9039_REG_CONFIG0 0x060 /* Configuration Register 0. DSP measurements configuration register. */

#define	ADE9039_REG_MTTHR_L0

#define	ADE9039_REG_MTTHR_L1 0x062 /* Multipoint phase/gain threshold. See MTTHR_L0 for more information. */

#define	ADE9039_REG_MTTHR_L2 0x063 /* Multipoint phase/gain threshold. See MTTHR_L0 for more information. */

#define	ADE9039_REG_MTTHR_L3 0x064 /* Multipoint phase/gain threshold. See MTTHR_L0 for more information. */

#define	ADE9039_REG_MTTHR_L4 0x065 /* Multipoint phase/gain threshold. See MTTHR_L0 for more information. */

#define	ADE9039_REG_MTTHR_H0 0x066 /* Multipoint phase/gain threshold. See MTTHR_L0 for more information. */

#define	ADE9039_REG_MTTHR_H1 0x067 /* Multipoint phase/gain threshold. See MTTHR_L0 for more information. */

#define	ADE9039_REG_MTTHR_H2 0x068 /* Multipoint phase/gain threshold. See MTTHR_L0 for more information. */

#define	ADE9039_REG_MTTHR_H3 0x069 /* Multipoint phase/gain threshold. See MTTHR_L0 for more information. */

#define	ADE9039_REG_MTTHR_H4 0x06A /* Multipoint phase/gain threshold. See MTTHR_L0 for more information. */

#define	ADE9039_REG_NIRMSOS 0x06B /* Neutral current RMS offset for the NIRMS calculation. */

#define	ADE9039_REG_ISUMRMSOS 0x06C /* Offset correction for the ISUMRMS calculation based on the sum of IA + IB + IN. */

#define	ADE9039_REG_NIGAIN 0x06D /* Neutral current gain adjust. */

#define	ADE9039_REG_NPHCAL 0x06E /* Neutral current phase compensation. */

#define	ADE9039_REG_NIRMSONEOS 0x06F /* Neutral current RMS offset for the fast RMS½ NIRMSONE calculation. */

#define	ADE9039_REG_VNOM 0x071 /* Nominal phase voltage RMS used in the computation of apparent power, the VNOMx_EN bit is set in the CONFIG0 register. */

#define	ADE9039_REG_DICOEFF

#define	ADE9039_REG_ISUMLVL 0x073 /* Threshold to compare ISUMRMS against. Configure this register to receive indication in the STATUS0 register if ISUMRMS exceeds this */

#define	ADE9039_REG_AI_PCF 0x20A /* Instantaneous Phase A current channel waveform processed by the DSP at */

#define	ADE9039_REG_AV_PCF 0x20B /* Instantaneous Phase A voltage channel waveform processed by the DSP at */

#define	ADE9039_REG_AIRMS 0x20C /* Phase A filter-based current RMS value, updated at 4 kSPS. */

#define	ADE9039_REG_AVRMS 0x20D /* Phase A filter-based voltage RMS value, updated at 4 kSPS. */

#define	ADE9039_REG_AIFRMS 0x20E /* Phase A current fundamental RMS, updated at 4 kSPS. */

#define	ADE9039_REG_AVFRMS 0x20F /* Phase A voltage fundamental RMS, updated at 4 kSPS. */

#define	ADE9039_REG_AWATT 0x210 /* Phase A low-pass filtered total active power, updated at 4 kSPS. */

#define	ADE9039_REG_AVA 0x212 /* Phase A total apparent power, updated at 4 kSPS. */

#define	ADE9039_REG_AFWATT 0x213 /* Phase A fundamental active power, updated at 4 kSPS. */

#define	ADE9039_REG_AFVAR 0x214 /* Phase A fundamental reactive power, updated at 4 kSPS. */

#define	ADE9039_REG_AFVA 0x215 /* Phase A fundamental apparent power, updated at 4 kSPS. */

#define	ADE9039_REG_APF 0x216 /* Phase A total power factor, updated every 1.024 sec. */

#define	ADE9039_REG_AVTHD 0x217 /* Phase A voltage THD, updated every 1.024 sec. */

#define	ADE9039_REG_AITHD 0x218 /* Phase A current THD, updated every 1.024 sec. */

#define	ADE9039_REG_AIRMSONE 0x219 /* Phase A current fast RMS½ calculation, one cycle RMS updated every half */

#define	ADE9039_REG_AVRMSONE 0x21A /* Phase A voltage fast RMS½ calculation, one cycle RMS updated every half */

#define	ADE9039_REG_AMTREGION 0x21D /* If multipoint gain and phase compensation is enabled, with MTEN = 1 in the this register indicates which AIGAINx and APHCALx is used. */

#define	ADE9039_REG_AFPF 0x21E /* Phase A fundamental power factor, updated every 1.024 sec. */

#define	ADE9039_REG_AQUADINFO 0x21F /* Phase A power quadrant measurement information. */

#define	ADE9039_REG_BI_PCF 0x22A /* Instantaneous Phase B current channel waveform processed by the DSP at */

#define	ADE9039_REG_BV_PCF 0x22B /* Instantaneous Phase B voltage channel waveform processed by the DSP at */

#define	ADE9039_REG_BIRMS 0x22C /* Phase B filter-based current RMS value, updated at 4 kSPS. */

#define	ADE9039_REG_BVRMS 0x22D /* Phase B filter-based voltage RMS value, updated at 4 kSPS. */

#define	ADE9039_REG_BIFRMS 0x22E /* Phase B current fundamental RMS, updated at 4 kSPS. */

#define	ADE9039_REG_BVFRMS 0x22F /* Phase B voltage fundamental RMS, updated at 4 kSPS. */

#define	ADE9039_REG_BWATT 0x230 /* Phase B low-pass filtered total active power, updated at 4 kSPS. */

#define	ADE9039_REG_BVA 0x232 /* Phase B total apparent power, updated at 4 kSPS. */

#define	ADE9039_REG_BFWATT 0x233 /* Phase B fundamental active power, updated at 4 kSPS. */

#define	ADE9039_REG_BFVAR 0x234 /* Phase B fundamental reactive power, updated at 4 kSPS. */

#define	ADE9039_REG_BFVA 0x235 /* Phase B fundamental apparent power, updated at 4 kSPS. */

#define	ADE9039_REG_BPF 0x236 /* Phase B total power factor, updated every 1.024 sec. */

#define	ADE9039_REG_BVTHD 0x237 /* Phase B voltage THD, updated every 1.024 sec. */

#define	ADE9039_REG_BITHD 0x238 /* Phase B current THD, updated every 1.024 sec. */

#define	ADE9039_REG_BIRMSONE 0x239 /* Phase B current fast RMS½ calculation, one cycle RMS updated every half */

#define	ADE9039_REG_BVRMSONE 0x23A /* Phase B voltage fast RMS½ calculation, one cycle RMS updated every half */

#define	ADE9039_REG_BMTREGION 0x23D /* If multipoint gain and phase compensation is enabled, with MTEN = 1 in the this register indicates which BIGAINx and BPHCALx is used. */

#define	ADE9039_REG_BFPF 0x23E /* Phase B fundamental power factor, updated every 1.024 sec. */

#define	ADE9039_REG_BQUADINFO 0x23F /* Phase B power quadrant measurement information. */

#define	ADE9039_REG_CI_PCF 0x24A /* Instantaneous Phase C current channel waveform processed by the DSP at */

#define	ADE9039_REG_CV_PCF 0x24B /* Instantaneous Phase C voltage channel waveform processed by the DSP at */

#define	ADE9039_REG_CIRMS 0x24C /* Phase C filter-based current RMS value, updated at 4 kSPS. */

#define	ADE9039_REG_CVRMS 0x24D /* Phase C filter-based voltage RMS value, updated at 4 kSPS. */

#define	ADE9039_REG_CIFRMS 0x24E /* Phase C current fundamental RMS, updated at 4 kSPS. */

#define	ADE9039_REG_CVFRMS 0x24F /* Phase C voltage fundamental RMS, updated at 4 kSPS. */

#define	ADE9039_REG_CWATT 0x250 /* Phase C low-pass filtered total active power, updated at 4 kSPS. */

#define	ADE9039_REG_CVA 0x252 /* Phase C total apparent power, updated at 4 kSPS. */

#define	ADE9039_REG_CFWATT 0x253 /* Phase C fundamental active power, updated at 4 kSPS. */

#define	ADE9039_REG_CFVAR 0x254 /* Phase C fundamental reactive power, updated at 4 kSPS. */

#define	ADE9039_REG_CFVA 0x255 /* Phase C fundamental apparent power, updated at 4 kSPS. */

#define	ADE9039_REG_CPF 0x256 /* Phase C total power factor, updated every 1.024 sec. */

#define	ADE9039_REG_CVTHD 0x257 /* Phase C voltage THD, updated every 1.024 sec. */

#define	ADE9039_REG_CITHD 0x258 /* Phase C current total THD, updated every 1.024 sec. */

#define	ADE9039_REG_CIRMSONE 0x259 /* Phase C current fast RMS½ calculation, one cycle RMS updated every half */

#define	ADE9039_REG_CVRMSONE 0x25A /* Phase C voltage fast RMS½ calculation, one cycle RMS updated every half */

#define	ADE9039_REG_CMTREGION 0x25D /* If multipoint gain and phase compensation is enabled, with MTEN = 1 in register, these bits indicate which CIGAINx and CPHCALx is used. */

#define	ADE9039_REG_CFPF 0x25E /* Phase C fundamental power factor, updated every 1.024 sec. */

#define	ADE9039_REG_CQUADINFO 0x25F /* Phase C quadrant measurement information. */

#define	ADE9039_REG_NI_PCF 0x265 /* Instantaneous neutral current channel waveform processed by the DSP at 4 */

#define	ADE9039_REG_NIRMS 0x266 /* Neutral current filter-based RMS value. */

#define	ADE9039_REG_NIRMSONE 0x267 /* Neutral current fast RMS½ calculation, one cycle RMS updated every half */

#define	ADE9039_REG_ISUMRMS 0x269 /* Filter-based RMS based on the sum of IA + IB + IC ± IN. */

#define	ADE9039_REG_VERSION2 0x26A /* This register indicates the version of the metrology algorithms after the user = 1 to start the measurements. */

#define	ADE9039_REG_RESAMPLE_RESET_A 0x26B /* the waveform buffer when WF_CAP_EN bit is reset or disabled. */

#define	ADE9039_REG_RESAMPLE_LAST_CY 0x26C /* cycle index. A value between 0 to 7. This register contains the the last cycle resampled. */

#define	ADE9039_REG_TWATTHR 0x26D /* The sum of the total active energy of Phase A, Phase B, and Phase C when bits are enabled in the CONFIG0. */

#define	ADE9039_REG_TFVARHR 0x26E /* The sum of the fundamental reactive energy of Phase A, Phase B, and when the related bits are enabled in the CONFIG0. */

#define	ADE9039_REG_AWATT_ACC 0x2E5 /* Phase A accumulated total active power, updated after PWR_TIME 4 kSPS */

#define	ADE9039_REG_AWATTHR_LO 0x2E6 /* Phase A accumulated total active energy, LSB. Updated according to the the EP_CFG and EGY_TIME registers. */

#define	ADE9039_REG_AWATTHR_HI 0x2E7 /* Phase A accumulated total active energy, MSB. Updated according to the the EP_CFG and EGY_TIME registers. */

#define	ADE9039_REG_AVA_ACC 0x2F9 /* Phase A accumulated total apparent power, updated after PWR_TIME 4 */

#define	ADE9039_REG_AVAHR_LO 0x2FA /* Phase A accumulated total apparent energy, LSB. Updated according to the the EP_CFG and EGY_TIME registers. */

#define	ADE9039_REG_AVAHR_HI 0x2FB /* Phase A accumulated total apparent energy, LSB. Updated according to the the EP_CFG and EGY_TIME registers. */

#define	ADE9039_REG_AFWATT_ACC 0x303 /* Phase A accumulated fundamental active power, updated after PWR_TIME 4 */

#define	ADE9039_REG_AFWATTHR_LO 0x304 /* Phase A accumulated fundamental active energy, LSB. Updated according to in the EP_CFG and EGY_TIME registers. */

#define	ADE9039_REG_AFWATTHR_HI 0x305 /* Phase A accumulated fundamental active energy, MSB. Updated according settings in the EP_CFG and EGY_TIME registers. */

#define	ADE9039_REG_AFVAR_ACC 0x30D /* Phase A accumulated fundamental reactive power, updated after kSPS samples. */

#define	ADE9039_REG_AFVARHR_LO 0x30E /* Phase A accumulated fundamental reactive energy, LSB. Updated according settings in the EP_CFG and EGY_TIME registers. */

#define	ADE9039_REG_AFVARHR_HI 0x30F /* Phase A accumulated fundamental reactive energy, MSB. Updated the settings in the EP_CFG and EGY_TIME registers. */

#define	ADE9039_REG_AFVA_ACC 0x317 /* Phase A accumulated fundamental apparent power, updated after kSPS samples. */

#define	ADE9039_REG_AFVAHR_LO 0x318 /* Phase A accumulated fundamental apparent energy, LSB. Updated the settings in the EP_CFG and EGY_TIME registers. */

#define	ADE9039_REG_AFVAHR_HI 0x319 /* Phase A accumulated fundamental apparent energy, MSB. Updated the settings in the EP_CFG and EGY_TIME registers. */

#define	ADE9039_REG_BWATT_ACC 0x321 /* Phase B accumulated total active power, updated after PWR_TIME 4 kSPS */

#define	ADE9039_REG_BWATTHR_LO 0x322 /* Phase B accumulated total active energy, LSB. Updated according to the the EP_CFG and EGY_TIME registers. */

#define	ADE9039_REG_BWATTHR_HI 0x323 /* Phase B accumulated total active energy, MSB. Updated according to the the EP_CFG and EGY_TIME registers. */

#define	ADE9039_REG_BVA_ACC 0x335 /* Phase B accumulated total apparent power, updated after PWR_TIME 4 */

#define	ADE9039_REG_BVAHR_LO 0x336 /* Phase B accumulated total apparent energy, LSB. Updated according to the the EP_CFG and EGY_TIME registers. */

#define	ADE9039_REG_BVAHR_HI 0x337 /* Phase B accumulated total apparent energy, MSB. Updated according to the the EP_CFG and EGY_TIME registers. */

#define	ADE9039_REG_BFWATT_ACC 0x33F /* Phase B accumulated fundamental active power, updated after PWR_TIME 4 */

#define	ADE9039_REG_BFWATTHR_LO 0x340 /* Phase B accumulated fundamental active energy, LSB. Updated according to in the EP_CFG and EGY_TIME registers. */

#define	ADE9039_REG_BFWATTHR_HI 0x341 /* Phase B accumulated fundamental active energy, MSB. Updated according settings in EP_CFG and EGY_TIME registers. */

#define	ADE9039_REG_BFVAR_ACC 0x349 /* Phase B accumulated fundamental reactive power, updated after kSPS samples. */

#define	ADE9039_REG_BFVARHR_LO 0x34A /* Phase B accumulated fundamental reactive energy, LSB. Updated according settings in the EP_CFG and EGY_TIME registers. */

#define	ADE9039_REG_BFVARHR_HI 0x34B /* Phase B accumulated fundamental reactive energy, MSB. Updated the settings in the EP_CFG and EGY_TIME registers. */

#define	ADE9039_REG_BFVA_ACC 0x353 /* Phase B accumulated fundamental apparent power, updated after kSPS samples. */

#define	ADE9039_REG_BFVAHR_LO 0x354 /* Phase B accumulated fundamental apparent energy, LSB. Updated the settings in the EP_CFG and EGY_TIME registers. */

#define	ADE9039_REG_BFVAHR_HI 0x355 /* Phase B accumulated fundamental apparent energy, MSB. Updated the settings in the EP_CFG and EGY_TIME registers. */

#define	ADE9039_REG_CWATT_ACC 0x35D /* Phase C accumulated total active power, updated after PWR_TIME 4 kSPS */

#define	ADE9039_REG_CWATTHR_LO 0x35E /* Phase C accumulated total active energy, LSB. Updated according to the the EP_CFG and EGY_TIME registers. */

#define	ADE9039_REG_CWATTHR_HI 0x35F /* Phase C accumulated total active energy, MSB. Updated according to the the EP_CFG and EGY_TIME registers. */

#define	ADE9039_REG_CVA_ACC 0x371 /* Phase C accumulated total apparent power, updated after PWR_TIME 4 */

#define	ADE9039_REG_CVAHR_LO 0x372 /* Phase C accumulated total apparent energy, LSB. Updated according to the the EP_CFG and EGY_TIME registers. */

#define	ADE9039_REG_CVAHR_HI 0x373 /* Phase C accumulated total apparent energy, MSB. Updated according to the the EP_CFG and EGY_TIME registers. */

#define	ADE9039_REG_CFWATT_ACC 0x37B /* Phase C accumulated fundamental active power, updated after PWR_TIME samples. */

#define	ADE9039_REG_CFWATTHR_LO 0x37C /* Phase C accumulated fundamental active energy, LSB. Updated according settings in the EP_CFG and EGY_TIME registers. */

#define	ADE9039_REG_CFWATTHR_HI 0x37D /* Phase C accumulated fundamental active energy, MSB. Updated according settings in the EP_CFG and EGY_TIME registers. */

#define	ADE9039_REG_CFVAR_ACC 0x385 /* Phase C accumulated fundamental reactive power, updated after kSPS samples. */

#define	ADE9039_REG_CFVARHR_LO 0x386 /* Phase C accumulated fundamental reactive energy, LSB. Updated according settings in the EP_CFG and EGY_TIME registers. */

#define	ADE9039_REG_CFVARHR_HI 0x387 /* Phase C accumulated fundamental reactive energy, MSB. Updated the settings in the EP_CFG and EGY_TIME registers. */

#define	ADE9039_REG_CFVA_ACC 0x38F /* Phase C accumulated fundamental apparent power, updated after kSPS samples. */

#define	ADE9039_REG_CFVAHR_LO 0x390 /* Phase C accumulated fundamental apparent energy, LSB. Updated the settings in the EP_CFG and EGY_TIME registers. */

#define	ADE9039_REG_CFVAHR_HI 0x391 /* Phase C accumulated fundamental apparent energy, MSB. Updated the settings in the EP_CFG and EGY_TIME registers. */

#define	ADE9039_REG_PWATT_ACC 0x397 /* Accumulated positive total active power, MSB, from AWATT, BWATT, and updated after PWR_TIME 4 kSPS samples. */

#define	ADE9039_REG_NWATT_ACC 0x39B /* Accumulated Negative total active power, MSB, from AWATT, BWATT, and updated after PWR_TIME 4 kSPS samples. */

#define	ADE9039_REG_IPEAK 0x400 /* Current peak register. */

#define	ADE9039_REG_VPEAK 0x401 /* Voltage peak register. */

#define	ADE9039_REG_STATUS0 0x402 /* Status Register 0. */

#define	ADE9039_REG_STATUS1 0x403 /* Status Register 1. */

#define	ADE9039_REG_EVENT_STATUS 0x404 /* Event status register. */

#define	ADE9039_REG_MASK0 0x405 /* Interrupt Enable Register 0. */

#define	ADE9039_REG_MASK1 0x406 /* Interrupt Enable Register 1. */

#define	ADE9039_REG_EVENT_MASK 0x407 /* Event enable register. */

#define	ADE9039_REG_OILVL 0x409 /* Overcurrent detection threshold level. */

#define	ADE9039_REG_OIA

#define	ADE9039_REG_OIB

#define	ADE9039_REG_OIC

#define	ADE9039_REG_OIN

#define	ADE9039_REG_USER_PERIOD 0x40E /* User configured line period value used for resampling and fast RMS½ when bit in the CONFIG2 register is set. */

#define	ADE9039_REG_VLEVEL 0x40F /* Register used in the algorithm that computes the fundamental active, apparent powers as well as the fundamental IRMS and VRMS */

#define	ADE9039_REG_DIP_LVL 0x410 /* Voltage RMS½ dip detection threshold level. */

#define	ADE9039_REG_DIPA 0x411 /* Phase A voltage RMS½ value during a dip condition. */

#define	ADE9039_REG_DIPB 0x412 /* Phase B voltage RMS½ value during a dip condition. */

#define	ADE9039_REG_DIPC 0x413 /* Phase C voltage RMS½ value during a dip condition. */

#define	ADE9039_REG_SWELL_LVL 0x414 /* Voltage RMS½ swell detection threshold level. */

#define	ADE9039_REG_SWELLA 0x415 /* Phase A voltage RMS½ value during a swell condition. */

#define	ADE9039_REG_SWELLB 0x416 /* Phase B voltage RMS½ value during a swell condition. */

#define	ADE9039_REG_SWELLC 0x417 /* Phase C voltage RMS½ value during a swell condition. */

#define	ADE9039_REG_APERIOD 0x418 /* Line period on Phase A voltage. */

#define	ADE9039_REG_BPERIOD 0x419 /* Line period on Phase B voltage. */

#define	ADE9039_REG_CPERIOD 0x41A /* Line period on Phase C voltage. */

#define	ADE9039_REG_COM_PERIOD 0x41B /* Line period measurement on combined signal from Phase A, Phase B, and voltages. */

#define	ADE9039_REG_ACT_NL_LVL 0x41C /* No load threshold in the total and fundamental active power datapath. */

#define	ADE9039_REG_REACT_NL_LVL 0x41D /* No load threshold in the fundamental reactive power datapath. */

#define	ADE9039_REG_APP_NL_LVL 0x41E /* No load threshold in the total and fundamental apparent power datapath. */

#define	ADE9039_REG_PHNOLOAD 0x41F /* Phase no load register. */

#define	ADE9039_REG_WTHR

#define	ADE9039_REG_FVARTHR

#define	ADE9039_REG_VATHR

#define	ADE9039_REG_LAST_DATA_32 0x423 /* This register holds the data read or written during the last 32-bit transaction SPI port. */

#define	ADE9039_REG_ADC_REDIRECT 0x424 /* This register allows any ADC output to be redirected to any digital datapath. */

#define	ADE9039_REG_CF_LCFG 0x425 /* CFx calibration pulse width configuration register. */

#define	ADE9039_REG_PART_ID 0x472 /* This register identifies the IC. If the ADE9039_ID bit = 1, after the run bit has the IC is the ADE9039. */

#define	ADE9039_REG_TEMP_TRIM 0x474 /* Temperature sensor gain and offset, calculated during the manufacturing */

#define	ADE9039_REG_RUN 0x480 /* This is the DSP run register. Write 0x1 to this register to start measurements. */

#define	ADE9039_REG_CONFIG1 0x481 /* Configuration Register 1. */

#define	ADE9039_REG_ANGL_VA_VB 0x482 /* Time between positive to negative zero crossings on Phase A and Phase B */

#define	ADE9039_REG_ANGL_VB_VC 0x483 /* Time between positive to negative zero crossings on Phase B and Phase C */

#define	ADE9039_REG_ANGL_VA_VC 0x484 /* Time between positive to negative zero crossings on Phase A and Phase C */

#define	ADE9039_REG_ANGL_VA_IA 0x485 /* Time between positive to negative zero crossings on Phase A voltage and */

#define	ADE9039_REG_ANGL_VB_IB 0x486 /* Time between positive to negative zero crossings on Phase B voltage and */

#define	ADE9039_REG_ANGL_VC_IC 0x487 /* Time between positive to negative zero crossings on Phase C voltage and */

#define	ADE9039_REG_ANGL_IA_IB 0x488 /* Time between positive to negative zero crossings on Phase A and Phase B */

#define	ADE9039_REG_ANGL_IB_IC 0x489 /* Time between positive to negative zero crossings on Phase B and Phase C */

#define	ADE9039_REG_ANGL_IA_IC 0x48A /* Time between positive to negative zero crossings on Phase A and Phase C */

#define	ADE9039_REG_DIP_CYC 0x48B /* Voltage RMS½ dip detection cycle configuration. */

#define	ADE9039_REG_SWELL_CYC 0x48C /* Voltage RMS½ swell detection cycle configuration. */

#define	ADE9039_REG_OISTATUS 0x48F /* Overcurrent status register. */

#define	ADE9039_REG_CFMODE 0x490 /* CFx configuration register. */

#define	ADE9039_REG_COMPMODE 0x491 /* Computation mode register. */

#define	ADE9039_REG_ACCMODE 0x492 /* Accumulation mode register. */

#define	ADE9039_REG_CONFIG3 0x493 /* Configuration Register 3. */

#define	ADE9039_REG_CF1DEN 0x494 /* CF1 denominator register. */

#define	ADE9039_REG_CF2DEN 0x495 /* CF2 denominator register. */

#define	ADE9039_REG_CF3DEN 0x496 /* CF3 denominator register. */

#define	ADE9039_REG_CF4DEN 0x497 /* CF4 denominator register. */

#define	ADE9039_REG_ZXTOUT 0x498 /* Zero-crossing timeout configuration register. */

#define	ADE9039_REG_ZXTHRSH 0x499 /* Voltage channel zero-crossing threshold register. */

#define	ADE9039_REG_ZX_LP_SEL 0x49A /* This register selects which zero crossing and which line period measurement for other calculations. */

#define	ADE9039_REG_SEQ_CYC 0x49C /* Number of line cycles used for phase sequence detection. It is recommended this register to 1. */

#define	ADE9039_REG_PHSIGN 0x49D /* Power sign register. */

#define	ADE9039_REG_WFB_CFG 0x4A0 /* Waveform buffer configuration register. */

#define	ADE9039_REG_WFB_PG_IRQEN 0x4A1 /* This register enables interrupts to occur after specific pages of the waveform filled. */

#define	ADE9039_REG_WFB_TRG_CFG 0x4A2 /* This register enables events to trigger a capture in the waveform buffer. */

#define	ADE9039_REG_WFB_TRG_STAT 0x4A3 /* This register indicates the last page that was filled in the waveform buffer and of trigger events. */

#define	ADE9039_REG_CONFIG5 0x4A4 /* Configuration Register 5. */

#define	ADE9039_REG_CRC_RSLT 0x4A8 /* This register holds the CRC of the configuration registers. */

#define	ADE9039_REG_CRC_SPI 0x4A9 /* This register holds the 16-bit CRC of the data sent out on the MOSI pin last SPI register read. */

#define	ADE9039_REG_LAST_DATA_16 0x4AC /* This register holds the data read or written during the last 16-bit transaction SPI port. */

#define	ADE9039_REG_LAST_CMD 0x4AE /* This register holds the address and read/write operation request the last transaction on the SPI port. */

#define	ADE9039_REG_CONFIG2 0x4AF /* Configuration Register 2. */

#define	ADE9039_REG_EP_CFG 0x4B0 /* Energy and power accumulation configuration. */

#define	ADE9039_REG_PWR_TIME 0x4B1 /* Power update time configuration. */

#define	ADE9039_REG_EGY_TIME 0x4B2 /* Energy accumulation update time configuration. */

#define	ADE9039_REG_CRC_FORCE 0x4B4 /* This register forces an update of the CRC of configuration registers. */

#define	ADE9039_REG_CRC_OPTEN 0x4B5 /* This register selects which registers are optionally included in the CRC feature. */

#define	ADE9039_REG_TEMP_CFG 0x4B6 /* Temperature sensor configuration register. */

#define	ADE9039_REG_TEMP_RSLT 0x4B7 /* Temperature measurement result. */

#define	ADE9039_REG_PGA_GAIN 0x4B9 /* This register configures the PGA gain for each ADC. */

#define	ADE9039_REG_CHNL_DIS 0x4BA /* ADC channel enable/disable. */

#define	ADE9039_REG_WR_LOCK 0x4BF /* This register enables the configuration lock feature. */

#define	ADE9039_REG_VERSION 0x4FE /* This is the chip version of the ADE9039 IC. */

#define	ADE9039_REG_AI_SINC_DAT 0x500 /* Current Channel A ADC waveforms from the sinc4 output at 16 kSPS. */

#define	ADE9039_REG_AV_SINC_DAT 0x501 /* Voltage Channel A ADC waveforms from the sinc4 output at 16 kSPS. */

#define	ADE9039_REG_BI_SINC_DAT 0x502 /* Current Channel B ADC waveforms from the sinc4 output at 16 kSPS. */

#define	ADE9039_REG_BV_SINC_DAT 0x503 /* Voltage Channel B ADC waveforms from the sinc4 output at 16 kSPS. */

#define	ADE9039_REG_CI_SINC_DAT 0x504 /* Current Channel C ADC waveforms from the sinc4 output at 16 kSPS. */

#define	ADE9039_REG_CV_SINC_DAT 0x505 /* Voltage Channel C ADC waveforms from the sinc4 output at 16 kSPS. */

#define	ADE9039_REG_NI_SINC_DAT 0x506 /* Neutral current channel ADC waveforms from the sinc4 output at 16 kSPS. */

#define	ADE9039_REG_AI_LPF_DAT 0x510 /* Current Channel A ADC waveforms from the sinc4 + IIR LPF output at 4 */

#define	ADE9039_REG_AV_LPF_DAT 0x511 /* Voltage Channel A ADC waveforms from the sinc4 + IIR LPF output at 4 */

#define	ADE9039_REG_BI_LPF_DAT 0x512 /* Current Channel B ADC waveforms from the sinc4 + IIR LPF output at 4 */

#define	ADE9039_REG_BV_LPF_DAT 0x513 /* Voltage Channel B ADC waveforms from the sinc4 + IIR LPF output at 4 */

#define	ADE9039_REG_CI_LPF_DAT 0x514 /* Current Channel C ADC waveforms from the sinc4 + IIR LPF output at 4 */

#define	ADE9039_REG_CV_LPF_DAT 0x515 /* Voltage Channel C ADC waveforms from the sinc4 + IIR LPF output at 4 */

#define	ADE9039_REG_NI_LPF_DAT 0x516 /* Neutral current channel ADC waveforms from the sinc4 + IIR LPF output at 4 */

#define	ADE9039_REG_AV_PCF_1 0x600 /* SPI burst read accessible. Registers organized functionally. See AV_PCF. */

#define	ADE9039_REG_BV_PCF_1 0x601 /* SPI burst read accessible. Registers organized functionally. See BV_PCF. */

#define	ADE9039_REG_CV_PCF_1 0x602 /* SPI burst read accessible. Registers organized functionally. See CV_PCF. */

#define	ADE9039_REG_NI_PCF_1 0x603 /* SPI burst read accessible. Registers organized functionally. See NI_PCF. */

#define	ADE9039_REG_AI_PCF_1 0x604 /* SPI burst read accessible. Registers organized functionally. See AI_PCF. */

#define	ADE9039_REG_BI_PCF_1 0x605 /* SPI burst read accessible. Registers organized functionally. See BI_PCF. */

#define	ADE9039_REG_CI_PCF_1 0x606 /* SPI burst read accessible. Registers organized functionally. See CI_PCF. */

#define	ADE9039_REG_AIRMS_1 0x607 /* SPI burst read accessible. Registers organized functionally. See AIRMS. */

#define	ADE9039_REG_BIRMS_1 0x608 /* SPI burst read accessible. Registers organized functionally. See BIRMS. */

#define	ADE9039_REG_CIRMS_1 0x609 /* SPI burst read accessible. Registers organized functionally. See CIRMS. */

#define	ADE9039_REG_AVRMS_1 0x60A /* SPI burst read accessible. Registers organized functionally. See AVRMS. */

#define	ADE9039_REG_BVRMS_1 0x60B /* SPI burst read accessible. Registers organized functionally. See BVRMS. */

#define	ADE9039_REG_CVRMS_1 0x60C /* SPI burst read accessible. Registers organized functionally. See CVRMS. */

#define	ADE9039_REG_NIRMS_1 0x60D /* SPI burst read accessible. Registers organized functionally. See NIRMS. */

#define	ADE9039_REG_AWATT_1 0x60E /* SPI burst read accessible. Registers organized functionally. See AWATT. */

#define	ADE9039_REG_BWATT_1 0x60F /* SPI burst read accessible. Registers organized functionally. See BWATT. */

#define	ADE9039_REG_CWATT_1 0x610 /* SPI burst read accessible. Registers organized functionally. See CWATT. */

#define	ADE9039_REG_AVA_1 0x611 /* SPI burst read accessible. Registers organized functionally. See AVA. */

#define	ADE9039_REG_BVA_1 0x612 /* SPI burst read accessible. Registers organized functionally. See BVA. */

#define	ADE9039_REG_CVA_1 0x613 /* SPI burst read accessible. Registers organized functionally. See CVA. */

#define	ADE9039_REG_AFVAR_1 0x617 /* SPI burst read accessible. Registers organized functionally. See AFVAR. */

#define	ADE9039_REG_BFVAR_1 0x618 /* SPI burst read accessible. Registers organized functionally. See BFVAR. */

#define	ADE9039_REG_CFVAR_1 0x619 /* SPI burst read accessible. Registers organized functionally. See CFVAR. */

#define	ADE9039_REG_APF_1 0x61A /* SPI burst read accessible. Registers organized functionally. See APF. */

#define	ADE9039_REG_BPF_1 0x61B /* SPI burst read accessible. Registers organized functionally. See BPF. */

#define	ADE9039_REG_CPF_1 0x61C /* SPI burst read accessible. Registers organized functionally. See CPF. */

#define	ADE9039_REG_AVTHD_1 0x61D /* SPI burst read accessible. Registers organized functionally. See AVTHD. */

#define	ADE9039_REG_BVTHD_1 0x61E /* SPI burst read accessible. Registers organized functionally. See BVTHD. */

#define	ADE9039_REG_CVTHD_1 0x61F /* SPI burst read accessible. Registers organized functionally. See CVTHD. */

#define	ADE9039_REG_AITHD_1 0x620 /* SPI burst read accessible. Registers organized functionally. See AITHD. */

#define	ADE9039_REG_BITHD_1 0x621 /* SPI burst read accessible. Registers organized functionally. See BITHD. */

#define	ADE9039_REG_CITHD_1 0x622 /* SPI burst read accessible. Registers organized functionally. See CITHD. */

#define	ADE9039_REG_AFWATT_1 0x623 /* SPI burst read accessible. Registers organized functionally. See AFWATT. */

#define	ADE9039_REG_BFWATT_1 0x624 /* SPI burst read accessible. Registers organized functionally. See BFWATT. */

#define	ADE9039_REG_CFWATT_1 0x625 /* SPI burst read accessible. Registers organized functionally. See CFWATT. */

#define	ADE9039_REG_AFVA_1 0x626 /* SPI burst read accessible. Registers organized functionally. See AFVA. */

#define	ADE9039_REG_BFVA_1 0x627 /* SPI burst read accessible. Registers organized functionally. See BFVA. */

#define	ADE9039_REG_CFVA_1 0x628 /* SPI burst read accessible. Registers organized functionally. See CFVA. */

#define	ADE9039_REG_AFIRMS_1 0x629 /* SPI burst read accessible. Registers organized functionally. See AFIRMS. */

#define	ADE9039_REG_BFIRMS_1 0x62A /* SPI burst read accessible. Registers organized functionally. See BFIRMS. */

#define	ADE9039_REG_CFIRMS_1 0x62B /* SPI burst read accessible. Registers organized functionally. See CFIRMS. */

#define	ADE9039_REG_AFVRMS_1 0x62C /* SPI burst read accessible. Registers organized functionally. See AFVRMS. */

#define	ADE9039_REG_BFVRMS_1 0x62D /* SPI burst read accessible. Registers organized functionally. See BFVRMS. */

#define	ADE9039_REG_CFVRMS_1 0x62E /* SPI burst read accessible. Registers organized functionally. See CFVRMS. */

#define	ADE9039_REG_AIRMSONE_1 0x62F /* SPI burst read accessible. Registers organized functionally. See */

#define	ADE9039_REG_BIRMSONE_1 0x630 /* SPI burst read accessible. Registers organized functionally. See */

#define	ADE9039_REG_CIRMSONE_1 0x631 /* SPI burst read accessible. Registers organized functionally. See */

#define	ADE9039_REG_AVRMSONE_1 0x632 /* SPI burst read accessible. Registers organized functionally. See */

#define	ADE9039_REG_BVRMSONE_1 0x633 /* SPI burst read accessible. Registers organized functionally. See */

#define	ADE9039_REG_CVRMSONE_1 0x634 /* SPI burst read accessible. Registers organized functionally. See */

#define	ADE9039_REG_NIRMSONE_1 0x635 /* SPI burst read accessible. Registers organized functionally. See */

#define	ADE9039_REG_AV_PCF_2 0x680 /* SPI burst read accessible. Registers organized by phase. See AV_PCF. */

#define	ADE9039_REG_AI_PCF_2 0x681 /* SPI burst read accessible. Registers organized by phase. See AI_PCF. */

#define	ADE9039_REG_AIRMS_2 0x682 /* SPI burst read accessible. Registers organized by phase. See AIRMS. */

#define	ADE9039_REG_AVRMS_2 0x683 /* SPI burst read accessible. Registers organized by phase. See AVRMS. */

#define	ADE9039_REG_AWATT_2 0x684 /* SPI burst read accessible. Registers organized by phase. See AWATT. */

#define	ADE9039_REG_AVA_2 0x685 /* SPI burst read accessible. Registers organized by phase. See AVA. */

#define	ADE9039_REG_AFVAR_2 0x687 /* SPI burst read accessible. Registers organized by phase. See AFVAR. */

#define	ADE9039_REG_APF_2 0x688 /* SPI burst read accessible. Registers organized by phase. See APF. */

#define	ADE9039_REG_AVTHD_2 0x689 /* SPI burst read accessible. Registers organized by phase. See AVTHD. */

#define	ADE9039_REG_AITHD_2 0x68A /* SPI burst read accessible. Registers organized by phase. See AITHD. */

#define	ADE9039_REG_AFWATT_2 0x68B /* SPI burst read accessible. Registers organized by phase. See AFWATT. */

#define	ADE9039_REG_AFVA_2 0x68C /* SPI burst read accessible. Registers organized by phase. See AFVA. */

#define	ADE9039_REG_AFIRMS_2 0x68D /* SPI burst read accessible. Registers organized by phase. See AFIRMS. */

#define	ADE9039_REG_AFVRMS_2 0x68E /* SPI burst read accessible. Registers organized by phase. See AFVRMS. */

#define	ADE9039_REG_AIRMSONE_2 0x68F /* SPI burst read accessible. Registers organized by phase. See AIRMSONE. */

#define	ADE9039_REG_AVRMSONE_2 0x690 /* SPI burst read accessible. Registers organized by phase. See AVRMSONE. */

#define	ADE9039_REG_BV_PCF_2 0x693 /* SPI burst read accessible. Registers organized by phase. See BV_PCF. */

#define	ADE9039_REG_BI_PCF_2 0x694 /* SPI burst read accessible. Registers organized by phase. See BI_PCF. */

#define	ADE9039_REG_BIRMS_2 0x695 /* SPI burst read accessible. Registers organized by phase. See BIRMS. */

#define	ADE9039_REG_BVRMS_2 0x696 /* SPI burst read accessible. Registers organized by phase. See BVRMS. */

#define	ADE9039_REG_BWATT_2 0x697 /* SPI burst read accessible. Registers organized by phase. See BWATT. */

#define	ADE9039_REG_BVA_2 0x698 /* SPI burst read accessible. Registers organized by phase. See BVA. */

#define	ADE9039_REG_BFVAR_2 0x69A /* SPI burst read accessible. Registers organized by phase. See BFVAR. */

#define	ADE9039_REG_BPF_2 0x69B /* SPI burst read accessible. Registers organized by phase. See BPF. */

#define	ADE9039_REG_BVTHD_2 0x69C /* SPI burst read accessible. Registers organized by phase. See BVTHD. */

#define	ADE9039_REG_BITHD_2 0x69D /* SPI burst read accessible. Registers organized by phase. See BITHD. */

#define	ADE9039_REG_BFWATT_2 0x69E /* SPI burst read accessible. Registers organized by phase. See BFWATT. */

#define	ADE9039_REG_BFVA_2 0x69F /* SPI burst read accessible. Registers organized by phase. See BFVA. */

#define	ADE9039_REG_BFIRMS_2 0x6A0 /* SPI burst read accessible. Registers organized by phase. See BFIRMS. */

#define	ADE9039_REG_BFVRMS_2 0x6A1 /* SPI burst read accessible. Registers organized by phase. See BFVRMS. */

#define	ADE9039_REG_BIRMSONE_2 0x6A2 /* SPI burst read accessible. Registers organized by phase. See BIRMSONE. */

#define	ADE9039_REG_BVRMSONE_2 0x6A3 /* SPI burst read accessible. Registers organized by phase. See BVRMSONE. */

#define	ADE9039_REG_CV_PCF_2 0x6A6 /* SPI burst read accessible. Registers organized by phase. See CV_PCF. */

#define	ADE9039_REG_CI_PCF_2 0x6A7 /* SPI burst read accessible. Registers organized by phase. See CI_PCF. */

#define	ADE9039_REG_CIRMS_2 0x6A8 /* SPI burst read accessible. Registers organized by phase. See CIRMS. */

#define	ADE9039_REG_CVRMS_2 0x6A9 /* SPI burst read accessible. Registers organized by phase. See CVRMS. */

#define	ADE9039_REG_CWATT_2 0x6AA /* SPI burst read accessible. Registers organized by phase. See CWATT. */

#define	ADE9039_REG_CVA_2 0x6AB /* SPI burst read accessible. Registers organized by phase. See CVA. */

#define	ADE9039_REG_CFVAR_2 0x6AD /* SPI burst read accessible. Registers organized by phase. See CFVAR. */

#define	ADE9039_REG_CPF_2 0x6AE /* SPI burst read accessible. Registers organized by phase. See CPF. */

#define	ADE9039_REG_CVTHD_2 0x6AF /* SPI burst read accessible. Registers organized by phase. See CVTHD. */

#define	ADE9039_REG_CITHD_2 0x6B0 /* SPI burst read accessible. Registers organized by phase. See CITHD. */

#define	ADE9039_REG_CFWATT_2 0x6B1 /* SPI burst read accessible. Registers organized by phase. See CFWATT. */

#define	ADE9039_REG_CFVA_2 0x6B2 /* SPI burst read accessible. Registers organized by phase. See CFVA. */

#define	ADE9039_REG_CFIRMS_2 0x6B3 /* SPI burst read accessible. Registers organized by phase. See CFIRMS. */

#define	ADE9039_REG_CFVRMS_2 0x6B4 /* SPI burst read accessible. Registers organized by phase. See CFVRMS. */

#define	ADE9039_REG_CIRMSONE_2 0x6B5 /* SPI burst read accessible. Registers organized by phase. See CIRMSONE. */

#define	ADE9039_REG_CVRMSONE_2 0x6B6 /* SPI burst read accessible. Registers organized by phase. See CVRMSONE. */

#define	ADE9039_REG_NI_PCF_2 0x6B9 /* SPI burst read accessible. Registers organized by phase. See NI_PCF. */

#define	ADE9039_REG_NIRMS_2 0x6BA /* SPI burst read accessible. Registers organized by phase. See NIRMS. */

#define	ADE9039_REG_NIRMSONE_2 0x6BB /* SPI burst read accessible. Registers organized by phase. See NIRMSONE. */

#define	ADE9039_C_TFVARHR_EN NO_OS_BIT(19)

#define	ADE9039_B_TFVARHR_EN NO_OS_BIT(18)

#define	ADE9039_A_TFVARHR_EN NO_OS_BIT(17)

#define	ADE9039_C_TWATTHR_EN NO_OS_BIT(16)

#define	ADE9039_B_TWATTHR_EN NO_OS_BIT(15)

#define	ADE9039_A_TWATTHR_EN NO_OS_BIT(14)

#define	ADE9039_DISAPLPF NO_OS_BIT(12)

#define	ADE9039_ININTEN NO_OS_BIT(11)

#define	ADE9039_VNOMC_EN NO_OS_BIT(10)

#define	ADE9039_VNOMB_EN NO_OS_BIT(9)

#define	ADE9039_VNOMA_EN NO_OS_BIT(8)

#define	ADE9039_RMS_SRC_SEL NO_OS_BIT(7)

#define	ADE9039_ZX_SRC_SEL NO_OS_BIT(6)

#define	ADE9039_INTEN NO_OS_BIT(5)

#define	ADE9039_MTEN NO_OS_BIT(4)

#define	ADE9039_HPFDIS NO_OS_BIT(3)

#define	ADE9039_ISUM_CFG NO_OS_GENMASK(1, 0)

#define	ADE9039_AREGION NO_OS_GENMASK(3, 0)

#define	ADE9039_BREGION NO_OS_GENMASK(3, 0)

#define	ADE9039_CREGION NO_OS_GENMASK(3, 0)

#define	ADE9039_IPPHASE NO_OS_GENMASK(26, 24)

#define	ADE9039_IPEAKVAL NO_OS_GENMASK(23, 0)

#define	ADE9039_VPPHASE NO_OS_GENMASK(26, 24)

#define	ADE9039_VPEAKVAL NO_OS_GENMASK(23, 0)

#define	ADE9039_STATUS0_TEMP_RDY NO_OS_BIT(25)

#define	ADE9039_STATUS0_MISMTCH NO_OS_BIT(24)

#define	ADE9039_STATUS0_COH_CYCLE_DONE NO_OS_BIT(23)

#define	ADE9039_STATUS0_WFB_TRIG NO_OS_BIT(22)

#define	ADE9039_STATUS0_THD_PF_RDY NO_OS_BIT(21)

#define	ADE9039_STATUS0_RMSONEREDY NO_OS_BIT(19)

#define	ADE9039_STATUS0_PWRRDY NO_OS_BIT(18)

#define	ADE9039_STATUS0_PAGE_FULL NO_OS_BIT(17)

#define	ADE9039_STATUS0_WFB_TRIG_IRQ NO_OS_BIT(16)

#define	ADE9039_STATUS0_DREADY NO_OS_BIT(15)

#define	ADE9039_STATUS0_CF4 NO_OS_BIT(14)

#define	ADE9039_STATUS0_CF3 NO_OS_BIT(13)

#define	ADE9039_STATUS0_CF2 NO_OS_BIT(12)

#define	ADE9039_STATUS0_CF1 NO_OS_BIT(11)

#define	ADE9039_STATUS0_REVPSUM4 NO_OS_BIT(10)

#define	ADE9039_STATUS0_REVPSUM3 NO_OS_BIT(9)

#define	ADE9039_STATUS0_REVPSUM2 NO_OS_BIT(8)

#define	ADE9039_STATUS0_REVPSUM1 NO_OS_BIT(7)

#define	ADE9039_STATUS0_REVRPC NO_OS_BIT(6)

#define	ADE9039_STATUS0_REVRPB NO_OS_BIT(5)

#define	ADE9039_STATUS0_REVRPA NO_OS_BIT(4)

#define	ADE9039_STATUS0_REVAPC NO_OS_BIT(3)

#define	ADE9039_STATUS0_REVAPB NO_OS_BIT(2)

#define	ADE9039_STATUS0_REVAPA NO_OS_BIT(1)

#define	ADE9039_STATUS0_EGYRDY NO_OS_BIT(0)

#define	ADE9039_STATUS1_ERROR3 NO_OS_BIT(31)

#define	ADE9039_STATUS1_ERROR2 NO_OS_BIT(30)

#define	ADE9039_STATUS1_ERROR1 NO_OS_BIT(29)

#define	ADE9039_STATUS1_ERROR0 NO_OS_BIT(28)

#define	ADE9039_STATUS1_CRC_DONE NO_OS_BIT(27)

#define	ADE9039_STATUS1_CRC_CHG NO_OS_BIT(26)

#define	ADE9039_STATUS1_DIPC NO_OS_BIT(25)

#define	ADE9039_STATUS1_DIPB NO_OS_BIT(24)

#define	ADE9039_STATUS1_DIPA NO_OS_BIT(23)

#define	ADE9039_STATUS1_SWELLC NO_OS_BIT(22)

#define	ADE9039_STATUS1_SWELLB NO_OS_BIT(21)

#define	ADE9039_STATUS1_SWELLA NO_OS_BIT(20)

#define	ADE9039_STATUS1_SEQERR NO_OS_BIT(18)

#define	ADE9039_STATUS1_OI NO_OS_BIT(17)

#define	ADE9039_STATUS1_RSTDONE NO_OS_BIT(16)

#define	ADE9039_STATUS1_ZXIC NO_OS_BIT(15)

#define	ADE9039_STATUS1_ZXIB NO_OS_BIT(14)

#define	ADE9039_STATUS1_ZXIA NO_OS_BIT(13)

#define	ADE9039_STATUS1_ZXCOMB NO_OS_BIT(12)

#define	ADE9039_STATUS1_ZXVC NO_OS_BIT(11)

#define	ADE9039_STATUS1_ZXVB NO_OS_BIT(10)

#define	ADE9039_STATUS1_ZXVA NO_OS_BIT(9)

#define	ADE9039_STATUS1_ZXTOVC NO_OS_BIT(8)

#define	ADE9039_STATUS1_ZXTOVB NO_OS_BIT(7)

#define	ADE9039_STATUS1_ZXTOVA NO_OS_BIT(6)

#define	ADE9039_STATUS1_VAFNOLOAD NO_OS_BIT(5)

#define	ADE9039_STATUS1_RFNOLOAD NO_OS_BIT(4)

#define	ADE9039_STATUS1_AFNOLOAD NO_OS_BIT(3)

#define	ADE9039_STATUS1_VANLOAD NO_OS_BIT(2)

#define	ADE9039_STATUS1_ANLOAD NO_OS_BIT(0)

#define	ADE9039_EVENT_DREADY NO_OS_BIT(16)

#define	ADE9039_EVENT_VAFNOLOAD NO_OS_BIT(15)

#define	ADE9039_EVENT_RFNOLOAD NO_OS_BIT(14)

#define	ADE9039_EVENT_AFNOLOAD NO_OS_BIT(13)

#define	ADE9039_EVENT_VANLOAD NO_OS_BIT(12)

#define	ADE9039_EVENT_RNLOAD NO_OS_BIT(11)

#define	ADE9039_EVENT_ANLOAD NO_OS_BIT(10)

#define	ADE9039_EVENT_REVPSUM4 NO_OS_BIT(9)

#define	ADE9039_EVENT_REVPSUM3 NO_OS_BIT(8)

#define	ADE9039_EVENT_REVPSUM2 NO_OS_BIT(7)

#define	ADE9039_EVENT_REVPSUM1 NO_OS_BIT(6)

#define	ADE9039_EVENT_SWELLC NO_OS_BIT(5)

#define	ADE9039_EVENT_SWELLB NO_OS_BIT(4)

#define	ADE9039_EVENT_SWELLA NO_OS_BIT(3)

#define	ADE9039_EVENT_DIPC NO_OS_BIT(2)

#define	ADE9039_EVENT_DIPB NO_OS_BIT(1)

#define	ADE9039_EVENT_DIPA NO_OS_BIT(0)

#define	ADE9039_MASK0_TEMP_RDY_MASK NO_OS_BIT(25)

#define	ADE9039_MASK0_MISMTCH NO_OS_BIT(24)

#define	ADE9039_MASK0_COH_WFB_FULL NO_OS_BIT(23)

#define	ADE9039_MASK0_WFB_TRIG NO_OS_BIT(22)

#define	ADE9039_MASK0_THD_PF_RDY NO_OS_BIT(21)

#define	ADE9039_MASK0_PWRRDY NO_OS_BIT(18)

#define	ADE9039_MASK0_PAGE_FULL NO_OS_BIT(17)

#define	ADE9039_MASK0_WFB_TRIG_IRQ NO_OS_BIT(16)

#define	ADE9039_MASK0_DREADY NO_OS_BIT(15)

#define	ADE9039_MASK0_CF4 NO_OS_BIT(14)

#define	ADE9039_MASK0_CF3 NO_OS_BIT(13)

#define	ADE9039_MASK0_CF2 NO_OS_BIT(12)

#define	ADE9039_MASK0_CF1 NO_OS_BIT(11)

#define	ADE9039_MASK0_REVPSUM4 NO_OS_BIT(10)

#define	ADE9039_MASK0_REVPSUM3 NO_OS_BIT(9)

#define	ADE9039_MASK0_REVPSUM2 NO_OS_BIT(8)

#define	ADE9039_MASK0_REVPSUM1 NO_OS_BIT(7)

#define	ADE9039_MASK0_REVRPC NO_OS_BIT(6)

#define	ADE9039_MASK0_REVRPB NO_OS_BIT(5)

#define	ADE9039_MASK0_REVRPA NO_OS_BIT(4)

#define	ADE9039_MASK0_REVAPC NO_OS_BIT(3)

#define	ADE9039_MASK0_REVAPB NO_OS_BIT(2)

#define	ADE9039_MASK0_REVAPA NO_OS_BIT(1)

#define	ADE9039_MASK0_EGYRDY NO_OS_BIT(0)

#define	ADE9039_MASK1_ERROR3 NO_OS_BIT(31)

#define	ADE9039_MASK1_ERROR2 NO_OS_BIT(30)

#define	ADE9039_MASK1_ERROR1 NO_OS_BIT(29)

#define	ADE9039_MASK1_ERROR0 NO_OS_BIT(28)

#define	ADE9039_MASK1_CRC_DONE NO_OS_BIT(27)

#define	ADE9039_MASK1_CRC_CHG NO_OS_BIT(26)

#define	ADE9039_MASK1_DIPC NO_OS_BIT(25)

#define	ADE9039_MASK1_DIPB NO_OS_BIT(24)

#define	ADE9039_MASK1_DIPA NO_OS_BIT(23)

#define	ADE9039_MASK1_SWELLC NO_OS_BIT(22)

#define	ADE9039_MASK1_SWELLB NO_OS_BIT(21)

#define	ADE9039_MASK1_SWELLA NO_OS_BIT(20)

#define	ADE9039_MASK1_SEQERR NO_OS_BIT(18)

#define	ADE9039_MASK1_OI NO_OS_BIT(17)

#define	ADE9039_MASK1_ZXIC NO_OS_BIT(15)

#define	ADE9039_MASK1_ZXIB NO_OS_BIT(14)

#define	ADE9039_MASK1_ZXIA NO_OS_BIT(13)

#define	ADE9039_MASK1_ZXCOMB NO_OS_BIT(12)

#define	ADE9039_MASK1_ZXVC NO_OS_BIT(11)

#define	ADE9039_MASK1_ZXVB NO_OS_BIT(10)

#define	ADE9039_MASK1_ZXVA NO_OS_BIT(9)

#define	ADE9039_MASK1_ZXTOVC NO_OS_BIT(8)

#define	ADE9039_MASK1_ZXTOVB NO_OS_BIT(7)

#define	ADE9039_MASK1_ZXTOVA NO_OS_BIT(6)

#define	ADE9039_MASK1_VAFNOLOAD NO_OS_BIT(5)

#define	ADE9039_MASK1_AFNOLOAD NO_OS_BIT(3)

#define	ADE9039_MASK1_VANLOAD NO_OS_BIT(2)

#define	ADE9039_MASK1_ANLOAD NO_OS_BIT(0)

#define	ADE9039_EVENT_DREADY_MSK NO_OS_BIT(16)

#define	ADE9039_EVENT_VAFNOLOAD_MSK NO_OS_BIT(15)

#define	ADE9039_EVENT_RFNOLOAD_MSK NO_OS_BIT(14)

#define	ADE9039_EVENT_AFNOLOAD_MSK NO_OS_BIT(13)

#define	ADE9039_EVENT_VANLOAD_MSK NO_OS_BIT(12)

#define	ADE9039_EVENT_ANLOAD_MSK NO_OS_BIT(10)

#define	ADE9039_EVENT_REVPSUM4_MSK NO_OS_BIT(9)

#define	ADE9039_EVENT_REVPSUM3_MSK NO_OS_BIT(8)

#define	ADE9039_EVENT_REVPSUM2_MSK NO_OS_BIT(7)

#define	ADE9039_EVENT_REVPSUM1_MSK NO_OS_BIT(6)

#define	ADE9039_EVENT_SWELLCEN_MSK NO_OS_BIT(5)

#define	ADE9039_EVENT_SWELLBEN_MSK NO_OS_BIT(4)

#define	ADE9039_EVENT_SWELLAEN_MSK NO_OS_BIT(3)

#define	ADE9039_EVENT_DIPCEN_MSK NO_OS_BIT(2)

#define	ADE9039_EVENT_DIPBEN_MSK NO_OS_BIT(1)

#define	ADE9039_EVENT_DIPAEN_MSK NO_OS_BIT(0)

#define	ADE9039_OILVL_VAL NO_OS_GENMASK(23, 0)

#define	ADE9039_OIA_VAL NO_OS_GENMASK(23, 0)

#define	ADE9039_OIB_VAL NO_OS_GENMASK(23, 0)

#define	ADE9039_OIC_VAL NO_OS_GENMASK(23, 0)

#define	ADE9039_OIN_VAL NO_OS_GENMASK(23, 0)

#define	ADE9039_VLEVEL_VAL NO_OS_GENMASK(23, 0)

#define	ADE9039_REG_DIPLVL NO_OS_GENMASK(23, 0)

#define	ADE9039_DIPA_VAL NO_OS_GENMASK(23, 0)

#define	ADE9039_DIPB_VAL NO_OS_GENMASK(23, 0)

#define	ADE9039_DIPC_VAL NO_OS_GENMASK(23, 0)

#define	ADE9039_SWELLLVL NO_OS_GENMASK(23, 0)

#define	ADE9039_SWELLA_VAL NO_OS_GENMASK(23, 0)

#define	ADE9039_SWELLB_VAL NO_OS_GENMASK(23, 0)

#define	ADE9039_SWELLC_VAL NO_OS_GENMASK(23, 0)

#define	ADE9039_CFVANL NO_OS_BIT(17)

#define	ADE9039_CFVARNL NO_OS_BIT(16)

#define	ADE9039_CFWATTNL NO_OS_BIT(15)

#define	ADE9039_CVANL NO_OS_BIT(14)

#define	ADE9039_CWATTNL NO_OS_BIT(12)

#define	ADE9039_BFVANL NO_OS_BIT(11)

#define	ADE9039_BFVARNL NO_OS_BIT(10)

#define	ADE9039_BFWATTNL NO_OS_BIT(9)

#define	ADE9039_BVANL NO_OS_BIT(8)

#define	ADE9039_BWATTNL NO_OS_BIT(6)

#define	ADE9039_AFVANL NO_OS_BIT(5)

#define	ADE9039_AFVARNL NO_OS_BIT(4)

#define	ADE9039_AVANL NO_OS_BIT(2)

#define	ADE9039_AWATTNL NO_OS_BIT(0)

#define	ADE9039_VC_DIN NO_OS_GENMASK(20, 18)

#define	ADE9039_VB_DIN NO_OS_GENMASK(17, 15)

#define	ADE9039_VA_DIN NO_OS_GENMASK(14, 12)

#define	ADE9039_IN_DIN NO_OS_GENMASK(11, 9)

#define	ADE9039_IC_DIN NO_OS_GENMASK(8, 6)

#define	ADE9039_IB_DIN NO_OS_GENMASK(5, 3)

#define	ADE9039_IA_DIN NO_OS_GENMASK(2, 0)

#define	ADE9039_CF4_LT NO_OS_BIT(22)

#define	ADE9039_CF3_LT NO_OS_BIT(21)

#define	ADE9039_CF2_LT NO_OS_BIT(20)

#define	ADE9039_CF1_LT NO_OS_BIT(19)

#define	ADE9039_CF_LTMR NO_OS_GENMASK(18, 0)

#define	ADE9039_ADE9039_ID NO_OS_BIT(20)

#define	ADE9039_TEMP_OFFSET NO_OS_GENMASK(31, 16)

#define	ADE9039_TEMP_GAIN NO_OS_GENMASK(15, 0)

#define	ADE9039_EXT_REF NO_OS_BIT(15)

#define	ADE9039_IRQ0_ON_IRQ1 NO_OS_BIT(12)

#define	ADE9039_BURST_EN NO_OS_BIT(11)

#define	ADE9039_DIP_SWELL_IRQ_MODE NO_OS_BIT(10)

#define	ADE9039_PWR_SETTLE NO_OS_GENMASK(9, 8)

#define	ADE9039_CF_ACC_CLR NO_OS_BIT(5)

#define	ADE9039_CF4_CFG NO_OS_GENMASK(3, 2)

#define	ADE9039_CF3_CFG NO_OS_BIT(1)

#define	ADE9039_SWRST NO_OS_BIT(0)

#define	ADE9039_OIPHASE NO_OS_GENMASK(3, 0)

#define	ADE9039_CF4DIS NO_OS_BIT(15)

#define	ADE9039_CF3DIS NO_OS_BIT(14)

#define	ADE9039_CF2DIS NO_OS_BIT(13)

#define	ADE9039_CF1DIS NO_OS_BIT(12)

#define	ADE9039_CF4SEL NO_OS_GENMASK(11, 9)

#define	ADE9039_CF3SEL NO_OS_GENMASK(8, 6)

#define	ADE9039_CF2SEL NO_OS_GENMASK(5, 3)

#define	ADE9039_CF1SEL NO_OS_GENMASK(2, 0)

#define	ADE9039_TERMSEL4 NO_OS_GENMASK(11, 9)

#define	ADE9039_TERMSEL3 NO_OS_GENMASK(8, 6)

#define	ADE9039_TERMSEL2 NO_OS_GENMASK(5, 3)

#define	ADE9039_TERMSEL1 NO_OS_GENMASK(2, 0)

#define	ADE9039_SELFREQ NO_OS_BIT(8)

#define	ADE9039_ICONSEL NO_OS_BIT(7)

#define	ADE9039_VCONSEL NO_OS_GENMASK(6, 4)

#define	ADE9039_VARACC NO_OS_GENMASK(3, 2)

#define	ADE9039_WATTACC NO_OS_GENMASK(1, 0)

#define	ADE9039_OC_EN NO_OS_GENMASK(15, 12)

#define	ADE9039_PEAKSEL NO_OS_GENMASK(4, 2)

#define	ADE9039_LP_SEL NO_OS_GENMASK(4, 3)

#define	ADE9039_ZX_SEL NO_OS_GENMASK(2, 1)

#define	ADE9039_SUM4SIGN NO_OS_BIT(9)

#define	ADE9039_SUM3SIGN NO_OS_BIT(8)

#define	ADE9039_SUM2SIGN NO_OS_BIT(7)

#define	ADE9039_SUM1SIGN NO_OS_BIT(6)

#define	ADE9039_CVARSIGN NO_OS_BIT(5)

#define	ADE9039_CWSIGN NO_OS_BIT(4)

#define	ADE9039_BVARSIGN NO_OS_BIT(3)

#define	ADE9039_BWSIGN NO_OS_BIT(2)

#define	ADE9039_AVARSIGN NO_OS_BIT(1)

#define	ADE9039_AWSIGN NO_OS_BIT(0)

#define	ADE9039_WF_IN_EN NO_OS_BIT(12)

#define	ADE9039_WF_SRC NO_OS_GENMASK(9, 8)

#define	ADE9039_WF_MODE NO_OS_GENMASK(7, 6)

#define	ADE9039_WF_CAP_SEL NO_OS_BIT(5)

#define	ADE9039_WF_CAP_EN NO_OS_BIT(4)

#define	ADE9039_BURST_CHAN NO_OS_GENMASK(3, 0)

#define	ADE9039_TRIG_FORCE NO_OS_BIT(10)

#define	ADE9039_ZXCOMB NO_OS_BIT(9)

#define	ADE9039_ZXVC NO_OS_BIT(8)

#define	ADE9039_ZXVB NO_OS_BIT(7)

#define	ADE9039_ZXVA NO_OS_BIT(6)

#define	ADE9039_ZXIC NO_OS_BIT(5)

#define	ADE9039_ZXIB NO_OS_BIT(4)

#define	ADE9039_ZXIA NO_OS_BIT(3)

#define	ADE9039_OI NO_OS_BIT(2)

#define	ADE9039_SWELL NO_OS_BIT(1)

#define	ADE9039_DIP NO_OS_BIT(0)

#define	ADE9039_WFB_LAST_PAGE NO_OS_GENMASK(15, 12)

#define	ADE9039_WFB_TRIG_ADDR NO_OS_GENMASK(10, 0)

#define	ADE9039_UPERIOD_SEL NO_OS_BIT(12)

#define	ADE9039_HPF_CRN NO_OS_GENMASK(11, 9)

#define	ADE9039_NOLOAD_TMR NO_OS_GENMASK(15, 13)

#define	ADE9039_PWR_SIGN_SEL_1 NO_OS_BIT(7)

#define	ADE9039_PWR_SIGN_SEL_0 NO_OS_BIT(6)

#define	ADE9039_EGY_LD_ACCUM NO_OS_BIT(4)

#define	ADE9039_EGY_TMR_MODE NO_OS_BIT(1)

#define	ADE9039_EGY_PWR_EN NO_OS_BIT(0)

#define	ADE9039_FORCE_CRC_UPDATE NO_OS_BIT(0)

#define	ADE9039_CRC_WFB_TRG_CFG_EN NO_OS_BIT(15)

#define	ADE9039_CRC_WFB_PG_IRQEN NO_OS_BIT(14)

#define	ADE9039_CRC_WFB_CFG_EN NO_OS_BIT(13)

#define	ADE9039_CRC_SEQ_CYC_EN NO_OS_BIT(12)

#define	ADE9039_CRC_ZXLPSEL_EN NO_OS_BIT(11)

#define	ADE9039_CRC_ZXTOUT_EN NO_OS_BIT(10)

#define	ADE9039_CRC_APP_NL_LVL_EN NO_OS_BIT(9)

#define	ADE9039_CRC_REACT_NL_LVL_EN NO_OS_BIT(8)

#define	ADE9039_CRC_ACT_NL_LVL_EN NO_OS_BIT(7)

#define	ADE9039_CRC_SWELL_CYC_EN NO_OS_BIT(6)

#define	ADE9039_CRC_SWELL_LVL_EN NO_OS_BIT(5)

#define	ADE9039_CRC_DIP_CYC_EN NO_OS_BIT(4)

#define	ADE9039_CRC_DIP_LVL_EN NO_OS_BIT(3)

#define	ADE9039_CRC_EVENT_MASK_EN NO_OS_BIT(2)

#define	ADE9039_CRC_MASK1_EN NO_OS_BIT(1)

#define	ADE9039_CRC_MASK0_EN NO_OS_BIT(0)

#define	ADE9039_TEMP_START NO_OS_BIT(3)

#define	ADE9039_TEMP_EN NO_OS_BIT(2)

#define	ADE9039_TEMP_TIME NO_OS_GENMASK(1, 0)

#define	ADE9039_TEMP_RSLT NO_OS_GENMASK(11, 0)

#define	ADE9039_VC_GAIN NO_OS_GENMASK(13, 12)

#define	ADE9039_VB_GAIN NO_OS_GENMASK(11, 10)

#define	ADE9039_VA_GAIN NO_OS_GENMASK(9, 8)

#define	ADE9039_IN_GAIN NO_OS_GENMASK(7, 6)

#define	ADE9039_IC_GAIN NO_OS_GENMASK(5, 4)

#define	ADE9039_IB_GAIN NO_OS_GENMASK(3, 2)

#define	ADE9039_IA_GAIN NO_OS_GENMASK(1, 0)

#define	ADE9039_VC_DISADC NO_OS_BIT(6)

#define	ADE9039_VB_DISADC NO_OS_BIT(5)

#define	ADE9039_VA_DISADC NO_OS_BIT(4)

#define	ADE9039_IN_DISADC NO_OS_BIT(3)

#define	ADE9039_IC_DISADC NO_OS_BIT(2)

#define	ADE9039_IB_DISADC NO_OS_BIT(1)

#define	ADE9039_IA_DISADC NO_OS_BIT(0)

#define	ADE9039_CHIP_ID 0xFE

#define	ADE9039_PART_ID 1

#define	ADE9039_RESET_RECOVER 100

#define	ADE9039_PGA_GAIN 0x0000

#define	ADE9039_CONFIG0 0x00000000

#define	ADE9039_CONFIG1 0x0002

#define	ADE9039_CONFIG2 0x0A00

#define	ADE9039_CONFIG3 0x0000

#define	ADE9039_ACCMODE 0x0000

#define	ADE9039_ZX_LP_SEL 0x001E

#define	ADE9039_MASK0 0x00000001

#define	ADE9039_MASK1 0x00000000

#define	ADE9039_EVENT_MASK 0x00000000

#define	ADE9039_VLEVEL 0x00144084

#define	ADE9039_DICOEFF 0x00000000

#define	ADE9039_RUN_ON 0x0001

#define	ADE9039_COMPMODE 0x0007

#define	ADE9039_WFB_CFG 0x1000

#define	WFB_ELEMENT_ARRAY_SIZE 512

#define	ADE9039_RMS_FS_CODES 52866837

#define	ADE9039_WATT_FS_CODES 20823646

#define	ADE9039_BURDEN_RES 10

#define	ADE9039_CURRENT_TR_RATIO 1000

#define	ADE9039_CURRENT_TR_FCN (ADE9039_CURRENT_TR_RATIO / ADE9039_BURDEN_RES)

#define	ADE9039_UP_RES 990000

#define	ADE9039_DOWN_RES 1000

#define	ADE9039_VOLTAGE_TR_FCN ((ADE9039_DOWN_RES + ADE9039_UP_RES) / ADE9039_DOWN_RES)

#define	ADE9039_FS_VOLTAGE 707

Enumerations
enum	ade9039_isum_cfg_e { ADE9039_ISUM_APROX_N , ADE9039_ISUM_DET_MISM_POS , ADE9039_ISUM_DET_MISM_NEG , ADE9039_ISUM_APROX_N_RMS }
	ADE9039 isum calculation configuration. More...

enum	ade9039_aregion_sel_e { ADE9039_AIGAIN_APHCAL_0 , ADE9039_AIGAIN_APHCAL_1 , ADE9039_AIGAIN_APHCAL_2 , ADE9039_AIGAIN_APHCAL_3 , ADE9039_AIGAIN_APHCAL_4 , ADE9039_AIGAIN_APHCAL_DISABLE = 15 }
	ADE9039 These bits indicate which AIGAINx and APHCALx is currently being used. More...

enum	ade9039_bregion_sel_e { ADE9039_BIGAIN_BPHCAL_0 , ADE9039_BIGAIN_BPHCAL_1 , ADE9039_BIGAIN_BPHCAL_2 , ADE9039_BIGAIN_BPHCAL_3 , ADE9039_BIGAIN_BPHCAL_4 , ADE9039_BIGAIN_BPHCAL_DISABLE = 15 }
	ADE9039 These bits indicate which BIGAINx and BPHCALx is currently being used. More...

enum	ade9039_cregion_sel_e { ADE9039_CIGAIN_CPHCAL_0 , ADE9039_CIGAIN_CPHCAL_1 , ADE9039_CIGAIN_CPHCAL_2 , ADE9039_CIGAIN_CPHCAL_3 , ADE9039_CIGAIN_CPHCAL_4 , ADE9039_CIGAIN_CPHCAL_DISABLE = 15 }
	ADE9039 These bits indicate which CIGAINx and CPHCALx is currently being used. More...

enum	ade9039_cf4_pin_out_cfg_e { ADE9039_CF4_D_F_CONV , ADE9039_CF4_D_F_CONV2 , ADE9039_CF4_EVENT , ADE9039_CF4_DREADY }
	ADE9039 These bits indicate which function to output on CF4 pin. More...

enum	ade9039_pwr_settle_e { ADE9039_PWR_SETTLE_0 , ADE9039_PWR_SETTLE_1 , ADE9039_PWR_SETTLE_2 , ADE9039_PWR_SETTLE_3 }
	ADE9039 Power settle time. More...

enum	ade9039_oiphase_e { ADE9039_OIPHASE_A , ADE9039_OIPHASE_B , ADE9039_OIPHASE_C , ADE9039_OIPHASE_N }
	ADE9039 indicates that a phase is above OILVL. More...

enum	ade9039_cf4_sel_e { ADE9039_CF4_SEL_ACTIV_P , ADE9039_CF4_SEL_APPARENT_P = 2 , ADE9039_CF4_SEL_FUNDAMENTAL_ACTIVE_P , ADE9039_CF4_SEL_FUN_REACTIVE_P , ADE9039_CF4_SEL_FUN_APPARENT_P , ADE9039_CF4_SEL_TOTAL_ACTIVE_P , ADE9039_CF4_SEL_TOTAL_ACTIVE_P_2 }
	ADE9039 Type of energy output on the CF4 pin. Configure TERMSEL4 in the COMPMODE register to select which phases are included. More...

enum	ade9039_freq_sel_e { ADE9039_SELFREQ_50 , ADE9039_SELFREQ_60 }
	ADE9039 Freq value. More...

enum	ade9039_vconsel_e { ADE9039_4WIRE_WYE , ADE9039_3WIRE_DELTA , ADE9039_4WIRE_WYE_VA_VC , ADE9039_4WIRE_WYE_VA , ADE9039_3WIRE_DELTA_2 }
	ADE9039 3-wire and 4-wire hardware configuration selection. More...

enum	ade9039_var_acc_mode_e { ADE9039_ACC_SIGNED , ADE9039_ACC_ABSOLUTE , ADE9039_ACC_POSITIVE , ADE9039_ACC_NEGATIVE }
	ADE9039 Total and fundamental reactive power accumulation mode for energy registers and CFx pulses. More...

enum	ade9039_line_period_sel_e { ADE9039_APERIOD , ADE9039_BPERIOD , ADE9039_CPERIOD , ADE9039_COM_PERIOD }
	Selects line period measurement used for VRMS½ cycle, 10 cycle rms/12 cycle rms, and resampling. More...

enum	ade9039_zx_select_e { ADE9039_ZXVA_SEL , ADE9039_ZXVB_SEL , ADE9039_ZXVC_SEL , ADE9039_ZXCOMB_SEL }
	Selects the zero-crossing signal, which can be routed to the CF3/ZX output pin and used for line cycle energy accumulation. More...

enum	ade9039_wf_src_e { ADE9039_SRC_SINC4 , ADE9039_SRC_SINC4_IIR = 2 , ADE9039_SRC_DSP }
	Waveform buffer source and DREADY (data ready update rate) selection. More...

enum	ade9039_wf_mode_e { ADE9039_MODE_STOP_FULL , ADE9039_MODE_TRIG_EN_EVENTS , ADE9039_MODE_CENTER_CAPTURE , ADE9039_MODE_SAVE_EVENT_ADDR }
	Fixed data rate waveforms filling and trigger based modes. More...

enum	ade9039_burst_ch_e { ADE9039_BURST_ALL_CH , ADE9039_BURST_IA_VA , ADE9039_BURST_IB_VB , ADE9039_BURST_IC_VC , ADE9039_BURST_IA = 8 , ADE9039_BURST_VA , ADE9039_BURST_IB , ADE9039_BURST_VB , ADE9039_BURST_IC , ADE9039_BURST_VC , ADE9039_BURST_IN , ADE9039_BURST_DISABLED }
	Selects which data to read out of the waveform buffer through SPI. More...

enum	ade9039_hpf_freq_e { ADE9039_HPF_0_2 , ADE9039_HPF_1 , ADE9039_HPF_3 , ADE9039_HPF_6 , ADE9039_HPF_10 , ADE9039_HPF_12 , ADE9039_HPF_18 , ADE9039_HPF_21_6 }
	High-pass filter corner (f3dB) enabled when the HPFDIS bit in the CONFIG0 register is equal to zero. More...

enum	ade9039_no_load_tmr_e { ADE9039_NOLOAD_SAMPLES_64 , ADE9039_NOLOAD_SAMPLES_128 , ADE9039_NOLOAD_SAMPLES_256 , ADE9039_NOLOAD_SAMPLES_512 , ADE9039_NOLOAD_SAMPLES_1024 , ADE9039_NOLOAD_SAMPLES_2048 , ADE9039_NOLOAD_SAMPLES_4096 , ADE9039_NOLOAD_SAMPLES_DISABLE }
	This register configures how many 4 kSPS samples to evaluate the no load condition over. More...

enum	ade9039_temp_time_e { ADE9039_TEMP_TIME_1 , ADE9039_TEMP_TIME_256 , ADE9039_TEMP_TIME_512 , ADE9039_TEMP_TIME_1024 }
	ADE9039 Temperature measurement time. More...

enum	ade9039_vc_gain_e { ADE9039_VC_GAIN_1 , ADE9039_VC_GAIN_2 , ADE9039_VC_GAIN_4 , ADE9039_VC_GAIN_4_2 }
	ADE9039 PGA gain for Voltage Channel C ADC. More...

enum	ade9039_phase { ADE9039_PHASE_A , ADE9039_PHASE_B , ADE9039_PHASE_C }
	ADE9039 available phases. More...

enum	ade9039_egy_model { ADE9039_EGY_WITH_RESET , ADE9039_EGY_HALF_LINE_CYCLES , ADE9039_EGY_NR_SAMPLES }
	ADE9039 available user energy use models. More...

enum	ade9039_power_mode_e { NORMAL_MODE , TAMPER_MODE , CURRENT_PEAK_DETECT_MODE , IDLE_MODE }
	ADE9039 Power mode selection. More...

Functions
int	ade9039_read (struct ade9039_dev dev, uint16_t reg_addr, uint32_t reg_data)
	Read device register.

int	ade9039_write (struct ade9039_dev *dev, uint16_t reg_addr, uint32_t reg_data)
	Write device register.

int	ade9039_set_power_mode (struct ade9039_dev *dev)
	Set power mode.

int	ade9039_update_bits (struct ade9039_dev *dev, uint16_t reg_addr, uint32_t mask, uint32_t reg_data)
	Update specific register bits.

int	ade9039_read_rms_ph (struct ade9039_dev *dev, enum ade9039_phase phase)
	Read the rms values for a specific phase.

int	ade9039_read_power_ph (struct ade9039_dev *dev, enum ade9039_phase phase)
	Read the power values for a specific phase.

int	ade9039_read_energy_ph (struct ade9039_dev *dev, enum ade9039_phase phase)
	Read the energy values for a specific phase.

int	ade9039_read_power_factor_ph (struct ade9039_dev *dev, enum ade9039_phase phase)
	Read the power factor values for a specific phase.

int	ade9039_set_egy_model (struct ade9039_dev *dev, enum ade9039_egy_model model, uint16_t value)
	Set User Energy use model.

int	ade9039_init (struct ade9039_dev **device, struct ade9039_init_param init_param)
	Initialize the device.

int	ade9039_setup (struct ade9039_dev *dev)
	Setup the device.

int	ade9039_remove (struct ade9039_dev *dev)
	Remove the device and release resources.

int	ade9039_read_temp (struct ade9039_dev *dev)
	Read the ADE9039 temperature using the conversion ready status.

int	ade9039_get_int_status0 (struct ade9039_dev dev, uint32_t msk, uint8_t status)
	Get interrupt indicator from STATUS0 register.

int	ade9039_check_bit_status (struct ade9039_dev dev, uint16_t reg_addr, uint32_t bit_mask, uint8_t status)
	Check bit status of a register.

Detailed Description

Header file of ADE9039 Driver.

Author: REtz (radu..nosp@m.etz@.nosp@m.analo.nosp@m.g.co.nosp@m.m)

SPDX-License-Identifier: BSD-3-Clause

Macro Definition Documentation

◆ ADE9039_A_TFVARHR_EN

#define ADE9039_A_TFVARHR_EN NO_OS_BIT(17)

◆ ADE9039_A_TWATTHR_EN

#define ADE9039_A_TWATTHR_EN NO_OS_BIT(14)

◆ ADE9039_ACCMODE

#define ADE9039_ACCMODE 0x0000

◆ ADE9039_ADE9039_ID

#define ADE9039_ADE9039_ID NO_OS_BIT(20)

◆ ADE9039_AFVANL

#define ADE9039_AFVANL NO_OS_BIT(5)

◆ ADE9039_AFVARNL

#define ADE9039_AFVARNL NO_OS_BIT(4)

◆ ADE9039_AREGION

#define ADE9039_AREGION NO_OS_GENMASK(3, 0)

◆ ADE9039_AVANL

#define ADE9039_AVANL NO_OS_BIT(2)

◆ ADE9039_AVARSIGN

#define ADE9039_AVARSIGN NO_OS_BIT(1)

◆ ADE9039_AWATTNL

#define ADE9039_AWATTNL NO_OS_BIT(0)

◆ ADE9039_AWSIGN

#define ADE9039_AWSIGN NO_OS_BIT(0)

◆ ADE9039_B_TFVARHR_EN

#define ADE9039_B_TFVARHR_EN NO_OS_BIT(18)

◆ ADE9039_B_TWATTHR_EN

#define ADE9039_B_TWATTHR_EN NO_OS_BIT(15)

◆ ADE9039_BFVANL

#define ADE9039_BFVANL NO_OS_BIT(11)

◆ ADE9039_BFVARNL

#define ADE9039_BFVARNL NO_OS_BIT(10)

◆ ADE9039_BFWATTNL

#define ADE9039_BFWATTNL NO_OS_BIT(9)

◆ ADE9039_BREGION

#define ADE9039_BREGION NO_OS_GENMASK(3, 0)

◆ ADE9039_BURDEN_RES

#define ADE9039_BURDEN_RES 10

◆ ADE9039_BURST_CHAN

#define ADE9039_BURST_CHAN NO_OS_GENMASK(3, 0)

◆ ADE9039_BURST_EN

#define ADE9039_BURST_EN NO_OS_BIT(11)

◆ ADE9039_BVANL

#define ADE9039_BVANL NO_OS_BIT(8)

◆ ADE9039_BVARSIGN

#define ADE9039_BVARSIGN NO_OS_BIT(3)

◆ ADE9039_BWATTNL

#define ADE9039_BWATTNL NO_OS_BIT(6)

◆ ADE9039_BWSIGN

#define ADE9039_BWSIGN NO_OS_BIT(2)

◆ ADE9039_C_TFVARHR_EN

#define ADE9039_C_TFVARHR_EN NO_OS_BIT(19)

◆ ADE9039_C_TWATTHR_EN

#define ADE9039_C_TWATTHR_EN NO_OS_BIT(16)

◆ ADE9039_CF1_LT

#define ADE9039_CF1_LT NO_OS_BIT(19)

◆ ADE9039_CF1DIS

#define ADE9039_CF1DIS NO_OS_BIT(12)

◆ ADE9039_CF1SEL

#define ADE9039_CF1SEL NO_OS_GENMASK(2, 0)

◆ ADE9039_CF2_LT

#define ADE9039_CF2_LT NO_OS_BIT(20)

◆ ADE9039_CF2DIS

#define ADE9039_CF2DIS NO_OS_BIT(13)

◆ ADE9039_CF2SEL

#define ADE9039_CF2SEL NO_OS_GENMASK(5, 3)

◆ ADE9039_CF3_CFG

#define ADE9039_CF3_CFG NO_OS_BIT(1)

◆ ADE9039_CF3_LT

#define ADE9039_CF3_LT NO_OS_BIT(21)

◆ ADE9039_CF3DIS

#define ADE9039_CF3DIS NO_OS_BIT(14)

◆ ADE9039_CF3SEL

#define ADE9039_CF3SEL NO_OS_GENMASK(8, 6)

◆ ADE9039_CF4_CFG

#define ADE9039_CF4_CFG NO_OS_GENMASK(3, 2)

◆ ADE9039_CF4_LT

#define ADE9039_CF4_LT NO_OS_BIT(22)

◆ ADE9039_CF4DIS

#define ADE9039_CF4DIS NO_OS_BIT(15)

◆ ADE9039_CF4SEL

#define ADE9039_CF4SEL NO_OS_GENMASK(11, 9)

◆ ADE9039_CF_ACC_CLR

#define ADE9039_CF_ACC_CLR NO_OS_BIT(5)

◆ ADE9039_CF_LTMR

#define ADE9039_CF_LTMR NO_OS_GENMASK(18, 0)

◆ ADE9039_CFVANL

#define ADE9039_CFVANL NO_OS_BIT(17)

◆ ADE9039_CFVARNL

#define ADE9039_CFVARNL NO_OS_BIT(16)

◆ ADE9039_CFWATTNL

#define ADE9039_CFWATTNL NO_OS_BIT(15)

◆ ADE9039_CHIP_ID

#define ADE9039_CHIP_ID 0xFE

◆ ADE9039_COMPMODE

#define ADE9039_COMPMODE 0x0007

◆ ADE9039_CONFIG0

#define ADE9039_CONFIG0 0x00000000

◆ ADE9039_CONFIG1

#define ADE9039_CONFIG1 0x0002

◆ ADE9039_CONFIG2

#define ADE9039_CONFIG2 0x0A00

◆ ADE9039_CONFIG3

#define ADE9039_CONFIG3 0x0000

◆ ADE9039_CRC_ACT_NL_LVL_EN

#define ADE9039_CRC_ACT_NL_LVL_EN NO_OS_BIT(7)

◆ ADE9039_CRC_APP_NL_LVL_EN

#define ADE9039_CRC_APP_NL_LVL_EN NO_OS_BIT(9)

◆ ADE9039_CRC_DIP_CYC_EN

#define ADE9039_CRC_DIP_CYC_EN NO_OS_BIT(4)

◆ ADE9039_CRC_DIP_LVL_EN

#define ADE9039_CRC_DIP_LVL_EN NO_OS_BIT(3)

◆ ADE9039_CRC_EVENT_MASK_EN

#define ADE9039_CRC_EVENT_MASK_EN NO_OS_BIT(2)

◆ ADE9039_CRC_MASK0_EN

#define ADE9039_CRC_MASK0_EN NO_OS_BIT(0)

◆ ADE9039_CRC_MASK1_EN

#define ADE9039_CRC_MASK1_EN NO_OS_BIT(1)

◆ ADE9039_CRC_REACT_NL_LVL_EN

#define ADE9039_CRC_REACT_NL_LVL_EN NO_OS_BIT(8)

◆ ADE9039_CRC_SEQ_CYC_EN

#define ADE9039_CRC_SEQ_CYC_EN NO_OS_BIT(12)

◆ ADE9039_CRC_SWELL_CYC_EN

#define ADE9039_CRC_SWELL_CYC_EN NO_OS_BIT(6)

◆ ADE9039_CRC_SWELL_LVL_EN

#define ADE9039_CRC_SWELL_LVL_EN NO_OS_BIT(5)

◆ ADE9039_CRC_WFB_CFG_EN

#define ADE9039_CRC_WFB_CFG_EN NO_OS_BIT(13)

◆ ADE9039_CRC_WFB_PG_IRQEN

#define ADE9039_CRC_WFB_PG_IRQEN NO_OS_BIT(14)

◆ ADE9039_CRC_WFB_TRG_CFG_EN

#define ADE9039_CRC_WFB_TRG_CFG_EN NO_OS_BIT(15)

◆ ADE9039_CRC_ZXLPSEL_EN

#define ADE9039_CRC_ZXLPSEL_EN NO_OS_BIT(11)

◆ ADE9039_CRC_ZXTOUT_EN

#define ADE9039_CRC_ZXTOUT_EN NO_OS_BIT(10)

◆ ADE9039_CREGION

#define ADE9039_CREGION NO_OS_GENMASK(3, 0)

◆ ADE9039_CURRENT_TR_FCN

#define ADE9039_CURRENT_TR_FCN (ADE9039_CURRENT_TR_RATIO / ADE9039_BURDEN_RES)

◆ ADE9039_CURRENT_TR_RATIO

#define ADE9039_CURRENT_TR_RATIO 1000

◆ ADE9039_CVANL

#define ADE9039_CVANL NO_OS_BIT(14)

◆ ADE9039_CVARSIGN

#define ADE9039_CVARSIGN NO_OS_BIT(5)

◆ ADE9039_CWATTNL

#define ADE9039_CWATTNL NO_OS_BIT(12)

◆ ADE9039_CWSIGN

#define ADE9039_CWSIGN NO_OS_BIT(4)

◆ ADE9039_DICOEFF

#define ADE9039_DICOEFF 0x00000000

◆ ADE9039_DIP

#define ADE9039_DIP NO_OS_BIT(0)

◆ ADE9039_DIP_SWELL_IRQ_MODE

#define ADE9039_DIP_SWELL_IRQ_MODE NO_OS_BIT(10)

◆ ADE9039_DIPA_VAL

#define ADE9039_DIPA_VAL NO_OS_GENMASK(23, 0)

◆ ADE9039_DIPB_VAL

#define ADE9039_DIPB_VAL NO_OS_GENMASK(23, 0)

◆ ADE9039_DIPC_VAL

#define ADE9039_DIPC_VAL NO_OS_GENMASK(23, 0)

◆ ADE9039_DISAPLPF

#define ADE9039_DISAPLPF NO_OS_BIT(12)

◆ ADE9039_DOWN_RES

#define ADE9039_DOWN_RES 1000

◆ ADE9039_EGY_LD_ACCUM

#define ADE9039_EGY_LD_ACCUM NO_OS_BIT(4)

◆ ADE9039_EGY_PWR_EN

#define ADE9039_EGY_PWR_EN NO_OS_BIT(0)

◆ ADE9039_EGY_TMR_MODE

#define ADE9039_EGY_TMR_MODE NO_OS_BIT(1)

◆ ADE9039_EVENT_AFNOLOAD

#define ADE9039_EVENT_AFNOLOAD NO_OS_BIT(13)

◆ ADE9039_EVENT_AFNOLOAD_MSK

#define ADE9039_EVENT_AFNOLOAD_MSK NO_OS_BIT(13)

◆ ADE9039_EVENT_ANLOAD

#define ADE9039_EVENT_ANLOAD NO_OS_BIT(10)

◆ ADE9039_EVENT_ANLOAD_MSK

#define ADE9039_EVENT_ANLOAD_MSK NO_OS_BIT(10)

◆ ADE9039_EVENT_DIPA

#define ADE9039_EVENT_DIPA NO_OS_BIT(0)

◆ ADE9039_EVENT_DIPAEN_MSK

#define ADE9039_EVENT_DIPAEN_MSK NO_OS_BIT(0)

◆ ADE9039_EVENT_DIPB

#define ADE9039_EVENT_DIPB NO_OS_BIT(1)

◆ ADE9039_EVENT_DIPBEN_MSK

#define ADE9039_EVENT_DIPBEN_MSK NO_OS_BIT(1)

◆ ADE9039_EVENT_DIPC

#define ADE9039_EVENT_DIPC NO_OS_BIT(2)

◆ ADE9039_EVENT_DIPCEN_MSK

#define ADE9039_EVENT_DIPCEN_MSK NO_OS_BIT(2)

◆ ADE9039_EVENT_DREADY

#define ADE9039_EVENT_DREADY NO_OS_BIT(16)

◆ ADE9039_EVENT_DREADY_MSK

#define ADE9039_EVENT_DREADY_MSK NO_OS_BIT(16)

◆ ADE9039_EVENT_MASK

#define ADE9039_EVENT_MASK 0x00000000

◆ ADE9039_EVENT_REVPSUM1

#define ADE9039_EVENT_REVPSUM1 NO_OS_BIT(6)

◆ ADE9039_EVENT_REVPSUM1_MSK

#define ADE9039_EVENT_REVPSUM1_MSK NO_OS_BIT(6)

◆ ADE9039_EVENT_REVPSUM2

#define ADE9039_EVENT_REVPSUM2 NO_OS_BIT(7)

◆ ADE9039_EVENT_REVPSUM2_MSK

#define ADE9039_EVENT_REVPSUM2_MSK NO_OS_BIT(7)

◆ ADE9039_EVENT_REVPSUM3

#define ADE9039_EVENT_REVPSUM3 NO_OS_BIT(8)

◆ ADE9039_EVENT_REVPSUM3_MSK

#define ADE9039_EVENT_REVPSUM3_MSK NO_OS_BIT(8)

◆ ADE9039_EVENT_REVPSUM4

#define ADE9039_EVENT_REVPSUM4 NO_OS_BIT(9)

◆ ADE9039_EVENT_REVPSUM4_MSK

#define ADE9039_EVENT_REVPSUM4_MSK NO_OS_BIT(9)

◆ ADE9039_EVENT_RFNOLOAD

#define ADE9039_EVENT_RFNOLOAD NO_OS_BIT(14)

◆ ADE9039_EVENT_RFNOLOAD_MSK

#define ADE9039_EVENT_RFNOLOAD_MSK NO_OS_BIT(14)

◆ ADE9039_EVENT_RNLOAD

#define ADE9039_EVENT_RNLOAD NO_OS_BIT(11)

◆ ADE9039_EVENT_SWELLA

#define ADE9039_EVENT_SWELLA NO_OS_BIT(3)

◆ ADE9039_EVENT_SWELLAEN_MSK

#define ADE9039_EVENT_SWELLAEN_MSK NO_OS_BIT(3)

◆ ADE9039_EVENT_SWELLB

#define ADE9039_EVENT_SWELLB NO_OS_BIT(4)

◆ ADE9039_EVENT_SWELLBEN_MSK

#define ADE9039_EVENT_SWELLBEN_MSK NO_OS_BIT(4)

◆ ADE9039_EVENT_SWELLC

#define ADE9039_EVENT_SWELLC NO_OS_BIT(5)

◆ ADE9039_EVENT_SWELLCEN_MSK

#define ADE9039_EVENT_SWELLCEN_MSK NO_OS_BIT(5)

◆ ADE9039_EVENT_VAFNOLOAD

#define ADE9039_EVENT_VAFNOLOAD NO_OS_BIT(15)

◆ ADE9039_EVENT_VAFNOLOAD_MSK

#define ADE9039_EVENT_VAFNOLOAD_MSK NO_OS_BIT(15)

◆ ADE9039_EVENT_VANLOAD

#define ADE9039_EVENT_VANLOAD NO_OS_BIT(12)

◆ ADE9039_EVENT_VANLOAD_MSK

#define ADE9039_EVENT_VANLOAD_MSK NO_OS_BIT(12)

◆ ADE9039_EXT_REF

#define ADE9039_EXT_REF NO_OS_BIT(15)

◆ ADE9039_FORCE_CRC_UPDATE

#define ADE9039_FORCE_CRC_UPDATE NO_OS_BIT(0)

◆ ADE9039_FS_VOLTAGE

#define ADE9039_FS_VOLTAGE 707

◆ ADE9039_HPF_CRN

#define ADE9039_HPF_CRN NO_OS_GENMASK(11, 9)

◆ ADE9039_HPFDIS

#define ADE9039_HPFDIS NO_OS_BIT(3)

◆ ADE9039_IA_DIN

#define ADE9039_IA_DIN NO_OS_GENMASK(2, 0)

◆ ADE9039_IA_DISADC

#define ADE9039_IA_DISADC NO_OS_BIT(0)

◆ ADE9039_IA_GAIN

#define ADE9039_IA_GAIN NO_OS_GENMASK(1, 0)

◆ ADE9039_IB_DIN

#define ADE9039_IB_DIN NO_OS_GENMASK(5, 3)

◆ ADE9039_IB_DISADC

#define ADE9039_IB_DISADC NO_OS_BIT(1)

◆ ADE9039_IB_GAIN

#define ADE9039_IB_GAIN NO_OS_GENMASK(3, 2)

◆ ADE9039_IC_DIN

#define ADE9039_IC_DIN NO_OS_GENMASK(8, 6)

◆ ADE9039_IC_DISADC

#define ADE9039_IC_DISADC NO_OS_BIT(2)

◆ ADE9039_IC_GAIN

#define ADE9039_IC_GAIN NO_OS_GENMASK(5, 4)

◆ ADE9039_ICONSEL

#define ADE9039_ICONSEL NO_OS_BIT(7)

◆ ADE9039_IN_DIN

#define ADE9039_IN_DIN NO_OS_GENMASK(11, 9)

◆ ADE9039_IN_DISADC

#define ADE9039_IN_DISADC NO_OS_BIT(3)

◆ ADE9039_IN_GAIN

#define ADE9039_IN_GAIN NO_OS_GENMASK(7, 6)

◆ ADE9039_ININTEN

#define ADE9039_ININTEN NO_OS_BIT(11)

◆ ADE9039_INTEN

#define ADE9039_INTEN NO_OS_BIT(5)

◆ ADE9039_IPEAKVAL

#define ADE9039_IPEAKVAL NO_OS_GENMASK(23, 0)

◆ ADE9039_IPPHASE

#define ADE9039_IPPHASE NO_OS_GENMASK(26, 24)

◆ ADE9039_IRQ0_ON_IRQ1

#define ADE9039_IRQ0_ON_IRQ1 NO_OS_BIT(12)

◆ ADE9039_ISUM_CFG

#define ADE9039_ISUM_CFG NO_OS_GENMASK(1, 0)

◆ ADE9039_LP_SEL

#define ADE9039_LP_SEL NO_OS_GENMASK(4, 3)

◆ ADE9039_MASK0

#define ADE9039_MASK0 0x00000001

◆ ADE9039_MASK0_CF1

#define ADE9039_MASK0_CF1 NO_OS_BIT(11)

◆ ADE9039_MASK0_CF2

#define ADE9039_MASK0_CF2 NO_OS_BIT(12)

◆ ADE9039_MASK0_CF3

#define ADE9039_MASK0_CF3 NO_OS_BIT(13)

◆ ADE9039_MASK0_CF4

#define ADE9039_MASK0_CF4 NO_OS_BIT(14)

◆ ADE9039_MASK0_COH_WFB_FULL

#define ADE9039_MASK0_COH_WFB_FULL NO_OS_BIT(23)

◆ ADE9039_MASK0_DREADY

#define ADE9039_MASK0_DREADY NO_OS_BIT(15)

◆ ADE9039_MASK0_EGYRDY

#define ADE9039_MASK0_EGYRDY NO_OS_BIT(0)

◆ ADE9039_MASK0_MISMTCH

#define ADE9039_MASK0_MISMTCH NO_OS_BIT(24)

◆ ADE9039_MASK0_PAGE_FULL

#define ADE9039_MASK0_PAGE_FULL NO_OS_BIT(17)

◆ ADE9039_MASK0_PWRRDY

#define ADE9039_MASK0_PWRRDY NO_OS_BIT(18)

◆ ADE9039_MASK0_REVAPA

#define ADE9039_MASK0_REVAPA NO_OS_BIT(1)

◆ ADE9039_MASK0_REVAPB

#define ADE9039_MASK0_REVAPB NO_OS_BIT(2)

◆ ADE9039_MASK0_REVAPC

#define ADE9039_MASK0_REVAPC NO_OS_BIT(3)

◆ ADE9039_MASK0_REVPSUM1

#define ADE9039_MASK0_REVPSUM1 NO_OS_BIT(7)

◆ ADE9039_MASK0_REVPSUM2

#define ADE9039_MASK0_REVPSUM2 NO_OS_BIT(8)

◆ ADE9039_MASK0_REVPSUM3

#define ADE9039_MASK0_REVPSUM3 NO_OS_BIT(9)

◆ ADE9039_MASK0_REVPSUM4

#define ADE9039_MASK0_REVPSUM4 NO_OS_BIT(10)

◆ ADE9039_MASK0_REVRPA

#define ADE9039_MASK0_REVRPA NO_OS_BIT(4)

◆ ADE9039_MASK0_REVRPB

#define ADE9039_MASK0_REVRPB NO_OS_BIT(5)

◆ ADE9039_MASK0_REVRPC

#define ADE9039_MASK0_REVRPC NO_OS_BIT(6)

◆ ADE9039_MASK0_TEMP_RDY_MASK

#define ADE9039_MASK0_TEMP_RDY_MASK NO_OS_BIT(25)

◆ ADE9039_MASK0_THD_PF_RDY

#define ADE9039_MASK0_THD_PF_RDY NO_OS_BIT(21)

◆ ADE9039_MASK0_WFB_TRIG

#define ADE9039_MASK0_WFB_TRIG NO_OS_BIT(22)

◆ ADE9039_MASK0_WFB_TRIG_IRQ

#define ADE9039_MASK0_WFB_TRIG_IRQ NO_OS_BIT(16)

◆ ADE9039_MASK1

#define ADE9039_MASK1 0x00000000

◆ ADE9039_MASK1_AFNOLOAD

#define ADE9039_MASK1_AFNOLOAD NO_OS_BIT(3)

◆ ADE9039_MASK1_ANLOAD

#define ADE9039_MASK1_ANLOAD NO_OS_BIT(0)

◆ ADE9039_MASK1_CRC_CHG

#define ADE9039_MASK1_CRC_CHG NO_OS_BIT(26)

◆ ADE9039_MASK1_CRC_DONE

#define ADE9039_MASK1_CRC_DONE NO_OS_BIT(27)

◆ ADE9039_MASK1_DIPA

#define ADE9039_MASK1_DIPA NO_OS_BIT(23)

◆ ADE9039_MASK1_DIPB

#define ADE9039_MASK1_DIPB NO_OS_BIT(24)

◆ ADE9039_MASK1_DIPC

#define ADE9039_MASK1_DIPC NO_OS_BIT(25)

◆ ADE9039_MASK1_ERROR0

#define ADE9039_MASK1_ERROR0 NO_OS_BIT(28)

◆ ADE9039_MASK1_ERROR1

#define ADE9039_MASK1_ERROR1 NO_OS_BIT(29)

◆ ADE9039_MASK1_ERROR2

#define ADE9039_MASK1_ERROR2 NO_OS_BIT(30)

◆ ADE9039_MASK1_ERROR3

#define ADE9039_MASK1_ERROR3 NO_OS_BIT(31)

◆ ADE9039_MASK1_OI

#define ADE9039_MASK1_OI NO_OS_BIT(17)

◆ ADE9039_MASK1_SEQERR

#define ADE9039_MASK1_SEQERR NO_OS_BIT(18)

◆ ADE9039_MASK1_SWELLA

#define ADE9039_MASK1_SWELLA NO_OS_BIT(20)

◆ ADE9039_MASK1_SWELLB

#define ADE9039_MASK1_SWELLB NO_OS_BIT(21)

◆ ADE9039_MASK1_SWELLC

#define ADE9039_MASK1_SWELLC NO_OS_BIT(22)

◆ ADE9039_MASK1_VAFNOLOAD

#define ADE9039_MASK1_VAFNOLOAD NO_OS_BIT(5)

◆ ADE9039_MASK1_VANLOAD

#define ADE9039_MASK1_VANLOAD NO_OS_BIT(2)

◆ ADE9039_MASK1_ZXCOMB

#define ADE9039_MASK1_ZXCOMB NO_OS_BIT(12)

◆ ADE9039_MASK1_ZXIA

#define ADE9039_MASK1_ZXIA NO_OS_BIT(13)

◆ ADE9039_MASK1_ZXIB

#define ADE9039_MASK1_ZXIB NO_OS_BIT(14)

◆ ADE9039_MASK1_ZXIC

#define ADE9039_MASK1_ZXIC NO_OS_BIT(15)

◆ ADE9039_MASK1_ZXTOVA

#define ADE9039_MASK1_ZXTOVA NO_OS_BIT(6)

◆ ADE9039_MASK1_ZXTOVB

#define ADE9039_MASK1_ZXTOVB NO_OS_BIT(7)

◆ ADE9039_MASK1_ZXTOVC

#define ADE9039_MASK1_ZXTOVC NO_OS_BIT(8)

◆ ADE9039_MASK1_ZXVA

#define ADE9039_MASK1_ZXVA NO_OS_BIT(9)

◆ ADE9039_MASK1_ZXVB

#define ADE9039_MASK1_ZXVB NO_OS_BIT(10)

◆ ADE9039_MASK1_ZXVC

#define ADE9039_MASK1_ZXVC NO_OS_BIT(11)

◆ ADE9039_MTEN

#define ADE9039_MTEN NO_OS_BIT(4)

◆ ADE9039_NOLOAD_TMR

#define ADE9039_NOLOAD_TMR NO_OS_GENMASK(15, 13)

◆ ADE9039_OC_EN

#define ADE9039_OC_EN NO_OS_GENMASK(15, 12)

◆ ADE9039_OI

#define ADE9039_OI NO_OS_BIT(2)

◆ ADE9039_OIA_VAL

#define ADE9039_OIA_VAL NO_OS_GENMASK(23, 0)

◆ ADE9039_OIB_VAL

#define ADE9039_OIB_VAL NO_OS_GENMASK(23, 0)

◆ ADE9039_OIC_VAL

#define ADE9039_OIC_VAL NO_OS_GENMASK(23, 0)

◆ ADE9039_OILVL_VAL

#define ADE9039_OILVL_VAL NO_OS_GENMASK(23, 0)

◆ ADE9039_OIN_VAL

#define ADE9039_OIN_VAL NO_OS_GENMASK(23, 0)

◆ ADE9039_OIPHASE

#define ADE9039_OIPHASE NO_OS_GENMASK(3, 0)

◆ ADE9039_PART_ID

#define ADE9039_PART_ID 1

◆ ADE9039_PEAKSEL

#define ADE9039_PEAKSEL NO_OS_GENMASK(4, 2)

◆ ADE9039_PGA_GAIN

#define ADE9039_PGA_GAIN 0x0000

◆ ADE9039_PWR_SETTLE

#define ADE9039_PWR_SETTLE NO_OS_GENMASK(9, 8)

◆ ADE9039_PWR_SIGN_SEL_0

#define ADE9039_PWR_SIGN_SEL_0 NO_OS_BIT(6)

◆ ADE9039_PWR_SIGN_SEL_1

#define ADE9039_PWR_SIGN_SEL_1 NO_OS_BIT(7)

◆ ADE9039_REG_ACCMODE

#define ADE9039_REG_ACCMODE 0x492 /* Accumulation mode register. */

◆ ADE9039_REG_ACT_NL_LVL

#define ADE9039_REG_ACT_NL_LVL 0x41C /* No load threshold in the total and fundamental active power datapath. */

◆ ADE9039_REG_ADC_REDIRECT

#define ADE9039_REG_ADC_REDIRECT 0x424 /* This register allows any ADC output to be redirected to any digital datapath. */

◆ ADE9039_REG_AECCOEF

#define ADE9039_REG_AECCOEF 0x019 /* Phase A coupling coefficient used to compensate for the electrostatic the Analog Devices PCB-based di/dt sensor. Format is 5.27. */

◆ ADE9039_REG_AFIRMS_1

#define ADE9039_REG_AFIRMS_1 0x629 /* SPI burst read accessible. Registers organized functionally. See AFIRMS. */

◆ ADE9039_REG_AFIRMS_2

#define ADE9039_REG_AFIRMS_2 0x68D /* SPI burst read accessible. Registers organized by phase. See AFIRMS. */

◆ ADE9039_REG_AFPF

#define ADE9039_REG_AFPF 0x21E /* Phase A fundamental power factor, updated every 1.024 sec. */

◆ ADE9039_REG_AFVA

#define ADE9039_REG_AFVA 0x215 /* Phase A fundamental apparent power, updated at 4 kSPS. */

◆ ADE9039_REG_AFVA_1

#define ADE9039_REG_AFVA_1 0x626 /* SPI burst read accessible. Registers organized functionally. See AFVA. */

◆ ADE9039_REG_AFVA_2

#define ADE9039_REG_AFVA_2 0x68C /* SPI burst read accessible. Registers organized by phase. See AFVA. */

◆ ADE9039_REG_AFVA_ACC

#define ADE9039_REG_AFVA_ACC 0x317 /* Phase A accumulated fundamental apparent power, updated after kSPS samples. */

◆ ADE9039_REG_AFVAHR_HI

#define ADE9039_REG_AFVAHR_HI 0x319 /* Phase A accumulated fundamental apparent energy, MSB. Updated the settings in the EP_CFG and EGY_TIME registers. */

◆ ADE9039_REG_AFVAHR_LO

#define ADE9039_REG_AFVAHR_LO 0x318 /* Phase A accumulated fundamental apparent energy, LSB. Updated the settings in the EP_CFG and EGY_TIME registers. */

◆ ADE9039_REG_AFVAR

#define ADE9039_REG_AFVAR 0x214 /* Phase A fundamental reactive power, updated at 4 kSPS. */

◆ ADE9039_REG_AFVAR_1

#define ADE9039_REG_AFVAR_1 0x617 /* SPI burst read accessible. Registers organized functionally. See AFVAR. */

◆ ADE9039_REG_AFVAR_2

#define ADE9039_REG_AFVAR_2 0x687 /* SPI burst read accessible. Registers organized by phase. See AFVAR. */

◆ ADE9039_REG_AFVAR_ACC

#define ADE9039_REG_AFVAR_ACC 0x30D /* Phase A accumulated fundamental reactive power, updated after kSPS samples. */

◆ ADE9039_REG_AFVARHR_HI

#define ADE9039_REG_AFVARHR_HI 0x30F /* Phase A accumulated fundamental reactive energy, MSB. Updated the settings in the EP_CFG and EGY_TIME registers. */

◆ ADE9039_REG_AFVARHR_LO

#define ADE9039_REG_AFVARHR_LO 0x30E /* Phase A accumulated fundamental reactive energy, LSB. Updated according settings in the EP_CFG and EGY_TIME registers. */

◆ ADE9039_REG_AFVAROS

#define ADE9039_REG_AFVAROS 0x012 /* Phase A fundamental reactive power offset correction for the AFVAR */

◆ ADE9039_REG_AFVRMS_1

#define ADE9039_REG_AFVRMS_1 0x62C /* SPI burst read accessible. Registers organized functionally. See AFVRMS. */

◆ ADE9039_REG_AFVRMS_2

#define ADE9039_REG_AFVRMS_2 0x68E /* SPI burst read accessible. Registers organized by phase. See AFVRMS. */

◆ ADE9039_REG_AFWATT

#define ADE9039_REG_AFWATT 0x213 /* Phase A fundamental active power, updated at 4 kSPS. */

◆ ADE9039_REG_AFWATT_1

#define ADE9039_REG_AFWATT_1 0x623 /* SPI burst read accessible. Registers organized functionally. See AFWATT. */

◆ ADE9039_REG_AFWATT_2

#define ADE9039_REG_AFWATT_2 0x68B /* SPI burst read accessible. Registers organized by phase. See AFWATT. */

◆ ADE9039_REG_AFWATT_ACC

#define ADE9039_REG_AFWATT_ACC 0x303 /* Phase A accumulated fundamental active power, updated after PWR_TIME 4 */

◆ ADE9039_REG_AFWATTHR_HI

#define ADE9039_REG_AFWATTHR_HI 0x305 /* Phase A accumulated fundamental active energy, MSB. Updated according settings in the EP_CFG and EGY_TIME registers. */

◆ ADE9039_REG_AFWATTHR_LO

#define ADE9039_REG_AFWATTHR_LO 0x304 /* Phase A accumulated fundamental active energy, LSB. Updated according to in the EP_CFG and EGY_TIME registers. */

◆ ADE9039_REG_AFWATTOS

#define ADE9039_REG_AFWATTOS 0x011 /* Phase A fundamental active power offset correction for the AFWATT */

◆ ADE9039_REG_AI_LPF_DAT

#define ADE9039_REG_AI_LPF_DAT 0x510 /* Current Channel A ADC waveforms from the sinc4 + IIR LPF output at 4 */

◆ ADE9039_REG_AI_PCF

#define ADE9039_REG_AI_PCF 0x20A /* Instantaneous Phase A current channel waveform processed by the DSP at */

◆ ADE9039_REG_AI_PCF_1

#define ADE9039_REG_AI_PCF_1 0x604 /* SPI burst read accessible. Registers organized functionally. See AI_PCF. */

◆ ADE9039_REG_AI_PCF_2

#define ADE9039_REG_AI_PCF_2 0x681 /* SPI burst read accessible. Registers organized by phase. See AI_PCF. */

◆ ADE9039_REG_AI_SINC_DAT

#define ADE9039_REG_AI_SINC_DAT 0x500 /* Current Channel A ADC waveforms from the sinc4 output at 16 kSPS. */

◆ ADE9039_REG_AIFRMS

#define ADE9039_REG_AIFRMS 0x20E /* Phase A current fundamental RMS, updated at 4 kSPS. */

◆ ADE9039_REG_AIFRMSOS

#define ADE9039_REG_AIFRMSOS 0x013 /* Phase A current RMS offset for the fundamental current RMS, AIFRMS */

◆ ADE9039_REG_AIGAIN

#define ADE9039_REG_AIGAIN 0x000 /* Phase A current gain adjust. */

◆ ADE9039_REG_AIGAIN0

#define ADE9039_REG_AIGAIN0

Value:

0x001 /* Phase A multipoint gain correction factor. If multipoint gain and phase enabled, with MTEN = 1 in the CONFIG0 register,

an factor, AIGAIN0 through AIGAIN4, is applied based on the RMS amplitude, and the MTTHR_Lx and MTTHR_Hx register */

◆ ADE9039_REG_AIGAIN1

#define ADE9039_REG_AIGAIN1 0x002 /* See the AIGAIN0 description. */

◆ ADE9039_REG_AIGAIN2

#define ADE9039_REG_AIGAIN2 0x003 /* See the AIGAIN0 description. */

◆ ADE9039_REG_AIGAIN3

#define ADE9039_REG_AIGAIN3 0x004 /* See the AIGAIN0 description. */

◆ ADE9039_REG_AIGAIN4

#define ADE9039_REG_AIGAIN4 0x005 /* See the AIGAIN0 description. */

◆ ADE9039_REG_AIRMS

#define ADE9039_REG_AIRMS 0x20C /* Phase A filter-based current RMS value, updated at 4 kSPS. */

◆ ADE9039_REG_AIRMS_1

#define ADE9039_REG_AIRMS_1 0x607 /* SPI burst read accessible. Registers organized functionally. See AIRMS. */

◆ ADE9039_REG_AIRMS_2

#define ADE9039_REG_AIRMS_2 0x682 /* SPI burst read accessible. Registers organized by phase. See AIRMS. */

◆ ADE9039_REG_AIRMSONE

#define ADE9039_REG_AIRMSONE 0x219 /* Phase A current fast RMS½ calculation, one cycle RMS updated every half */

◆ ADE9039_REG_AIRMSONE_1

#define ADE9039_REG_AIRMSONE_1 0x62F /* SPI burst read accessible. Registers organized functionally. See */

◆ ADE9039_REG_AIRMSONE_2

#define ADE9039_REG_AIRMSONE_2 0x68F /* SPI burst read accessible. Registers organized by phase. See AIRMSONE. */

◆ ADE9039_REG_AIRMSONEOS

#define ADE9039_REG_AIRMSONEOS 0x016 /* Phase A current RMS offset for the fast AIRMSONE calculation. */

◆ ADE9039_REG_AIRMSOS

#define ADE9039_REG_AIRMSOS 0x00C /* Phase A current RMS offset for the filter-based AIRMS calculation. */

◆ ADE9039_REG_AITHD

#define ADE9039_REG_AITHD 0x218 /* Phase A current THD, updated every 1.024 sec. */

◆ ADE9039_REG_AITHD_1

#define ADE9039_REG_AITHD_1 0x620 /* SPI burst read accessible. Registers organized functionally. See AITHD. */

◆ ADE9039_REG_AITHD_2

#define ADE9039_REG_AITHD_2 0x68A /* SPI burst read accessible. Registers organized by phase. See AITHD. */

◆ ADE9039_REG_AMTREGION

#define ADE9039_REG_AMTREGION 0x21D /* If multipoint gain and phase compensation is enabled, with MTEN = 1 in the this register indicates which AIGAINx and APHCALx is used. */

◆ ADE9039_REG_ANGL_IA_IB

#define ADE9039_REG_ANGL_IA_IB 0x488 /* Time between positive to negative zero crossings on Phase A and Phase B */

◆ ADE9039_REG_ANGL_IA_IC

#define ADE9039_REG_ANGL_IA_IC 0x48A /* Time between positive to negative zero crossings on Phase A and Phase C */

◆ ADE9039_REG_ANGL_IB_IC

#define ADE9039_REG_ANGL_IB_IC 0x489 /* Time between positive to negative zero crossings on Phase B and Phase C */

◆ ADE9039_REG_ANGL_VA_IA

#define ADE9039_REG_ANGL_VA_IA 0x485 /* Time between positive to negative zero crossings on Phase A voltage and */

◆ ADE9039_REG_ANGL_VA_VB

#define ADE9039_REG_ANGL_VA_VB 0x482 /* Time between positive to negative zero crossings on Phase A and Phase B */

◆ ADE9039_REG_ANGL_VA_VC

#define ADE9039_REG_ANGL_VA_VC 0x484 /* Time between positive to negative zero crossings on Phase A and Phase C */

◆ ADE9039_REG_ANGL_VB_IB

#define ADE9039_REG_ANGL_VB_IB 0x486 /* Time between positive to negative zero crossings on Phase B voltage and */

◆ ADE9039_REG_ANGL_VB_VC

#define ADE9039_REG_ANGL_VB_VC 0x483 /* Time between positive to negative zero crossings on Phase B and Phase C */

◆ ADE9039_REG_ANGL_VC_IC

#define ADE9039_REG_ANGL_VC_IC 0x487 /* Time between positive to negative zero crossings on Phase C voltage and */

◆ ADE9039_REG_APERIOD

#define ADE9039_REG_APERIOD 0x418 /* Line period on Phase A voltage. */

◆ ADE9039_REG_APF

#define ADE9039_REG_APF 0x216 /* Phase A total power factor, updated every 1.024 sec. */

◆ ADE9039_REG_APF_1

#define ADE9039_REG_APF_1 0x61A /* SPI burst read accessible. Registers organized functionally. See APF. */

◆ ADE9039_REG_APF_2

#define ADE9039_REG_APF_2 0x688 /* SPI burst read accessible. Registers organized by phase. See APF. */

◆ ADE9039_REG_APGAIN

#define ADE9039_REG_APGAIN 0x00E /* Phase A power gain adjust for the AWATT, AVA, AFWATT, AFVA, and */

◆ ADE9039_REG_APHCAL0

#define ADE9039_REG_APHCAL0

Value:

                        0x006 /* Phase A multipoint phase correction factor. If multipoint phase and gain disabled, with MTEN = 0 in the CONFIG0 register,
                        the compensation is applied. If multipoint phase and gain enabled, with MTEN = 1, the APHCAL0 through APHCAL4 applied based
                        on the AIRMS current RMS amplitude, and the MTTHR_Hx register values. */

◆ ADE9039_REG_APHCAL1

#define ADE9039_REG_APHCAL1 0x007 /* See the APHCAL0 description. */

◆ ADE9039_REG_APHCAL2

#define ADE9039_REG_APHCAL2 0x008 /* See the APHCAL0 description. */

◆ ADE9039_REG_APHCAL3

#define ADE9039_REG_APHCAL3 0x009 /* See the APHCAL0 description. */

◆ ADE9039_REG_APHCAL4

#define ADE9039_REG_APHCAL4 0x00A /* See the APHCAL0 description. */

◆ ADE9039_REG_APP_NL_LVL

#define ADE9039_REG_APP_NL_LVL 0x41E /* No load threshold in the total and fundamental apparent power datapath. */

◆ ADE9039_REG_AQUADINFO

#define ADE9039_REG_AQUADINFO 0x21F /* Phase A power quadrant measurement information. */

◆ ADE9039_REG_AV_LPF_DAT

#define ADE9039_REG_AV_LPF_DAT 0x511 /* Voltage Channel A ADC waveforms from the sinc4 + IIR LPF output at 4 */

◆ ADE9039_REG_AV_PCF

#define ADE9039_REG_AV_PCF 0x20B /* Instantaneous Phase A voltage channel waveform processed by the DSP at */

◆ ADE9039_REG_AV_PCF_1

#define ADE9039_REG_AV_PCF_1 0x600 /* SPI burst read accessible. Registers organized functionally. See AV_PCF. */

◆ ADE9039_REG_AV_PCF_2

#define ADE9039_REG_AV_PCF_2 0x680 /* SPI burst read accessible. Registers organized by phase. See AV_PCF. */

◆ ADE9039_REG_AV_SINC_DAT

#define ADE9039_REG_AV_SINC_DAT 0x501 /* Voltage Channel A ADC waveforms from the sinc4 output at 16 kSPS. */

◆ ADE9039_REG_AVA

#define ADE9039_REG_AVA 0x212 /* Phase A total apparent power, updated at 4 kSPS. */

◆ ADE9039_REG_AVA_1

#define ADE9039_REG_AVA_1 0x611 /* SPI burst read accessible. Registers organized functionally. See AVA. */

◆ ADE9039_REG_AVA_2

#define ADE9039_REG_AVA_2 0x685 /* SPI burst read accessible. Registers organized by phase. See AVA. */

◆ ADE9039_REG_AVA_ACC

#define ADE9039_REG_AVA_ACC 0x2F9 /* Phase A accumulated total apparent power, updated after PWR_TIME 4 */

◆ ADE9039_REG_AVAHR_HI

#define ADE9039_REG_AVAHR_HI 0x2FB /* Phase A accumulated total apparent energy, LSB. Updated according to the the EP_CFG and EGY_TIME registers. */

◆ ADE9039_REG_AVAHR_LO

#define ADE9039_REG_AVAHR_LO 0x2FA /* Phase A accumulated total apparent energy, LSB. Updated according to the the EP_CFG and EGY_TIME registers. */

◆ ADE9039_REG_AVFRMS

#define ADE9039_REG_AVFRMS 0x20F /* Phase A voltage fundamental RMS, updated at 4 kSPS. */

◆ ADE9039_REG_AVFRMSOS

#define ADE9039_REG_AVFRMSOS 0x014 /* Phase A voltage RMS offset for the fundamental voltage RMS, AVFRMS */

◆ ADE9039_REG_AVGAIN

#define ADE9039_REG_AVGAIN 0x00B /* Phase A voltage gain adjust. */

◆ ADE9039_REG_AVRMS

#define ADE9039_REG_AVRMS 0x20D /* Phase A filter-based voltage RMS value, updated at 4 kSPS. */

◆ ADE9039_REG_AVRMS_1

#define ADE9039_REG_AVRMS_1 0x60A /* SPI burst read accessible. Registers organized functionally. See AVRMS. */

◆ ADE9039_REG_AVRMS_2

#define ADE9039_REG_AVRMS_2 0x683 /* SPI burst read accessible. Registers organized by phase. See AVRMS. */

◆ ADE9039_REG_AVRMSONE

#define ADE9039_REG_AVRMSONE 0x21A /* Phase A voltage fast RMS½ calculation, one cycle RMS updated every half */

◆ ADE9039_REG_AVRMSONE_1

#define ADE9039_REG_AVRMSONE_1 0x632 /* SPI burst read accessible. Registers organized functionally. See */

◆ ADE9039_REG_AVRMSONE_2

#define ADE9039_REG_AVRMSONE_2 0x690 /* SPI burst read accessible. Registers organized by phase. See AVRMSONE. */

◆ ADE9039_REG_AVRMSONEOS

#define ADE9039_REG_AVRMSONEOS 0x015 /* Phase A voltage RMS offset for the fast AVRMSONE calculation. */

◆ ADE9039_REG_AVRMSOS

#define ADE9039_REG_AVRMSOS 0x00D /* Phase A voltage RMS offset for the filter-based AVRMS calculation. */

◆ ADE9039_REG_AVTHD

#define ADE9039_REG_AVTHD 0x217 /* Phase A voltage THD, updated every 1.024 sec. */

◆ ADE9039_REG_AVTHD_1

#define ADE9039_REG_AVTHD_1 0x61D /* SPI burst read accessible. Registers organized functionally. See AVTHD. */

◆ ADE9039_REG_AVTHD_2

#define ADE9039_REG_AVTHD_2 0x689 /* SPI burst read accessible. Registers organized by phase. See AVTHD. */

◆ ADE9039_REG_AWATT

#define ADE9039_REG_AWATT 0x210 /* Phase A low-pass filtered total active power, updated at 4 kSPS. */

◆ ADE9039_REG_AWATT_1

#define ADE9039_REG_AWATT_1 0x60E /* SPI burst read accessible. Registers organized functionally. See AWATT. */

◆ ADE9039_REG_AWATT_2

#define ADE9039_REG_AWATT_2 0x684 /* SPI burst read accessible. Registers organized by phase. See AWATT. */

◆ ADE9039_REG_AWATT_ACC

#define ADE9039_REG_AWATT_ACC 0x2E5 /* Phase A accumulated total active power, updated after PWR_TIME 4 kSPS */

◆ ADE9039_REG_AWATTHR_HI

#define ADE9039_REG_AWATTHR_HI 0x2E7 /* Phase A accumulated total active energy, MSB. Updated according to the the EP_CFG and EGY_TIME registers. */

◆ ADE9039_REG_AWATTHR_LO

#define ADE9039_REG_AWATTHR_LO 0x2E6 /* Phase A accumulated total active energy, LSB. Updated according to the the EP_CFG and EGY_TIME registers. */

◆ ADE9039_REG_AWATTOS

#define ADE9039_REG_AWATTOS 0x00F /* Phase A total active power offset correction for the AWATT calculation. */

◆ ADE9039_REG_BECCOEF

#define ADE9039_REG_BECCOEF 0x039 /* Phase B coupling coefficient used to compensate for the electrostatic the Analog Devices PCB-based di/dt sensor. Format is 5.27. */

◆ ADE9039_REG_BFIRMS_1

#define ADE9039_REG_BFIRMS_1 0x62A /* SPI burst read accessible. Registers organized functionally. See BFIRMS. */

◆ ADE9039_REG_BFIRMS_2

#define ADE9039_REG_BFIRMS_2 0x6A0 /* SPI burst read accessible. Registers organized by phase. See BFIRMS. */

◆ ADE9039_REG_BFPF

#define ADE9039_REG_BFPF 0x23E /* Phase B fundamental power factor, updated every 1.024 sec. */

◆ ADE9039_REG_BFVA

#define ADE9039_REG_BFVA 0x235 /* Phase B fundamental apparent power, updated at 4 kSPS. */

◆ ADE9039_REG_BFVA_1

#define ADE9039_REG_BFVA_1 0x627 /* SPI burst read accessible. Registers organized functionally. See BFVA. */

◆ ADE9039_REG_BFVA_2

#define ADE9039_REG_BFVA_2 0x69F /* SPI burst read accessible. Registers organized by phase. See BFVA. */

◆ ADE9039_REG_BFVA_ACC

#define ADE9039_REG_BFVA_ACC 0x353 /* Phase B accumulated fundamental apparent power, updated after kSPS samples. */

◆ ADE9039_REG_BFVAHR_HI

#define ADE9039_REG_BFVAHR_HI 0x355 /* Phase B accumulated fundamental apparent energy, MSB. Updated the settings in the EP_CFG and EGY_TIME registers. */

◆ ADE9039_REG_BFVAHR_LO

#define ADE9039_REG_BFVAHR_LO 0x354 /* Phase B accumulated fundamental apparent energy, LSB. Updated the settings in the EP_CFG and EGY_TIME registers. */

◆ ADE9039_REG_BFVAR

#define ADE9039_REG_BFVAR 0x234 /* Phase B fundamental reactive power, updated at 4 kSPS. */

◆ ADE9039_REG_BFVAR_1

#define ADE9039_REG_BFVAR_1 0x618 /* SPI burst read accessible. Registers organized functionally. See BFVAR. */

◆ ADE9039_REG_BFVAR_2

#define ADE9039_REG_BFVAR_2 0x69A /* SPI burst read accessible. Registers organized by phase. See BFVAR. */

◆ ADE9039_REG_BFVAR_ACC

#define ADE9039_REG_BFVAR_ACC 0x349 /* Phase B accumulated fundamental reactive power, updated after kSPS samples. */

◆ ADE9039_REG_BFVARHR_HI

#define ADE9039_REG_BFVARHR_HI 0x34B /* Phase B accumulated fundamental reactive energy, MSB. Updated the settings in the EP_CFG and EGY_TIME registers. */

◆ ADE9039_REG_BFVARHR_LO

#define ADE9039_REG_BFVARHR_LO 0x34A /* Phase B accumulated fundamental reactive energy, LSB. Updated according settings in the EP_CFG and EGY_TIME registers. */

◆ ADE9039_REG_BFVAROS

#define ADE9039_REG_BFVAROS 0x032 /* Phase B fundamental reactive power offset correction for the BFVAR */

◆ ADE9039_REG_BFVRMS_1

#define ADE9039_REG_BFVRMS_1 0x62D /* SPI burst read accessible. Registers organized functionally. See BFVRMS. */

◆ ADE9039_REG_BFVRMS_2

#define ADE9039_REG_BFVRMS_2 0x6A1 /* SPI burst read accessible. Registers organized by phase. See BFVRMS. */

◆ ADE9039_REG_BFWATT

#define ADE9039_REG_BFWATT 0x233 /* Phase B fundamental active power, updated at 4 kSPS. */

◆ ADE9039_REG_BFWATT_1

#define ADE9039_REG_BFWATT_1 0x624 /* SPI burst read accessible. Registers organized functionally. See BFWATT. */

◆ ADE9039_REG_BFWATT_2

#define ADE9039_REG_BFWATT_2 0x69E /* SPI burst read accessible. Registers organized by phase. See BFWATT. */

◆ ADE9039_REG_BFWATT_ACC

#define ADE9039_REG_BFWATT_ACC 0x33F /* Phase B accumulated fundamental active power, updated after PWR_TIME 4 */

◆ ADE9039_REG_BFWATTHR_HI

#define ADE9039_REG_BFWATTHR_HI 0x341 /* Phase B accumulated fundamental active energy, MSB. Updated according settings in EP_CFG and EGY_TIME registers. */

◆ ADE9039_REG_BFWATTHR_LO

#define ADE9039_REG_BFWATTHR_LO 0x340 /* Phase B accumulated fundamental active energy, LSB. Updated according to in the EP_CFG and EGY_TIME registers. */

◆ ADE9039_REG_BFWATTOS

#define ADE9039_REG_BFWATTOS 0x031 /* Phase B fundamental active power offset correction for the BFWATT */

◆ ADE9039_REG_BI_LPF_DAT

#define ADE9039_REG_BI_LPF_DAT 0x512 /* Current Channel B ADC waveforms from the sinc4 + IIR LPF output at 4 */

◆ ADE9039_REG_BI_PCF

#define ADE9039_REG_BI_PCF 0x22A /* Instantaneous Phase B current channel waveform processed by the DSP at */

◆ ADE9039_REG_BI_PCF_1

#define ADE9039_REG_BI_PCF_1 0x605 /* SPI burst read accessible. Registers organized functionally. See BI_PCF. */

◆ ADE9039_REG_BI_PCF_2

#define ADE9039_REG_BI_PCF_2 0x694 /* SPI burst read accessible. Registers organized by phase. See BI_PCF. */

◆ ADE9039_REG_BI_SINC_DAT

#define ADE9039_REG_BI_SINC_DAT 0x502 /* Current Channel B ADC waveforms from the sinc4 output at 16 kSPS. */

◆ ADE9039_REG_BIFRMS

#define ADE9039_REG_BIFRMS 0x22E /* Phase B current fundamental RMS, updated at 4 kSPS. */

◆ ADE9039_REG_BIFRMSOS

#define ADE9039_REG_BIFRMSOS 0x033 /* Phase B current RMS offset for the fundamental current RMS, BIFRMS */

◆ ADE9039_REG_BIGAIN

#define ADE9039_REG_BIGAIN 0x020 /* Phase B current gain adjust. */

◆ ADE9039_REG_BIGAIN0

#define ADE9039_REG_BIGAIN0

Value:

0x021 /* Phase B multipoint gain correction factor. If multipoint gain and phase enabled, with MTEN = 1 in the CONFIG0 register, an factor,

BIGAIN0 through BIGAIN4, is applied based on the RMS amplitude, and the MTTHR_Lx and MTTHR_Hx register */

◆ ADE9039_REG_BIGAIN1

#define ADE9039_REG_BIGAIN1 0x022 /* See the BIGAIN0 description. */

◆ ADE9039_REG_BIGAIN2

#define ADE9039_REG_BIGAIN2 0x023 /* See the BIGAIN0 description. */

◆ ADE9039_REG_BIGAIN3

#define ADE9039_REG_BIGAIN3 0x024 /* See the BIGAIN0 description. */

◆ ADE9039_REG_BIGAIN4

#define ADE9039_REG_BIGAIN4 0x025 /* See the BIGAIN0 description. */

◆ ADE9039_REG_BIRMS

#define ADE9039_REG_BIRMS 0x22C /* Phase B filter-based current RMS value, updated at 4 kSPS. */

◆ ADE9039_REG_BIRMS_1

#define ADE9039_REG_BIRMS_1 0x608 /* SPI burst read accessible. Registers organized functionally. See BIRMS. */

◆ ADE9039_REG_BIRMS_2

#define ADE9039_REG_BIRMS_2 0x695 /* SPI burst read accessible. Registers organized by phase. See BIRMS. */

◆ ADE9039_REG_BIRMSONE

#define ADE9039_REG_BIRMSONE 0x239 /* Phase B current fast RMS½ calculation, one cycle RMS updated every half */

◆ ADE9039_REG_BIRMSONE_1

#define ADE9039_REG_BIRMSONE_1 0x630 /* SPI burst read accessible. Registers organized functionally. See */

◆ ADE9039_REG_BIRMSONE_2

#define ADE9039_REG_BIRMSONE_2 0x6A2 /* SPI burst read accessible. Registers organized by phase. See BIRMSONE. */

◆ ADE9039_REG_BIRMSONEOS

#define ADE9039_REG_BIRMSONEOS 0x036 /* Phase B current RMS offset for the fast BIRMSONE calculation. */

◆ ADE9039_REG_BIRMSOS

#define ADE9039_REG_BIRMSOS 0x02C /* Phase B current RMS offset for the BIRMS calculation. */

◆ ADE9039_REG_BITHD

#define ADE9039_REG_BITHD 0x238 /* Phase B current THD, updated every 1.024 sec. */

◆ ADE9039_REG_BITHD_1

#define ADE9039_REG_BITHD_1 0x621 /* SPI burst read accessible. Registers organized functionally. See BITHD. */

◆ ADE9039_REG_BITHD_2

#define ADE9039_REG_BITHD_2 0x69D /* SPI burst read accessible. Registers organized by phase. See BITHD. */

◆ ADE9039_REG_BMTREGION

#define ADE9039_REG_BMTREGION 0x23D /* If multipoint gain and phase compensation is enabled, with MTEN = 1 in the this register indicates which BIGAINx and BPHCALx is used. */

◆ ADE9039_REG_BPERIOD

#define ADE9039_REG_BPERIOD 0x419 /* Line period on Phase B voltage. */

◆ ADE9039_REG_BPF

#define ADE9039_REG_BPF 0x236 /* Phase B total power factor, updated every 1.024 sec. */

◆ ADE9039_REG_BPF_1

#define ADE9039_REG_BPF_1 0x61B /* SPI burst read accessible. Registers organized functionally. See BPF. */

◆ ADE9039_REG_BPF_2

#define ADE9039_REG_BPF_2 0x69B /* SPI burst read accessible. Registers organized by phase. See BPF. */

◆ ADE9039_REG_BPGAIN

#define ADE9039_REG_BPGAIN 0x02E /* Phase B power gain adjust for the BWATT, BVA, BFWATT, BFVA, and */

◆ ADE9039_REG_BPHCAL0

#define ADE9039_REG_BPHCAL0 0x026 /* Phase B multipoint phase correction factor. If multipoint phase and gain disabled, with MTEN = 0 in the CONFIG0 register, the */

◆ ADE9039_REG_BPHCAL1

#define ADE9039_REG_BPHCAL1 0x027 /* See the BPHCAL0 description. */

◆ ADE9039_REG_BPHCAL2

#define ADE9039_REG_BPHCAL2 0x028 /* See the BPHCAL0 description. */

◆ ADE9039_REG_BPHCAL3

#define ADE9039_REG_BPHCAL3 0x029 /* See the BPHCAL0 description. */

◆ ADE9039_REG_BPHCAL4

#define ADE9039_REG_BPHCAL4 0x02A /* See the BPHCAL0 description. */

◆ ADE9039_REG_BQUADINFO

#define ADE9039_REG_BQUADINFO 0x23F /* Phase B power quadrant measurement information. */

◆ ADE9039_REG_BV_LPF_DAT

#define ADE9039_REG_BV_LPF_DAT 0x513 /* Voltage Channel B ADC waveforms from the sinc4 + IIR LPF output at 4 */

◆ ADE9039_REG_BV_PCF

#define ADE9039_REG_BV_PCF 0x22B /* Instantaneous Phase B voltage channel waveform processed by the DSP at */

◆ ADE9039_REG_BV_PCF_1

#define ADE9039_REG_BV_PCF_1 0x601 /* SPI burst read accessible. Registers organized functionally. See BV_PCF. */

◆ ADE9039_REG_BV_PCF_2

#define ADE9039_REG_BV_PCF_2 0x693 /* SPI burst read accessible. Registers organized by phase. See BV_PCF. */

◆ ADE9039_REG_BV_SINC_DAT

#define ADE9039_REG_BV_SINC_DAT 0x503 /* Voltage Channel B ADC waveforms from the sinc4 output at 16 kSPS. */

◆ ADE9039_REG_BVA

#define ADE9039_REG_BVA 0x232 /* Phase B total apparent power, updated at 4 kSPS. */

◆ ADE9039_REG_BVA_1

#define ADE9039_REG_BVA_1 0x612 /* SPI burst read accessible. Registers organized functionally. See BVA. */

◆ ADE9039_REG_BVA_2

#define ADE9039_REG_BVA_2 0x698 /* SPI burst read accessible. Registers organized by phase. See BVA. */

◆ ADE9039_REG_BVA_ACC

#define ADE9039_REG_BVA_ACC 0x335 /* Phase B accumulated total apparent power, updated after PWR_TIME 4 */

◆ ADE9039_REG_BVAHR_HI

#define ADE9039_REG_BVAHR_HI 0x337 /* Phase B accumulated total apparent energy, MSB. Updated according to the the EP_CFG and EGY_TIME registers. */

◆ ADE9039_REG_BVAHR_LO

#define ADE9039_REG_BVAHR_LO 0x336 /* Phase B accumulated total apparent energy, LSB. Updated according to the the EP_CFG and EGY_TIME registers. */

◆ ADE9039_REG_BVFRMS

#define ADE9039_REG_BVFRMS 0x22F /* Phase B voltage fundamental RMS, updated at 4 kSPS. */

◆ ADE9039_REG_BVFRMSOS

#define ADE9039_REG_BVFRMSOS 0x034 /* Phase B voltage RMS offset for the fundamental voltage RMS, BVFRMS */

◆ ADE9039_REG_BVGAIN

#define ADE9039_REG_BVGAIN 0x02B /* Phase B voltage gain adjust. */

◆ ADE9039_REG_BVRMS

#define ADE9039_REG_BVRMS 0x22D /* Phase B filter-based voltage RMS value, updated at 4 kSPS. */

◆ ADE9039_REG_BVRMS_1

#define ADE9039_REG_BVRMS_1 0x60B /* SPI burst read accessible. Registers organized functionally. See BVRMS. */

◆ ADE9039_REG_BVRMS_2

#define ADE9039_REG_BVRMS_2 0x696 /* SPI burst read accessible. Registers organized by phase. See BVRMS. */

◆ ADE9039_REG_BVRMSONE

#define ADE9039_REG_BVRMSONE 0x23A /* Phase B voltage fast RMS½ calculation, one cycle RMS updated every half */

◆ ADE9039_REG_BVRMSONE_1

#define ADE9039_REG_BVRMSONE_1 0x633 /* SPI burst read accessible. Registers organized functionally. See */

◆ ADE9039_REG_BVRMSONE_2

#define ADE9039_REG_BVRMSONE_2 0x6A3 /* SPI burst read accessible. Registers organized by phase. See BVRMSONE. */

◆ ADE9039_REG_BVRMSONEOS

#define ADE9039_REG_BVRMSONEOS 0x035 /* Phase B voltage RMS offset for the fast BVRMSONE calculation. */

◆ ADE9039_REG_BVRMSOS

#define ADE9039_REG_BVRMSOS 0x02D /* Phase B voltage RMS offset for the BVRMS calculation. */

◆ ADE9039_REG_BVTHD

#define ADE9039_REG_BVTHD 0x237 /* Phase B voltage THD, updated every 1.024 sec. */

◆ ADE9039_REG_BVTHD_1

#define ADE9039_REG_BVTHD_1 0x61E /* SPI burst read accessible. Registers organized functionally. See BVTHD. */

◆ ADE9039_REG_BVTHD_2

#define ADE9039_REG_BVTHD_2 0x69C /* SPI burst read accessible. Registers organized by phase. See BVTHD. */

◆ ADE9039_REG_BWATT

#define ADE9039_REG_BWATT 0x230 /* Phase B low-pass filtered total active power, updated at 4 kSPS. */

◆ ADE9039_REG_BWATT_1

#define ADE9039_REG_BWATT_1 0x60F /* SPI burst read accessible. Registers organized functionally. See BWATT. */

◆ ADE9039_REG_BWATT_2

#define ADE9039_REG_BWATT_2 0x697 /* SPI burst read accessible. Registers organized by phase. See BWATT. */

◆ ADE9039_REG_BWATT_ACC

#define ADE9039_REG_BWATT_ACC 0x321 /* Phase B accumulated total active power, updated after PWR_TIME 4 kSPS */

◆ ADE9039_REG_BWATTHR_HI

#define ADE9039_REG_BWATTHR_HI 0x323 /* Phase B accumulated total active energy, MSB. Updated according to the the EP_CFG and EGY_TIME registers. */

◆ ADE9039_REG_BWATTHR_LO

#define ADE9039_REG_BWATTHR_LO 0x322 /* Phase B accumulated total active energy, LSB. Updated according to the the EP_CFG and EGY_TIME registers. */

◆ ADE9039_REG_BWATTOS

#define ADE9039_REG_BWATTOS 0x02F /* Phase B total active power offset correction for the BWATT calculation. */

◆ ADE9039_REG_CECCOEF

#define ADE9039_REG_CECCOEF 0x059 /* Phase C coupling coefficient used to compensate for the electrostatic the Analog Devices PCB-based di/dt sensor. Format is 5.27. */

◆ ADE9039_REG_CF1DEN

#define ADE9039_REG_CF1DEN 0x494 /* CF1 denominator register. */

◆ ADE9039_REG_CF2DEN

#define ADE9039_REG_CF2DEN 0x495 /* CF2 denominator register. */

◆ ADE9039_REG_CF3DEN

#define ADE9039_REG_CF3DEN 0x496 /* CF3 denominator register. */

◆ ADE9039_REG_CF4DEN

#define ADE9039_REG_CF4DEN 0x497 /* CF4 denominator register. */

◆ ADE9039_REG_CF_LCFG

#define ADE9039_REG_CF_LCFG 0x425 /* CFx calibration pulse width configuration register. */

◆ ADE9039_REG_CFIRMS_1

#define ADE9039_REG_CFIRMS_1 0x62B /* SPI burst read accessible. Registers organized functionally. See CFIRMS. */

◆ ADE9039_REG_CFIRMS_2

#define ADE9039_REG_CFIRMS_2 0x6B3 /* SPI burst read accessible. Registers organized by phase. See CFIRMS. */

◆ ADE9039_REG_CFMODE

#define ADE9039_REG_CFMODE 0x490 /* CFx configuration register. */

◆ ADE9039_REG_CFPF

#define ADE9039_REG_CFPF 0x25E /* Phase C fundamental power factor, updated every 1.024 sec. */

◆ ADE9039_REG_CFVA

#define ADE9039_REG_CFVA 0x255 /* Phase C fundamental apparent power, updated at 4 kSPS. */

◆ ADE9039_REG_CFVA_1

#define ADE9039_REG_CFVA_1 0x628 /* SPI burst read accessible. Registers organized functionally. See CFVA. */

◆ ADE9039_REG_CFVA_2

#define ADE9039_REG_CFVA_2 0x6B2 /* SPI burst read accessible. Registers organized by phase. See CFVA. */

◆ ADE9039_REG_CFVA_ACC

#define ADE9039_REG_CFVA_ACC 0x38F /* Phase C accumulated fundamental apparent power, updated after kSPS samples. */

◆ ADE9039_REG_CFVAHR_HI

#define ADE9039_REG_CFVAHR_HI 0x391 /* Phase C accumulated fundamental apparent energy, MSB. Updated the settings in the EP_CFG and EGY_TIME registers. */

◆ ADE9039_REG_CFVAHR_LO

#define ADE9039_REG_CFVAHR_LO 0x390 /* Phase C accumulated fundamental apparent energy, LSB. Updated the settings in the EP_CFG and EGY_TIME registers. */

◆ ADE9039_REG_CFVAR

#define ADE9039_REG_CFVAR 0x254 /* Phase C fundamental reactive power, updated at 4 kSPS. */

◆ ADE9039_REG_CFVAR_1

#define ADE9039_REG_CFVAR_1 0x619 /* SPI burst read accessible. Registers organized functionally. See CFVAR. */

◆ ADE9039_REG_CFVAR_2

#define ADE9039_REG_CFVAR_2 0x6AD /* SPI burst read accessible. Registers organized by phase. See CFVAR. */

◆ ADE9039_REG_CFVAR_ACC

#define ADE9039_REG_CFVAR_ACC 0x385 /* Phase C accumulated fundamental reactive power, updated after kSPS samples. */

◆ ADE9039_REG_CFVARHR_HI

#define ADE9039_REG_CFVARHR_HI 0x387 /* Phase C accumulated fundamental reactive energy, MSB. Updated the settings in the EP_CFG and EGY_TIME registers. */

◆ ADE9039_REG_CFVARHR_LO

#define ADE9039_REG_CFVARHR_LO 0x386 /* Phase C accumulated fundamental reactive energy, LSB. Updated according settings in the EP_CFG and EGY_TIME registers. */

◆ ADE9039_REG_CFVAROS

#define ADE9039_REG_CFVAROS 0x052 /* Phase C fundamental reactive power offset correction for the CFVAR */

◆ ADE9039_REG_CFVRMS_1

#define ADE9039_REG_CFVRMS_1 0x62E /* SPI burst read accessible. Registers organized functionally. See CFVRMS. */

◆ ADE9039_REG_CFVRMS_2

#define ADE9039_REG_CFVRMS_2 0x6B4 /* SPI burst read accessible. Registers organized by phase. See CFVRMS. */

◆ ADE9039_REG_CFWATT

#define ADE9039_REG_CFWATT 0x253 /* Phase C fundamental active power, updated at 4 kSPS. */

◆ ADE9039_REG_CFWATT_1

#define ADE9039_REG_CFWATT_1 0x625 /* SPI burst read accessible. Registers organized functionally. See CFWATT. */

◆ ADE9039_REG_CFWATT_2

#define ADE9039_REG_CFWATT_2 0x6B1 /* SPI burst read accessible. Registers organized by phase. See CFWATT. */

◆ ADE9039_REG_CFWATT_ACC

#define ADE9039_REG_CFWATT_ACC 0x37B /* Phase C accumulated fundamental active power, updated after PWR_TIME samples. */

◆ ADE9039_REG_CFWATTHR_HI

#define ADE9039_REG_CFWATTHR_HI 0x37D /* Phase C accumulated fundamental active energy, MSB. Updated according settings in the EP_CFG and EGY_TIME registers. */

◆ ADE9039_REG_CFWATTHR_LO

#define ADE9039_REG_CFWATTHR_LO 0x37C /* Phase C accumulated fundamental active energy, LSB. Updated according settings in the EP_CFG and EGY_TIME registers. */

◆ ADE9039_REG_CFWATTOS

#define ADE9039_REG_CFWATTOS 0x051 /* Phase C fundamental active power offset correction for the CFWATT */

◆ ADE9039_REG_CHNL_DIS

#define ADE9039_REG_CHNL_DIS 0x4BA /* ADC channel enable/disable. */

◆ ADE9039_REG_CI_LPF_DAT

#define ADE9039_REG_CI_LPF_DAT 0x514 /* Current Channel C ADC waveforms from the sinc4 + IIR LPF output at 4 */

◆ ADE9039_REG_CI_PCF

#define ADE9039_REG_CI_PCF 0x24A /* Instantaneous Phase C current channel waveform processed by the DSP at */

◆ ADE9039_REG_CI_PCF_1

#define ADE9039_REG_CI_PCF_1 0x606 /* SPI burst read accessible. Registers organized functionally. See CI_PCF. */

◆ ADE9039_REG_CI_PCF_2

#define ADE9039_REG_CI_PCF_2 0x6A7 /* SPI burst read accessible. Registers organized by phase. See CI_PCF. */

◆ ADE9039_REG_CI_SINC_DAT

#define ADE9039_REG_CI_SINC_DAT 0x504 /* Current Channel C ADC waveforms from the sinc4 output at 16 kSPS. */

◆ ADE9039_REG_CIFRMS

#define ADE9039_REG_CIFRMS 0x24E /* Phase C current fundamental RMS, updated at 4 kSPS. */

◆ ADE9039_REG_CIFRMSOS

#define ADE9039_REG_CIFRMSOS 0x053 /* Phase C current RMS offset for the fundamental current RMS, CIFRMS */

◆ ADE9039_REG_CIGAIN

#define ADE9039_REG_CIGAIN 0x040 /* Phase C current gain adjust. */

◆ ADE9039_REG_CIGAIN0

#define ADE9039_REG_CIGAIN0

Value:

0x041 /* Phase C multipoint gain correction factor. If multipoint gain and phase enabled, with MTEN = 1 in the CONFIG0 register, an factor,

CIGAIN0 through CIGAIN4, is applied based on the RMS amplitude, and the MTTHR_Lx and MTTHR_Hx register */

◆ ADE9039_REG_CIGAIN1

#define ADE9039_REG_CIGAIN1 0x042 /* See the CIGAIN0 description. */

◆ ADE9039_REG_CIGAIN2

#define ADE9039_REG_CIGAIN2 0x043 /* See the CIGAIN0 description. */

◆ ADE9039_REG_CIGAIN3

#define ADE9039_REG_CIGAIN3 0x044 /* See the CIGAIN0 description. */

◆ ADE9039_REG_CIGAIN4

#define ADE9039_REG_CIGAIN4 0x045 /* See the CIGAIN0 description. */

◆ ADE9039_REG_CIRMS

#define ADE9039_REG_CIRMS 0x24C /* Phase C filter-based current RMS value, updated at 4 kSPS. */

◆ ADE9039_REG_CIRMS_1

#define ADE9039_REG_CIRMS_1 0x609 /* SPI burst read accessible. Registers organized functionally. See CIRMS. */

◆ ADE9039_REG_CIRMS_2

#define ADE9039_REG_CIRMS_2 0x6A8 /* SPI burst read accessible. Registers organized by phase. See CIRMS. */

◆ ADE9039_REG_CIRMSONE

#define ADE9039_REG_CIRMSONE 0x259 /* Phase C current fast RMS½ calculation, one cycle RMS updated every half */

◆ ADE9039_REG_CIRMSONE_1

#define ADE9039_REG_CIRMSONE_1 0x631 /* SPI burst read accessible. Registers organized functionally. See */

◆ ADE9039_REG_CIRMSONE_2

#define ADE9039_REG_CIRMSONE_2 0x6B5 /* SPI burst read accessible. Registers organized by phase. See CIRMSONE. */

◆ ADE9039_REG_CIRMSONEOS

#define ADE9039_REG_CIRMSONEOS 0x056 /* Phase C current RMS offset for the fast CIRMSONE calculation. */

◆ ADE9039_REG_CIRMSOS

#define ADE9039_REG_CIRMSOS 0x04C /* Phase C current RMS offset for the CIRMS calculation. */

◆ ADE9039_REG_CITHD

#define ADE9039_REG_CITHD 0x258 /* Phase C current total THD, updated every 1.024 sec. */

◆ ADE9039_REG_CITHD_1

#define ADE9039_REG_CITHD_1 0x622 /* SPI burst read accessible. Registers organized functionally. See CITHD. */

◆ ADE9039_REG_CITHD_2

#define ADE9039_REG_CITHD_2 0x6B0 /* SPI burst read accessible. Registers organized by phase. See CITHD. */

◆ ADE9039_REG_CMTREGION

#define ADE9039_REG_CMTREGION 0x25D /* If multipoint gain and phase compensation is enabled, with MTEN = 1 in register, these bits indicate which CIGAINx and CPHCALx is used. */

◆ ADE9039_REG_COM_PERIOD

#define ADE9039_REG_COM_PERIOD 0x41B /* Line period measurement on combined signal from Phase A, Phase B, and voltages. */

◆ ADE9039_REG_COMPMODE

#define ADE9039_REG_COMPMODE 0x491 /* Computation mode register. */

◆ ADE9039_REG_CONFIG0

#define ADE9039_REG_CONFIG0 0x060 /* Configuration Register 0. DSP measurements configuration register. */

◆ ADE9039_REG_CONFIG1

#define ADE9039_REG_CONFIG1 0x481 /* Configuration Register 1. */

◆ ADE9039_REG_CONFIG2

#define ADE9039_REG_CONFIG2 0x4AF /* Configuration Register 2. */

◆ ADE9039_REG_CONFIG3

#define ADE9039_REG_CONFIG3 0x493 /* Configuration Register 3. */

◆ ADE9039_REG_CONFIG5

#define ADE9039_REG_CONFIG5 0x4A4 /* Configuration Register 5. */

◆ ADE9039_REG_CPERIOD

#define ADE9039_REG_CPERIOD 0x41A /* Line period on Phase C voltage. */

◆ ADE9039_REG_CPF

#define ADE9039_REG_CPF 0x256 /* Phase C total power factor, updated every 1.024 sec. */

◆ ADE9039_REG_CPF_1

#define ADE9039_REG_CPF_1 0x61C /* SPI burst read accessible. Registers organized functionally. See CPF. */

◆ ADE9039_REG_CPF_2

#define ADE9039_REG_CPF_2 0x6AE /* SPI burst read accessible. Registers organized by phase. See CPF. */

◆ ADE9039_REG_CPGAIN

#define ADE9039_REG_CPGAIN 0x04E /* Phase C power gain adjust for the CWATT, CVA, CFWATT, CFVA, and */

◆ ADE9039_REG_CPHCAL0

#define ADE9039_REG_CPHCAL0

Value:

                        0x046 /* Phase C multipoint phase correction factor. If multipoint phase and gain disabled, with MTEN = 0 in the CONFIG0 register, the
                        compensation is applied. If multipoint phase and gain enabled, with MTEN = 1, the CPHCAL0 through CPHCAL4 applied, based on the
                        CIRMS current RMS amplitude, and the MTTHR_Hx register values. */

◆ ADE9039_REG_CPHCAL1

#define ADE9039_REG_CPHCAL1 0x047 /* See the CPHCAL0 description. */

◆ ADE9039_REG_CPHCAL2

#define ADE9039_REG_CPHCAL2 0x048 /* See the CPHCAL0 description. */

◆ ADE9039_REG_CPHCAL3

#define ADE9039_REG_CPHCAL3 0x049 /* See the CPHCAL0 description. */

◆ ADE9039_REG_CPHCAL4

#define ADE9039_REG_CPHCAL4 0x04A /* See the CPHCAL0 description. */

◆ ADE9039_REG_CQUADINFO

#define ADE9039_REG_CQUADINFO 0x25F /* Phase C quadrant measurement information. */

◆ ADE9039_REG_CRC_FORCE

#define ADE9039_REG_CRC_FORCE 0x4B4 /* This register forces an update of the CRC of configuration registers. */

◆ ADE9039_REG_CRC_OPTEN

#define ADE9039_REG_CRC_OPTEN 0x4B5 /* This register selects which registers are optionally included in the CRC feature. */

◆ ADE9039_REG_CRC_RSLT

#define ADE9039_REG_CRC_RSLT 0x4A8 /* This register holds the CRC of the configuration registers. */

◆ ADE9039_REG_CRC_SPI

#define ADE9039_REG_CRC_SPI 0x4A9 /* This register holds the 16-bit CRC of the data sent out on the MOSI pin last SPI register read. */

◆ ADE9039_REG_CV_LPF_DAT

#define ADE9039_REG_CV_LPF_DAT 0x515 /* Voltage Channel C ADC waveforms from the sinc4 + IIR LPF output at 4 */

◆ ADE9039_REG_CV_PCF

#define ADE9039_REG_CV_PCF 0x24B /* Instantaneous Phase C voltage channel waveform processed by the DSP at */

◆ ADE9039_REG_CV_PCF_1

#define ADE9039_REG_CV_PCF_1 0x602 /* SPI burst read accessible. Registers organized functionally. See CV_PCF. */

◆ ADE9039_REG_CV_PCF_2

#define ADE9039_REG_CV_PCF_2 0x6A6 /* SPI burst read accessible. Registers organized by phase. See CV_PCF. */

◆ ADE9039_REG_CV_SINC_DAT

#define ADE9039_REG_CV_SINC_DAT 0x505 /* Voltage Channel C ADC waveforms from the sinc4 output at 16 kSPS. */

◆ ADE9039_REG_CVA

#define ADE9039_REG_CVA 0x252 /* Phase C total apparent power, updated at 4 kSPS. */

◆ ADE9039_REG_CVA_1

#define ADE9039_REG_CVA_1 0x613 /* SPI burst read accessible. Registers organized functionally. See CVA. */

◆ ADE9039_REG_CVA_2

#define ADE9039_REG_CVA_2 0x6AB /* SPI burst read accessible. Registers organized by phase. See CVA. */

◆ ADE9039_REG_CVA_ACC

#define ADE9039_REG_CVA_ACC 0x371 /* Phase C accumulated total apparent power, updated after PWR_TIME 4 */

◆ ADE9039_REG_CVAHR_HI

#define ADE9039_REG_CVAHR_HI 0x373 /* Phase C accumulated total apparent energy, MSB. Updated according to the the EP_CFG and EGY_TIME registers. */

◆ ADE9039_REG_CVAHR_LO

#define ADE9039_REG_CVAHR_LO 0x372 /* Phase C accumulated total apparent energy, LSB. Updated according to the the EP_CFG and EGY_TIME registers. */

◆ ADE9039_REG_CVFRMS

#define ADE9039_REG_CVFRMS 0x24F /* Phase C voltage fundamental RMS, updated at 4 kSPS. */

◆ ADE9039_REG_CVFRMSOS

#define ADE9039_REG_CVFRMSOS 0x054 /* Phase C voltage RMS offset for the fundamental voltage RMS, CVFRMS */

◆ ADE9039_REG_CVGAIN

#define ADE9039_REG_CVGAIN 0x04B /* Phase C voltage gain adjust. */

◆ ADE9039_REG_CVRMS

#define ADE9039_REG_CVRMS 0x24D /* Phase C filter-based voltage RMS value, updated at 4 kSPS. */

◆ ADE9039_REG_CVRMS_1

#define ADE9039_REG_CVRMS_1 0x60C /* SPI burst read accessible. Registers organized functionally. See CVRMS. */

◆ ADE9039_REG_CVRMS_2

#define ADE9039_REG_CVRMS_2 0x6A9 /* SPI burst read accessible. Registers organized by phase. See CVRMS. */

◆ ADE9039_REG_CVRMSONE

#define ADE9039_REG_CVRMSONE 0x25A /* Phase C voltage fast RMS½ calculation, one cycle RMS updated every half */

◆ ADE9039_REG_CVRMSONE_1

#define ADE9039_REG_CVRMSONE_1 0x634 /* SPI burst read accessible. Registers organized functionally. See */

◆ ADE9039_REG_CVRMSONE_2

#define ADE9039_REG_CVRMSONE_2 0x6B6 /* SPI burst read accessible. Registers organized by phase. See CVRMSONE. */

◆ ADE9039_REG_CVRMSONEOS

#define ADE9039_REG_CVRMSONEOS 0x055 /* Phase C voltage RMS offset for the fast CVRMSONE calculation. */

◆ ADE9039_REG_CVRMSOS

#define ADE9039_REG_CVRMSOS 0x04D /* Phase C voltage RMS offset for the CVRMS calculation. */

◆ ADE9039_REG_CVTHD

#define ADE9039_REG_CVTHD 0x257 /* Phase C voltage THD, updated every 1.024 sec. */

◆ ADE9039_REG_CVTHD_1

#define ADE9039_REG_CVTHD_1 0x61F /* SPI burst read accessible. Registers organized functionally. See CVTHD. */

◆ ADE9039_REG_CVTHD_2

#define ADE9039_REG_CVTHD_2 0x6AF /* SPI burst read accessible. Registers organized by phase. See CVTHD. */

◆ ADE9039_REG_CWATT

#define ADE9039_REG_CWATT 0x250 /* Phase C low-pass filtered total active power, updated at 4 kSPS. */

◆ ADE9039_REG_CWATT_1

#define ADE9039_REG_CWATT_1 0x610 /* SPI burst read accessible. Registers organized functionally. See CWATT. */

◆ ADE9039_REG_CWATT_2

#define ADE9039_REG_CWATT_2 0x6AA /* SPI burst read accessible. Registers organized by phase. See CWATT. */

◆ ADE9039_REG_CWATT_ACC

#define ADE9039_REG_CWATT_ACC 0x35D /* Phase C accumulated total active power, updated after PWR_TIME 4 kSPS */

◆ ADE9039_REG_CWATTHR_HI

#define ADE9039_REG_CWATTHR_HI 0x35F /* Phase C accumulated total active energy, MSB. Updated according to the the EP_CFG and EGY_TIME registers. */

◆ ADE9039_REG_CWATTHR_LO

#define ADE9039_REG_CWATTHR_LO 0x35E /* Phase C accumulated total active energy, LSB. Updated according to the the EP_CFG and EGY_TIME registers. */

◆ ADE9039_REG_CWATTOS

#define ADE9039_REG_CWATTOS 0x04F /* Phase C total active power offset correction for the CWATT calculation. */

◆ ADE9039_REG_DICOEFF

#define ADE9039_REG_DICOEFF

Value:

0x072 /* Value used in the digital integrator algorithm. If the integrator is turned INTEN or ININTEN equal to one in the CONFIG0 register,

it is set this value to 0x0. */

◆ ADE9039_REG_DIP_CYC

#define ADE9039_REG_DIP_CYC 0x48B /* Voltage RMS½ dip detection cycle configuration. */

◆ ADE9039_REG_DIP_LVL

#define ADE9039_REG_DIP_LVL 0x410 /* Voltage RMS½ dip detection threshold level. */

◆ ADE9039_REG_DIPA

#define ADE9039_REG_DIPA 0x411 /* Phase A voltage RMS½ value during a dip condition. */

◆ ADE9039_REG_DIPB

#define ADE9039_REG_DIPB 0x412 /* Phase B voltage RMS½ value during a dip condition. */

◆ ADE9039_REG_DIPC

#define ADE9039_REG_DIPC 0x413 /* Phase C voltage RMS½ value during a dip condition. */

◆ ADE9039_REG_DIPLVL

#define ADE9039_REG_DIPLVL NO_OS_GENMASK(23, 0)

◆ ADE9039_REG_EGY_TIME

#define ADE9039_REG_EGY_TIME 0x4B2 /* Energy accumulation update time configuration. */

◆ ADE9039_REG_EP_CFG

#define ADE9039_REG_EP_CFG 0x4B0 /* Energy and power accumulation configuration. */

◆ ADE9039_REG_EVENT_MASK

#define ADE9039_REG_EVENT_MASK 0x407 /* Event enable register. */

◆ ADE9039_REG_EVENT_STATUS

#define ADE9039_REG_EVENT_STATUS 0x404 /* Event status register. */

◆ ADE9039_REG_FVARTHR

#define ADE9039_REG_FVARTHR

Value:

0x421 /* Sets the maximum output rate from the digital to frequency converter for reactive power for the CFx calibration pulse output.

It is write VARTHR = 0x0010_0000. */

◆ ADE9039_REG_IPEAK

#define ADE9039_REG_IPEAK 0x400 /* Current peak register. */

◆ ADE9039_REG_ISUMLVL

#define ADE9039_REG_ISUMLVL 0x073 /* Threshold to compare ISUMRMS against. Configure this register to receive indication in the STATUS0 register if ISUMRMS exceeds this */

◆ ADE9039_REG_ISUMRMS

#define ADE9039_REG_ISUMRMS 0x269 /* Filter-based RMS based on the sum of IA + IB + IC ± IN. */

◆ ADE9039_REG_ISUMRMSOS

#define ADE9039_REG_ISUMRMSOS 0x06C /* Offset correction for the ISUMRMS calculation based on the sum of IA + IB + IN. */

◆ ADE9039_REG_LAST_CMD

#define ADE9039_REG_LAST_CMD 0x4AE /* This register holds the address and read/write operation request the last transaction on the SPI port. */

◆ ADE9039_REG_LAST_DATA_16

#define ADE9039_REG_LAST_DATA_16 0x4AC /* This register holds the data read or written during the last 16-bit transaction SPI port. */

◆ ADE9039_REG_LAST_DATA_32

#define ADE9039_REG_LAST_DATA_32 0x423 /* This register holds the data read or written during the last 32-bit transaction SPI port. */

◆ ADE9039_REG_MASK0

#define ADE9039_REG_MASK0 0x405 /* Interrupt Enable Register 0. */

◆ ADE9039_REG_MASK1

#define ADE9039_REG_MASK1 0x406 /* Interrupt Enable Register 1. */

◆ ADE9039_REG_MTTHR_H0

#define ADE9039_REG_MTTHR_H0 0x066 /* Multipoint phase/gain threshold. See MTTHR_L0 for more information. */

◆ ADE9039_REG_MTTHR_H1

#define ADE9039_REG_MTTHR_H1 0x067 /* Multipoint phase/gain threshold. See MTTHR_L0 for more information. */

◆ ADE9039_REG_MTTHR_H2

#define ADE9039_REG_MTTHR_H2 0x068 /* Multipoint phase/gain threshold. See MTTHR_L0 for more information. */

◆ ADE9039_REG_MTTHR_H3

#define ADE9039_REG_MTTHR_H3 0x069 /* Multipoint phase/gain threshold. See MTTHR_L0 for more information. */

◆ ADE9039_REG_MTTHR_H4

#define ADE9039_REG_MTTHR_H4 0x06A /* Multipoint phase/gain threshold. See MTTHR_L0 for more information. */

◆ ADE9039_REG_MTTHR_L0

#define ADE9039_REG_MTTHR_L0

Value:

0x061 /* Multipoint phase/gain threshold. If MTEN = 1 in the CONFIG0 register, the MTTHR_Hx registers set up the ranges in which to apply of

corrections, allowing hysteresis. */

◆ ADE9039_REG_MTTHR_L1

#define ADE9039_REG_MTTHR_L1 0x062 /* Multipoint phase/gain threshold. See MTTHR_L0 for more information. */

◆ ADE9039_REG_MTTHR_L2

#define ADE9039_REG_MTTHR_L2 0x063 /* Multipoint phase/gain threshold. See MTTHR_L0 for more information. */

◆ ADE9039_REG_MTTHR_L3

#define ADE9039_REG_MTTHR_L3 0x064 /* Multipoint phase/gain threshold. See MTTHR_L0 for more information. */

◆ ADE9039_REG_MTTHR_L4

#define ADE9039_REG_MTTHR_L4 0x065 /* Multipoint phase/gain threshold. See MTTHR_L0 for more information. */

◆ ADE9039_REG_NI_LPF_DAT

#define ADE9039_REG_NI_LPF_DAT 0x516 /* Neutral current channel ADC waveforms from the sinc4 + IIR LPF output at 4 */

◆ ADE9039_REG_NI_PCF

#define ADE9039_REG_NI_PCF 0x265 /* Instantaneous neutral current channel waveform processed by the DSP at 4 */

◆ ADE9039_REG_NI_PCF_1

#define ADE9039_REG_NI_PCF_1 0x603 /* SPI burst read accessible. Registers organized functionally. See NI_PCF. */

◆ ADE9039_REG_NI_PCF_2

#define ADE9039_REG_NI_PCF_2 0x6B9 /* SPI burst read accessible. Registers organized by phase. See NI_PCF. */

◆ ADE9039_REG_NI_SINC_DAT

#define ADE9039_REG_NI_SINC_DAT 0x506 /* Neutral current channel ADC waveforms from the sinc4 output at 16 kSPS. */

◆ ADE9039_REG_NIGAIN

#define ADE9039_REG_NIGAIN 0x06D /* Neutral current gain adjust. */

◆ ADE9039_REG_NIRMS

#define ADE9039_REG_NIRMS 0x266 /* Neutral current filter-based RMS value. */

◆ ADE9039_REG_NIRMS_1

#define ADE9039_REG_NIRMS_1 0x60D /* SPI burst read accessible. Registers organized functionally. See NIRMS. */

◆ ADE9039_REG_NIRMS_2

#define ADE9039_REG_NIRMS_2 0x6BA /* SPI burst read accessible. Registers organized by phase. See NIRMS. */

◆ ADE9039_REG_NIRMSONE

#define ADE9039_REG_NIRMSONE 0x267 /* Neutral current fast RMS½ calculation, one cycle RMS updated every half */

◆ ADE9039_REG_NIRMSONE_1

#define ADE9039_REG_NIRMSONE_1 0x635 /* SPI burst read accessible. Registers organized functionally. See */

◆ ADE9039_REG_NIRMSONE_2

#define ADE9039_REG_NIRMSONE_2 0x6BB /* SPI burst read accessible. Registers organized by phase. See NIRMSONE. */

◆ ADE9039_REG_NIRMSONEOS

#define ADE9039_REG_NIRMSONEOS 0x06F /* Neutral current RMS offset for the fast RMS½ NIRMSONE calculation. */

◆ ADE9039_REG_NIRMSOS

#define ADE9039_REG_NIRMSOS 0x06B /* Neutral current RMS offset for the NIRMS calculation. */

◆ ADE9039_REG_NPHCAL

#define ADE9039_REG_NPHCAL 0x06E /* Neutral current phase compensation. */

◆ ADE9039_REG_NWATT_ACC

#define ADE9039_REG_NWATT_ACC 0x39B /* Accumulated Negative total active power, MSB, from AWATT, BWATT, and updated after PWR_TIME 4 kSPS samples. */

◆ ADE9039_REG_OIA

#define ADE9039_REG_OIA

Value:

0x40A /* Phase A overcurrent RMS½ value. If a phase is enabled, with the OC_EN bit set in the CONFIG3 register and AIRMSONE greater

than the this value is updated. */

◆ ADE9039_REG_OIB

#define ADE9039_REG_OIB

Value:

0x40B /* Phase B overcurrent RMS½ value. If a phase is enabled, with the OC_EN bit set in the CONFIG3 register and BIRMSONE greater

than the this value is updated. */

◆ ADE9039_REG_OIC

#define ADE9039_REG_OIC

Value:

0x40C /* Phase C overcurrent RMS½ value. If a phase is enabled, with the OC_EN bit set in the CONFIG3 register and CIRMSONE greater

than the this value is updated. */

◆ ADE9039_REG_OILVL

#define ADE9039_REG_OILVL 0x409 /* Overcurrent detection threshold level. */

◆ ADE9039_REG_OIN

#define ADE9039_REG_OIN

Value:

0x40D /* Neutral current overcurrent RMS½ value. If enabled, with the OC_EN neutral set in the CONFIG3 register and NIRMSONE greater

than the this value is updated. */

◆ ADE9039_REG_OISTATUS

#define ADE9039_REG_OISTATUS 0x48F /* Overcurrent status register. */

◆ ADE9039_REG_PART_ID

#define ADE9039_REG_PART_ID 0x472 /* This register identifies the IC. If the ADE9039_ID bit = 1, after the run bit has the IC is the ADE9039. */

◆ ADE9039_REG_PGA_GAIN

#define ADE9039_REG_PGA_GAIN 0x4B9 /* This register configures the PGA gain for each ADC. */

◆ ADE9039_REG_PHNOLOAD

#define ADE9039_REG_PHNOLOAD 0x41F /* Phase no load register. */

◆ ADE9039_REG_PHSIGN

#define ADE9039_REG_PHSIGN 0x49D /* Power sign register. */

◆ ADE9039_REG_PWATT_ACC

#define ADE9039_REG_PWATT_ACC 0x397 /* Accumulated positive total active power, MSB, from AWATT, BWATT, and updated after PWR_TIME 4 kSPS samples. */

◆ ADE9039_REG_PWR_TIME

#define ADE9039_REG_PWR_TIME 0x4B1 /* Power update time configuration. */

◆ ADE9039_REG_REACT_NL_LVL

#define ADE9039_REG_REACT_NL_LVL 0x41D /* No load threshold in the fundamental reactive power datapath. */

◆ ADE9039_REG_RESAMPLE_LAST_CY

#define ADE9039_REG_RESAMPLE_LAST_CY 0x26C /* cycle index. A value between 0 to 7. This register contains the the last cycle resampled. */

◆ ADE9039_REG_RESAMPLE_RESET_A

#define ADE9039_REG_RESAMPLE_RESET_A 0x26B /* the waveform buffer when WF_CAP_EN bit is reset or disabled. */

◆ ADE9039_REG_RUN

#define ADE9039_REG_RUN 0x480 /* This is the DSP run register. Write 0x1 to this register to start measurements. */

◆ ADE9039_REG_SEQ_CYC

#define ADE9039_REG_SEQ_CYC 0x49C /* Number of line cycles used for phase sequence detection. It is recommended this register to 1. */

◆ ADE9039_REG_STATUS0

#define ADE9039_REG_STATUS0 0x402 /* Status Register 0. */

◆ ADE9039_REG_STATUS1

#define ADE9039_REG_STATUS1 0x403 /* Status Register 1. */

◆ ADE9039_REG_SWELL_CYC

#define ADE9039_REG_SWELL_CYC 0x48C /* Voltage RMS½ swell detection cycle configuration. */

◆ ADE9039_REG_SWELL_LVL

#define ADE9039_REG_SWELL_LVL 0x414 /* Voltage RMS½ swell detection threshold level. */

◆ ADE9039_REG_SWELLA

#define ADE9039_REG_SWELLA 0x415 /* Phase A voltage RMS½ value during a swell condition. */

◆ ADE9039_REG_SWELLB

#define ADE9039_REG_SWELLB 0x416 /* Phase B voltage RMS½ value during a swell condition. */

◆ ADE9039_REG_SWELLC

#define ADE9039_REG_SWELLC 0x417 /* Phase C voltage RMS½ value during a swell condition. */

◆ ADE9039_REG_TEMP_CFG

#define ADE9039_REG_TEMP_CFG 0x4B6 /* Temperature sensor configuration register. */

◆ ADE9039_REG_TEMP_RSLT

#define ADE9039_REG_TEMP_RSLT 0x4B7 /* Temperature measurement result. */

◆ ADE9039_REG_TEMP_TRIM

#define ADE9039_REG_TEMP_TRIM 0x474 /* Temperature sensor gain and offset, calculated during the manufacturing */

◆ ADE9039_REG_TFVARHR

#define ADE9039_REG_TFVARHR 0x26E /* The sum of the fundamental reactive energy of Phase A, Phase B, and when the related bits are enabled in the CONFIG0. */

◆ ADE9039_REG_TWATTHR

#define ADE9039_REG_TWATTHR 0x26D /* The sum of the total active energy of Phase A, Phase B, and Phase C when bits are enabled in the CONFIG0. */

◆ ADE9039_REG_USER_PERIOD

#define ADE9039_REG_USER_PERIOD 0x40E /* User configured line period value used for resampling and fast RMS½ when bit in the CONFIG2 register is set. */

◆ ADE9039_REG_VATHR

#define ADE9039_REG_VATHR

Value:

0x422 /* Sets the maximum output rate from the digital to frequency converter for the fundamental apparent power for the CFx calibration

pulse output. It to write VATHR = 0x0010_0000. */

◆ ADE9039_REG_VERSION

#define ADE9039_REG_VERSION 0x4FE /* This is the chip version of the ADE9039 IC. */

◆ ADE9039_REG_VERSION2

#define ADE9039_REG_VERSION2 0x26A /* This register indicates the version of the metrology algorithms after the user = 1 to start the measurements. */

◆ ADE9039_REG_VLEVEL

#define ADE9039_REG_VLEVEL 0x40F /* Register used in the algorithm that computes the fundamental active, apparent powers as well as the fundamental IRMS and VRMS */

◆ ADE9039_REG_VNOM

#define ADE9039_REG_VNOM 0x071 /* Nominal phase voltage RMS used in the computation of apparent power, the VNOMx_EN bit is set in the CONFIG0 register. */

◆ ADE9039_REG_VPEAK

#define ADE9039_REG_VPEAK 0x401 /* Voltage peak register. */

◆ ADE9039_REG_WFB_CFG

#define ADE9039_REG_WFB_CFG 0x4A0 /* Waveform buffer configuration register. */

◆ ADE9039_REG_WFB_PG_IRQEN

#define ADE9039_REG_WFB_PG_IRQEN 0x4A1 /* This register enables interrupts to occur after specific pages of the waveform filled. */

◆ ADE9039_REG_WFB_TRG_CFG

#define ADE9039_REG_WFB_TRG_CFG 0x4A2 /* This register enables events to trigger a capture in the waveform buffer. */

◆ ADE9039_REG_WFB_TRG_STAT

#define ADE9039_REG_WFB_TRG_STAT 0x4A3 /* This register indicates the last page that was filled in the waveform buffer and of trigger events. */

◆ ADE9039_REG_WR_LOCK

#define ADE9039_REG_WR_LOCK 0x4BF /* This register enables the configuration lock feature. */

◆ ADE9039_REG_WTHR

#define ADE9039_REG_WTHR

Value:

0x420 /* Sets the maximum output rate from the digital to frequency converter for the fundamental active power for the CFx calibration

pulse output. It is write WTHR = 0x0010_0000. */

◆ ADE9039_REG_ZX_LP_SEL

#define ADE9039_REG_ZX_LP_SEL 0x49A /* This register selects which zero crossing and which line period measurement for other calculations. */

◆ ADE9039_REG_ZXTHRSH

#define ADE9039_REG_ZXTHRSH 0x499 /* Voltage channel zero-crossing threshold register. */

◆ ADE9039_REG_ZXTOUT

#define ADE9039_REG_ZXTOUT 0x498 /* Zero-crossing timeout configuration register. */

◆ ADE9039_RESET_RECOVER

#define ADE9039_RESET_RECOVER 100

◆ ADE9039_RMS_FS_CODES

#define ADE9039_RMS_FS_CODES 52866837

◆ ADE9039_RMS_SRC_SEL

#define ADE9039_RMS_SRC_SEL NO_OS_BIT(7)

◆ ADE9039_RUN_ON

#define ADE9039_RUN_ON 0x0001

◆ ADE9039_SELFREQ

#define ADE9039_SELFREQ NO_OS_BIT(8)

◆ ADE9039_SPI_READ

#define ADE9039_SPI_READ NO_OS_BIT(3)

◆ ADE9039_STATUS0_CF1

#define ADE9039_STATUS0_CF1 NO_OS_BIT(11)

◆ ADE9039_STATUS0_CF2

#define ADE9039_STATUS0_CF2 NO_OS_BIT(12)

◆ ADE9039_STATUS0_CF3

#define ADE9039_STATUS0_CF3 NO_OS_BIT(13)

◆ ADE9039_STATUS0_CF4

#define ADE9039_STATUS0_CF4 NO_OS_BIT(14)

◆ ADE9039_STATUS0_COH_CYCLE_DONE

#define ADE9039_STATUS0_COH_CYCLE_DONE NO_OS_BIT(23)

◆ ADE9039_STATUS0_DREADY

#define ADE9039_STATUS0_DREADY NO_OS_BIT(15)

◆ ADE9039_STATUS0_EGYRDY

#define ADE9039_STATUS0_EGYRDY NO_OS_BIT(0)

◆ ADE9039_STATUS0_MISMTCH

#define ADE9039_STATUS0_MISMTCH NO_OS_BIT(24)

◆ ADE9039_STATUS0_PAGE_FULL

#define ADE9039_STATUS0_PAGE_FULL NO_OS_BIT(17)

◆ ADE9039_STATUS0_PWRRDY

#define ADE9039_STATUS0_PWRRDY NO_OS_BIT(18)

◆ ADE9039_STATUS0_REVAPA

#define ADE9039_STATUS0_REVAPA NO_OS_BIT(1)

◆ ADE9039_STATUS0_REVAPB

#define ADE9039_STATUS0_REVAPB NO_OS_BIT(2)

◆ ADE9039_STATUS0_REVAPC

#define ADE9039_STATUS0_REVAPC NO_OS_BIT(3)

◆ ADE9039_STATUS0_REVPSUM1

#define ADE9039_STATUS0_REVPSUM1 NO_OS_BIT(7)

◆ ADE9039_STATUS0_REVPSUM2

#define ADE9039_STATUS0_REVPSUM2 NO_OS_BIT(8)

◆ ADE9039_STATUS0_REVPSUM3

#define ADE9039_STATUS0_REVPSUM3 NO_OS_BIT(9)

◆ ADE9039_STATUS0_REVPSUM4

#define ADE9039_STATUS0_REVPSUM4 NO_OS_BIT(10)

◆ ADE9039_STATUS0_REVRPA

#define ADE9039_STATUS0_REVRPA NO_OS_BIT(4)

◆ ADE9039_STATUS0_REVRPB

#define ADE9039_STATUS0_REVRPB NO_OS_BIT(5)

◆ ADE9039_STATUS0_REVRPC

#define ADE9039_STATUS0_REVRPC NO_OS_BIT(6)

◆ ADE9039_STATUS0_RMSONEREDY

#define ADE9039_STATUS0_RMSONEREDY NO_OS_BIT(19)

◆ ADE9039_STATUS0_TEMP_RDY

#define ADE9039_STATUS0_TEMP_RDY NO_OS_BIT(25)

◆ ADE9039_STATUS0_THD_PF_RDY

#define ADE9039_STATUS0_THD_PF_RDY NO_OS_BIT(21)

◆ ADE9039_STATUS0_WFB_TRIG

#define ADE9039_STATUS0_WFB_TRIG NO_OS_BIT(22)

◆ ADE9039_STATUS0_WFB_TRIG_IRQ

#define ADE9039_STATUS0_WFB_TRIG_IRQ NO_OS_BIT(16)

◆ ADE9039_STATUS1_AFNOLOAD

#define ADE9039_STATUS1_AFNOLOAD NO_OS_BIT(3)

◆ ADE9039_STATUS1_ANLOAD

#define ADE9039_STATUS1_ANLOAD NO_OS_BIT(0)

◆ ADE9039_STATUS1_CRC_CHG

#define ADE9039_STATUS1_CRC_CHG NO_OS_BIT(26)

◆ ADE9039_STATUS1_CRC_DONE

#define ADE9039_STATUS1_CRC_DONE NO_OS_BIT(27)

◆ ADE9039_STATUS1_DIPA

#define ADE9039_STATUS1_DIPA NO_OS_BIT(23)

◆ ADE9039_STATUS1_DIPB

#define ADE9039_STATUS1_DIPB NO_OS_BIT(24)

◆ ADE9039_STATUS1_DIPC

#define ADE9039_STATUS1_DIPC NO_OS_BIT(25)

◆ ADE9039_STATUS1_ERROR0

#define ADE9039_STATUS1_ERROR0 NO_OS_BIT(28)

◆ ADE9039_STATUS1_ERROR1

#define ADE9039_STATUS1_ERROR1 NO_OS_BIT(29)

◆ ADE9039_STATUS1_ERROR2

#define ADE9039_STATUS1_ERROR2 NO_OS_BIT(30)

◆ ADE9039_STATUS1_ERROR3

#define ADE9039_STATUS1_ERROR3 NO_OS_BIT(31)

◆ ADE9039_STATUS1_OI

#define ADE9039_STATUS1_OI NO_OS_BIT(17)

◆ ADE9039_STATUS1_RFNOLOAD

#define ADE9039_STATUS1_RFNOLOAD NO_OS_BIT(4)

◆ ADE9039_STATUS1_RSTDONE

#define ADE9039_STATUS1_RSTDONE NO_OS_BIT(16)

◆ ADE9039_STATUS1_SEQERR

#define ADE9039_STATUS1_SEQERR NO_OS_BIT(18)

◆ ADE9039_STATUS1_SWELLA

#define ADE9039_STATUS1_SWELLA NO_OS_BIT(20)

◆ ADE9039_STATUS1_SWELLB

#define ADE9039_STATUS1_SWELLB NO_OS_BIT(21)

◆ ADE9039_STATUS1_SWELLC

#define ADE9039_STATUS1_SWELLC NO_OS_BIT(22)

◆ ADE9039_STATUS1_VAFNOLOAD

#define ADE9039_STATUS1_VAFNOLOAD NO_OS_BIT(5)

◆ ADE9039_STATUS1_VANLOAD

#define ADE9039_STATUS1_VANLOAD NO_OS_BIT(2)

◆ ADE9039_STATUS1_ZXCOMB

#define ADE9039_STATUS1_ZXCOMB NO_OS_BIT(12)

◆ ADE9039_STATUS1_ZXIA

#define ADE9039_STATUS1_ZXIA NO_OS_BIT(13)

◆ ADE9039_STATUS1_ZXIB

#define ADE9039_STATUS1_ZXIB NO_OS_BIT(14)

◆ ADE9039_STATUS1_ZXIC

#define ADE9039_STATUS1_ZXIC NO_OS_BIT(15)

◆ ADE9039_STATUS1_ZXTOVA

#define ADE9039_STATUS1_ZXTOVA NO_OS_BIT(6)

◆ ADE9039_STATUS1_ZXTOVB

#define ADE9039_STATUS1_ZXTOVB NO_OS_BIT(7)

◆ ADE9039_STATUS1_ZXTOVC

#define ADE9039_STATUS1_ZXTOVC NO_OS_BIT(8)

◆ ADE9039_STATUS1_ZXVA

#define ADE9039_STATUS1_ZXVA NO_OS_BIT(9)

◆ ADE9039_STATUS1_ZXVB

#define ADE9039_STATUS1_ZXVB NO_OS_BIT(10)

◆ ADE9039_STATUS1_ZXVC

#define ADE9039_STATUS1_ZXVC NO_OS_BIT(11)

◆ ADE9039_SUM1SIGN

#define ADE9039_SUM1SIGN NO_OS_BIT(6)

◆ ADE9039_SUM2SIGN

#define ADE9039_SUM2SIGN NO_OS_BIT(7)

◆ ADE9039_SUM3SIGN

#define ADE9039_SUM3SIGN NO_OS_BIT(8)

◆ ADE9039_SUM4SIGN

#define ADE9039_SUM4SIGN NO_OS_BIT(9)

◆ ADE9039_SWELL

#define ADE9039_SWELL NO_OS_BIT(1)

◆ ADE9039_SWELLA_VAL

#define ADE9039_SWELLA_VAL NO_OS_GENMASK(23, 0)

◆ ADE9039_SWELLB_VAL

#define ADE9039_SWELLB_VAL NO_OS_GENMASK(23, 0)

◆ ADE9039_SWELLC_VAL

#define ADE9039_SWELLC_VAL NO_OS_GENMASK(23, 0)

◆ ADE9039_SWELLLVL

#define ADE9039_SWELLLVL NO_OS_GENMASK(23, 0)

◆ ADE9039_SWRST

#define ADE9039_SWRST NO_OS_BIT(0)

◆ ADE9039_TEMP_EN

#define ADE9039_TEMP_EN NO_OS_BIT(2)

◆ ADE9039_TEMP_GAIN

#define ADE9039_TEMP_GAIN NO_OS_GENMASK(15, 0)

◆ ADE9039_TEMP_OFFSET

#define ADE9039_TEMP_OFFSET NO_OS_GENMASK(31, 16)

◆ ADE9039_TEMP_RSLT

#define ADE9039_TEMP_RSLT NO_OS_GENMASK(11, 0)

◆ ADE9039_TEMP_START

#define ADE9039_TEMP_START NO_OS_BIT(3)

◆ ADE9039_TEMP_TIME

#define ADE9039_TEMP_TIME NO_OS_GENMASK(1, 0)

◆ ADE9039_TERMSEL1

#define ADE9039_TERMSEL1 NO_OS_GENMASK(2, 0)

◆ ADE9039_TERMSEL2

#define ADE9039_TERMSEL2 NO_OS_GENMASK(5, 3)

◆ ADE9039_TERMSEL3

#define ADE9039_TERMSEL3 NO_OS_GENMASK(8, 6)

◆ ADE9039_TERMSEL4

#define ADE9039_TERMSEL4 NO_OS_GENMASK(11, 9)

◆ ADE9039_TRIG_FORCE

#define ADE9039_TRIG_FORCE NO_OS_BIT(10)

◆ ADE9039_UP_RES

#define ADE9039_UP_RES 990000

◆ ADE9039_UPERIOD_SEL

#define ADE9039_UPERIOD_SEL NO_OS_BIT(12)

◆ ADE9039_VA_DIN

#define ADE9039_VA_DIN NO_OS_GENMASK(14, 12)

◆ ADE9039_VA_DISADC

#define ADE9039_VA_DISADC NO_OS_BIT(4)

◆ ADE9039_VA_GAIN

#define ADE9039_VA_GAIN NO_OS_GENMASK(9, 8)

◆ ADE9039_VARACC

#define ADE9039_VARACC NO_OS_GENMASK(3, 2)

◆ ADE9039_VB_DIN

#define ADE9039_VB_DIN NO_OS_GENMASK(17, 15)

◆ ADE9039_VB_DISADC

#define ADE9039_VB_DISADC NO_OS_BIT(5)

◆ ADE9039_VB_GAIN

#define ADE9039_VB_GAIN NO_OS_GENMASK(11, 10)

◆ ADE9039_VC_DIN

#define ADE9039_VC_DIN NO_OS_GENMASK(20, 18)

◆ ADE9039_VC_DISADC

#define ADE9039_VC_DISADC NO_OS_BIT(6)

◆ ADE9039_VC_GAIN

#define ADE9039_VC_GAIN NO_OS_GENMASK(13, 12)

◆ ADE9039_VCONSEL

#define ADE9039_VCONSEL NO_OS_GENMASK(6, 4)

◆ ADE9039_VLEVEL

#define ADE9039_VLEVEL 0x00144084

◆ ADE9039_VLEVEL_VAL

#define ADE9039_VLEVEL_VAL NO_OS_GENMASK(23, 0)

◆ ADE9039_VNOMA_EN

#define ADE9039_VNOMA_EN NO_OS_BIT(8)

◆ ADE9039_VNOMB_EN

#define ADE9039_VNOMB_EN NO_OS_BIT(9)

◆ ADE9039_VNOMC_EN

#define ADE9039_VNOMC_EN NO_OS_BIT(10)

◆ ADE9039_VOLTAGE_TR_FCN

#define ADE9039_VOLTAGE_TR_FCN ((ADE9039_DOWN_RES + ADE9039_UP_RES) / ADE9039_DOWN_RES)

◆ ADE9039_VPEAKVAL

#define ADE9039_VPEAKVAL NO_OS_GENMASK(23, 0)

◆ ADE9039_VPPHASE

#define ADE9039_VPPHASE NO_OS_GENMASK(26, 24)

◆ ADE9039_WATT_FS_CODES

#define ADE9039_WATT_FS_CODES 20823646

◆ ADE9039_WATTACC

#define ADE9039_WATTACC NO_OS_GENMASK(1, 0)

◆ ADE9039_WF_CAP_EN

#define ADE9039_WF_CAP_EN NO_OS_BIT(4)

◆ ADE9039_WF_CAP_SEL

#define ADE9039_WF_CAP_SEL NO_OS_BIT(5)

◆ ADE9039_WF_IN_EN

#define ADE9039_WF_IN_EN NO_OS_BIT(12)

◆ ADE9039_WF_MODE

#define ADE9039_WF_MODE NO_OS_GENMASK(7, 6)

◆ ADE9039_WF_SRC

#define ADE9039_WF_SRC NO_OS_GENMASK(9, 8)

◆ ADE9039_WFB_CFG

#define ADE9039_WFB_CFG 0x1000

◆ ADE9039_WFB_LAST_PAGE

#define ADE9039_WFB_LAST_PAGE NO_OS_GENMASK(15, 12)

◆ ADE9039_WFB_TRIG_ADDR

#define ADE9039_WFB_TRIG_ADDR NO_OS_GENMASK(10, 0)

◆ ADE9039_ZX_LP_SEL

#define ADE9039_ZX_LP_SEL 0x001E

◆ ADE9039_ZX_SEL

#define ADE9039_ZX_SEL NO_OS_GENMASK(2, 1)

◆ ADE9039_ZX_SRC_SEL

#define ADE9039_ZX_SRC_SEL NO_OS_BIT(6)

◆ ADE9039_ZXCOMB

#define ADE9039_ZXCOMB NO_OS_BIT(9)

◆ ADE9039_ZXIA

#define ADE9039_ZXIA NO_OS_BIT(3)

◆ ADE9039_ZXIB

#define ADE9039_ZXIB NO_OS_BIT(4)

◆ ADE9039_ZXIC

#define ADE9039_ZXIC NO_OS_BIT(5)

◆ ADE9039_ZXVA

#define ADE9039_ZXVA NO_OS_BIT(6)

◆ ADE9039_ZXVB

#define ADE9039_ZXVB NO_OS_BIT(7)

◆ ADE9039_ZXVC

#define ADE9039_ZXVC NO_OS_BIT(8)

◆ DISABLE

#define DISABLE 0x0000

◆ ENABLE

#define ENABLE 0x0001

◆ WFB_ELEMENT_ARRAY_SIZE

#define WFB_ELEMENT_ARRAY_SIZE 512

Enumeration Type Documentation

◆ ade9039_aregion_sel_e

enum ade9039_aregion_sel_e

ADE9039 These bits indicate which AIGAINx and APHCALx is currently being used.

Enumerator
ADE9039_AIGAIN_APHCAL_0
ADE9039_AIGAIN_APHCAL_1
ADE9039_AIGAIN_APHCAL_2
ADE9039_AIGAIN_APHCAL_3
ADE9039_AIGAIN_APHCAL_4
ADE9039_AIGAIN_APHCAL_DISABLE

◆ ade9039_bregion_sel_e

enum ade9039_bregion_sel_e

ADE9039 These bits indicate which BIGAINx and BPHCALx is currently being used.

Enumerator
ADE9039_BIGAIN_BPHCAL_0
ADE9039_BIGAIN_BPHCAL_1
ADE9039_BIGAIN_BPHCAL_2
ADE9039_BIGAIN_BPHCAL_3
ADE9039_BIGAIN_BPHCAL_4
ADE9039_BIGAIN_BPHCAL_DISABLE

◆ ade9039_burst_ch_e

enum ade9039_burst_ch_e

Selects which data to read out of the waveform buffer through SPI.

Enumerator
ADE9039_BURST_ALL_CH
ADE9039_BURST_IA_VA
ADE9039_BURST_IB_VB
ADE9039_BURST_IC_VC
ADE9039_BURST_IA
ADE9039_BURST_VA
ADE9039_BURST_IB
ADE9039_BURST_VB
ADE9039_BURST_IC
ADE9039_BURST_VC
ADE9039_BURST_IN
ADE9039_BURST_DISABLED

◆ ade9039_cf4_pin_out_cfg_e

enum ade9039_cf4_pin_out_cfg_e

ADE9039 These bits indicate which function to output on CF4 pin.

Enumerator
ADE9039_CF4_D_F_CONV
ADE9039_CF4_D_F_CONV2
ADE9039_CF4_EVENT
ADE9039_CF4_DREADY

◆ ade9039_cf4_sel_e

enum ade9039_cf4_sel_e

ADE9039 Type of energy output on the CF4 pin. Configure TERMSEL4 in the COMPMODE register to select which phases are included.

Enumerator
ADE9039_CF4_SEL_ACTIV_P
ADE9039_CF4_SEL_APPARENT_P
ADE9039_CF4_SEL_FUNDAMENTAL_ACTIVE_P
ADE9039_CF4_SEL_FUN_REACTIVE_P
ADE9039_CF4_SEL_FUN_APPARENT_P
ADE9039_CF4_SEL_TOTAL_ACTIVE_P
ADE9039_CF4_SEL_TOTAL_ACTIVE_P_2

◆ ade9039_cregion_sel_e

enum ade9039_cregion_sel_e

ADE9039 These bits indicate which CIGAINx and CPHCALx is currently being used.

Enumerator
ADE9039_CIGAIN_CPHCAL_0
ADE9039_CIGAIN_CPHCAL_1
ADE9039_CIGAIN_CPHCAL_2
ADE9039_CIGAIN_CPHCAL_3
ADE9039_CIGAIN_CPHCAL_4
ADE9039_CIGAIN_CPHCAL_DISABLE

◆ ade9039_egy_model

enum ade9039_egy_model

ADE9039 available user energy use models.

Enumerator
ADE9039_EGY_WITH_RESET
ADE9039_EGY_HALF_LINE_CYCLES
ADE9039_EGY_NR_SAMPLES

◆ ade9039_freq_sel_e

enum ade9039_freq_sel_e

ADE9039 Freq value.

Enumerator
ADE9039_SELFREQ_50
ADE9039_SELFREQ_60

◆ ade9039_hpf_freq_e

enum ade9039_hpf_freq_e

High-pass filter corner (f3dB) enabled when the HPFDIS bit in the CONFIG0 register is equal to zero.

Enumerator
ADE9039_HPF_0_2
ADE9039_HPF_1
ADE9039_HPF_3
ADE9039_HPF_6
ADE9039_HPF_10
ADE9039_HPF_12
ADE9039_HPF_18
ADE9039_HPF_21_6

◆ ade9039_isum_cfg_e

enum ade9039_isum_cfg_e

ADE9039 isum calculation configuration.

Enumerator
ADE9039_ISUM_APROX_N
ADE9039_ISUM_DET_MISM_POS
ADE9039_ISUM_DET_MISM_NEG
ADE9039_ISUM_APROX_N_RMS

◆ ade9039_line_period_sel_e

enum ade9039_line_period_sel_e

Selects line period measurement used for VRMS½ cycle, 10 cycle rms/12 cycle rms, and resampling.

Enumerator
ADE9039_APERIOD
ADE9039_BPERIOD
ADE9039_CPERIOD
ADE9039_COM_PERIOD

◆ ade9039_no_load_tmr_e

enum ade9039_no_load_tmr_e

This register configures how many 4 kSPS samples to evaluate the no load condition over.

Enumerator
ADE9039_NOLOAD_SAMPLES_64
ADE9039_NOLOAD_SAMPLES_128
ADE9039_NOLOAD_SAMPLES_256
ADE9039_NOLOAD_SAMPLES_512
ADE9039_NOLOAD_SAMPLES_1024
ADE9039_NOLOAD_SAMPLES_2048
ADE9039_NOLOAD_SAMPLES_4096
ADE9039_NOLOAD_SAMPLES_DISABLE

◆ ade9039_oiphase_e

enum ade9039_oiphase_e

ADE9039 indicates that a phase is above OILVL.

Enumerator
ADE9039_OIPHASE_A
ADE9039_OIPHASE_B
ADE9039_OIPHASE_C
ADE9039_OIPHASE_N

◆ ade9039_phase

enum ade9039_phase

ADE9039 available phases.

Enumerator
ADE9039_PHASE_A
ADE9039_PHASE_B
ADE9039_PHASE_C

◆ ade9039_power_mode_e

enum ade9039_power_mode_e

ADE9039 Power mode selection.

Enumerator
NORMAL_MODE
TAMPER_MODE
CURRENT_PEAK_DETECT_MODE
IDLE_MODE

◆ ade9039_pwr_settle_e

enum ade9039_pwr_settle_e

ADE9039 Power settle time.

Enumerator
ADE9039_PWR_SETTLE_0
ADE9039_PWR_SETTLE_1
ADE9039_PWR_SETTLE_2
ADE9039_PWR_SETTLE_3

◆ ade9039_temp_time_e

enum ade9039_temp_time_e

ADE9039 Temperature measurement time.

Enumerator
ADE9039_TEMP_TIME_1
ADE9039_TEMP_TIME_256
ADE9039_TEMP_TIME_512
ADE9039_TEMP_TIME_1024

◆ ade9039_var_acc_mode_e

enum ade9039_var_acc_mode_e

ADE9039 Total and fundamental reactive power accumulation mode for energy registers and CFx pulses.

Enumerator
ADE9039_ACC_SIGNED
ADE9039_ACC_ABSOLUTE
ADE9039_ACC_POSITIVE
ADE9039_ACC_NEGATIVE

◆ ade9039_vc_gain_e

enum ade9039_vc_gain_e

ADE9039 PGA gain for Voltage Channel C ADC.

Enumerator
ADE9039_VC_GAIN_1
ADE9039_VC_GAIN_2
ADE9039_VC_GAIN_4
ADE9039_VC_GAIN_4_2

◆ ade9039_vconsel_e

enum ade9039_vconsel_e

ADE9039 3-wire and 4-wire hardware configuration selection.

Enumerator
ADE9039_4WIRE_WYE
ADE9039_3WIRE_DELTA
ADE9039_4WIRE_WYE_VA_VC
ADE9039_4WIRE_WYE_VA
ADE9039_3WIRE_DELTA_2

◆ ade9039_wf_mode_e

enum ade9039_wf_mode_e

Fixed data rate waveforms filling and trigger based modes.

Enumerator
ADE9039_MODE_STOP_FULL
ADE9039_MODE_TRIG_EN_EVENTS
ADE9039_MODE_CENTER_CAPTURE
ADE9039_MODE_SAVE_EVENT_ADDR

◆ ade9039_wf_src_e

enum ade9039_wf_src_e

Waveform buffer source and DREADY (data ready update rate) selection.

Enumerator
ADE9039_SRC_SINC4
ADE9039_SRC_SINC4_IIR
ADE9039_SRC_DSP

◆ ade9039_zx_select_e

enum ade9039_zx_select_e

Selects the zero-crossing signal, which can be routed to the CF3/ZX output pin and used for line cycle energy accumulation.

Enumerator
ADE9039_ZXVA_SEL
ADE9039_ZXVB_SEL
ADE9039_ZXVC_SEL
ADE9039_ZXCOMB_SEL

Function Documentation

◆ ade9039_check_bit_status()

int ade9039_check_bit_status	(	struct ade9039_dev *	dev,
		uint16_t	reg_addr,
		uint32_t	bit_mask,
		uint8_t *	status )

Check bit status of a register.

Parameters

dev	- The device structure.
reg_addr	- The register address.
bit_mask	- The bit mask to check.
status	- The status of the bit (1 if set, 0 if not).

Returns: 0 in case of success, negative error code otherwise.

◆ ade9039_get_int_status0()

int ade9039_get_int_status0	(	struct ade9039_dev *	dev,
		uint32_t	msk,
		uint8_t *	status )

Get interrupt indicator from STATUS0 register.

Parameters

dev	- The device structure.
msk	- Interrupt mask.
status	- Status indicator.

Returns: 0 in case of success, negative error code otherwise.

◆ ade9039_init()

int ade9039_init	(	struct ade9039_dev **	device,
		struct ade9039_init_param	init_param )

Initialize the device.

Parameters

device	- The device structure.
init_param	- The structure that contains the device initial parameters.

Returns: 0 in case of success, negative error code otherwise.

◆ ade9039_read()

int ade9039_read	(	struct ade9039_dev *	dev,
		uint16_t	reg_addr,
		uint32_t *	reg_data )

Read device register.

Parameters

dev	- The device structure.
reg_addr	- The register address.
reg_data	- The data read from the register.

Returns: 0 in case of success, negative error code otherwise.

◆ ade9039_read_energy_ph()

int ade9039_read_energy_ph	(	struct ade9039_dev *	dev,
		enum ade9039_phase	phase )

Read the energy values for a specific phase.

Parameters

dev	- The device structure.
phase	- ADE9039 Phase.

Returns: 0 in case of success, negative error code otherwise.

◆ ade9039_read_power_factor_ph()

int ade9039_read_power_factor_ph	(	struct ade9039_dev *	dev,
		enum ade9039_phase	phase )

Read the power factor values for a specific phase.

Parameters

dev	- The device structure.
phase	- ADE9039 Phase.

Returns: 0 in case of success, negative error code otherwise.

◆ ade9039_read_power_ph()

int ade9039_read_power_ph	(	struct ade9039_dev *	dev,
		enum ade9039_phase	phase )

Read the power values for a specific phase.

Parameters

dev	- The device structure.
phase	- ADE9039 Phase.

Returns: 0 in case of success, negative error code otherwise.

◆ ade9039_read_rms_ph()

int ade9039_read_rms_ph	(	struct ade9039_dev *	dev,
		enum ade9039_phase	phase )

Read the rms values for a specific phase.

Parameters

dev	- The device structure.
phase	- ADE9039 Phase.

Returns: 0 in case of success, negative error code otherwise.

◆ ade9039_read_temp()

int ade9039_read_temp ( struct ade9039_dev * dev )

Read the ADE9039 temperature using the conversion ready status.

Parameters

dev	- The ADE9039 device structure.

Returns: 0 in case of success, negative error code otherwise.

◆ ade9039_remove()

int ade9039_remove ( struct ade9039_dev * dev )

Remove the device and release resources.

Parameters

dev	- The device structure.

Returns: 0 in case of success, negative error code otherwise.

◆ ade9039_set_egy_model()

int ade9039_set_egy_model	(	struct ade9039_dev *	dev,
		enum ade9039_egy_model	model,
		uint16_t	value )

Set User Energy use model.

Parameters

dev	- The device structure.
model	- The User Energy use model to be set.
value	- value specific to the user energy use model, it can be either 1 for reading with reset, number of half line cycles or number of samples.

Returns: 0 in case of success, negative error code otherwise.

◆ ade9039_set_power_mode()

int ade9039_set_power_mode ( struct ade9039_dev * dev )

Set power mode.

Parameters

dev	- The device structure.

Returns: 0 in case of success, negative error code otherwise.

◆ ade9039_setup()

int ade9039_setup ( struct ade9039_dev * dev )

Setup the device.

Parameters

dev	- The device structure.

Returns: 0 in case of success, negative error code otherwise.

◆ ade9039_update_bits()

int ade9039_update_bits	(	struct ade9039_dev *	dev,
		uint16_t	reg_addr,
		uint32_t	mask,
		uint32_t	reg_data )

Update specific register bits.

Parameters

dev	- The device structure.
reg_addr	- The register address.
mask	- Specific bits mask.
reg_data	- The data to be written.

Returns: 0 in case of success, negative error code otherwise.

◆ ade9039_write()

int ade9039_write	(	struct ade9039_dev *	dev,
		uint16_t	reg_addr,
		uint32_t	reg_data )

Write device register.

Parameters

dev-	The device structure.
reg_addr	- The register address.
reg_data	- The data to be written.

Returns: 0 in case of success, negative error code otherwise.

Classes

Macros

Enumerations

Functions

Detailed Description

Macro Definition Documentation

◆ ADE9039_A_TFVARHR_EN

◆ ADE9039_A_TWATTHR_EN

◆ ADE9039_ACCMODE

◆ ADE9039_ADE9039_ID

◆ ADE9039_AFVANL

◆ ADE9039_AFVARNL

◆ ADE9039_AREGION

◆ ADE9039_AVANL

◆ ADE9039_AVARSIGN

◆ ADE9039_AWATTNL

◆ ADE9039_AWSIGN

◆ ADE9039_B_TFVARHR_EN

◆ ADE9039_B_TWATTHR_EN

◆ ADE9039_BFVANL

◆ ADE9039_BFVARNL

◆ ADE9039_BFWATTNL

◆ ADE9039_BREGION

◆ ADE9039_BURDEN_RES

◆ ADE9039_BURST_CHAN

◆ ADE9039_BURST_EN

◆ ADE9039_BVANL

◆ ADE9039_BVARSIGN

◆ ADE9039_BWATTNL

◆ ADE9039_BWSIGN

◆ ADE9039_C_TFVARHR_EN

◆ ADE9039_C_TWATTHR_EN

◆ ADE9039_CF1_LT

◆ ADE9039_CF1DIS

◆ ADE9039_CF1SEL

◆ ADE9039_CF2_LT

◆ ADE9039_CF2DIS

◆ ADE9039_CF2SEL

◆ ADE9039_CF3_CFG

◆ ADE9039_CF3_LT

◆ ADE9039_CF3DIS

◆ ADE9039_CF3SEL

◆ ADE9039_CF4_CFG

◆ ADE9039_CF4_LT

◆ ADE9039_CF4DIS

◆ ADE9039_CF4SEL

◆ ADE9039_CF_ACC_CLR

◆ ADE9039_CF_LTMR

◆ ADE9039_CFVANL

◆ ADE9039_CFVARNL

◆ ADE9039_CFWATTNL

◆ ADE9039_CHIP_ID

◆ ADE9039_COMPMODE

◆ ADE9039_CONFIG0

◆ ADE9039_CONFIG1

◆ ADE9039_CONFIG2

◆ ADE9039_CONFIG3

◆ ADE9039_CRC_ACT_NL_LVL_EN

◆ ADE9039_CRC_APP_NL_LVL_EN

◆ ADE9039_CRC_DIP_CYC_EN

◆ ADE9039_CRC_DIP_LVL_EN

◆ ADE9039_CRC_EVENT_MASK_EN

◆ ADE9039_CRC_MASK0_EN

◆ ADE9039_CRC_MASK1_EN

◆ ADE9039_CRC_REACT_NL_LVL_EN

◆ ADE9039_CRC_SEQ_CYC_EN

◆ ADE9039_CRC_SWELL_CYC_EN

◆ ADE9039_CRC_SWELL_LVL_EN

◆ ADE9039_CRC_WFB_CFG_EN

◆ ADE9039_CRC_WFB_PG_IRQEN

◆ ADE9039_CRC_WFB_TRG_CFG_EN

◆ ADE9039_CRC_ZXLPSEL_EN

◆ ADE9039_CRC_ZXTOUT_EN

◆ ADE9039_CREGION

◆ ADE9039_CURRENT_TR_FCN

◆ ADE9039_CURRENT_TR_RATIO

◆ ADE9039_CVANL

◆ ADE9039_CVARSIGN

◆ ADE9039_CWATTNL

◆ ADE9039_CWSIGN