|
| #define | ADF4371_WRITE (0 << 15) |
| |
| #define | ADF4371_READ (1 << 15) |
| |
| #define | ADF4371_ADDR(x) ((x) & 0x7FFF) |
| |
| #define | ADF4371_REG(x) (x) |
| |
| #define | ADF4371_ADDR_ASC_MSK NO_OS_BIT(2) |
| |
| #define | ADF4371_ADDR_ASC(x) no_os_field_prep(ADF4371_ADDR_ASC_MSK, x) |
| |
| #define | ADF4371_ADDR_ASC_R_MSK NO_OS_BIT(5) |
| |
| #define | ADF4371_ADDR_ASC_R(x) no_os_field_prep(ADF4371_ADDR_ASC_R_MSK, x) |
| |
| #define | ADF4371_SDO_ACT_MSK NO_OS_BIT(3) |
| |
| #define | ADF4371_SDO_ACT(x) no_os_field_prep(ADF4371_SDO_ACT_MSK, x) |
| |
| #define | ADF4371_SDO_ACT_R_MSK NO_OS_BIT(4) |
| |
| #define | ADF4371_SDO_ACT_R(x) no_os_field_prep(ADF4371_SDO_ACT_R_MSK, x) |
| |
| #define | ADF4371_RESET_CMD 0x81 |
| |
| #define | ADF4371_FRAC2WORD_L_MSK NO_OS_GENMASK(7, 1) |
| |
| #define | ADF4371_FRAC2WORD_L(x) no_os_field_prep(ADF4371_FRAC2WORD_L_MSK, x) |
| |
| #define | ADF4371_FRAC1WORD_MSK NO_OS_BIT(0) |
| |
| #define | ADF4371_FRAC1WORD(x) no_os_field_prep(ADF4371_FRAC1WORD_MSK, x) |
| |
| #define | ADF4371_FRAC2WORD_H_MSK NO_OS_GENMASK(6, 0) |
| |
| #define | ADF4371_FRAC2WORD_H(x) no_os_field_prep(ADF4371_FRAC2WORD_H_MSK, x) |
| |
| #define | ADF4371_MOD2WORD_MSK NO_OS_GENMASK(5, 0) |
| |
| #define | ADF4371_MOD2WORD(x) no_os_field_prep(ADF4371_MOD2WORD_MSK, x) |
| |
| #define | ADF4371_CP_CURRENT_MSK NO_OS_GENMASK(7, 4) |
| |
| #define | ADF4371_CP_CURRENT(x) no_os_field_prep(ADF4371_CP_CURRENT_MSK, x) |
| |
| #define | ADF4371_PD_POL_MSK NO_OS_BIT(3) |
| |
| #define | ADF4371_PD_POL(x) no_os_field_prep(ADF4371_PD_POL_MSK, x) |
| |
| #define | ADF4371_MUXOUT_MSK NO_OS_GENMASK(7, 4) |
| |
| #define | ADF4371_MUXOUT(x) no_os_field_prep(ADF4371_MUXOUT_MSK, x) |
| |
| #define | ADF4371_MUXOUT_LVL_MSK NO_OS_BIT(2) |
| |
| #define | ADF4371_MUXOUT_LVL(x) no_os_field_prep(ADF4371_MUXOUT_LVL_MSK, x) |
| |
| #define | ADF4371_MUXOUT_EN_MSK NO_OS_BIT(3) |
| |
| #define | ADF4371_MUXOUT_EN(x) no_os_field_prep(ADF4371_MUXOUT_EN_MSK, x) |
| |
| #define | ADF4371_REFIN_MODE_MASK NO_OS_BIT(6) |
| |
| #define | ADF4371_REFIN_MODE(x) no_os_field_prep(ADF4371_REFIN_MODE_MASK, x) |
| |
| #define | ADF4371_RF_DIV_SEL_MSK NO_OS_GENMASK(6, 4) |
| |
| #define | ADF4371_RF_DIV_SEL(x) no_os_field_prep(ADF4371_RF_DIV_SEL_MSK, x) |
| |
| #define | ADF4371_MUTE_LD_MSK NO_OS_BIT(7) |
| |
| #define | ADF4371_MUTE_LD(x) no_os_field_prep(ADF4371_MUTE_LD_MSK, x) |
| |
| #define | ADF4371_TIMEOUT_MSK NO_OS_GENMASK(1, 0) |
| |
| #define | ADF4371_TIMEOUT(x) no_os_field_prep(ADF4371_TIMEOUT_MSK, x) |
| |
| #define | ADF4371_VCO_ALC_TOUT_MSK NO_OS_GENMASK(4, 0) |
| |
| #define | ADF4371_VCO_ALC_TOUT(x) no_os_field_prep(ADF4371_VCO_ALC_TOUT_MSK, x) |
| |
| #define | ADF4371_MIN_VCO_FREQ 4000000000ULL /* 4000 MHz */ |
| |
| #define | ADF4371_MAX_VCO_FREQ 8000000000ULL /* 8000 MHz */ |
| |
| #define | ADF4371_MAX_OUT_RF8_FREQ ADF4371_MAX_VCO_FREQ /* Hz */ |
| |
| #define | ADF4371_MIN_OUT_RF8_FREQ (ADF4371_MIN_VCO_FREQ / 64) /* Hz */ |
| |
| #define | ADF4371_MAX_OUT_RF16_FREQ (ADF4371_MAX_VCO_FREQ * 2) /* Hz */ |
| |
| #define | ADF4371_MIN_OUT_RF16_FREQ (ADF4371_MIN_VCO_FREQ * 2) /* Hz */ |
| |
| #define | ADF4371_MAX_OUT_RF32_FREQ (ADF4371_MAX_VCO_FREQ * 4) /* Hz */ |
| |
| #define | ADF4371_MIN_OUT_RF32_FREQ (ADF4371_MIN_VCO_FREQ * 4) /* Hz */ |
| |
| #define | ADF4371_MAX_FREQ_PFD 250000000UL /* Hz */ |
| |
| #define | ADF4371_MAX_FREQ_REFIN 600000000UL /* Hz */ |
| |
| #define | ADF4371_MODULUS1 33554432ULL |
| |
| #define | ADF4371_MAX_MODULUS2 NO_OS_BIT(14) |
| |
| #define | ADF4371_CHECK_RANGE(freq, range) ((freq > ADF4371_MAX_ ## range) || (freq < ADF4371_MIN_ ## range)) |
| |
Implementation of ADF4371 Driver.
- Author
- DBogdan (drago.nosp@m.s.bo.nosp@m.gdan@.nosp@m.anal.nosp@m.og.co.nosp@m.m)
Copyright 2020(c) Analog Devices, Inc.
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