altera_a10_atx_pll.c File Reference

Driver for the Altera ATX PLL dynamic reconfiguration. More...

#include <limits.h>
#include "no_os_util.h"
#include "altera_a10_atx_pll.h"

Include dependency graph for altera_a10_atx_pll.c:

Macros
#define	A10_ATX_PLL_PFD_MIN   61440 /* 61.44 Mhz */
#define	A10_ATX_PLL_PFD_MAX   800000 /* 800.00 Mhz */
#define	A10_ATX_PLL_VCO_MIN   7200000 /* 7.20 GHz */
#define	A10_ATX_PLL_VCO_MAX   14400000 /* 14.40 GHz */

Functions
int32_t	altera_a10_atx_pll_round_rate (struct adxcvr *xcvr, uint32_t rate_khz)
	altera_a10_atx_pll_round_rate
int32_t	altera_a10_atx_pll_set_rate (struct adxcvr *xcvr, uint32_t rate_khz)
	altera_a10_atx_pll_set_rate
uint32_t	altera_a10_atx_pll_recalc_rate (struct adxcvr *xcvr)
	altera_a10_atx_pll_recalc_rate

Detailed Description

Driver for the Altera ATX PLL dynamic reconfiguration.

Author

DBogdan (drago.nosp@m.s.bo.nosp@m.gdan@.nosp@m.anal.nosp@m.og.co.nosp@m.m)

Copyright 2018(c) Analog Devices, Inc.

SPDX-License-Identifier: BSD-3-Clause

Macro Definition Documentation

A10_ATX_PLL_PFD_MAX

#define A10_ATX_PLL_PFD_MAX   800000 /* 800.00 Mhz */

A10_ATX_PLL_PFD_MIN

#define A10_ATX_PLL_PFD_MIN   61440 /* 61.44 Mhz */

A10_ATX_PLL_VCO_MAX

#define A10_ATX_PLL_VCO_MAX   14400000 /* 14.40 GHz */

A10_ATX_PLL_VCO_MIN

#define A10_ATX_PLL_VCO_MIN   7200000 /* 7.20 GHz */

Function Documentation

altera_a10_atx_pll_recalc_rate()

uint32_t altera_a10_atx_pll_recalc_rate

(

struct adxcvr *

xcvr

)

altera_a10_atx_pll_recalc_rate

altera_a10_atx_pll_round_rate()

int32_t altera_a10_atx_pll_round_rate	(	struct adxcvr *	xcvr,
		uint32_t	rate_khz )

altera_a10_atx_pll_round_rate

altera_a10_atx_pll_set_rate()

int32_t altera_a10_atx_pll_set_rate	(	struct adxcvr *	xcvr,
		uint32_t	rate_khz )

altera_a10_atx_pll_set_rate