no-OS
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platform specific information More...
#include <ad9528.h>
platform specific information
struct ad9528_channel_spec* ad9528_platform_data::channels |
Pointer to channel array.
uint8_t ad9528_platform_data::cpole1 |
PLL2 loop filter Cpole capacitor value.
uint32_t ad9528_platform_data::jdev_desired_sysref_freq |
uint32_t ad9528_platform_data::jdev_max_sysref_freq |
uint32_t ad9528_platform_data::num_channels |
Array size of struct ad9528_channel_spec.
uint8_t ad9528_platform_data::osc_in_cmos_neg_inp_en |
OSC single-ended neg./pos. input enable.
uint8_t ad9528_platform_data::osc_in_diff_en |
OSC differential/ single-ended input selection.
uint8_t ad9528_platform_data::pll1_bypass_en |
Bypass PLL1 - Single loop mode
uint16_t ad9528_platform_data::pll1_charge_pump_current_nA |
Magnitude of PLL1 charge pump current (nA).
uint16_t ad9528_platform_data::pll1_feedback_div |
PLL1 10-bit Feedback N divider.
uint8_t ad9528_platform_data::pll1_feedback_src_vcxo |
PLL1 Feedback source, True = VCXO, False = VCO
bool ad9528_platform_data::pll2_bypass_en |
Bypass PLL2
uint32_t ad9528_platform_data::pll2_charge_pump_current_nA |
Magnitude of PLL2 charge pump current (nA).
uint8_t ad9528_platform_data::pll2_freq_doubler_en |
PLL2 frequency doubler enable.
uint8_t ad9528_platform_data::pll2_n2_div |
PLL2 N2 divider, range 1..256.
uint8_t ad9528_platform_data::pll2_ndiv_a_cnt |
PLL2 Feedback N-divider, A Counter, range 0..4.
uint8_t ad9528_platform_data::pll2_ndiv_b_cnt |
PLL2 Feedback N-divider, B Counter, range 0..63.
uint8_t ad9528_platform_data::pll2_r1_div |
PLL2 R1 divider, range 1..31.
uint8_t ad9528_platform_data::pll2_vco_div_m1 |
VCO1 divider, range 3..5.
uint8_t ad9528_platform_data::ref_mode |
Reference selection mode.
uint8_t ad9528_platform_data::refa_cmos_neg_inp_en |
REFA single-ended neg./pos. input enable.
uint8_t ad9528_platform_data::refa_diff_rcv_en |
REFA differential/single-ended input selection.
uint8_t ad9528_platform_data::refa_en |
REFA input enable.
uint16_t ad9528_platform_data::refa_r_div |
PLL1 10-bit REFA R divider.
uint8_t ad9528_platform_data::refb_cmos_neg_inp_en |
REFB single-ended neg./pos. input enable.
uint8_t ad9528_platform_data::refb_diff_rcv_en |
REFB differential/single-ended input selection.
uint8_t ad9528_platform_data::refb_en |
REFB input enable.
uint16_t ad9528_platform_data::refb_r_div |
PLL1 10-bit REFB R divider.
uint8_t ad9528_platform_data::rpole2 |
PLL2 loop filter Rpole resistor value.
uint8_t ad9528_platform_data::rzero |
PLL2 loop filter Rzero resistor value.
uint8_t ad9528_platform_data::rzero_bypass_en |
PLL2 loop filter Rzero bypass enable.
uint8_t ad9528_platform_data::spi3wire |
SPI 3-Wire mode enable
uint8_t ad9528_platform_data::stat0_pin_func_sel |
Status Monitor Pin 0 function selection.
uint8_t ad9528_platform_data::stat1_pin_func_sel |
Status Monitor Pin 1 function selection.
uint16_t ad9528_platform_data::sysref_k_div |
SYSREF pattern generator K divier
uint8_t ad9528_platform_data::sysref_nshot_mode |
SYSREF pattern NSHOT mode
uint8_t ad9528_platform_data::sysref_pattern_mode |
SYSREF pattern mode
bool ad9528_platform_data::sysref_req_en |
SYSREF request pin mode enable (default SPI mode)
uint8_t ad9528_platform_data::sysref_req_trigger_mode |
SYSREF request trigger mode
uint8_t ad9528_platform_data::sysref_src |
SYSREF pattern generator clock source
uint32_t ad9528_platform_data::vcxo_freq |
External VCXO frequency in Hz