Modules
	Register Offsets

	CSI2_CFG_NUM_LANES

	CSI2_CFG_CLK_LANE_EN

	CSI2_CFG_DATA_LANE_EN

	CSI2_CFG_FLUSH_COUNT

	CSI2_CFG_BIT_ERR

	CSI2_IRQ_STATUS

	CSI2_IRQ_ENABLE

	CSI2_IRQ_CLR

	CSI2_ULPS_CLK_STATUS

	CSI2_ULPS_STATUS

	CSI2_ULPS_CLK_MARK_STATUS

	CSI2_ULPS_MARK_STATUS

	CSI2_CFG_DISABLE_PAYLOAD_0

	CSI2_CFG_DISABLE_PAYLOAD_1

	CSI2_CFG_DATABUS16_SEL

	CSI2_CFG_D0_SWAP_SEL

	CSI2_CFG_D1_SWAP_SEL

	CSI2_CFG_D2_SWAP_SEL

	CSI2_CFG_D3_SWAP_SEL

	CSI2_CFG_C0_SWAP_SEL

	CSI2_CFG_DPDN_SWAP

	CSI2_RESET_DESKEW

	CSI2_VCONTROL

	CSI2_RG_CDRX_DSIRX_EN

	CSI2_RG_CDRX_BISTHS_PLL_PRE_DIV2

	CSI2_VFIFO_CFG0

	CSI2_VFIFO_CFG1

	CSI2_VFIFO_CTRL

	CSI2_VFIFO_STS

	CSI2_VFIFO_LINE_NUM

	CSI2_VFIFO_PIXEL_NUM

	CSI2_VFIFO_LINE_CNT

	CSI2_VFIFO_PIXEL_CNT

	CSI2_VFIFO_FRAME_STS

	CSI2_VFIFO_RAW_CTRL

	CSI2_VFIFO_RAW_BUF0_ADDR

	CSI2_VFIFO_RAW_BUF1_ADDR

	CSI2_VFIFO_AHBM_CTRL

	CSI2_VFIFO_AHBM_STS

	CSI2_VFIFO_AHBM_START_ADDR

	CSI2_VFIFO_AHBM_ADDR_RANGE

	CSI2_VFIFO_AHBM_MAX_TRANS

	CSI2_VFIFO_AHBM_TRANS_CNT

	CSI2_RX_EINT_VFF_IE

	CSI2_RX_EINT_VFF_IF

	CSI2_RX_EINT_PPI_IE

	CSI2_RX_EINT_PPI_IF

	CSI2_RX_EINT_CTRL_IE

	CSI2_RX_EINT_CTRL_IF

	CSI2_PPI_STOPSTATE

	CSI2_PPI_TURNAROUND_CFG

Files
file	csi2_regs.h

Data Structures
struct	mxc_csi2_regs_t

Detailed Description

Registers, Bit Masks and Bit Positions for the CSI2 Peripheral Module.

Camera Serial Interface Registers.

Data Structure Documentation

◆ mxc_csi2_regs_t

struct mxc_csi2_regs_t

Structure type to access the CSI2 Registers.

Data Fields
__IO uint32_t	cfg_num_lanes

__IO uint32_t	cfg_clk_lane_en

__IO uint32_t	cfg_data_lane_en

__IO uint32_t	cfg_flush_count

__IO uint32_t	cfg_bit_err

__IO uint32_t	irq_status

__IO uint32_t	irq_enable

__IO uint32_t	irq_clr

__IO uint32_t	ulps_clk_status

__IO uint32_t	ulps_status

__IO uint32_t	ulps_clk_mark_status

__IO uint32_t	ulps_mark_status

__IO uint32_t	ppi_errsot_hs

__IO uint32_t	ppi_errsotsync_hs

__IO uint32_t	ppi_erresc

__IO uint32_t	ppi_errsyncesc

__IO uint32_t	ppi_errcontrol

__IO uint32_t	cfg_cphy_en

__IO uint32_t	cfg_ppi_16_en

__IO uint32_t	cfg_packet_interface_en

__IO uint32_t	cfg_vcx_en

__IO uint32_t	cfg_byte_data_format

__IO uint32_t	cfg_disable_payload_0

__IO uint32_t	cfg_disable_payload_1

__IO uint32_t	cfg_vid_ignore_vc

__IO uint32_t	cfg_vid_vc

__IO uint32_t	cfg_p_fifo_send_level

__IO uint32_t	cfg_vid_vsync

__IO uint32_t	cfg_vid_hsync_fp

__IO uint32_t	cfg_vid_hsync

__IO uint32_t	cfg_vid_hsync_bp

__IO uint32_t	cfg_databus16_sel

__IO uint32_t	cfg_d0_swap_sel

__IO uint32_t	cfg_d1_swap_sel

__IO uint32_t	cfg_d2_swap_sel

__IO uint32_t	cfg_d3_swap_sel

__IO uint32_t	cfg_c0_swap_sel

__IO uint32_t	cfg_dpdn_swap

__IO uint32_t	rg_cfgclk_1us_cnt

__IO uint32_t	rg_hsrx_clk_pre_time_grp0

__IO uint32_t	rg_hsrx_data_pre_time_grp0

__IO uint32_t	reset_deskew

__IO uint32_t	pma_rdy

__IO uint32_t	xcfgi_dw00

__IO uint32_t	xcfgi_dw01

__IO uint32_t	xcfgi_dw02

__IO uint32_t	xcfgi_dw03

__IO uint32_t	xcfgi_dw04

__IO uint32_t	xcfgi_dw05

__IO uint32_t	xcfgi_dw06

__IO uint32_t	xcfgi_dw07

__IO uint32_t	xcfgi_dw08

__IO uint32_t	xcfgi_dw09

__IO uint32_t	xcfgi_dw0a

__IO uint32_t	xcfgi_dw0b

__IO uint32_t	xcfgi_dw0c

__IO uint32_t	xcfgi_dw0d

__IO uint32_t	gpio_mode

__IO uint32_t	gpio_dp_ie

__IO uint32_t	gpio_dn_ie

__IO uint32_t	gpio_dp_c

__IO uint32_t	gpio_dn_c

__IO uint32_t	vcontrol

__IO uint32_t	mpsov1

__IO uint32_t	mpsov2

__IO uint32_t	mpsov3

__IO uint32_t	rg_cdrx_dsirx_en

__IO uint32_t	rg_cdrx_l012_sublvds_en

__IO uint32_t	rg_cdrx_l012_hsrt_ctrl

__IO uint32_t	rg_cdrx_bisths_pll_en

__IO uint32_t	rg_cdrx_bisths_pll_pre_div2

__IO uint32_t	rg_cdrx_bisths_pll_fbk_int

__IO uint32_t	dbg1_mux_sel

__IO uint32_t	dbg2_mux_sel

__IO uint32_t	dbg1_mux_dout

__IO uint32_t	dbg2_mux_dout

__IO uint32_t	aon_power_ready_n

__IO uint32_t	dphy_rst_n

__IO uint32_t	rxbyteclkhs_inv

__IO uint32_t	vfifo_cfg0

__IO uint32_t	vfifo_cfg1

__IO uint32_t	vfifo_ctrl

__IO uint32_t	vfifo_sts

__IO uint32_t	vfifo_line_num

__IO uint32_t	vfifo_pixel_num

__IO uint32_t	vfifo_line_cnt

__IO uint32_t	vfifo_pixel_cnt

__IO uint32_t	vfifo_frame_sts

__IO uint32_t	vfifo_raw_ctrl

__IO uint32_t	vfifo_raw_buf0_addr

__IO uint32_t	vfifo_raw_buf1_addr

__IO uint32_t	vfifo_ahbm_ctrl

__IO uint32_t	vfifo_ahbm_sts

__IO uint32_t	vfifo_ahbm_start_addr

__IO uint32_t	vfifo_ahbm_addr_range

__IO uint32_t	vfifo_ahbm_max_trans

__IO uint32_t	vfifo_ahbm_trans_cnt

__IO uint32_t	rx_eint_vff_ie

__IO uint32_t	rx_eint_vff_if

__IO uint32_t	rx_eint_ppi_ie

__IO uint32_t	rx_eint_ppi_if

__IO uint32_t	rx_eint_ctrl_ie

__IO uint32_t	rx_eint_ctrl_if

__IO uint32_t	ppi_stopstate

__IO uint32_t	ppi_turnaround_cfg

Field Documentation

◆ aon_power_ready_n

__IO uint32_t aon_power_ready_n

0x4B8: CSI2 AON_POWER_READY_N Register

◆ cfg_bit_err

__IO uint32_t cfg_bit_err

0x010: CSI2 CFG_BIT_ERR Register

◆ cfg_byte_data_format

__IO uint32_t cfg_byte_data_format

0x054: CSI2 CFG_BYTE_DATA_FORMAT Register

◆ cfg_c0_swap_sel

__IO uint32_t cfg_c0_swap_sel

0x414: CSI2 CFG_C0_SWAP_SEL Register

◆ cfg_clk_lane_en

__IO uint32_t cfg_clk_lane_en

0x004: CSI2 CFG_CLK_LANE_EN Register

◆ cfg_cphy_en

__IO uint32_t cfg_cphy_en

0x044: CSI2 CFG_CPHY_EN Register

◆ cfg_d0_swap_sel

__IO uint32_t cfg_d0_swap_sel

0x404: CSI2 CFG_D0_SWAP_SEL Register

◆ cfg_d1_swap_sel

__IO uint32_t cfg_d1_swap_sel

0x408: CSI2 CFG_D1_SWAP_SEL Register

◆ cfg_d2_swap_sel

__IO uint32_t cfg_d2_swap_sel

0x40C: CSI2 CFG_D2_SWAP_SEL Register

◆ cfg_d3_swap_sel

__IO uint32_t cfg_d3_swap_sel

0x410: CSI2 CFG_D3_SWAP_SEL Register

◆ cfg_data_lane_en

__IO uint32_t cfg_data_lane_en

0x008: CSI2 CFG_DATA_LANE_EN Register

◆ cfg_databus16_sel

__IO uint32_t cfg_databus16_sel

0x400: CSI2 CFG_DATABUS16_SEL Register

◆ cfg_disable_payload_0

__IO uint32_t cfg_disable_payload_0

0x058: CSI2 CFG_DISABLE_PAYLOAD_0 Register

◆ cfg_disable_payload_1

__IO uint32_t cfg_disable_payload_1

0x05C: CSI2 CFG_DISABLE_PAYLOAD_1 Register

◆ cfg_dpdn_swap

__IO uint32_t cfg_dpdn_swap

0x418: CSI2 CFG_DPDN_SWAP Register

◆ cfg_flush_count

__IO uint32_t cfg_flush_count

0x00C: CSI2 CFG_FLUSH_COUNT Register

◆ cfg_num_lanes

__IO uint32_t cfg_num_lanes

0x000: CSI2 CFG_NUM_LANES Register

◆ cfg_p_fifo_send_level

__IO uint32_t cfg_p_fifo_send_level

0x088: CSI2 CFG_P_FIFO_SEND_LEVEL Register

◆ cfg_packet_interface_en

__IO uint32_t cfg_packet_interface_en

0x04C: CSI2 CFG_PACKET_INTERFACE_EN Register

◆ cfg_ppi_16_en

__IO uint32_t cfg_ppi_16_en

0x048: CSI2 CFG_PPI_16_EN Register

◆ cfg_vcx_en

__IO uint32_t cfg_vcx_en

0x050: CSI2 CFG_VCX_EN Register

◆ cfg_vid_hsync

__IO uint32_t cfg_vid_hsync

0x094: CSI2 CFG_VID_HSYNC Register

◆ cfg_vid_hsync_bp

__IO uint32_t cfg_vid_hsync_bp

0x098: CSI2 CFG_VID_HSYNC_BP Register

◆ cfg_vid_hsync_fp

__IO uint32_t cfg_vid_hsync_fp

0x090: CSI2 CFG_VID_HSYNC_FP Register

◆ cfg_vid_ignore_vc

__IO uint32_t cfg_vid_ignore_vc

0x080: CSI2 CFG_VID_IGNORE_VC Register

◆ cfg_vid_vc

__IO uint32_t cfg_vid_vc

0x084: CSI2 CFG_VID_VC Register

◆ cfg_vid_vsync

__IO uint32_t cfg_vid_vsync

0x08C: CSI2 CFG_VID_VSYNC Register

◆ dbg1_mux_dout

__IO uint32_t dbg1_mux_dout

0x4B0: CSI2 DBG1_MUX_DOUT Register

◆ dbg1_mux_sel

__IO uint32_t dbg1_mux_sel

0x4A8: CSI2 DBG1_MUX_SEL Register

◆ dbg2_mux_dout

__IO uint32_t dbg2_mux_dout

0x4B4: CSI2 DBG2_MUX_DOUT Register

◆ dbg2_mux_sel

__IO uint32_t dbg2_mux_sel

0x4AC: CSI2 DBG2_MUX_SEL Register

◆ dphy_rst_n

__IO uint32_t dphy_rst_n

0x4BC: CSI2 DPHY_RST_N Register

◆ gpio_dn_c

__IO uint32_t gpio_dn_c

0x478: CSI2 GPIO_DN_C Register

◆ gpio_dn_ie

__IO uint32_t gpio_dn_ie

0x470: CSI2 GPIO_DN_IE Register

◆ gpio_dp_c

__IO uint32_t gpio_dp_c

0x474: CSI2 GPIO_DP_C Register

◆ gpio_dp_ie

__IO uint32_t gpio_dp_ie

0x46C: CSI2 GPIO_DP_IE Register

◆ gpio_mode

__IO uint32_t gpio_mode

0x468: CSI2 GPIO_MODE Register

◆ irq_clr

__IO uint32_t irq_clr

0x01C: CSI2 IRQ_CLR Register

◆ irq_enable

__IO uint32_t irq_enable

0x018: CSI2 IRQ_ENABLE Register

◆ irq_status

__IO uint32_t irq_status

0x014: CSI2 IRQ_STATUS Register

◆ mpsov1

__IO uint32_t mpsov1

0x480: CSI2 MPSOV1 Register

◆ mpsov2

__IO uint32_t mpsov2

0x484: CSI2 MPSOV2 Register

◆ mpsov3

__IO uint32_t mpsov3

0x488: CSI2 MPSOV3 Register

◆ pma_rdy

__IO uint32_t pma_rdy

0x42C: CSI2 PMA_RDY Register

◆ ppi_errcontrol

__IO uint32_t ppi_errcontrol

0x040: CSI2 PPI_ERRCONTROL Register

◆ ppi_erresc

__IO uint32_t ppi_erresc

0x038: CSI2 PPI_ERRESC Register

◆ ppi_errsot_hs

__IO uint32_t ppi_errsot_hs

0x030: CSI2 PPI_ERRSOT_HS Register

◆ ppi_errsotsync_hs

__IO uint32_t ppi_errsotsync_hs

0x034: CSI2 PPI_ERRSOTSYNC_HS Register

◆ ppi_errsyncesc

__IO uint32_t ppi_errsyncesc

0x03C: CSI2 PPI_ERRSYNCESC Register

◆ ppi_stopstate

__IO uint32_t ppi_stopstate

0x700: CSI2 PPI_STOPSTATE Register

◆ ppi_turnaround_cfg

__IO uint32_t ppi_turnaround_cfg

0x704: CSI2 PPI_TURNAROUND_CFG Register

◆ reset_deskew

__IO uint32_t reset_deskew

0x428: CSI2 RESET_DESKEW Register

◆ rg_cdrx_bisths_pll_en

__IO uint32_t rg_cdrx_bisths_pll_en

0x49C: CSI2 RG_CDRX_BISTHS_PLL_EN Register

◆ rg_cdrx_bisths_pll_fbk_int

__IO uint32_t rg_cdrx_bisths_pll_fbk_int

0x4A4: CSI2 RG_CDRX_BISTHS_PLL_FBK_INT Register

◆ rg_cdrx_bisths_pll_pre_div2

__IO uint32_t rg_cdrx_bisths_pll_pre_div2

0x4A0: CSI2 RG_CDRX_BISTHS_PLL_PRE_DIV2 Register

◆ rg_cdrx_dsirx_en

__IO uint32_t rg_cdrx_dsirx_en

0x490: CSI2 RG_CDRX_DSIRX_EN Register

◆ rg_cdrx_l012_hsrt_ctrl

__IO uint32_t rg_cdrx_l012_hsrt_ctrl

0x498: CSI2 RG_CDRX_L012_HSRT_CTRL Register

◆ rg_cdrx_l012_sublvds_en

__IO uint32_t rg_cdrx_l012_sublvds_en

0x494: CSI2 RG_CDRX_L012_SUBLVDS_EN Register

◆ rg_cfgclk_1us_cnt

__IO uint32_t rg_cfgclk_1us_cnt

0x41C: CSI2 RG_CFGCLK_1US_CNT Register

◆ rg_hsrx_clk_pre_time_grp0

__IO uint32_t rg_hsrx_clk_pre_time_grp0

0x420: CSI2 RG_HSRX_CLK_PRE_TIME_GRP0 Register

◆ rg_hsrx_data_pre_time_grp0

__IO uint32_t rg_hsrx_data_pre_time_grp0

0x424: CSI2 RG_HSRX_DATA_PRE_TIME_GRP0 Register

◆ rx_eint_ctrl_ie

__IO uint32_t rx_eint_ctrl_ie

0x610: CSI2 RX_EINT_CTRL_IE Register

◆ rx_eint_ctrl_if

__IO uint32_t rx_eint_ctrl_if

0x614: CSI2 RX_EINT_CTRL_IF Register

◆ rx_eint_ppi_ie

__IO uint32_t rx_eint_ppi_ie

0x608: CSI2 RX_EINT_PPI_IE Register

◆ rx_eint_ppi_if

__IO uint32_t rx_eint_ppi_if

0x60C: CSI2 RX_EINT_PPI_IF Register

◆ rx_eint_vff_ie

__IO uint32_t rx_eint_vff_ie

0x600: CSI2 RX_EINT_VFF_IE Register

◆ rx_eint_vff_if

__IO uint32_t rx_eint_vff_if

0x604: CSI2 RX_EINT_VFF_IF Register

◆ rxbyteclkhs_inv

__IO uint32_t rxbyteclkhs_inv

0x4C0: CSI2 RXBYTECLKHS_INV Register

◆ ulps_clk_mark_status

__IO uint32_t ulps_clk_mark_status

0x028: CSI2 ULPS_CLK_MARK_STATUS Register

◆ ulps_clk_status

__IO uint32_t ulps_clk_status

0x020: CSI2 ULPS_CLK_STATUS Register

◆ ulps_mark_status

__IO uint32_t ulps_mark_status

0x02C: CSI2 ULPS_MARK_STATUS Register

◆ ulps_status

__IO uint32_t ulps_status

0x024: CSI2 ULPS_STATUS Register

◆ vcontrol

__IO uint32_t vcontrol

0x47C: CSI2 VCONTROL Register

◆ vfifo_ahbm_addr_range

__IO uint32_t vfifo_ahbm_addr_range

0x53C: CSI2 VFIFO_AHBM_ADDR_RANGE Register

◆ vfifo_ahbm_ctrl

__IO uint32_t vfifo_ahbm_ctrl

0x530: CSI2 VFIFO_AHBM_CTRL Register

◆ vfifo_ahbm_max_trans

__IO uint32_t vfifo_ahbm_max_trans

0x540: CSI2 VFIFO_AHBM_MAX_TRANS Register

◆ vfifo_ahbm_start_addr

__IO uint32_t vfifo_ahbm_start_addr

0x538: CSI2 VFIFO_AHBM_START_ADDR Register

◆ vfifo_ahbm_sts

__IO uint32_t vfifo_ahbm_sts

0x534: CSI2 VFIFO_AHBM_STS Register

◆ vfifo_ahbm_trans_cnt

__IO uint32_t vfifo_ahbm_trans_cnt

0x544: CSI2 VFIFO_AHBM_TRANS_CNT Register

◆ vfifo_cfg0

__IO uint32_t vfifo_cfg0

0x500: CSI2 VFIFO_CFG0 Register

◆ vfifo_cfg1

__IO uint32_t vfifo_cfg1

0x504: CSI2 VFIFO_CFG1 Register

◆ vfifo_ctrl

__IO uint32_t vfifo_ctrl

0x508: CSI2 VFIFO_CTRL Register

◆ vfifo_frame_sts

__IO uint32_t vfifo_frame_sts

0x520: CSI2 VFIFO_FRAME_STS Register

◆ vfifo_line_cnt

__IO uint32_t vfifo_line_cnt

0x518: CSI2 VFIFO_LINE_CNT Register

◆ vfifo_line_num

__IO uint32_t vfifo_line_num

0x510: CSI2 VFIFO_LINE_NUM Register

◆ vfifo_pixel_cnt

__IO uint32_t vfifo_pixel_cnt

0x51C: CSI2 VFIFO_PIXEL_CNT Register

◆ vfifo_pixel_num

__IO uint32_t vfifo_pixel_num

0x514: CSI2 VFIFO_PIXEL_NUM Register

◆ vfifo_raw_buf0_addr

__IO uint32_t vfifo_raw_buf0_addr

0x528: CSI2 VFIFO_RAW_BUF0_ADDR Register

◆ vfifo_raw_buf1_addr

__IO uint32_t vfifo_raw_buf1_addr

0x52C: CSI2 VFIFO_RAW_BUF1_ADDR Register

◆ vfifo_raw_ctrl

__IO uint32_t vfifo_raw_ctrl

0x524: CSI2 VFIFO_RAW_CTRL Register

◆ vfifo_sts

__IO uint32_t vfifo_sts

0x50C: CSI2 VFIFO_STS Register

◆ xcfgi_dw00

__IO uint32_t xcfgi_dw00

0x430: CSI2 XCFGI_DW00 Register

◆ xcfgi_dw01

__IO uint32_t xcfgi_dw01

0x434: CSI2 XCFGI_DW01 Register

◆ xcfgi_dw02

__IO uint32_t xcfgi_dw02

0x438: CSI2 XCFGI_DW02 Register

◆ xcfgi_dw03

__IO uint32_t xcfgi_dw03

0x43C: CSI2 XCFGI_DW03 Register

◆ xcfgi_dw04

__IO uint32_t xcfgi_dw04

0x440: CSI2 XCFGI_DW04 Register

◆ xcfgi_dw05

__IO uint32_t xcfgi_dw05

0x444: CSI2 XCFGI_DW05 Register

◆ xcfgi_dw06

__IO uint32_t xcfgi_dw06

0x448: CSI2 XCFGI_DW06 Register

◆ xcfgi_dw07

__IO uint32_t xcfgi_dw07

0x44C: CSI2 XCFGI_DW07 Register

◆ xcfgi_dw08

__IO uint32_t xcfgi_dw08

0x450: CSI2 XCFGI_DW08 Register

◆ xcfgi_dw09

__IO uint32_t xcfgi_dw09

0x454: CSI2 XCFGI_DW09 Register

◆ xcfgi_dw0a

__IO uint32_t xcfgi_dw0a

0x458: CSI2 XCFGI_DW0A Register

◆ xcfgi_dw0b

__IO uint32_t xcfgi_dw0b

0x45C: CSI2 XCFGI_DW0B Register

◆ xcfgi_dw0c

__IO uint32_t xcfgi_dw0c

0x460: CSI2 XCFGI_DW0C Register

◆ xcfgi_dw0d

__IO uint32_t xcfgi_dw0d

0x464: CSI2 XCFGI_DW0D Register

Modules

Files

Data Structures