|
| #define | MXC_R_CSI2_CFG_NUM_LANES ((uint32_t)0x00000000UL) |
| |
| #define | MXC_R_CSI2_CFG_CLK_LANE_EN ((uint32_t)0x00000004UL) |
| |
| #define | MXC_R_CSI2_CFG_DATA_LANE_EN ((uint32_t)0x00000008UL) |
| |
| #define | MXC_R_CSI2_CFG_FLUSH_COUNT ((uint32_t)0x0000000CUL) |
| |
| #define | MXC_R_CSI2_CFG_BIT_ERR ((uint32_t)0x00000010UL) |
| |
| #define | MXC_R_CSI2_IRQ_STATUS ((uint32_t)0x00000014UL) |
| |
| #define | MXC_R_CSI2_IRQ_ENABLE ((uint32_t)0x00000018UL) |
| |
| #define | MXC_R_CSI2_IRQ_CLR ((uint32_t)0x0000001CUL) |
| |
| #define | MXC_R_CSI2_ULPS_CLK_STATUS ((uint32_t)0x00000020UL) |
| |
| #define | MXC_R_CSI2_ULPS_STATUS ((uint32_t)0x00000024UL) |
| |
| #define | MXC_R_CSI2_ULPS_CLK_MARK_STATUS ((uint32_t)0x00000028UL) |
| |
| #define | MXC_R_CSI2_ULPS_MARK_STATUS ((uint32_t)0x0000002CUL) |
| |
| #define | MXC_R_CSI2_PPI_ERRSOT_HS ((uint32_t)0x00000030UL) |
| |
| #define | MXC_R_CSI2_PPI_ERRSOTSYNC_HS ((uint32_t)0x00000034UL) |
| |
| #define | MXC_R_CSI2_PPI_ERRESC ((uint32_t)0x00000038UL) |
| |
| #define | MXC_R_CSI2_PPI_ERRSYNCESC ((uint32_t)0x0000003CUL) |
| |
| #define | MXC_R_CSI2_PPI_ERRCONTROL ((uint32_t)0x00000040UL) |
| |
| #define | MXC_R_CSI2_CFG_CPHY_EN ((uint32_t)0x00000044UL) |
| |
| #define | MXC_R_CSI2_CFG_PPI_16_EN ((uint32_t)0x00000048UL) |
| |
| #define | MXC_R_CSI2_CFG_PACKET_INTERFACE_EN ((uint32_t)0x0000004CUL) |
| |
| #define | MXC_R_CSI2_CFG_VCX_EN ((uint32_t)0x00000050UL) |
| |
| #define | MXC_R_CSI2_CFG_BYTE_DATA_FORMAT ((uint32_t)0x00000054UL) |
| |
| #define | MXC_R_CSI2_CFG_DISABLE_PAYLOAD_0 ((uint32_t)0x00000058UL) |
| |
| #define | MXC_R_CSI2_CFG_DISABLE_PAYLOAD_1 ((uint32_t)0x0000005CUL) |
| |
| #define | MXC_R_CSI2_CFG_VID_IGNORE_VC ((uint32_t)0x00000080UL) |
| |
| #define | MXC_R_CSI2_CFG_VID_VC ((uint32_t)0x00000084UL) |
| |
| #define | MXC_R_CSI2_CFG_P_FIFO_SEND_LEVEL ((uint32_t)0x00000088UL) |
| |
| #define | MXC_R_CSI2_CFG_VID_VSYNC ((uint32_t)0x0000008CUL) |
| |
| #define | MXC_R_CSI2_CFG_VID_HSYNC_FP ((uint32_t)0x00000090UL) |
| |
| #define | MXC_R_CSI2_CFG_VID_HSYNC ((uint32_t)0x00000094UL) |
| |
| #define | MXC_R_CSI2_CFG_VID_HSYNC_BP ((uint32_t)0x00000098UL) |
| |
| #define | MXC_R_CSI2_CFG_DATABUS16_SEL ((uint32_t)0x00000400UL) |
| |
| #define | MXC_R_CSI2_CFG_D0_SWAP_SEL ((uint32_t)0x00000404UL) |
| |
| #define | MXC_R_CSI2_CFG_D1_SWAP_SEL ((uint32_t)0x00000408UL) |
| |
| #define | MXC_R_CSI2_CFG_D2_SWAP_SEL ((uint32_t)0x0000040CUL) |
| |
| #define | MXC_R_CSI2_CFG_D3_SWAP_SEL ((uint32_t)0x00000410UL) |
| |
| #define | MXC_R_CSI2_CFG_C0_SWAP_SEL ((uint32_t)0x00000414UL) |
| |
| #define | MXC_R_CSI2_CFG_DPDN_SWAP ((uint32_t)0x00000418UL) |
| |
| #define | MXC_R_CSI2_RG_CFGCLK_1US_CNT ((uint32_t)0x0000041CUL) |
| |
| #define | MXC_R_CSI2_RG_HSRX_CLK_PRE_TIME_GRP0 ((uint32_t)0x00000420UL) |
| |
| #define | MXC_R_CSI2_RG_HSRX_DATA_PRE_TIME_GRP0 ((uint32_t)0x00000424UL) |
| |
| #define | MXC_R_CSI2_RESET_DESKEW ((uint32_t)0x00000428UL) |
| |
| #define | MXC_R_CSI2_PMA_RDY ((uint32_t)0x0000042CUL) |
| |
| #define | MXC_R_CSI2_XCFGI_DW00 ((uint32_t)0x00000430UL) |
| |
| #define | MXC_R_CSI2_XCFGI_DW01 ((uint32_t)0x00000434UL) |
| |
| #define | MXC_R_CSI2_XCFGI_DW02 ((uint32_t)0x00000438UL) |
| |
| #define | MXC_R_CSI2_XCFGI_DW03 ((uint32_t)0x0000043CUL) |
| |
| #define | MXC_R_CSI2_XCFGI_DW04 ((uint32_t)0x00000440UL) |
| |
| #define | MXC_R_CSI2_XCFGI_DW05 ((uint32_t)0x00000444UL) |
| |
| #define | MXC_R_CSI2_XCFGI_DW06 ((uint32_t)0x00000448UL) |
| |
| #define | MXC_R_CSI2_XCFGI_DW07 ((uint32_t)0x0000044CUL) |
| |
| #define | MXC_R_CSI2_XCFGI_DW08 ((uint32_t)0x00000450UL) |
| |
| #define | MXC_R_CSI2_XCFGI_DW09 ((uint32_t)0x00000454UL) |
| |
| #define | MXC_R_CSI2_XCFGI_DW0A ((uint32_t)0x00000458UL) |
| |
| #define | MXC_R_CSI2_XCFGI_DW0B ((uint32_t)0x0000045CUL) |
| |
| #define | MXC_R_CSI2_XCFGI_DW0C ((uint32_t)0x00000460UL) |
| |
| #define | MXC_R_CSI2_XCFGI_DW0D ((uint32_t)0x00000464UL) |
| |
| #define | MXC_R_CSI2_GPIO_MODE ((uint32_t)0x00000468UL) |
| |
| #define | MXC_R_CSI2_GPIO_DP_IE ((uint32_t)0x0000046CUL) |
| |
| #define | MXC_R_CSI2_GPIO_DN_IE ((uint32_t)0x00000470UL) |
| |
| #define | MXC_R_CSI2_GPIO_DP_C ((uint32_t)0x00000474UL) |
| |
| #define | MXC_R_CSI2_GPIO_DN_C ((uint32_t)0x00000478UL) |
| |
| #define | MXC_R_CSI2_VCONTROL ((uint32_t)0x0000047CUL) |
| |
| #define | MXC_R_CSI2_MPSOV1 ((uint32_t)0x00000480UL) |
| |
| #define | MXC_R_CSI2_MPSOV2 ((uint32_t)0x00000484UL) |
| |
| #define | MXC_R_CSI2_MPSOV3 ((uint32_t)0x00000488UL) |
| |
| #define | MXC_R_CSI2_RG_CDRX_DSIRX_EN ((uint32_t)0x00000490UL) |
| |
| #define | MXC_R_CSI2_RG_CDRX_L012_SUBLVDS_EN ((uint32_t)0x00000494UL) |
| |
| #define | MXC_R_CSI2_RG_CDRX_L012_HSRT_CTRL ((uint32_t)0x00000498UL) |
| |
| #define | MXC_R_CSI2_RG_CDRX_BISTHS_PLL_EN ((uint32_t)0x0000049CUL) |
| |
| #define | MXC_R_CSI2_RG_CDRX_BISTHS_PLL_PRE_DIV2 ((uint32_t)0x000004A0UL) |
| |
| #define | MXC_R_CSI2_RG_CDRX_BISTHS_PLL_FBK_INT ((uint32_t)0x000004A4UL) |
| |
| #define | MXC_R_CSI2_DBG1_MUX_SEL ((uint32_t)0x000004A8UL) |
| |
| #define | MXC_R_CSI2_DBG2_MUX_SEL ((uint32_t)0x000004ACUL) |
| |
| #define | MXC_R_CSI2_DBG1_MUX_DOUT ((uint32_t)0x000004B0UL) |
| |
| #define | MXC_R_CSI2_DBG2_MUX_DOUT ((uint32_t)0x000004B4UL) |
| |
| #define | MXC_R_CSI2_AON_POWER_READY_N ((uint32_t)0x000004B8UL) |
| |
| #define | MXC_R_CSI2_DPHY_RST_N ((uint32_t)0x000004BCUL) |
| |
| #define | MXC_R_CSI2_RXBYTECLKHS_INV ((uint32_t)0x000004C0UL) |
| |
| #define | MXC_R_CSI2_VFIFO_CFG0 ((uint32_t)0x00000500UL) |
| |
| #define | MXC_R_CSI2_VFIFO_CFG1 ((uint32_t)0x00000504UL) |
| |
| #define | MXC_R_CSI2_VFIFO_CTRL ((uint32_t)0x00000508UL) |
| |
| #define | MXC_R_CSI2_VFIFO_STS ((uint32_t)0x0000050CUL) |
| |
| #define | MXC_R_CSI2_VFIFO_LINE_NUM ((uint32_t)0x00000510UL) |
| |
| #define | MXC_R_CSI2_VFIFO_PIXEL_NUM ((uint32_t)0x00000514UL) |
| |
| #define | MXC_R_CSI2_VFIFO_LINE_CNT ((uint32_t)0x00000518UL) |
| |
| #define | MXC_R_CSI2_VFIFO_PIXEL_CNT ((uint32_t)0x0000051CUL) |
| |
| #define | MXC_R_CSI2_VFIFO_FRAME_STS ((uint32_t)0x00000520UL) |
| |
| #define | MXC_R_CSI2_VFIFO_RAW_CTRL ((uint32_t)0x00000524UL) |
| |
| #define | MXC_R_CSI2_VFIFO_RAW_BUF0_ADDR ((uint32_t)0x00000528UL) |
| |
| #define | MXC_R_CSI2_VFIFO_RAW_BUF1_ADDR ((uint32_t)0x0000052CUL) |
| |
| #define | MXC_R_CSI2_VFIFO_AHBM_CTRL ((uint32_t)0x00000530UL) |
| |
| #define | MXC_R_CSI2_VFIFO_AHBM_STS ((uint32_t)0x00000534UL) |
| |
| #define | MXC_R_CSI2_VFIFO_AHBM_START_ADDR ((uint32_t)0x00000538UL) |
| |
| #define | MXC_R_CSI2_VFIFO_AHBM_ADDR_RANGE ((uint32_t)0x0000053CUL) |
| |
| #define | MXC_R_CSI2_VFIFO_AHBM_MAX_TRANS ((uint32_t)0x00000540UL) |
| |
| #define | MXC_R_CSI2_VFIFO_AHBM_TRANS_CNT ((uint32_t)0x00000544UL) |
| |
| #define | MXC_R_CSI2_RX_EINT_VFF_IE ((uint32_t)0x00000600UL) |
| |
| #define | MXC_R_CSI2_RX_EINT_VFF_IF ((uint32_t)0x00000604UL) |
| |
| #define | MXC_R_CSI2_RX_EINT_PPI_IE ((uint32_t)0x00000608UL) |
| |
| #define | MXC_R_CSI2_RX_EINT_PPI_IF ((uint32_t)0x0000060CUL) |
| |
| #define | MXC_R_CSI2_RX_EINT_CTRL_IE ((uint32_t)0x00000610UL) |
| |
| #define | MXC_R_CSI2_RX_EINT_CTRL_IF ((uint32_t)0x00000614UL) |
| |
| #define | MXC_R_CSI2_PPI_STOPSTATE ((uint32_t)0x00000700UL) |
| |
| #define | MXC_R_CSI2_PPI_TURNAROUND_CFG ((uint32_t)0x00000704UL) |
| |
| #define | MXC_F_CSI2_CFG_NUM_LANES_LANES_POS 0 |
| |
| #define | MXC_F_CSI2_CFG_NUM_LANES_LANES ((uint32_t)(0xFUL << MXC_F_CSI2_CFG_NUM_LANES_LANES_POS)) |
| |
| #define | MXC_F_CSI2_CFG_CLK_LANE_EN_EN_POS 0 |
| |
| #define | MXC_F_CSI2_CFG_CLK_LANE_EN_EN ((uint32_t)(0x1UL << MXC_F_CSI2_CFG_CLK_LANE_EN_EN_POS)) |
| |
| #define | MXC_F_CSI2_CFG_DATA_LANE_EN_EN_POS 0 |
| |
| #define | MXC_F_CSI2_CFG_DATA_LANE_EN_EN ((uint32_t)(0xFFUL << MXC_F_CSI2_CFG_DATA_LANE_EN_EN_POS)) |
| |
| #define | MXC_F_CSI2_CFG_FLUSH_COUNT_COUNT_POS 0 |
| |
| #define | MXC_F_CSI2_CFG_FLUSH_COUNT_COUNT ((uint32_t)(0xFUL << MXC_F_CSI2_CFG_FLUSH_COUNT_COUNT_POS)) |
| |
| #define | MXC_F_CSI2_CFG_BIT_ERR_MBE_POS 0 |
| |
| #define | MXC_F_CSI2_CFG_BIT_ERR_MBE ((uint32_t)(0x1UL << MXC_F_CSI2_CFG_BIT_ERR_MBE_POS)) |
| |
| #define | MXC_F_CSI2_CFG_BIT_ERR_SBE_POS 1 |
| |
| #define | MXC_F_CSI2_CFG_BIT_ERR_SBE ((uint32_t)(0x1UL << MXC_F_CSI2_CFG_BIT_ERR_SBE_POS)) |
| |
| #define | MXC_F_CSI2_CFG_BIT_ERR_HEADER_POS 2 |
| |
| #define | MXC_F_CSI2_CFG_BIT_ERR_HEADER ((uint32_t)(0x1FUL << MXC_F_CSI2_CFG_BIT_ERR_HEADER_POS)) |
| |
| #define | MXC_F_CSI2_CFG_BIT_ERR_CRC_POS 7 |
| |
| #define | MXC_F_CSI2_CFG_BIT_ERR_CRC ((uint32_t)(0x1UL << MXC_F_CSI2_CFG_BIT_ERR_CRC_POS)) |
| |
| #define | MXC_F_CSI2_CFG_BIT_ERR_VID_ERR_SEND_LVL_POS 8 |
| |
| #define | MXC_F_CSI2_CFG_BIT_ERR_VID_ERR_SEND_LVL ((uint32_t)(0x1UL << MXC_F_CSI2_CFG_BIT_ERR_VID_ERR_SEND_LVL_POS)) |
| |
| #define | MXC_F_CSI2_CFG_BIT_ERR_VID_ERR_FIFO_WR_OV_POS 9 |
| |
| #define | MXC_F_CSI2_CFG_BIT_ERR_VID_ERR_FIFO_WR_OV ((uint32_t)(0x1UL << MXC_F_CSI2_CFG_BIT_ERR_VID_ERR_FIFO_WR_OV_POS)) |
| |
| #define | MXC_F_CSI2_IRQ_STATUS_CRC_POS 0 |
| |
| #define | MXC_F_CSI2_IRQ_STATUS_CRC ((uint32_t)(0x1UL << MXC_F_CSI2_IRQ_STATUS_CRC_POS)) |
| |
| #define | MXC_F_CSI2_IRQ_STATUS_SBE_POS 1 |
| |
| #define | MXC_F_CSI2_IRQ_STATUS_SBE ((uint32_t)(0x1UL << MXC_F_CSI2_IRQ_STATUS_SBE_POS)) |
| |
| #define | MXC_F_CSI2_IRQ_STATUS_MBE_POS 2 |
| |
| #define | MXC_F_CSI2_IRQ_STATUS_MBE ((uint32_t)(0x1UL << MXC_F_CSI2_IRQ_STATUS_MBE_POS)) |
| |
| #define | MXC_F_CSI2_IRQ_STATUS_ULPS_ACTIVE_POS 3 |
| |
| #define | MXC_F_CSI2_IRQ_STATUS_ULPS_ACTIVE ((uint32_t)(0x1UL << MXC_F_CSI2_IRQ_STATUS_ULPS_ACTIVE_POS)) |
| |
| #define | MXC_F_CSI2_IRQ_STATUS_ULPS_MARK_ACTIVE_POS 4 |
| |
| #define | MXC_F_CSI2_IRQ_STATUS_ULPS_MARK_ACTIVE ((uint32_t)(0x1UL << MXC_F_CSI2_IRQ_STATUS_ULPS_MARK_ACTIVE_POS)) |
| |
| #define | MXC_F_CSI2_IRQ_STATUS_VID_ERR_SEND_LVL_POS 5 |
| |
| #define | MXC_F_CSI2_IRQ_STATUS_VID_ERR_SEND_LVL ((uint32_t)(0x1UL << MXC_F_CSI2_IRQ_STATUS_VID_ERR_SEND_LVL_POS)) |
| |
| #define | MXC_F_CSI2_IRQ_STATUS_VID_ERR_FIFO_WR_OV_POS 6 |
| |
| #define | MXC_F_CSI2_IRQ_STATUS_VID_ERR_FIFO_WR_OV ((uint32_t)(0x1UL << MXC_F_CSI2_IRQ_STATUS_VID_ERR_FIFO_WR_OV_POS)) |
| |
| #define | MXC_F_CSI2_IRQ_ENABLE_CRC_POS 0 |
| |
| #define | MXC_F_CSI2_IRQ_ENABLE_CRC ((uint32_t)(0x1UL << MXC_F_CSI2_IRQ_ENABLE_CRC_POS)) |
| |
| #define | MXC_F_CSI2_IRQ_ENABLE_SBE_POS 1 |
| |
| #define | MXC_F_CSI2_IRQ_ENABLE_SBE ((uint32_t)(0x1UL << MXC_F_CSI2_IRQ_ENABLE_SBE_POS)) |
| |
| #define | MXC_F_CSI2_IRQ_ENABLE_MBE_POS 2 |
| |
| #define | MXC_F_CSI2_IRQ_ENABLE_MBE ((uint32_t)(0x1UL << MXC_F_CSI2_IRQ_ENABLE_MBE_POS)) |
| |
| #define | MXC_F_CSI2_IRQ_ENABLE_ULPS_ACTIVE_POS 3 |
| |
| #define | MXC_F_CSI2_IRQ_ENABLE_ULPS_ACTIVE ((uint32_t)(0x1UL << MXC_F_CSI2_IRQ_ENABLE_ULPS_ACTIVE_POS)) |
| |
| #define | MXC_F_CSI2_IRQ_ENABLE_ULPS_MARK_ACTIVE_POS 4 |
| |
| #define | MXC_F_CSI2_IRQ_ENABLE_ULPS_MARK_ACTIVE ((uint32_t)(0x1UL << MXC_F_CSI2_IRQ_ENABLE_ULPS_MARK_ACTIVE_POS)) |
| |
| #define | MXC_F_CSI2_IRQ_ENABLE_VID_ERR_SEND_LVL_POS 5 |
| |
| #define | MXC_F_CSI2_IRQ_ENABLE_VID_ERR_SEND_LVL ((uint32_t)(0x1UL << MXC_F_CSI2_IRQ_ENABLE_VID_ERR_SEND_LVL_POS)) |
| |
| #define | MXC_F_CSI2_IRQ_ENABLE_VID_ERR_FIFO_WR_OV_POS 6 |
| |
| #define | MXC_F_CSI2_IRQ_ENABLE_VID_ERR_FIFO_WR_OV ((uint32_t)(0x1UL << MXC_F_CSI2_IRQ_ENABLE_VID_ERR_FIFO_WR_OV_POS)) |
| |
| #define | MXC_F_CSI2_IRQ_CLR_CRC_POS 0 |
| |
| #define | MXC_F_CSI2_IRQ_CLR_CRC ((uint32_t)(0x1UL << MXC_F_CSI2_IRQ_CLR_CRC_POS)) |
| |
| #define | MXC_F_CSI2_IRQ_CLR_SBE_POS 1 |
| |
| #define | MXC_F_CSI2_IRQ_CLR_SBE ((uint32_t)(0x1UL << MXC_F_CSI2_IRQ_CLR_SBE_POS)) |
| |
| #define | MXC_F_CSI2_IRQ_CLR_MBE_POS 2 |
| |
| #define | MXC_F_CSI2_IRQ_CLR_MBE ((uint32_t)(0x1UL << MXC_F_CSI2_IRQ_CLR_MBE_POS)) |
| |
| #define | MXC_F_CSI2_IRQ_CLR_ULPS_ACTIVE_POS 3 |
| |
| #define | MXC_F_CSI2_IRQ_CLR_ULPS_ACTIVE ((uint32_t)(0x1UL << MXC_F_CSI2_IRQ_CLR_ULPS_ACTIVE_POS)) |
| |
| #define | MXC_F_CSI2_IRQ_CLR_ULPS_MARK_ACTIVE_POS 4 |
| |
| #define | MXC_F_CSI2_IRQ_CLR_ULPS_MARK_ACTIVE ((uint32_t)(0x1UL << MXC_F_CSI2_IRQ_CLR_ULPS_MARK_ACTIVE_POS)) |
| |
| #define | MXC_F_CSI2_IRQ_CLR_VID_ERR_SEND_LVL_POS 5 |
| |
| #define | MXC_F_CSI2_IRQ_CLR_VID_ERR_SEND_LVL ((uint32_t)(0x1UL << MXC_F_CSI2_IRQ_CLR_VID_ERR_SEND_LVL_POS)) |
| |
| #define | MXC_F_CSI2_IRQ_CLR_VID_ERR_FIFO_WR_OV_POS 6 |
| |
| #define | MXC_F_CSI2_IRQ_CLR_VID_ERR_FIFO_WR_OV ((uint32_t)(0x1UL << MXC_F_CSI2_IRQ_CLR_VID_ERR_FIFO_WR_OV_POS)) |
| |
| #define | MXC_F_CSI2_ULPS_CLK_STATUS_FIFO_POS 0 |
| |
| #define | MXC_F_CSI2_ULPS_CLK_STATUS_FIFO ((uint32_t)(0x1UL << MXC_F_CSI2_ULPS_CLK_STATUS_FIFO_POS)) |
| |
| #define | MXC_F_CSI2_ULPS_STATUS_DATA_LANE0_POS 0 |
| |
| #define | MXC_F_CSI2_ULPS_STATUS_DATA_LANE0 ((uint32_t)(0x1UL << MXC_F_CSI2_ULPS_STATUS_DATA_LANE0_POS)) |
| |
| #define | MXC_F_CSI2_ULPS_STATUS_DATA_LANE1_POS 1 |
| |
| #define | MXC_F_CSI2_ULPS_STATUS_DATA_LANE1 ((uint32_t)(0x1UL << MXC_F_CSI2_ULPS_STATUS_DATA_LANE1_POS)) |
| |
| #define | MXC_F_CSI2_ULPS_CLK_MARK_STATUS_CLK_LANE_POS 0 |
| |
| #define | MXC_F_CSI2_ULPS_CLK_MARK_STATUS_CLK_LANE ((uint32_t)(0x1UL << MXC_F_CSI2_ULPS_CLK_MARK_STATUS_CLK_LANE_POS)) |
| |
| #define | MXC_F_CSI2_ULPS_MARK_STATUS_DATA_LANE0_POS 0 |
| |
| #define | MXC_F_CSI2_ULPS_MARK_STATUS_DATA_LANE0 ((uint32_t)(0x1UL << MXC_F_CSI2_ULPS_MARK_STATUS_DATA_LANE0_POS)) |
| |
| #define | MXC_F_CSI2_ULPS_MARK_STATUS_DATA_LANE1_POS 1 |
| |
| #define | MXC_F_CSI2_ULPS_MARK_STATUS_DATA_LANE1 ((uint32_t)(0x1UL << MXC_F_CSI2_ULPS_MARK_STATUS_DATA_LANE1_POS)) |
| |
| #define | MXC_F_CSI2_CFG_DISABLE_PAYLOAD_0_NULL_POS 0 |
| |
| #define | MXC_F_CSI2_CFG_DISABLE_PAYLOAD_0_NULL ((uint32_t)(0x1UL << MXC_F_CSI2_CFG_DISABLE_PAYLOAD_0_NULL_POS)) |
| |
| #define | MXC_F_CSI2_CFG_DISABLE_PAYLOAD_0_BLANK_POS 1 |
| |
| #define | MXC_F_CSI2_CFG_DISABLE_PAYLOAD_0_BLANK ((uint32_t)(0x1UL << MXC_F_CSI2_CFG_DISABLE_PAYLOAD_0_BLANK_POS)) |
| |
| #define | MXC_F_CSI2_CFG_DISABLE_PAYLOAD_0_EMBEDDED_POS 2 |
| |
| #define | MXC_F_CSI2_CFG_DISABLE_PAYLOAD_0_EMBEDDED ((uint32_t)(0x1UL << MXC_F_CSI2_CFG_DISABLE_PAYLOAD_0_EMBEDDED_POS)) |
| |
| #define | MXC_F_CSI2_CFG_DISABLE_PAYLOAD_0_YUV420_8BIT_POS 8 |
| |
| #define | MXC_F_CSI2_CFG_DISABLE_PAYLOAD_0_YUV420_8BIT ((uint32_t)(0x1UL << MXC_F_CSI2_CFG_DISABLE_PAYLOAD_0_YUV420_8BIT_POS)) |
| |
| #define | MXC_F_CSI2_CFG_DISABLE_PAYLOAD_0_YUV420_10BIT_POS 9 |
| |
| #define | MXC_F_CSI2_CFG_DISABLE_PAYLOAD_0_YUV420_10BIT ((uint32_t)(0x1UL << MXC_F_CSI2_CFG_DISABLE_PAYLOAD_0_YUV420_10BIT_POS)) |
| |
| #define | MXC_F_CSI2_CFG_DISABLE_PAYLOAD_0_YUV420_8BIT_LEG_POS 10 |
| |
| #define | MXC_F_CSI2_CFG_DISABLE_PAYLOAD_0_YUV420_8BIT_LEG ((uint32_t)(0x1UL << MXC_F_CSI2_CFG_DISABLE_PAYLOAD_0_YUV420_8BIT_LEG_POS)) |
| |
| #define | MXC_F_CSI2_CFG_DISABLE_PAYLOAD_0_YUV420_8BIT_CSP_POS 12 |
| |
| #define | MXC_F_CSI2_CFG_DISABLE_PAYLOAD_0_YUV420_8BIT_CSP ((uint32_t)(0x1UL << MXC_F_CSI2_CFG_DISABLE_PAYLOAD_0_YUV420_8BIT_CSP_POS)) |
| |
| #define | MXC_F_CSI2_CFG_DISABLE_PAYLOAD_0_YUV420_10BIT_CSP_POS 13 |
| |
| #define | MXC_F_CSI2_CFG_DISABLE_PAYLOAD_0_YUV420_10BIT_CSP ((uint32_t)(0x1UL << MXC_F_CSI2_CFG_DISABLE_PAYLOAD_0_YUV420_10BIT_CSP_POS)) |
| |
| #define | MXC_F_CSI2_CFG_DISABLE_PAYLOAD_0_YUV422_8BIT_POS 14 |
| |
| #define | MXC_F_CSI2_CFG_DISABLE_PAYLOAD_0_YUV422_8BIT ((uint32_t)(0x1UL << MXC_F_CSI2_CFG_DISABLE_PAYLOAD_0_YUV422_8BIT_POS)) |
| |
| #define | MXC_F_CSI2_CFG_DISABLE_PAYLOAD_0_YUV422_10BIT_POS 15 |
| |
| #define | MXC_F_CSI2_CFG_DISABLE_PAYLOAD_0_YUV422_10BIT ((uint32_t)(0x1UL << MXC_F_CSI2_CFG_DISABLE_PAYLOAD_0_YUV422_10BIT_POS)) |
| |
| #define | MXC_F_CSI2_CFG_DISABLE_PAYLOAD_0_RGB444_POS 16 |
| |
| #define | MXC_F_CSI2_CFG_DISABLE_PAYLOAD_0_RGB444 ((uint32_t)(0x1UL << MXC_F_CSI2_CFG_DISABLE_PAYLOAD_0_RGB444_POS)) |
| |
| #define | MXC_F_CSI2_CFG_DISABLE_PAYLOAD_0_RGB555_POS 17 |
| |
| #define | MXC_F_CSI2_CFG_DISABLE_PAYLOAD_0_RGB555 ((uint32_t)(0x1UL << MXC_F_CSI2_CFG_DISABLE_PAYLOAD_0_RGB555_POS)) |
| |
| #define | MXC_F_CSI2_CFG_DISABLE_PAYLOAD_0_RGB565_POS 18 |
| |
| #define | MXC_F_CSI2_CFG_DISABLE_PAYLOAD_0_RGB565 ((uint32_t)(0x1UL << MXC_F_CSI2_CFG_DISABLE_PAYLOAD_0_RGB565_POS)) |
| |
| #define | MXC_F_CSI2_CFG_DISABLE_PAYLOAD_0_RGB666_POS 19 |
| |
| #define | MXC_F_CSI2_CFG_DISABLE_PAYLOAD_0_RGB666 ((uint32_t)(0x1UL << MXC_F_CSI2_CFG_DISABLE_PAYLOAD_0_RGB666_POS)) |
| |
| #define | MXC_F_CSI2_CFG_DISABLE_PAYLOAD_0_RGB888_POS 20 |
| |
| #define | MXC_F_CSI2_CFG_DISABLE_PAYLOAD_0_RGB888 ((uint32_t)(0x1UL << MXC_F_CSI2_CFG_DISABLE_PAYLOAD_0_RGB888_POS)) |
| |
| #define | MXC_F_CSI2_CFG_DISABLE_PAYLOAD_0_RAW6_POS 24 |
| |
| #define | MXC_F_CSI2_CFG_DISABLE_PAYLOAD_0_RAW6 ((uint32_t)(0x1UL << MXC_F_CSI2_CFG_DISABLE_PAYLOAD_0_RAW6_POS)) |
| |
| #define | MXC_F_CSI2_CFG_DISABLE_PAYLOAD_0_RAW7_POS 25 |
| |
| #define | MXC_F_CSI2_CFG_DISABLE_PAYLOAD_0_RAW7 ((uint32_t)(0x1UL << MXC_F_CSI2_CFG_DISABLE_PAYLOAD_0_RAW7_POS)) |
| |
| #define | MXC_F_CSI2_CFG_DISABLE_PAYLOAD_0_RAW8_POS 26 |
| |
| #define | MXC_F_CSI2_CFG_DISABLE_PAYLOAD_0_RAW8 ((uint32_t)(0x1UL << MXC_F_CSI2_CFG_DISABLE_PAYLOAD_0_RAW8_POS)) |
| |
| #define | MXC_F_CSI2_CFG_DISABLE_PAYLOAD_0_RAW10_POS 27 |
| |
| #define | MXC_F_CSI2_CFG_DISABLE_PAYLOAD_0_RAW10 ((uint32_t)(0x1UL << MXC_F_CSI2_CFG_DISABLE_PAYLOAD_0_RAW10_POS)) |
| |
| #define | MXC_F_CSI2_CFG_DISABLE_PAYLOAD_0_RAW12_POS 28 |
| |
| #define | MXC_F_CSI2_CFG_DISABLE_PAYLOAD_0_RAW12 ((uint32_t)(0x1UL << MXC_F_CSI2_CFG_DISABLE_PAYLOAD_0_RAW12_POS)) |
| |
| #define | MXC_F_CSI2_CFG_DISABLE_PAYLOAD_0_RAW14_POS 29 |
| |
| #define | MXC_F_CSI2_CFG_DISABLE_PAYLOAD_0_RAW14 ((uint32_t)(0x1UL << MXC_F_CSI2_CFG_DISABLE_PAYLOAD_0_RAW14_POS)) |
| |
| #define | MXC_F_CSI2_CFG_DISABLE_PAYLOAD_0_RAW16_POS 30 |
| |
| #define | MXC_F_CSI2_CFG_DISABLE_PAYLOAD_0_RAW16 ((uint32_t)(0x1UL << MXC_F_CSI2_CFG_DISABLE_PAYLOAD_0_RAW16_POS)) |
| |
| #define | MXC_F_CSI2_CFG_DISABLE_PAYLOAD_0_RAW20_POS 31 |
| |
| #define | MXC_F_CSI2_CFG_DISABLE_PAYLOAD_0_RAW20 ((uint32_t)(0x1UL << MXC_F_CSI2_CFG_DISABLE_PAYLOAD_0_RAW20_POS)) |
| |
| #define | MXC_F_CSI2_CFG_DISABLE_PAYLOAD_1_USR_DEF_TYPE30_POS 0 |
| |
| #define | MXC_F_CSI2_CFG_DISABLE_PAYLOAD_1_USR_DEF_TYPE30 ((uint32_t)(0x1UL << MXC_F_CSI2_CFG_DISABLE_PAYLOAD_1_USR_DEF_TYPE30_POS)) |
| |
| #define | MXC_F_CSI2_CFG_DISABLE_PAYLOAD_1_USR_DEF_TYPE31_POS 1 |
| |
| #define | MXC_F_CSI2_CFG_DISABLE_PAYLOAD_1_USR_DEF_TYPE31 ((uint32_t)(0x1UL << MXC_F_CSI2_CFG_DISABLE_PAYLOAD_1_USR_DEF_TYPE31_POS)) |
| |
| #define | MXC_F_CSI2_CFG_DISABLE_PAYLOAD_1_USR_DEF_TYPE32_POS 2 |
| |
| #define | MXC_F_CSI2_CFG_DISABLE_PAYLOAD_1_USR_DEF_TYPE32 ((uint32_t)(0x1UL << MXC_F_CSI2_CFG_DISABLE_PAYLOAD_1_USR_DEF_TYPE32_POS)) |
| |
| #define | MXC_F_CSI2_CFG_DISABLE_PAYLOAD_1_USR_DEF_TYPE33_POS 3 |
| |
| #define | MXC_F_CSI2_CFG_DISABLE_PAYLOAD_1_USR_DEF_TYPE33 ((uint32_t)(0x1UL << MXC_F_CSI2_CFG_DISABLE_PAYLOAD_1_USR_DEF_TYPE33_POS)) |
| |
| #define | MXC_F_CSI2_CFG_DISABLE_PAYLOAD_1_USR_DEF_TYPE34_POS 4 |
| |
| #define | MXC_F_CSI2_CFG_DISABLE_PAYLOAD_1_USR_DEF_TYPE34 ((uint32_t)(0x1UL << MXC_F_CSI2_CFG_DISABLE_PAYLOAD_1_USR_DEF_TYPE34_POS)) |
| |
| #define | MXC_F_CSI2_CFG_DISABLE_PAYLOAD_1_USR_DEF_TYPE35_POS 5 |
| |
| #define | MXC_F_CSI2_CFG_DISABLE_PAYLOAD_1_USR_DEF_TYPE35 ((uint32_t)(0x1UL << MXC_F_CSI2_CFG_DISABLE_PAYLOAD_1_USR_DEF_TYPE35_POS)) |
| |
| #define | MXC_F_CSI2_CFG_DISABLE_PAYLOAD_1_USR_DEF_TYPE36_POS 6 |
| |
| #define | MXC_F_CSI2_CFG_DISABLE_PAYLOAD_1_USR_DEF_TYPE36 ((uint32_t)(0x1UL << MXC_F_CSI2_CFG_DISABLE_PAYLOAD_1_USR_DEF_TYPE36_POS)) |
| |
| #define | MXC_F_CSI2_CFG_DISABLE_PAYLOAD_1_USR_DEF_TYPE37_POS 7 |
| |
| #define | MXC_F_CSI2_CFG_DISABLE_PAYLOAD_1_USR_DEF_TYPE37 ((uint32_t)(0x1UL << MXC_F_CSI2_CFG_DISABLE_PAYLOAD_1_USR_DEF_TYPE37_POS)) |
| |
| #define | MXC_F_CSI2_CFG_DATABUS16_SEL_EN_POS 0 |
| |
| #define | MXC_F_CSI2_CFG_DATABUS16_SEL_EN ((uint32_t)(0x1UL << MXC_F_CSI2_CFG_DATABUS16_SEL_EN_POS)) |
| |
| #define | MXC_F_CSI2_CFG_D0_SWAP_SEL_SRC_POS 0 |
| |
| #define | MXC_F_CSI2_CFG_D0_SWAP_SEL_SRC ((uint32_t)(0x7UL << MXC_F_CSI2_CFG_D0_SWAP_SEL_SRC_POS)) |
| |
| #define | MXC_V_CSI2_CFG_D0_SWAP_SEL_SRC_PAD_CDRX_L0 ((uint32_t)0x0UL) |
| |
| #define | MXC_S_CSI2_CFG_D0_SWAP_SEL_SRC_PAD_CDRX_L0 (MXC_V_CSI2_CFG_D0_SWAP_SEL_SRC_PAD_CDRX_L0 << MXC_F_CSI2_CFG_D0_SWAP_SEL_SRC_POS) |
| |
| #define | MXC_V_CSI2_CFG_D0_SWAP_SEL_SRC_PAD_CDRX_L1 ((uint32_t)0x1UL) |
| |
| #define | MXC_S_CSI2_CFG_D0_SWAP_SEL_SRC_PAD_CDRX_L1 (MXC_V_CSI2_CFG_D0_SWAP_SEL_SRC_PAD_CDRX_L1 << MXC_F_CSI2_CFG_D0_SWAP_SEL_SRC_POS) |
| |
| #define | MXC_V_CSI2_CFG_D0_SWAP_SEL_SRC_PAD_CDRX_L2 ((uint32_t)0x2UL) |
| |
| #define | MXC_S_CSI2_CFG_D0_SWAP_SEL_SRC_PAD_CDRX_L2 (MXC_V_CSI2_CFG_D0_SWAP_SEL_SRC_PAD_CDRX_L2 << MXC_F_CSI2_CFG_D0_SWAP_SEL_SRC_POS) |
| |
| #define | MXC_V_CSI2_CFG_D0_SWAP_SEL_SRC_PAD_CDRX_L3 ((uint32_t)0x3UL) |
| |
| #define | MXC_S_CSI2_CFG_D0_SWAP_SEL_SRC_PAD_CDRX_L3 (MXC_V_CSI2_CFG_D0_SWAP_SEL_SRC_PAD_CDRX_L3 << MXC_F_CSI2_CFG_D0_SWAP_SEL_SRC_POS) |
| |
| #define | MXC_V_CSI2_CFG_D0_SWAP_SEL_SRC_PAD_CDRX_L4 ((uint32_t)0x4UL) |
| |
| #define | MXC_S_CSI2_CFG_D0_SWAP_SEL_SRC_PAD_CDRX_L4 (MXC_V_CSI2_CFG_D0_SWAP_SEL_SRC_PAD_CDRX_L4 << MXC_F_CSI2_CFG_D0_SWAP_SEL_SRC_POS) |
| |
| #define | MXC_F_CSI2_CFG_D1_SWAP_SEL_SRC_POS 0 |
| |
| #define | MXC_F_CSI2_CFG_D1_SWAP_SEL_SRC ((uint32_t)(0x7UL << MXC_F_CSI2_CFG_D1_SWAP_SEL_SRC_POS)) |
| |
| #define | MXC_V_CSI2_CFG_D1_SWAP_SEL_SRC_PAD_CDRX_L0 ((uint32_t)0x0UL) |
| |
| #define | MXC_S_CSI2_CFG_D1_SWAP_SEL_SRC_PAD_CDRX_L0 (MXC_V_CSI2_CFG_D1_SWAP_SEL_SRC_PAD_CDRX_L0 << MXC_F_CSI2_CFG_D1_SWAP_SEL_SRC_POS) |
| |
| #define | MXC_V_CSI2_CFG_D1_SWAP_SEL_SRC_PAD_CDRX_L1 ((uint32_t)0x1UL) |
| |
| #define | MXC_S_CSI2_CFG_D1_SWAP_SEL_SRC_PAD_CDRX_L1 (MXC_V_CSI2_CFG_D1_SWAP_SEL_SRC_PAD_CDRX_L1 << MXC_F_CSI2_CFG_D1_SWAP_SEL_SRC_POS) |
| |
| #define | MXC_V_CSI2_CFG_D1_SWAP_SEL_SRC_PAD_CDRX_L2 ((uint32_t)0x2UL) |
| |
| #define | MXC_S_CSI2_CFG_D1_SWAP_SEL_SRC_PAD_CDRX_L2 (MXC_V_CSI2_CFG_D1_SWAP_SEL_SRC_PAD_CDRX_L2 << MXC_F_CSI2_CFG_D1_SWAP_SEL_SRC_POS) |
| |
| #define | MXC_V_CSI2_CFG_D1_SWAP_SEL_SRC_PAD_CDRX_L3 ((uint32_t)0x3UL) |
| |
| #define | MXC_S_CSI2_CFG_D1_SWAP_SEL_SRC_PAD_CDRX_L3 (MXC_V_CSI2_CFG_D1_SWAP_SEL_SRC_PAD_CDRX_L3 << MXC_F_CSI2_CFG_D1_SWAP_SEL_SRC_POS) |
| |
| #define | MXC_V_CSI2_CFG_D1_SWAP_SEL_SRC_PAD_CDRX_L4 ((uint32_t)0x4UL) |
| |
| #define | MXC_S_CSI2_CFG_D1_SWAP_SEL_SRC_PAD_CDRX_L4 (MXC_V_CSI2_CFG_D1_SWAP_SEL_SRC_PAD_CDRX_L4 << MXC_F_CSI2_CFG_D1_SWAP_SEL_SRC_POS) |
| |
| #define | MXC_F_CSI2_CFG_D2_SWAP_SEL_SRC_POS 0 |
| |
| #define | MXC_F_CSI2_CFG_D2_SWAP_SEL_SRC ((uint32_t)(0x7UL << MXC_F_CSI2_CFG_D2_SWAP_SEL_SRC_POS)) |
| |
| #define | MXC_V_CSI2_CFG_D2_SWAP_SEL_SRC_PAD_CDRX_L0 ((uint32_t)0x0UL) |
| |
| #define | MXC_S_CSI2_CFG_D2_SWAP_SEL_SRC_PAD_CDRX_L0 (MXC_V_CSI2_CFG_D2_SWAP_SEL_SRC_PAD_CDRX_L0 << MXC_F_CSI2_CFG_D2_SWAP_SEL_SRC_POS) |
| |
| #define | MXC_V_CSI2_CFG_D2_SWAP_SEL_SRC_PAD_CDRX_L1 ((uint32_t)0x1UL) |
| |
| #define | MXC_S_CSI2_CFG_D2_SWAP_SEL_SRC_PAD_CDRX_L1 (MXC_V_CSI2_CFG_D2_SWAP_SEL_SRC_PAD_CDRX_L1 << MXC_F_CSI2_CFG_D2_SWAP_SEL_SRC_POS) |
| |
| #define | MXC_V_CSI2_CFG_D2_SWAP_SEL_SRC_PAD_CDRX_L2 ((uint32_t)0x2UL) |
| |
| #define | MXC_S_CSI2_CFG_D2_SWAP_SEL_SRC_PAD_CDRX_L2 (MXC_V_CSI2_CFG_D2_SWAP_SEL_SRC_PAD_CDRX_L2 << MXC_F_CSI2_CFG_D2_SWAP_SEL_SRC_POS) |
| |
| #define | MXC_V_CSI2_CFG_D2_SWAP_SEL_SRC_PAD_CDRX_L3 ((uint32_t)0x3UL) |
| |
| #define | MXC_S_CSI2_CFG_D2_SWAP_SEL_SRC_PAD_CDRX_L3 (MXC_V_CSI2_CFG_D2_SWAP_SEL_SRC_PAD_CDRX_L3 << MXC_F_CSI2_CFG_D2_SWAP_SEL_SRC_POS) |
| |
| #define | MXC_V_CSI2_CFG_D2_SWAP_SEL_SRC_PAD_CDRX_L4 ((uint32_t)0x4UL) |
| |
| #define | MXC_S_CSI2_CFG_D2_SWAP_SEL_SRC_PAD_CDRX_L4 (MXC_V_CSI2_CFG_D2_SWAP_SEL_SRC_PAD_CDRX_L4 << MXC_F_CSI2_CFG_D2_SWAP_SEL_SRC_POS) |
| |
| #define | MXC_F_CSI2_CFG_D3_SWAP_SEL_SRC_POS 0 |
| |
| #define | MXC_F_CSI2_CFG_D3_SWAP_SEL_SRC ((uint32_t)(0x7UL << MXC_F_CSI2_CFG_D3_SWAP_SEL_SRC_POS)) |
| |
| #define | MXC_V_CSI2_CFG_D3_SWAP_SEL_SRC_PAD_CDRX_L0 ((uint32_t)0x0UL) |
| |
| #define | MXC_S_CSI2_CFG_D3_SWAP_SEL_SRC_PAD_CDRX_L0 (MXC_V_CSI2_CFG_D3_SWAP_SEL_SRC_PAD_CDRX_L0 << MXC_F_CSI2_CFG_D3_SWAP_SEL_SRC_POS) |
| |
| #define | MXC_V_CSI2_CFG_D3_SWAP_SEL_SRC_PAD_CDRX_L1 ((uint32_t)0x1UL) |
| |
| #define | MXC_S_CSI2_CFG_D3_SWAP_SEL_SRC_PAD_CDRX_L1 (MXC_V_CSI2_CFG_D3_SWAP_SEL_SRC_PAD_CDRX_L1 << MXC_F_CSI2_CFG_D3_SWAP_SEL_SRC_POS) |
| |
| #define | MXC_V_CSI2_CFG_D3_SWAP_SEL_SRC_PAD_CDRX_L2 ((uint32_t)0x2UL) |
| |
| #define | MXC_S_CSI2_CFG_D3_SWAP_SEL_SRC_PAD_CDRX_L2 (MXC_V_CSI2_CFG_D3_SWAP_SEL_SRC_PAD_CDRX_L2 << MXC_F_CSI2_CFG_D3_SWAP_SEL_SRC_POS) |
| |
| #define | MXC_V_CSI2_CFG_D3_SWAP_SEL_SRC_PAD_CDRX_L3 ((uint32_t)0x3UL) |
| |
| #define | MXC_S_CSI2_CFG_D3_SWAP_SEL_SRC_PAD_CDRX_L3 (MXC_V_CSI2_CFG_D3_SWAP_SEL_SRC_PAD_CDRX_L3 << MXC_F_CSI2_CFG_D3_SWAP_SEL_SRC_POS) |
| |
| #define | MXC_V_CSI2_CFG_D3_SWAP_SEL_SRC_PAD_CDRX_L4 ((uint32_t)0x4UL) |
| |
| #define | MXC_S_CSI2_CFG_D3_SWAP_SEL_SRC_PAD_CDRX_L4 (MXC_V_CSI2_CFG_D3_SWAP_SEL_SRC_PAD_CDRX_L4 << MXC_F_CSI2_CFG_D3_SWAP_SEL_SRC_POS) |
| |
| #define | MXC_F_CSI2_CFG_C0_SWAP_SEL_SRC_POS 0 |
| |
| #define | MXC_F_CSI2_CFG_C0_SWAP_SEL_SRC ((uint32_t)(0x7UL << MXC_F_CSI2_CFG_C0_SWAP_SEL_SRC_POS)) |
| |
| #define | MXC_V_CSI2_CFG_C0_SWAP_SEL_SRC_PAD_CDRX_L0 ((uint32_t)0x0UL) |
| |
| #define | MXC_S_CSI2_CFG_C0_SWAP_SEL_SRC_PAD_CDRX_L0 (MXC_V_CSI2_CFG_C0_SWAP_SEL_SRC_PAD_CDRX_L0 << MXC_F_CSI2_CFG_C0_SWAP_SEL_SRC_POS) |
| |
| #define | MXC_V_CSI2_CFG_C0_SWAP_SEL_SRC_PAD_CDRX_L1 ((uint32_t)0x1UL) |
| |
| #define | MXC_S_CSI2_CFG_C0_SWAP_SEL_SRC_PAD_CDRX_L1 (MXC_V_CSI2_CFG_C0_SWAP_SEL_SRC_PAD_CDRX_L1 << MXC_F_CSI2_CFG_C0_SWAP_SEL_SRC_POS) |
| |
| #define | MXC_V_CSI2_CFG_C0_SWAP_SEL_SRC_PAD_CDRX_L2 ((uint32_t)0x2UL) |
| |
| #define | MXC_S_CSI2_CFG_C0_SWAP_SEL_SRC_PAD_CDRX_L2 (MXC_V_CSI2_CFG_C0_SWAP_SEL_SRC_PAD_CDRX_L2 << MXC_F_CSI2_CFG_C0_SWAP_SEL_SRC_POS) |
| |
| #define | MXC_V_CSI2_CFG_C0_SWAP_SEL_SRC_PAD_CDRX_L3 ((uint32_t)0x3UL) |
| |
| #define | MXC_S_CSI2_CFG_C0_SWAP_SEL_SRC_PAD_CDRX_L3 (MXC_V_CSI2_CFG_C0_SWAP_SEL_SRC_PAD_CDRX_L3 << MXC_F_CSI2_CFG_C0_SWAP_SEL_SRC_POS) |
| |
| #define | MXC_V_CSI2_CFG_C0_SWAP_SEL_SRC_PAD_CDRX_L4 ((uint32_t)0x4UL) |
| |
| #define | MXC_S_CSI2_CFG_C0_SWAP_SEL_SRC_PAD_CDRX_L4 (MXC_V_CSI2_CFG_C0_SWAP_SEL_SRC_PAD_CDRX_L4 << MXC_F_CSI2_CFG_C0_SWAP_SEL_SRC_POS) |
| |
| #define | MXC_F_CSI2_CFG_DPDN_SWAP_SWAP_DATA_LANE0_POS 0 |
| |
| #define | MXC_F_CSI2_CFG_DPDN_SWAP_SWAP_DATA_LANE0 ((uint32_t)(0x1UL << MXC_F_CSI2_CFG_DPDN_SWAP_SWAP_DATA_LANE0_POS)) |
| |
| #define | MXC_F_CSI2_CFG_DPDN_SWAP_SWAP_DATA_LANE1_POS 1 |
| |
| #define | MXC_F_CSI2_CFG_DPDN_SWAP_SWAP_DATA_LANE1 ((uint32_t)(0x1UL << MXC_F_CSI2_CFG_DPDN_SWAP_SWAP_DATA_LANE1_POS)) |
| |
| #define | MXC_F_CSI2_CFG_DPDN_SWAP_SWAP_DATA_LANE2_POS 2 |
| |
| #define | MXC_F_CSI2_CFG_DPDN_SWAP_SWAP_DATA_LANE2 ((uint32_t)(0x1UL << MXC_F_CSI2_CFG_DPDN_SWAP_SWAP_DATA_LANE2_POS)) |
| |
| #define | MXC_F_CSI2_CFG_DPDN_SWAP_SWAP_DATA_LANE3_POS 3 |
| |
| #define | MXC_F_CSI2_CFG_DPDN_SWAP_SWAP_DATA_LANE3 ((uint32_t)(0x1UL << MXC_F_CSI2_CFG_DPDN_SWAP_SWAP_DATA_LANE3_POS)) |
| |
| #define | MXC_F_CSI2_CFG_DPDN_SWAP_SWAP_CLK_LANE_POS 4 |
| |
| #define | MXC_F_CSI2_CFG_DPDN_SWAP_SWAP_CLK_LANE ((uint32_t)(0x1UL << MXC_F_CSI2_CFG_DPDN_SWAP_SWAP_CLK_LANE_POS)) |
| |
| #define | MXC_F_CSI2_RESET_DESKEW_DATA_LANE0_POS 0 |
| |
| #define | MXC_F_CSI2_RESET_DESKEW_DATA_LANE0 ((uint32_t)(0x1UL << MXC_F_CSI2_RESET_DESKEW_DATA_LANE0_POS)) |
| |
| #define | MXC_F_CSI2_RESET_DESKEW_DATA_LANE1_POS 1 |
| |
| #define | MXC_F_CSI2_RESET_DESKEW_DATA_LANE1 ((uint32_t)(0x1UL << MXC_F_CSI2_RESET_DESKEW_DATA_LANE1_POS)) |
| |
| #define | MXC_F_CSI2_RESET_DESKEW_DATA_LANE2_POS 2 |
| |
| #define | MXC_F_CSI2_RESET_DESKEW_DATA_LANE2 ((uint32_t)(0x1UL << MXC_F_CSI2_RESET_DESKEW_DATA_LANE2_POS)) |
| |
| #define | MXC_F_CSI2_RESET_DESKEW_DATA_LANE3_POS 3 |
| |
| #define | MXC_F_CSI2_RESET_DESKEW_DATA_LANE3 ((uint32_t)(0x1UL << MXC_F_CSI2_RESET_DESKEW_DATA_LANE3_POS)) |
| |
| #define | MXC_F_CSI2_VCONTROL_NORMAL_MODE_POS 0 |
| |
| #define | MXC_F_CSI2_VCONTROL_NORMAL_MODE ((uint32_t)(0x1UL << MXC_F_CSI2_VCONTROL_NORMAL_MODE_POS)) |
| |
| #define | MXC_F_CSI2_VCONTROL_LP_RX_DC_TEST_POS 1 |
| |
| #define | MXC_F_CSI2_VCONTROL_LP_RX_DC_TEST ((uint32_t)(0x1UL << MXC_F_CSI2_VCONTROL_LP_RX_DC_TEST_POS)) |
| |
| #define | MXC_F_CSI2_VCONTROL_LP_RX_DC_1_POS 2 |
| |
| #define | MXC_F_CSI2_VCONTROL_LP_RX_DC_1 ((uint32_t)(0x1UL << MXC_F_CSI2_VCONTROL_LP_RX_DC_1_POS)) |
| |
| #define | MXC_F_CSI2_VCONTROL_LP_RX_DC_0_POS 3 |
| |
| #define | MXC_F_CSI2_VCONTROL_LP_RX_DC_0 ((uint32_t)(0x1UL << MXC_F_CSI2_VCONTROL_LP_RX_DC_0_POS)) |
| |
| #define | MXC_F_CSI2_VCONTROL_CAL_SEN_1_POS 4 |
| |
| #define | MXC_F_CSI2_VCONTROL_CAL_SEN_1 ((uint32_t)(0x1UL << MXC_F_CSI2_VCONTROL_CAL_SEN_1_POS)) |
| |
| #define | MXC_F_CSI2_VCONTROL_CAL_SEN_0_POS 5 |
| |
| #define | MXC_F_CSI2_VCONTROL_CAL_SEN_0 ((uint32_t)(0x1UL << MXC_F_CSI2_VCONTROL_CAL_SEN_0_POS)) |
| |
| #define | MXC_F_CSI2_VCONTROL_HSRT_0_POS 7 |
| |
| #define | MXC_F_CSI2_VCONTROL_HSRT_0 ((uint32_t)(0x1UL << MXC_F_CSI2_VCONTROL_HSRT_0_POS)) |
| |
| #define | MXC_F_CSI2_VCONTROL_HSRT_1_POS 8 |
| |
| #define | MXC_F_CSI2_VCONTROL_HSRT_1 ((uint32_t)(0x1UL << MXC_F_CSI2_VCONTROL_HSRT_1_POS)) |
| |
| #define | MXC_F_CSI2_VCONTROL_LP_RX_PARTBERT_POS 10 |
| |
| #define | MXC_F_CSI2_VCONTROL_LP_RX_PARTBERT ((uint32_t)(0x1UL << MXC_F_CSI2_VCONTROL_LP_RX_PARTBERT_POS)) |
| |
| #define | MXC_F_CSI2_VCONTROL_HS_INT_LOOPBACK_POS 11 |
| |
| #define | MXC_F_CSI2_VCONTROL_HS_INT_LOOPBACK ((uint32_t)(0x1UL << MXC_F_CSI2_VCONTROL_HS_INT_LOOPBACK_POS)) |
| |
| #define | MXC_F_CSI2_VCONTROL_HS_RX_PARTBERT_POS 27 |
| |
| #define | MXC_F_CSI2_VCONTROL_HS_RX_PARTBERT ((uint32_t)(0x1UL << MXC_F_CSI2_VCONTROL_HS_RX_PARTBERT_POS)) |
| |
| #define | MXC_F_CSI2_VCONTROL_HS_RX_PRBS9_POS 28 |
| |
| #define | MXC_F_CSI2_VCONTROL_HS_RX_PRBS9 ((uint32_t)(0x1UL << MXC_F_CSI2_VCONTROL_HS_RX_PRBS9_POS)) |
| |
| #define | MXC_F_CSI2_VCONTROL_SUSPEND_MODE_POS 31 |
| |
| #define | MXC_F_CSI2_VCONTROL_SUSPEND_MODE ((uint32_t)(0x1UL << MXC_F_CSI2_VCONTROL_SUSPEND_MODE_POS)) |
| |
| #define | MXC_F_CSI2_RG_CDRX_DSIRX_EN_RXMODE_POS 0 |
| |
| #define | MXC_F_CSI2_RG_CDRX_DSIRX_EN_RXMODE ((uint32_t)(0x1UL << MXC_F_CSI2_RG_CDRX_DSIRX_EN_RXMODE_POS)) |
| |
| #define | MXC_F_CSI2_RG_CDRX_BISTHS_PLL_PRE_DIV2_RXMODE_POS 0 |
| |
| #define | MXC_F_CSI2_RG_CDRX_BISTHS_PLL_PRE_DIV2_RXMODE ((uint32_t)(0x1UL << MXC_F_CSI2_RG_CDRX_BISTHS_PLL_PRE_DIV2_RXMODE_POS)) |
| |
| #define | MXC_F_CSI2_VFIFO_CFG0_VC_POS 0 |
| |
| #define | MXC_F_CSI2_VFIFO_CFG0_VC ((uint32_t)(0x3UL << MXC_F_CSI2_VFIFO_CFG0_VC_POS)) |
| |
| #define | MXC_F_CSI2_VFIFO_CFG0_DMAMODE_POS 6 |
| |
| #define | MXC_F_CSI2_VFIFO_CFG0_DMAMODE ((uint32_t)(0x3UL << MXC_F_CSI2_VFIFO_CFG0_DMAMODE_POS)) |
| |
| #define | MXC_V_CSI2_VFIFO_CFG0_DMAMODE_NO_DMA ((uint32_t)0x0UL) |
| |
| #define | MXC_S_CSI2_VFIFO_CFG0_DMAMODE_NO_DMA (MXC_V_CSI2_VFIFO_CFG0_DMAMODE_NO_DMA << MXC_F_CSI2_VFIFO_CFG0_DMAMODE_POS) |
| |
| #define | MXC_V_CSI2_VFIFO_CFG0_DMAMODE_DMA_REQ ((uint32_t)0x1UL) |
| |
| #define | MXC_S_CSI2_VFIFO_CFG0_DMAMODE_DMA_REQ (MXC_V_CSI2_VFIFO_CFG0_DMAMODE_DMA_REQ << MXC_F_CSI2_VFIFO_CFG0_DMAMODE_POS) |
| |
| #define | MXC_V_CSI2_VFIFO_CFG0_DMAMODE_FIFO_THD ((uint32_t)0x2UL) |
| |
| #define | MXC_S_CSI2_VFIFO_CFG0_DMAMODE_FIFO_THD (MXC_V_CSI2_VFIFO_CFG0_DMAMODE_FIFO_THD << MXC_F_CSI2_VFIFO_CFG0_DMAMODE_POS) |
| |
| #define | MXC_V_CSI2_VFIFO_CFG0_DMAMODE_FIFO_FULL ((uint32_t)0x3UL) |
| |
| #define | MXC_S_CSI2_VFIFO_CFG0_DMAMODE_FIFO_FULL (MXC_V_CSI2_VFIFO_CFG0_DMAMODE_FIFO_FULL << MXC_F_CSI2_VFIFO_CFG0_DMAMODE_POS) |
| |
| #define | MXC_F_CSI2_VFIFO_CFG0_AHBWAIT_POS 8 |
| |
| #define | MXC_F_CSI2_VFIFO_CFG0_AHBWAIT ((uint32_t)(0x1UL << MXC_F_CSI2_VFIFO_CFG0_AHBWAIT_POS)) |
| |
| #define | MXC_F_CSI2_VFIFO_CFG0_FIFORM_POS 9 |
| |
| #define | MXC_F_CSI2_VFIFO_CFG0_FIFORM ((uint32_t)(0x1UL << MXC_F_CSI2_VFIFO_CFG0_FIFORM_POS)) |
| |
| #define | MXC_F_CSI2_VFIFO_CFG0_ERRDE_POS 10 |
| |
| #define | MXC_F_CSI2_VFIFO_CFG0_ERRDE ((uint32_t)(0x1UL << MXC_F_CSI2_VFIFO_CFG0_ERRDE_POS)) |
| |
| #define | MXC_F_CSI2_VFIFO_CFG0_FBWM_POS 11 |
| |
| #define | MXC_F_CSI2_VFIFO_CFG0_FBWM ((uint32_t)(0x1UL << MXC_F_CSI2_VFIFO_CFG0_FBWM_POS)) |
| |
| #define | MXC_F_CSI2_VFIFO_CFG1_AHBWCYC_POS 0 |
| |
| #define | MXC_F_CSI2_VFIFO_CFG1_AHBWCYC ((uint32_t)(0xFFFFUL << MXC_F_CSI2_VFIFO_CFG1_AHBWCYC_POS)) |
| |
| #define | MXC_F_CSI2_VFIFO_CFG1_WAIT_FIRST_FS_POS 16 |
| |
| #define | MXC_F_CSI2_VFIFO_CFG1_WAIT_FIRST_FS ((uint32_t)(0x1UL << MXC_F_CSI2_VFIFO_CFG1_WAIT_FIRST_FS_POS)) |
| |
| #define | MXC_F_CSI2_VFIFO_CFG1_ACCU_FRAME_CTRL_POS 17 |
| |
| #define | MXC_F_CSI2_VFIFO_CFG1_ACCU_FRAME_CTRL ((uint32_t)(0x1UL << MXC_F_CSI2_VFIFO_CFG1_ACCU_FRAME_CTRL_POS)) |
| |
| #define | MXC_F_CSI2_VFIFO_CFG1_ACCU_LINE_CTRL_POS 18 |
| |
| #define | MXC_F_CSI2_VFIFO_CFG1_ACCU_LINE_CTRL ((uint32_t)(0x1UL << MXC_F_CSI2_VFIFO_CFG1_ACCU_LINE_CTRL_POS)) |
| |
| #define | MXC_F_CSI2_VFIFO_CFG1_ACCU_LINE_CNT_POS 19 |
| |
| #define | MXC_F_CSI2_VFIFO_CFG1_ACCU_LINE_CNT ((uint32_t)(0x1UL << MXC_F_CSI2_VFIFO_CFG1_ACCU_LINE_CNT_POS)) |
| |
| #define | MXC_F_CSI2_VFIFO_CFG1_ACCU_PIXEL_CNT_POS 20 |
| |
| #define | MXC_F_CSI2_VFIFO_CFG1_ACCU_PIXEL_CNT ((uint32_t)(0x1UL << MXC_F_CSI2_VFIFO_CFG1_ACCU_PIXEL_CNT_POS)) |
| |
| #define | MXC_F_CSI2_VFIFO_CFG1_ACCU_PIXEL_ZERO_POS 21 |
| |
| #define | MXC_F_CSI2_VFIFO_CFG1_ACCU_PIXEL_ZERO ((uint32_t)(0x1UL << MXC_F_CSI2_VFIFO_CFG1_ACCU_PIXEL_ZERO_POS)) |
| |
| #define | MXC_F_CSI2_VFIFO_CTRL_FIFOEN_POS 0 |
| |
| #define | MXC_F_CSI2_VFIFO_CTRL_FIFOEN ((uint32_t)(0x1UL << MXC_F_CSI2_VFIFO_CTRL_FIFOEN_POS)) |
| |
| #define | MXC_F_CSI2_VFIFO_CTRL_FLUSH_POS 4 |
| |
| #define | MXC_F_CSI2_VFIFO_CTRL_FLUSH ((uint32_t)(0x1UL << MXC_F_CSI2_VFIFO_CTRL_FLUSH_POS)) |
| |
| #define | MXC_F_CSI2_VFIFO_CTRL_THD_POS 8 |
| |
| #define | MXC_F_CSI2_VFIFO_CTRL_THD ((uint32_t)(0x7FUL << MXC_F_CSI2_VFIFO_CTRL_THD_POS)) |
| |
| #define | MXC_F_CSI2_VFIFO_STS_FEMPTY_POS 0 |
| |
| #define | MXC_F_CSI2_VFIFO_STS_FEMPTY ((uint32_t)(0x1UL << MXC_F_CSI2_VFIFO_STS_FEMPTY_POS)) |
| |
| #define | MXC_F_CSI2_VFIFO_STS_FTHD_POS 1 |
| |
| #define | MXC_F_CSI2_VFIFO_STS_FTHD ((uint32_t)(0x1UL << MXC_F_CSI2_VFIFO_STS_FTHD_POS)) |
| |
| #define | MXC_F_CSI2_VFIFO_STS_FFULL_POS 2 |
| |
| #define | MXC_F_CSI2_VFIFO_STS_FFULL ((uint32_t)(0x1UL << MXC_F_CSI2_VFIFO_STS_FFULL_POS)) |
| |
| #define | MXC_F_CSI2_VFIFO_STS_UNDERRUN_POS 3 |
| |
| #define | MXC_F_CSI2_VFIFO_STS_UNDERRUN ((uint32_t)(0x1UL << MXC_F_CSI2_VFIFO_STS_UNDERRUN_POS)) |
| |
| #define | MXC_F_CSI2_VFIFO_STS_OVERRUN_POS 4 |
| |
| #define | MXC_F_CSI2_VFIFO_STS_OVERRUN ((uint32_t)(0x1UL << MXC_F_CSI2_VFIFO_STS_OVERRUN_POS)) |
| |
| #define | MXC_F_CSI2_VFIFO_STS_OUTSYNC_POS 5 |
| |
| #define | MXC_F_CSI2_VFIFO_STS_OUTSYNC ((uint32_t)(0x1UL << MXC_F_CSI2_VFIFO_STS_OUTSYNC_POS)) |
| |
| #define | MXC_F_CSI2_VFIFO_STS_FMTERR_POS 6 |
| |
| #define | MXC_F_CSI2_VFIFO_STS_FMTERR ((uint32_t)(0x1UL << MXC_F_CSI2_VFIFO_STS_FMTERR_POS)) |
| |
| #define | MXC_F_CSI2_VFIFO_STS_AHBWTO_POS 7 |
| |
| #define | MXC_F_CSI2_VFIFO_STS_AHBWTO ((uint32_t)(0x1UL << MXC_F_CSI2_VFIFO_STS_AHBWTO_POS)) |
| |
| #define | MXC_F_CSI2_VFIFO_STS_FS_POS 8 |
| |
| #define | MXC_F_CSI2_VFIFO_STS_FS ((uint32_t)(0x1UL << MXC_F_CSI2_VFIFO_STS_FS_POS)) |
| |
| #define | MXC_F_CSI2_VFIFO_STS_FE_POS 9 |
| |
| #define | MXC_F_CSI2_VFIFO_STS_FE ((uint32_t)(0x1UL << MXC_F_CSI2_VFIFO_STS_FE_POS)) |
| |
| #define | MXC_F_CSI2_VFIFO_STS_LS_POS 10 |
| |
| #define | MXC_F_CSI2_VFIFO_STS_LS ((uint32_t)(0x1UL << MXC_F_CSI2_VFIFO_STS_LS_POS)) |
| |
| #define | MXC_F_CSI2_VFIFO_STS_LE_POS 11 |
| |
| #define | MXC_F_CSI2_VFIFO_STS_LE ((uint32_t)(0x1UL << MXC_F_CSI2_VFIFO_STS_LE_POS)) |
| |
| #define | MXC_F_CSI2_VFIFO_STS_FELT_POS 16 |
| |
| #define | MXC_F_CSI2_VFIFO_STS_FELT ((uint32_t)(0x7FUL << MXC_F_CSI2_VFIFO_STS_FELT_POS)) |
| |
| #define | MXC_F_CSI2_VFIFO_STS_FMT_POS 24 |
| |
| #define | MXC_F_CSI2_VFIFO_STS_FMT ((uint32_t)(0x3FUL << MXC_F_CSI2_VFIFO_STS_FMT_POS)) |
| |
| #define | MXC_F_CSI2_VFIFO_LINE_NUM_LINE_NUM_POS 0 |
| |
| #define | MXC_F_CSI2_VFIFO_LINE_NUM_LINE_NUM ((uint32_t)(0x1FFFUL << MXC_F_CSI2_VFIFO_LINE_NUM_LINE_NUM_POS)) |
| |
| #define | MXC_F_CSI2_VFIFO_PIXEL_NUM_PIXEL_NUM_POS 0 |
| |
| #define | MXC_F_CSI2_VFIFO_PIXEL_NUM_PIXEL_NUM ((uint32_t)(0x3FFFUL << MXC_F_CSI2_VFIFO_PIXEL_NUM_PIXEL_NUM_POS)) |
| |
| #define | MXC_F_CSI2_VFIFO_LINE_CNT_LINE_CNT_POS 0 |
| |
| #define | MXC_F_CSI2_VFIFO_LINE_CNT_LINE_CNT ((uint32_t)(0xFFFUL << MXC_F_CSI2_VFIFO_LINE_CNT_LINE_CNT_POS)) |
| |
| #define | MXC_F_CSI2_VFIFO_PIXEL_CNT_PIXEL_CNT_POS 0 |
| |
| #define | MXC_F_CSI2_VFIFO_PIXEL_CNT_PIXEL_CNT ((uint32_t)(0x1FFFUL << MXC_F_CSI2_VFIFO_PIXEL_CNT_PIXEL_CNT_POS)) |
| |
| #define | MXC_F_CSI2_VFIFO_FRAME_STS_FRAME_STATE_POS 0 |
| |
| #define | MXC_F_CSI2_VFIFO_FRAME_STS_FRAME_STATE ((uint32_t)(0x7UL << MXC_F_CSI2_VFIFO_FRAME_STS_FRAME_STATE_POS)) |
| |
| #define | MXC_F_CSI2_VFIFO_FRAME_STS_ERROR_CODE_POS 3 |
| |
| #define | MXC_F_CSI2_VFIFO_FRAME_STS_ERROR_CODE ((uint32_t)(0x7UL << MXC_F_CSI2_VFIFO_FRAME_STS_ERROR_CODE_POS)) |
| |
| #define | MXC_F_CSI2_VFIFO_RAW_CTRL_RAW_CEN_POS 0 |
| |
| #define | MXC_F_CSI2_VFIFO_RAW_CTRL_RAW_CEN ((uint32_t)(0x1UL << MXC_F_CSI2_VFIFO_RAW_CTRL_RAW_CEN_POS)) |
| |
| #define | MXC_F_CSI2_VFIFO_RAW_CTRL_RAW_FF_AFO_POS 1 |
| |
| #define | MXC_F_CSI2_VFIFO_RAW_CTRL_RAW_FF_AFO ((uint32_t)(0x1UL << MXC_F_CSI2_VFIFO_RAW_CTRL_RAW_FF_AFO_POS)) |
| |
| #define | MXC_F_CSI2_VFIFO_RAW_CTRL_RAW_FF_FO_POS 4 |
| |
| #define | MXC_F_CSI2_VFIFO_RAW_CTRL_RAW_FF_FO ((uint32_t)(0x1UL << MXC_F_CSI2_VFIFO_RAW_CTRL_RAW_FF_FO_POS)) |
| |
| #define | MXC_F_CSI2_VFIFO_RAW_CTRL_RAW_FMT_POS 8 |
| |
| #define | MXC_F_CSI2_VFIFO_RAW_CTRL_RAW_FMT ((uint32_t)(0x3UL << MXC_F_CSI2_VFIFO_RAW_CTRL_RAW_FMT_POS)) |
| |
| #define | MXC_V_CSI2_VFIFO_RAW_CTRL_RAW_FMT_RGRG_GBGB ((uint32_t)0x0UL) |
| |
| #define | MXC_S_CSI2_VFIFO_RAW_CTRL_RAW_FMT_RGRG_GBGB (MXC_V_CSI2_VFIFO_RAW_CTRL_RAW_FMT_RGRG_GBGB << MXC_F_CSI2_VFIFO_RAW_CTRL_RAW_FMT_POS) |
| |
| #define | MXC_V_CSI2_VFIFO_RAW_CTRL_RAW_FMT_GRGR_BGBG ((uint32_t)0x1UL) |
| |
| #define | MXC_S_CSI2_VFIFO_RAW_CTRL_RAW_FMT_GRGR_BGBG (MXC_V_CSI2_VFIFO_RAW_CTRL_RAW_FMT_GRGR_BGBG << MXC_F_CSI2_VFIFO_RAW_CTRL_RAW_FMT_POS) |
| |
| #define | MXC_V_CSI2_VFIFO_RAW_CTRL_RAW_FMT_GBGB_RGRG ((uint32_t)0x2UL) |
| |
| #define | MXC_S_CSI2_VFIFO_RAW_CTRL_RAW_FMT_GBGB_RGRG (MXC_V_CSI2_VFIFO_RAW_CTRL_RAW_FMT_GBGB_RGRG << MXC_F_CSI2_VFIFO_RAW_CTRL_RAW_FMT_POS) |
| |
| #define | MXC_V_CSI2_VFIFO_RAW_CTRL_RAW_FMT_BGBG_GRGR ((uint32_t)0x3UL) |
| |
| #define | MXC_S_CSI2_VFIFO_RAW_CTRL_RAW_FMT_BGBG_GRGR (MXC_V_CSI2_VFIFO_RAW_CTRL_RAW_FMT_BGBG_GRGR << MXC_F_CSI2_VFIFO_RAW_CTRL_RAW_FMT_POS) |
| |
| #define | MXC_F_CSI2_VFIFO_RAW_CTRL_RGB_TYP_POS 12 |
| |
| #define | MXC_F_CSI2_VFIFO_RAW_CTRL_RGB_TYP ((uint32_t)(0x7UL << MXC_F_CSI2_VFIFO_RAW_CTRL_RGB_TYP_POS)) |
| |
| #define | MXC_V_CSI2_VFIFO_RAW_CTRL_RGB_TYP_RGB444 ((uint32_t)0x0UL) |
| |
| #define | MXC_S_CSI2_VFIFO_RAW_CTRL_RGB_TYP_RGB444 (MXC_V_CSI2_VFIFO_RAW_CTRL_RGB_TYP_RGB444 << MXC_F_CSI2_VFIFO_RAW_CTRL_RGB_TYP_POS) |
| |
| #define | MXC_V_CSI2_VFIFO_RAW_CTRL_RGB_TYP_RGB555 ((uint32_t)0x1UL) |
| |
| #define | MXC_S_CSI2_VFIFO_RAW_CTRL_RGB_TYP_RGB555 (MXC_V_CSI2_VFIFO_RAW_CTRL_RGB_TYP_RGB555 << MXC_F_CSI2_VFIFO_RAW_CTRL_RGB_TYP_POS) |
| |
| #define | MXC_V_CSI2_VFIFO_RAW_CTRL_RGB_TYP_RGB565 ((uint32_t)0x2UL) |
| |
| #define | MXC_S_CSI2_VFIFO_RAW_CTRL_RGB_TYP_RGB565 (MXC_V_CSI2_VFIFO_RAW_CTRL_RGB_TYP_RGB565 << MXC_F_CSI2_VFIFO_RAW_CTRL_RGB_TYP_POS) |
| |
| #define | MXC_V_CSI2_VFIFO_RAW_CTRL_RGB_TYP_RGB666 ((uint32_t)0x3UL) |
| |
| #define | MXC_S_CSI2_VFIFO_RAW_CTRL_RGB_TYP_RGB666 (MXC_V_CSI2_VFIFO_RAW_CTRL_RGB_TYP_RGB666 << MXC_F_CSI2_VFIFO_RAW_CTRL_RGB_TYP_POS) |
| |
| #define | MXC_V_CSI2_VFIFO_RAW_CTRL_RGB_TYP_RGG888 ((uint32_t)0x4UL) |
| |
| #define | MXC_S_CSI2_VFIFO_RAW_CTRL_RGB_TYP_RGG888 (MXC_V_CSI2_VFIFO_RAW_CTRL_RGB_TYP_RGG888 << MXC_F_CSI2_VFIFO_RAW_CTRL_RGB_TYP_POS) |
| |
| #define | MXC_F_CSI2_VFIFO_RAW_BUF0_ADDR_ADDR_POS 2 |
| |
| #define | MXC_F_CSI2_VFIFO_RAW_BUF0_ADDR_ADDR ((uint32_t)(0x3FFFFFFFUL << MXC_F_CSI2_VFIFO_RAW_BUF0_ADDR_ADDR_POS)) |
| |
| #define | MXC_F_CSI2_VFIFO_RAW_BUF1_ADDR_ADDR_POS 2 |
| |
| #define | MXC_F_CSI2_VFIFO_RAW_BUF1_ADDR_ADDR ((uint32_t)(0x3FFFFFFFUL << MXC_F_CSI2_VFIFO_RAW_BUF1_ADDR_ADDR_POS)) |
| |
| #define | MXC_F_CSI2_VFIFO_AHBM_CTRL_AHBMEN_POS 0 |
| |
| #define | MXC_F_CSI2_VFIFO_AHBM_CTRL_AHBMEN ((uint32_t)(0x1UL << MXC_F_CSI2_VFIFO_AHBM_CTRL_AHBMEN_POS)) |
| |
| #define | MXC_F_CSI2_VFIFO_AHBM_CTRL_AHBMCLR_POS 1 |
| |
| #define | MXC_F_CSI2_VFIFO_AHBM_CTRL_AHBMCLR ((uint32_t)(0x1UL << MXC_F_CSI2_VFIFO_AHBM_CTRL_AHBMCLR_POS)) |
| |
| #define | MXC_F_CSI2_VFIFO_AHBM_CTRL_BSTLEN_POS 4 |
| |
| #define | MXC_F_CSI2_VFIFO_AHBM_CTRL_BSTLEN ((uint32_t)(0x3UL << MXC_F_CSI2_VFIFO_AHBM_CTRL_BSTLEN_POS)) |
| |
| #define | MXC_V_CSI2_VFIFO_AHBM_CTRL_BSTLEN_VFIFO_THD ((uint32_t)0x0UL) |
| |
| #define | MXC_S_CSI2_VFIFO_AHBM_CTRL_BSTLEN_VFIFO_THD (MXC_V_CSI2_VFIFO_AHBM_CTRL_BSTLEN_VFIFO_THD << MXC_F_CSI2_VFIFO_AHBM_CTRL_BSTLEN_POS) |
| |
| #define | MXC_V_CSI2_VFIFO_AHBM_CTRL_BSTLEN_ONE_WORD ((uint32_t)0x1UL) |
| |
| #define | MXC_S_CSI2_VFIFO_AHBM_CTRL_BSTLEN_ONE_WORD (MXC_V_CSI2_VFIFO_AHBM_CTRL_BSTLEN_ONE_WORD << MXC_F_CSI2_VFIFO_AHBM_CTRL_BSTLEN_POS) |
| |
| #define | MXC_V_CSI2_VFIFO_AHBM_CTRL_BSTLEN_FOUR_WORDS ((uint32_t)0x2UL) |
| |
| #define | MXC_S_CSI2_VFIFO_AHBM_CTRL_BSTLEN_FOUR_WORDS (MXC_V_CSI2_VFIFO_AHBM_CTRL_BSTLEN_FOUR_WORDS << MXC_F_CSI2_VFIFO_AHBM_CTRL_BSTLEN_POS) |
| |
| #define | MXC_V_CSI2_VFIFO_AHBM_CTRL_BSTLEN_EIGHT_WORDS ((uint32_t)0x3UL) |
| |
| #define | MXC_S_CSI2_VFIFO_AHBM_CTRL_BSTLEN_EIGHT_WORDS (MXC_V_CSI2_VFIFO_AHBM_CTRL_BSTLEN_EIGHT_WORDS << MXC_F_CSI2_VFIFO_AHBM_CTRL_BSTLEN_POS) |
| |
| #define | MXC_F_CSI2_VFIFO_AHBM_STS_HRDY_TO_POS 0 |
| |
| #define | MXC_F_CSI2_VFIFO_AHBM_STS_HRDY_TO ((uint32_t)(0x1UL << MXC_F_CSI2_VFIFO_AHBM_STS_HRDY_TO_POS)) |
| |
| #define | MXC_F_CSI2_VFIFO_AHBM_STS_IDLE_TO_POS 1 |
| |
| #define | MXC_F_CSI2_VFIFO_AHBM_STS_IDLE_TO ((uint32_t)(0x1UL << MXC_F_CSI2_VFIFO_AHBM_STS_IDLE_TO_POS)) |
| |
| #define | MXC_F_CSI2_VFIFO_AHBM_STS_TRANS_MAX_POS 2 |
| |
| #define | MXC_F_CSI2_VFIFO_AHBM_STS_TRANS_MAX ((uint32_t)(0x1UL << MXC_F_CSI2_VFIFO_AHBM_STS_TRANS_MAX_POS)) |
| |
| #define | MXC_F_CSI2_VFIFO_AHBM_START_ADDR_AHBM_START_ADDR_POS 2 |
| |
| #define | MXC_F_CSI2_VFIFO_AHBM_START_ADDR_AHBM_START_ADDR ((uint32_t)(0x3FFFFFFFUL << MXC_F_CSI2_VFIFO_AHBM_START_ADDR_AHBM_START_ADDR_POS)) |
| |
| #define | MXC_F_CSI2_VFIFO_AHBM_ADDR_RANGE_AHBM_ADDR_RANGE_POS 2 |
| |
| #define | MXC_F_CSI2_VFIFO_AHBM_ADDR_RANGE_AHBM_ADDR_RANGE ((uint32_t)(0x3FFFUL << MXC_F_CSI2_VFIFO_AHBM_ADDR_RANGE_AHBM_ADDR_RANGE_POS)) |
| |
| #define | MXC_F_CSI2_VFIFO_AHBM_MAX_TRANS_AHBM_MAX_TRANS_POS 0 |
| |
| #define | MXC_F_CSI2_VFIFO_AHBM_MAX_TRANS_AHBM_MAX_TRANS ((uint32_t)(0xFFFFFFFFUL << MXC_F_CSI2_VFIFO_AHBM_MAX_TRANS_AHBM_MAX_TRANS_POS)) |
| |
| #define | MXC_F_CSI2_VFIFO_AHBM_TRANS_CNT_AHBM_TRANS_CNT_POS 0 |
| |
| #define | MXC_F_CSI2_VFIFO_AHBM_TRANS_CNT_AHBM_TRANS_CNT ((uint32_t)(0xFFFFFFFFUL << MXC_F_CSI2_VFIFO_AHBM_TRANS_CNT_AHBM_TRANS_CNT_POS)) |
| |
| #define | MXC_F_CSI2_RX_EINT_VFF_IE_FNEMPTY_POS 0 |
| |
| #define | MXC_F_CSI2_RX_EINT_VFF_IE_FNEMPTY ((uint32_t)(0x1UL << MXC_F_CSI2_RX_EINT_VFF_IE_FNEMPTY_POS)) |
| |
| #define | MXC_F_CSI2_RX_EINT_VFF_IE_FTHD_POS 1 |
| |
| #define | MXC_F_CSI2_RX_EINT_VFF_IE_FTHD ((uint32_t)(0x1UL << MXC_F_CSI2_RX_EINT_VFF_IE_FTHD_POS)) |
| |
| #define | MXC_F_CSI2_RX_EINT_VFF_IE_FFULL_POS 2 |
| |
| #define | MXC_F_CSI2_RX_EINT_VFF_IE_FFULL ((uint32_t)(0x1UL << MXC_F_CSI2_RX_EINT_VFF_IE_FFULL_POS)) |
| |
| #define | MXC_F_CSI2_RX_EINT_VFF_IE_UNDERRUN_POS 3 |
| |
| #define | MXC_F_CSI2_RX_EINT_VFF_IE_UNDERRUN ((uint32_t)(0x1UL << MXC_F_CSI2_RX_EINT_VFF_IE_UNDERRUN_POS)) |
| |
| #define | MXC_F_CSI2_RX_EINT_VFF_IE_OVERRUN_POS 4 |
| |
| #define | MXC_F_CSI2_RX_EINT_VFF_IE_OVERRUN ((uint32_t)(0x1UL << MXC_F_CSI2_RX_EINT_VFF_IE_OVERRUN_POS)) |
| |
| #define | MXC_F_CSI2_RX_EINT_VFF_IE_OUTSYNC_POS 5 |
| |
| #define | MXC_F_CSI2_RX_EINT_VFF_IE_OUTSYNC ((uint32_t)(0x1UL << MXC_F_CSI2_RX_EINT_VFF_IE_OUTSYNC_POS)) |
| |
| #define | MXC_F_CSI2_RX_EINT_VFF_IE_FMTERR_POS 6 |
| |
| #define | MXC_F_CSI2_RX_EINT_VFF_IE_FMTERR ((uint32_t)(0x1UL << MXC_F_CSI2_RX_EINT_VFF_IE_FMTERR_POS)) |
| |
| #define | MXC_F_CSI2_RX_EINT_VFF_IE_AHBWTO_POS 7 |
| |
| #define | MXC_F_CSI2_RX_EINT_VFF_IE_AHBWTO ((uint32_t)(0x1UL << MXC_F_CSI2_RX_EINT_VFF_IE_AHBWTO_POS)) |
| |
| #define | MXC_F_CSI2_RX_EINT_VFF_IE_FS_POS 8 |
| |
| #define | MXC_F_CSI2_RX_EINT_VFF_IE_FS ((uint32_t)(0x1UL << MXC_F_CSI2_RX_EINT_VFF_IE_FS_POS)) |
| |
| #define | MXC_F_CSI2_RX_EINT_VFF_IE_FE_POS 9 |
| |
| #define | MXC_F_CSI2_RX_EINT_VFF_IE_FE ((uint32_t)(0x1UL << MXC_F_CSI2_RX_EINT_VFF_IE_FE_POS)) |
| |
| #define | MXC_F_CSI2_RX_EINT_VFF_IE_LS_POS 10 |
| |
| #define | MXC_F_CSI2_RX_EINT_VFF_IE_LS ((uint32_t)(0x1UL << MXC_F_CSI2_RX_EINT_VFF_IE_LS_POS)) |
| |
| #define | MXC_F_CSI2_RX_EINT_VFF_IE_LE_POS 11 |
| |
| #define | MXC_F_CSI2_RX_EINT_VFF_IE_LE ((uint32_t)(0x1UL << MXC_F_CSI2_RX_EINT_VFF_IE_LE_POS)) |
| |
| #define | MXC_F_CSI2_RX_EINT_VFF_IE_RAW_OVR_POS 12 |
| |
| #define | MXC_F_CSI2_RX_EINT_VFF_IE_RAW_OVR ((uint32_t)(0x1UL << MXC_F_CSI2_RX_EINT_VFF_IE_RAW_OVR_POS)) |
| |
| #define | MXC_F_CSI2_RX_EINT_VFF_IE_RAW_AHBERR_POS 13 |
| |
| #define | MXC_F_CSI2_RX_EINT_VFF_IE_RAW_AHBERR ((uint32_t)(0x1UL << MXC_F_CSI2_RX_EINT_VFF_IE_RAW_AHBERR_POS)) |
| |
| #define | MXC_F_CSI2_RX_EINT_VFF_IE_FNEMP_MD_POS 16 |
| |
| #define | MXC_F_CSI2_RX_EINT_VFF_IE_FNEMP_MD ((uint32_t)(0x1UL << MXC_F_CSI2_RX_EINT_VFF_IE_FNEMP_MD_POS)) |
| |
| #define | MXC_F_CSI2_RX_EINT_VFF_IE_FTHD_MD_POS 17 |
| |
| #define | MXC_F_CSI2_RX_EINT_VFF_IE_FTHD_MD ((uint32_t)(0x1UL << MXC_F_CSI2_RX_EINT_VFF_IE_FTHD_MD_POS)) |
| |
| #define | MXC_F_CSI2_RX_EINT_VFF_IE_FFUL_MD_POS 18 |
| |
| #define | MXC_F_CSI2_RX_EINT_VFF_IE_FFUL_MD ((uint32_t)(0x1UL << MXC_F_CSI2_RX_EINT_VFF_IE_FFUL_MD_POS)) |
| |
| #define | MXC_F_CSI2_RX_EINT_VFF_IE_AHBM_RDTO_POS 24 |
| |
| #define | MXC_F_CSI2_RX_EINT_VFF_IE_AHBM_RDTO ((uint32_t)(0x1UL << MXC_F_CSI2_RX_EINT_VFF_IE_AHBM_RDTO_POS)) |
| |
| #define | MXC_F_CSI2_RX_EINT_VFF_IE_AHBM_IDTO_POS 25 |
| |
| #define | MXC_F_CSI2_RX_EINT_VFF_IE_AHBM_IDTO ((uint32_t)(0x1UL << MXC_F_CSI2_RX_EINT_VFF_IE_AHBM_IDTO_POS)) |
| |
| #define | MXC_F_CSI2_RX_EINT_VFF_IE_AHBM_MAX_POS 26 |
| |
| #define | MXC_F_CSI2_RX_EINT_VFF_IE_AHBM_MAX ((uint32_t)(0x1UL << MXC_F_CSI2_RX_EINT_VFF_IE_AHBM_MAX_POS)) |
| |
| #define | MXC_F_CSI2_RX_EINT_VFF_IF_FNEMPTY_POS 0 |
| |
| #define | MXC_F_CSI2_RX_EINT_VFF_IF_FNEMPTY ((uint32_t)(0x1UL << MXC_F_CSI2_RX_EINT_VFF_IF_FNEMPTY_POS)) |
| |
| #define | MXC_F_CSI2_RX_EINT_VFF_IF_FTHD_POS 1 |
| |
| #define | MXC_F_CSI2_RX_EINT_VFF_IF_FTHD ((uint32_t)(0x1UL << MXC_F_CSI2_RX_EINT_VFF_IF_FTHD_POS)) |
| |
| #define | MXC_F_CSI2_RX_EINT_VFF_IF_FFULL_POS 2 |
| |
| #define | MXC_F_CSI2_RX_EINT_VFF_IF_FFULL ((uint32_t)(0x1UL << MXC_F_CSI2_RX_EINT_VFF_IF_FFULL_POS)) |
| |
| #define | MXC_F_CSI2_RX_EINT_VFF_IF_UNDERRUN_POS 3 |
| |
| #define | MXC_F_CSI2_RX_EINT_VFF_IF_UNDERRUN ((uint32_t)(0x1UL << MXC_F_CSI2_RX_EINT_VFF_IF_UNDERRUN_POS)) |
| |
| #define | MXC_F_CSI2_RX_EINT_VFF_IF_OVERRUN_POS 4 |
| |
| #define | MXC_F_CSI2_RX_EINT_VFF_IF_OVERRUN ((uint32_t)(0x1UL << MXC_F_CSI2_RX_EINT_VFF_IF_OVERRUN_POS)) |
| |
| #define | MXC_F_CSI2_RX_EINT_VFF_IF_OUTSYNC_POS 5 |
| |
| #define | MXC_F_CSI2_RX_EINT_VFF_IF_OUTSYNC ((uint32_t)(0x1UL << MXC_F_CSI2_RX_EINT_VFF_IF_OUTSYNC_POS)) |
| |
| #define | MXC_F_CSI2_RX_EINT_VFF_IF_FMTERR_POS 6 |
| |
| #define | MXC_F_CSI2_RX_EINT_VFF_IF_FMTERR ((uint32_t)(0x1UL << MXC_F_CSI2_RX_EINT_VFF_IF_FMTERR_POS)) |
| |
| #define | MXC_F_CSI2_RX_EINT_VFF_IF_AHBWTO_POS 7 |
| |
| #define | MXC_F_CSI2_RX_EINT_VFF_IF_AHBWTO ((uint32_t)(0x1UL << MXC_F_CSI2_RX_EINT_VFF_IF_AHBWTO_POS)) |
| |
| #define | MXC_F_CSI2_RX_EINT_VFF_IF_FS_POS 8 |
| |
| #define | MXC_F_CSI2_RX_EINT_VFF_IF_FS ((uint32_t)(0x1UL << MXC_F_CSI2_RX_EINT_VFF_IF_FS_POS)) |
| |
| #define | MXC_F_CSI2_RX_EINT_VFF_IF_FE_POS 9 |
| |
| #define | MXC_F_CSI2_RX_EINT_VFF_IF_FE ((uint32_t)(0x1UL << MXC_F_CSI2_RX_EINT_VFF_IF_FE_POS)) |
| |
| #define | MXC_F_CSI2_RX_EINT_VFF_IF_LS_POS 10 |
| |
| #define | MXC_F_CSI2_RX_EINT_VFF_IF_LS ((uint32_t)(0x1UL << MXC_F_CSI2_RX_EINT_VFF_IF_LS_POS)) |
| |
| #define | MXC_F_CSI2_RX_EINT_VFF_IF_LE_POS 11 |
| |
| #define | MXC_F_CSI2_RX_EINT_VFF_IF_LE ((uint32_t)(0x1UL << MXC_F_CSI2_RX_EINT_VFF_IF_LE_POS)) |
| |
| #define | MXC_F_CSI2_RX_EINT_VFF_IF_RAW_OVR_POS 12 |
| |
| #define | MXC_F_CSI2_RX_EINT_VFF_IF_RAW_OVR ((uint32_t)(0x1UL << MXC_F_CSI2_RX_EINT_VFF_IF_RAW_OVR_POS)) |
| |
| #define | MXC_F_CSI2_RX_EINT_VFF_IF_RAW_AHBERR_POS 13 |
| |
| #define | MXC_F_CSI2_RX_EINT_VFF_IF_RAW_AHBERR ((uint32_t)(0x1UL << MXC_F_CSI2_RX_EINT_VFF_IF_RAW_AHBERR_POS)) |
| |
| #define | MXC_F_CSI2_RX_EINT_VFF_IF_AHBM_RDTO_POS 24 |
| |
| #define | MXC_F_CSI2_RX_EINT_VFF_IF_AHBM_RDTO ((uint32_t)(0x1UL << MXC_F_CSI2_RX_EINT_VFF_IF_AHBM_RDTO_POS)) |
| |
| #define | MXC_F_CSI2_RX_EINT_VFF_IF_AHBM_IDTO_POS 25 |
| |
| #define | MXC_F_CSI2_RX_EINT_VFF_IF_AHBM_IDTO ((uint32_t)(0x1UL << MXC_F_CSI2_RX_EINT_VFF_IF_AHBM_IDTO_POS)) |
| |
| #define | MXC_F_CSI2_RX_EINT_VFF_IF_AHBM_MAX_POS 26 |
| |
| #define | MXC_F_CSI2_RX_EINT_VFF_IF_AHBM_MAX ((uint32_t)(0x1UL << MXC_F_CSI2_RX_EINT_VFF_IF_AHBM_MAX_POS)) |
| |
| #define | MXC_F_CSI2_RX_EINT_PPI_IE_DL0STOP_POS 0 |
| |
| #define | MXC_F_CSI2_RX_EINT_PPI_IE_DL0STOP ((uint32_t)(0x1UL << MXC_F_CSI2_RX_EINT_PPI_IE_DL0STOP_POS)) |
| |
| #define | MXC_F_CSI2_RX_EINT_PPI_IE_DL1STOP_POS 1 |
| |
| #define | MXC_F_CSI2_RX_EINT_PPI_IE_DL1STOP ((uint32_t)(0x1UL << MXC_F_CSI2_RX_EINT_PPI_IE_DL1STOP_POS)) |
| |
| #define | MXC_F_CSI2_RX_EINT_PPI_IE_CL0STOP_POS 4 |
| |
| #define | MXC_F_CSI2_RX_EINT_PPI_IE_CL0STOP ((uint32_t)(0x1UL << MXC_F_CSI2_RX_EINT_PPI_IE_CL0STOP_POS)) |
| |
| #define | MXC_F_CSI2_RX_EINT_PPI_IE_DL0ECONT0_POS 6 |
| |
| #define | MXC_F_CSI2_RX_EINT_PPI_IE_DL0ECONT0 ((uint32_t)(0x1UL << MXC_F_CSI2_RX_EINT_PPI_IE_DL0ECONT0_POS)) |
| |
| #define | MXC_F_CSI2_RX_EINT_PPI_IE_DL0ECONT1_POS 7 |
| |
| #define | MXC_F_CSI2_RX_EINT_PPI_IE_DL0ECONT1 ((uint32_t)(0x1UL << MXC_F_CSI2_RX_EINT_PPI_IE_DL0ECONT1_POS)) |
| |
| #define | MXC_F_CSI2_RX_EINT_PPI_IE_DL0ESOT_POS 8 |
| |
| #define | MXC_F_CSI2_RX_EINT_PPI_IE_DL0ESOT ((uint32_t)(0x1UL << MXC_F_CSI2_RX_EINT_PPI_IE_DL0ESOT_POS)) |
| |
| #define | MXC_F_CSI2_RX_EINT_PPI_IE_DL1ESOT_POS 9 |
| |
| #define | MXC_F_CSI2_RX_EINT_PPI_IE_DL1ESOT ((uint32_t)(0x1UL << MXC_F_CSI2_RX_EINT_PPI_IE_DL1ESOT_POS)) |
| |
| #define | MXC_F_CSI2_RX_EINT_PPI_IE_DL0ESOTS_POS 12 |
| |
| #define | MXC_F_CSI2_RX_EINT_PPI_IE_DL0ESOTS ((uint32_t)(0x1UL << MXC_F_CSI2_RX_EINT_PPI_IE_DL0ESOTS_POS)) |
| |
| #define | MXC_F_CSI2_RX_EINT_PPI_IE_DL1ESOTS_POS 13 |
| |
| #define | MXC_F_CSI2_RX_EINT_PPI_IE_DL1ESOTS ((uint32_t)(0x1UL << MXC_F_CSI2_RX_EINT_PPI_IE_DL1ESOTS_POS)) |
| |
| #define | MXC_F_CSI2_RX_EINT_PPI_IE_DL0EESC_POS 16 |
| |
| #define | MXC_F_CSI2_RX_EINT_PPI_IE_DL0EESC ((uint32_t)(0x1UL << MXC_F_CSI2_RX_EINT_PPI_IE_DL0EESC_POS)) |
| |
| #define | MXC_F_CSI2_RX_EINT_PPI_IE_DL1EESC_POS 17 |
| |
| #define | MXC_F_CSI2_RX_EINT_PPI_IE_DL1EESC ((uint32_t)(0x1UL << MXC_F_CSI2_RX_EINT_PPI_IE_DL1EESC_POS)) |
| |
| #define | MXC_F_CSI2_RX_EINT_PPI_IE_DL0ESESC_POS 20 |
| |
| #define | MXC_F_CSI2_RX_EINT_PPI_IE_DL0ESESC ((uint32_t)(0x1UL << MXC_F_CSI2_RX_EINT_PPI_IE_DL0ESESC_POS)) |
| |
| #define | MXC_F_CSI2_RX_EINT_PPI_IE_DL1ESESC_POS 21 |
| |
| #define | MXC_F_CSI2_RX_EINT_PPI_IE_DL1ESESC ((uint32_t)(0x1UL << MXC_F_CSI2_RX_EINT_PPI_IE_DL1ESESC_POS)) |
| |
| #define | MXC_F_CSI2_RX_EINT_PPI_IE_DL0ECTL_POS 24 |
| |
| #define | MXC_F_CSI2_RX_EINT_PPI_IE_DL0ECTL ((uint32_t)(0x1UL << MXC_F_CSI2_RX_EINT_PPI_IE_DL0ECTL_POS)) |
| |
| #define | MXC_F_CSI2_RX_EINT_PPI_IE_DL1ECTL_POS 25 |
| |
| #define | MXC_F_CSI2_RX_EINT_PPI_IE_DL1ECTL ((uint32_t)(0x1UL << MXC_F_CSI2_RX_EINT_PPI_IE_DL1ECTL_POS)) |
| |
| #define | MXC_F_CSI2_RX_EINT_PPI_IF_DL0STOP_POS 0 |
| |
| #define | MXC_F_CSI2_RX_EINT_PPI_IF_DL0STOP ((uint32_t)(0x1UL << MXC_F_CSI2_RX_EINT_PPI_IF_DL0STOP_POS)) |
| |
| #define | MXC_F_CSI2_RX_EINT_PPI_IF_DL1STOP_POS 1 |
| |
| #define | MXC_F_CSI2_RX_EINT_PPI_IF_DL1STOP ((uint32_t)(0x1UL << MXC_F_CSI2_RX_EINT_PPI_IF_DL1STOP_POS)) |
| |
| #define | MXC_F_CSI2_RX_EINT_PPI_IF_CL0STOP_POS 4 |
| |
| #define | MXC_F_CSI2_RX_EINT_PPI_IF_CL0STOP ((uint32_t)(0x1UL << MXC_F_CSI2_RX_EINT_PPI_IF_CL0STOP_POS)) |
| |
| #define | MXC_F_CSI2_RX_EINT_PPI_IF_DL0ECONT0_POS 6 |
| |
| #define | MXC_F_CSI2_RX_EINT_PPI_IF_DL0ECONT0 ((uint32_t)(0x1UL << MXC_F_CSI2_RX_EINT_PPI_IF_DL0ECONT0_POS)) |
| |
| #define | MXC_F_CSI2_RX_EINT_PPI_IF_DL0ECONT1_POS 7 |
| |
| #define | MXC_F_CSI2_RX_EINT_PPI_IF_DL0ECONT1 ((uint32_t)(0x1UL << MXC_F_CSI2_RX_EINT_PPI_IF_DL0ECONT1_POS)) |
| |
| #define | MXC_F_CSI2_RX_EINT_PPI_IF_DL0ESOT_POS 8 |
| |
| #define | MXC_F_CSI2_RX_EINT_PPI_IF_DL0ESOT ((uint32_t)(0x1UL << MXC_F_CSI2_RX_EINT_PPI_IF_DL0ESOT_POS)) |
| |
| #define | MXC_F_CSI2_RX_EINT_PPI_IF_DL1ESOT_POS 9 |
| |
| #define | MXC_F_CSI2_RX_EINT_PPI_IF_DL1ESOT ((uint32_t)(0x1UL << MXC_F_CSI2_RX_EINT_PPI_IF_DL1ESOT_POS)) |
| |
| #define | MXC_F_CSI2_RX_EINT_PPI_IF_DL0ESOTS_POS 12 |
| |
| #define | MXC_F_CSI2_RX_EINT_PPI_IF_DL0ESOTS ((uint32_t)(0x1UL << MXC_F_CSI2_RX_EINT_PPI_IF_DL0ESOTS_POS)) |
| |
| #define | MXC_F_CSI2_RX_EINT_PPI_IF_DL1ESOTS_POS 13 |
| |
| #define | MXC_F_CSI2_RX_EINT_PPI_IF_DL1ESOTS ((uint32_t)(0x1UL << MXC_F_CSI2_RX_EINT_PPI_IF_DL1ESOTS_POS)) |
| |
| #define | MXC_F_CSI2_RX_EINT_PPI_IF_DL0EESC_POS 16 |
| |
| #define | MXC_F_CSI2_RX_EINT_PPI_IF_DL0EESC ((uint32_t)(0x1UL << MXC_F_CSI2_RX_EINT_PPI_IF_DL0EESC_POS)) |
| |
| #define | MXC_F_CSI2_RX_EINT_PPI_IF_DL1EESC_POS 17 |
| |
| #define | MXC_F_CSI2_RX_EINT_PPI_IF_DL1EESC ((uint32_t)(0x1UL << MXC_F_CSI2_RX_EINT_PPI_IF_DL1EESC_POS)) |
| |
| #define | MXC_F_CSI2_RX_EINT_PPI_IF_DL0ESESC_POS 20 |
| |
| #define | MXC_F_CSI2_RX_EINT_PPI_IF_DL0ESESC ((uint32_t)(0x1UL << MXC_F_CSI2_RX_EINT_PPI_IF_DL0ESESC_POS)) |
| |
| #define | MXC_F_CSI2_RX_EINT_PPI_IF_DL1ESESC_POS 21 |
| |
| #define | MXC_F_CSI2_RX_EINT_PPI_IF_DL1ESESC ((uint32_t)(0x1UL << MXC_F_CSI2_RX_EINT_PPI_IF_DL1ESESC_POS)) |
| |
| #define | MXC_F_CSI2_RX_EINT_PPI_IF_DL0ECTL_POS 24 |
| |
| #define | MXC_F_CSI2_RX_EINT_PPI_IF_DL0ECTL ((uint32_t)(0x1UL << MXC_F_CSI2_RX_EINT_PPI_IF_DL0ECTL_POS)) |
| |
| #define | MXC_F_CSI2_RX_EINT_PPI_IF_DL1ECTL_POS 25 |
| |
| #define | MXC_F_CSI2_RX_EINT_PPI_IF_DL1ECTL ((uint32_t)(0x1UL << MXC_F_CSI2_RX_EINT_PPI_IF_DL1ECTL_POS)) |
| |
| #define | MXC_F_CSI2_RX_EINT_CTRL_IE_EECC2_POS 0 |
| |
| #define | MXC_F_CSI2_RX_EINT_CTRL_IE_EECC2 ((uint32_t)(0x1UL << MXC_F_CSI2_RX_EINT_CTRL_IE_EECC2_POS)) |
| |
| #define | MXC_F_CSI2_RX_EINT_CTRL_IE_EECC1_POS 1 |
| |
| #define | MXC_F_CSI2_RX_EINT_CTRL_IE_EECC1 ((uint32_t)(0x1UL << MXC_F_CSI2_RX_EINT_CTRL_IE_EECC1_POS)) |
| |
| #define | MXC_F_CSI2_RX_EINT_CTRL_IE_ECRC_POS 2 |
| |
| #define | MXC_F_CSI2_RX_EINT_CTRL_IE_ECRC ((uint32_t)(0x1UL << MXC_F_CSI2_RX_EINT_CTRL_IE_ECRC_POS)) |
| |
| #define | MXC_F_CSI2_RX_EINT_CTRL_IE_EID_POS 3 |
| |
| #define | MXC_F_CSI2_RX_EINT_CTRL_IE_EID ((uint32_t)(0x1UL << MXC_F_CSI2_RX_EINT_CTRL_IE_EID_POS)) |
| |
| #define | MXC_F_CSI2_RX_EINT_CTRL_IE_PKTFFOV_POS 4 |
| |
| #define | MXC_F_CSI2_RX_EINT_CTRL_IE_PKTFFOV ((uint32_t)(0x1UL << MXC_F_CSI2_RX_EINT_CTRL_IE_PKTFFOV_POS)) |
| |
| #define | MXC_F_CSI2_RX_EINT_CTRL_IE_DL0ULPSA_POS 8 |
| |
| #define | MXC_F_CSI2_RX_EINT_CTRL_IE_DL0ULPSA ((uint32_t)(0x1UL << MXC_F_CSI2_RX_EINT_CTRL_IE_DL0ULPSA_POS)) |
| |
| #define | MXC_F_CSI2_RX_EINT_CTRL_IE_DL1ULPSA_POS 9 |
| |
| #define | MXC_F_CSI2_RX_EINT_CTRL_IE_DL1ULPSA ((uint32_t)(0x1UL << MXC_F_CSI2_RX_EINT_CTRL_IE_DL1ULPSA_POS)) |
| |
| #define | MXC_F_CSI2_RX_EINT_CTRL_IE_DL0ULPSM_POS 12 |
| |
| #define | MXC_F_CSI2_RX_EINT_CTRL_IE_DL0ULPSM ((uint32_t)(0x1UL << MXC_F_CSI2_RX_EINT_CTRL_IE_DL0ULPSM_POS)) |
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| #define | MXC_F_CSI2_RX_EINT_CTRL_IE_DL1ULPSM_POS 13 |
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| #define | MXC_F_CSI2_RX_EINT_CTRL_IE_DL1ULPSM ((uint32_t)(0x1UL << MXC_F_CSI2_RX_EINT_CTRL_IE_DL1ULPSM_POS)) |
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| #define | MXC_F_CSI2_RX_EINT_CTRL_IE_CL0ULPSA_POS 16 |
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| #define | MXC_F_CSI2_RX_EINT_CTRL_IE_CL0ULPSA ((uint32_t)(0x1UL << MXC_F_CSI2_RX_EINT_CTRL_IE_CL0ULPSA_POS)) |
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| #define | MXC_F_CSI2_RX_EINT_CTRL_IE_CL0ULPSM_POS 17 |
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| #define | MXC_F_CSI2_RX_EINT_CTRL_IE_CL0ULPSM ((uint32_t)(0x1UL << MXC_F_CSI2_RX_EINT_CTRL_IE_CL0ULPSM_POS)) |
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| #define | MXC_F_CSI2_RX_EINT_CTRL_IF_EECC2_POS 0 |
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| #define | MXC_F_CSI2_RX_EINT_CTRL_IF_EECC2 ((uint32_t)(0x1UL << MXC_F_CSI2_RX_EINT_CTRL_IF_EECC2_POS)) |
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| #define | MXC_F_CSI2_RX_EINT_CTRL_IF_EECC1_POS 1 |
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| #define | MXC_F_CSI2_RX_EINT_CTRL_IF_EECC1 ((uint32_t)(0x1UL << MXC_F_CSI2_RX_EINT_CTRL_IF_EECC1_POS)) |
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| #define | MXC_F_CSI2_RX_EINT_CTRL_IF_ECRC_POS 2 |
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| #define | MXC_F_CSI2_RX_EINT_CTRL_IF_ECRC ((uint32_t)(0x1UL << MXC_F_CSI2_RX_EINT_CTRL_IF_ECRC_POS)) |
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| #define | MXC_F_CSI2_RX_EINT_CTRL_IF_EID_POS 3 |
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| #define | MXC_F_CSI2_RX_EINT_CTRL_IF_EID ((uint32_t)(0x1UL << MXC_F_CSI2_RX_EINT_CTRL_IF_EID_POS)) |
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| #define | MXC_F_CSI2_RX_EINT_CTRL_IF_PKTFFOV_POS 4 |
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| #define | MXC_F_CSI2_RX_EINT_CTRL_IF_PKTFFOV ((uint32_t)(0x1UL << MXC_F_CSI2_RX_EINT_CTRL_IF_PKTFFOV_POS)) |
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| #define | MXC_F_CSI2_RX_EINT_CTRL_IF_DL0ULPSA_POS 8 |
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| #define | MXC_F_CSI2_RX_EINT_CTRL_IF_DL0ULPSA ((uint32_t)(0x1UL << MXC_F_CSI2_RX_EINT_CTRL_IF_DL0ULPSA_POS)) |
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| #define | MXC_F_CSI2_RX_EINT_CTRL_IF_DL1ULPSA_POS 9 |
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| #define | MXC_F_CSI2_RX_EINT_CTRL_IF_DL1ULPSA ((uint32_t)(0x1UL << MXC_F_CSI2_RX_EINT_CTRL_IF_DL1ULPSA_POS)) |
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| #define | MXC_F_CSI2_RX_EINT_CTRL_IF_DL0ULPSM_POS 12 |
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| #define | MXC_F_CSI2_RX_EINT_CTRL_IF_DL0ULPSM ((uint32_t)(0x1UL << MXC_F_CSI2_RX_EINT_CTRL_IF_DL0ULPSM_POS)) |
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| #define | MXC_F_CSI2_RX_EINT_CTRL_IF_DL1ULPSM_POS 13 |
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| #define | MXC_F_CSI2_RX_EINT_CTRL_IF_DL1ULPSM ((uint32_t)(0x1UL << MXC_F_CSI2_RX_EINT_CTRL_IF_DL1ULPSM_POS)) |
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| #define | MXC_F_CSI2_RX_EINT_CTRL_IF_CL0ULPSA_POS 16 |
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| #define | MXC_F_CSI2_RX_EINT_CTRL_IF_CL0ULPSA ((uint32_t)(0x1UL << MXC_F_CSI2_RX_EINT_CTRL_IF_CL0ULPSA_POS)) |
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| #define | MXC_F_CSI2_RX_EINT_CTRL_IF_CL0ULPSM_POS 17 |
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| #define | MXC_F_CSI2_RX_EINT_CTRL_IF_CL0ULPSM ((uint32_t)(0x1UL << MXC_F_CSI2_RX_EINT_CTRL_IF_CL0ULPSM_POS)) |
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| #define | MXC_F_CSI2_PPI_STOPSTATE_DL0STOP_POS 0 |
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| #define | MXC_F_CSI2_PPI_STOPSTATE_DL0STOP ((uint32_t)(0x1UL << MXC_F_CSI2_PPI_STOPSTATE_DL0STOP_POS)) |
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| #define | MXC_F_CSI2_PPI_STOPSTATE_DL1STOP_POS 1 |
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| #define | MXC_F_CSI2_PPI_STOPSTATE_DL1STOP ((uint32_t)(0x1UL << MXC_F_CSI2_PPI_STOPSTATE_DL1STOP_POS)) |
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| #define | MXC_F_CSI2_PPI_STOPSTATE_CL0STOP_POS 2 |
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| #define | MXC_F_CSI2_PPI_STOPSTATE_CL0STOP ((uint32_t)(0x1UL << MXC_F_CSI2_PPI_STOPSTATE_CL0STOP_POS)) |
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| #define | MXC_F_CSI2_PPI_TURNAROUND_CFG_DL0TAREQ_POS 0 |
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| #define | MXC_F_CSI2_PPI_TURNAROUND_CFG_DL0TAREQ ((uint32_t)(0x1UL << MXC_F_CSI2_PPI_TURNAROUND_CFG_DL0TAREQ_POS)) |
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| #define | MXC_F_CSI2_PPI_TURNAROUND_CFG_DL0TADIS_POS 1 |
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| #define | MXC_F_CSI2_PPI_TURNAROUND_CFG_DL0TADIS ((uint32_t)(0x1UL << MXC_F_CSI2_PPI_TURNAROUND_CFG_DL0TADIS_POS)) |
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| #define | MXC_F_CSI2_PPI_TURNAROUND_CFG_DL0FRCRX_POS 2 |
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| #define | MXC_F_CSI2_PPI_TURNAROUND_CFG_DL0FRCRX ((uint32_t)(0x1UL << MXC_F_CSI2_PPI_TURNAROUND_CFG_DL0FRCRX_POS)) |
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1.9.4